[Qemu-devel] [SPARC] Accessing devices through MMU mapped memory region

[Qemu-devel] [SPARC] Accessing devices through MMU mapped memory region

[Jean-Christophe DUBOIS]

Hi,

I am using Qemu to emulate a Leon3 based board.

In the software I am running on top of Qemu, I am mapping devices to a 
virtual address using MMU table.

Now I am experimenting some issues when I am trying to access some 
device (here the UART port at 0x80000100) through the MMU mapping (with 
NOCACHE attribute for this page).

in my (user space) software I am doing something like:

    #define MY_VIRTUAL_ADDRESS 0x40808100 /* mapped to 0x80000100
    physical address through MMU */

    #define UART_CTRL_REG_OFFSET 0x8

    #define UART_CTRL_TE 0x00000002

    *(volatile uint32_t *)(MY_VIRTUAL_ADDRESS + UART_CTRL_REG_OFFSET) =
    UART_CTRL_TE;

But when the write is propagated by Qemu to the serial device, I am 
getting 4 x 8bits (1 byte) write access (0x8, 0x9, 0xa, 0xb) instead of 
a single 32 bits (4 bytes) access.

The Qemu driver emulator for the serial device is unhappy about this as 
it would not handle byte access for addresses 0x9, 0xa, 0xb which are 
then tagged as unsupported access.

I am wondering if I am missing something and if there is a reason for my 
single 32 bits access to be transformed by Qemu in 4 single byte access.

I believe it is expected to be able to get single atomic 32 bits 
read/write to the device.

Would you have any hint/advice for me?

JC

Re: [Qemu-devel] [SPARC] Accessing devices through MMU mapped memory region

[Jean-Christophe DUBOIS]

Surprisingly the GCC compiler transformed my 32 bits access into 4 x 8 
bits access in my application code.

So this is not a Qemu issue but I need to find why the compiler is not 
generating the code I was expecting.

Sorry for the noise.

JC

Le 27/11/2017 à 21:16, Jean-Christophe DUBOIS a écrit :
> Hi,
>
> I am using Qemu to emulate a Leon3 based board.
>
> In the software I am running on top of Qemu, I am mapping devices to a 
> virtual address using MMU table.
>
> Now I am experimenting some issues when I am trying to access some 
> device (here the UART port at 0x80000100) through the MMU mapping 
> (with NOCACHE attribute for this page).
>
> in my (user space) software I am doing something like:
>
>    #define MY_VIRTUAL_ADDRESS 0x40808100 /* mapped to 0x80000100
>    physical address through MMU */
>
>    #define UART_CTRL_REG_OFFSET 0x8
>
>    #define UART_CTRL_TE 0x00000002
>
>    *(volatile uint32_t *)(MY_VIRTUAL_ADDRESS + UART_CTRL_REG_OFFSET) =
>    UART_CTRL_TE;
>
> But when the write is propagated by Qemu to the serial device, I am 
> getting 4 x 8bits (1 byte) write access (0x8, 0x9, 0xa, 0xb) instead 
> of a single 32 bits (4 bytes) access.
>
> The Qemu driver emulator for the serial device is unhappy about this 
> as it would not handle byte access for addresses 0x9, 0xa, 0xb which 
> are then tagged as unsupported access.
>
> I am wondering if I am missing something and if there is a reason for 
> my single 32 bits access to be transformed by Qemu in 4 single byte 
> access.
>
> I believe it is expected to be able to get single atomic 32 bits 
> read/write to the device.
>
> Would you have any hint/advice for me?
>
> JC
>
>
>