* [U-Boot] [PATCH] 85xx: Fix the clock adjust of mpc8569mds board
@ 2009-03-27 6:32 Dave Liu
2009-06-02 21:45 ` Andy Fleming
0 siblings, 1 reply; 2+ messages in thread
From: Dave Liu @ 2009-03-27 6:32 UTC (permalink / raw)
To: u-boot
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.
Signed-off-by: Dave Liu <daveliu@freescale.com>
---
board/freescale/mpc8569mds/ddr.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index c4e63fb..da1e675 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -56,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
- popts->clk_adjust = 6;
+ popts->clk_adjust = 4;
/*
* Factors to consider for CPO:
--
1.5.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] 85xx: Fix the clock adjust of mpc8569mds board
2009-03-27 6:32 [U-Boot] [PATCH] 85xx: Fix the clock adjust of mpc8569mds board Dave Liu
@ 2009-06-02 21:45 ` Andy Fleming
0 siblings, 0 replies; 2+ messages in thread
From: Andy Fleming @ 2009-06-02 21:45 UTC (permalink / raw)
To: u-boot
On Fri, Mar 27, 2009 at 1:32 AM, Dave Liu <daveliu@freescale.com> wrote:
> Currently the clk_adj is 6 (3/4 cycle), The settings will cause
> the DDR controller hang at the data init. Change the clk_adj
> from 6 to 4 (1/2 cycle), make the memory system stable.
>
> Signed-off-by: Dave Liu <daveliu@freescale.com>
Applied to HEAD, thanks!
Andy
^ permalink raw reply [flat|nested] 2+ messages in thread
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2009-03-27 6:32 [U-Boot] [PATCH] 85xx: Fix the clock adjust of mpc8569mds board Dave Liu
2009-06-02 21:45 ` Andy Fleming
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