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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Tomer Maimon <tmaimon77@gmail.com>
Cc: "Rob Herring" <robh@kernel.org>,
	"Avi Fishman" <avifishman70@gmail.com>,
	"Tali Perry" <tali.perry1@gmail.com>,
	"Joel Stanley" <joel@jms.id.au>,
	"Patrick Venture" <venture@google.com>,
	"Nancy Yuen" <yuenn@google.com>,
	"Benjamin Fair" <benjaminfair@google.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Jonathan Neuschäfer" <j.neuschaefer@gmx.net>,
	zhengbin13@huawei.com,
	"OpenBMC Maillist" <openbmc@lists.ozlabs.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	devicetree <devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Date: Tue, 20 Sep 2022 10:21:49 +0200	[thread overview]
Message-ID: <2b0e6e33-ef76-4bd4-8894-53f9a3fe68b4@linaro.org> (raw)
In-Reply-To: <CAP6Zq1gyDW8ZwwAZ1jyfNEZa09WN-biZZJY8tBmW_gzMzpj3ZA@mail.gmail.com>

On 20/09/2022 09:59, Tomer Maimon wrote:
>>>>>>> +      pinctrl: pinctrl@f0800000 {
>>>>>>> +        compatible = "nuvoton,npcm845-pinctrl";
>>>>>>> +        ranges = <0x0 0x0 0xf0010000 0x8000>;
>>>>>>> +        #address-cells = <1>;
>>>>>>> +        #size-cells = <1>;
>>>>>>> +        nuvoton,sysgcr = <&gcr>;
>>>>>>> +
>>>>>>> +        gpio0: gpio@f0010000 {
>>>>>>
>>>>>> gpio@0
>>>>>>
>>>>>> Is this really a child block of the pinctrl? Doesn't really look like it
>>>>>> based on addressess. Where are the pinctrl registers? In the sysgcr? If
>>>>>> so, then pinctrl should be a child of it. But that doesn't really work
>>>>>> too well with gpio child nodes...
>>>>> the pin controller mux is handled by sysgcr this is why the sysgcr in
>>>>> the mother node,
>>>>> and the pin configuration are handled by the GPIO registers.  each
>>>>> GPIO bank (child) contains 32 GPIO.
>>>>> this is why the GPIO is the child node.
>>>>
>>>> Then maybe pinctrl should be the sysgcr and expose regmap for other devices?
>>> The pin controller using the sysgcr to handle the pinmux, this is why
>>> the sysgcr is in the mother node, is it problematic?
>>
>> You said pin-controller mux registers are in sysgcr, so it should not be
>> used via syscon.
> Sorry but maybe I missed something.
> the sysgcr is used for miscellaneous features and not only for the pin
> controller mux, this is why it used syscon and defined in the dtsi:
>                 gcr: system-controller@f0800000 {
>                         compatible = "nuvoton,npcm845-gcr", "syscon";
>                         reg = <0x0 0xf0800000 0x0 0x1000>;
>                 };
>>
>> Please provide address map description to convince us that this is
>> correct HW representation.
> GCR (sysgcr) registers 0xf0800000-0xf0801000 - used for miscellaneous
> features, not only pin mux.
> GPIO0 0xf0010000-0xf0011000
> GPIO1 0xf0011000-0xf0012000
> ...
> GPIO7 0xf0017000-0xf0018000
>>

Then why your pinctrl is in sysgcr IO range? (pinctrl@f0800000)

Your map looks quite different from what you described in example.

Best regards,
Krzysztof

  reply	other threads:[~2022-09-20  8:24 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-14 12:23 [PATCH v2 0/2] pinctrl: nuvoton: add pinmux and GPIO driver for NPCM8XX Tomer Maimon
2022-07-14 12:23 ` Tomer Maimon
2022-07-14 12:23 ` [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation Tomer Maimon
2022-07-14 12:23   ` Tomer Maimon
2022-07-18 21:10   ` Rob Herring
2022-07-18 21:10     ` Rob Herring
2022-09-18 18:28     ` Tomer Maimon
2022-09-18 18:28       ` Tomer Maimon
2022-09-19  6:56       ` Krzysztof Kozlowski
2022-09-19 14:31         ` Tomer Maimon
2022-09-19 14:31           ` Tomer Maimon
2022-09-19 16:06           ` Krzysztof Kozlowski
2022-09-20  7:59             ` Tomer Maimon
2022-09-20  7:59               ` Tomer Maimon
2022-09-20  8:21               ` Krzysztof Kozlowski [this message]
2022-09-20  8:32                 ` Tomer Maimon
2022-09-20  8:32                   ` Tomer Maimon
2022-09-20  8:47                   ` Krzysztof Kozlowski
2022-09-20  9:27                     ` Tomer Maimon
2022-09-20  9:27                       ` Tomer Maimon
2022-09-20 15:16                       ` Krzysztof Kozlowski
2022-09-20 17:00                         ` Tomer Maimon
2022-09-20 17:00                           ` Tomer Maimon
2022-07-14 12:23 ` [PATCH v2 2/2] pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver Tomer Maimon
2022-07-14 12:23   ` Tomer Maimon
2022-07-14 12:25   ` Krzysztof Kozlowski
2022-07-14 13:14     ` Andy Shevchenko
2022-07-14 13:14       ` Andy Shevchenko
2022-07-14 16:59   ` Andy Shevchenko
2022-07-14 16:59     ` Andy Shevchenko
2022-07-18  1:24   ` kernel test robot
2022-07-18  1:24     ` kernel test robot

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