* [PATCH 01/37] target/i386: Define XMMReg and access macros, align ZMM registers
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-11 23:03 ` [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
` (35 subsequent siblings)
36 siblings, 0 replies; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson
From: Richard Henderson <richard.henderson@linaro.org>
This will be used for emission and endian adjustments of gvec operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822223722.1697758-2-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.h | 56 ++++++++++++++++++++++++++++++++++++-----------
1 file changed, 43 insertions(+), 13 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 82004b65b9..8311b69c88 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1233,18 +1233,34 @@ typedef struct SegmentCache {
uint32_t flags;
} SegmentCache;
-#define MMREG_UNION(n, bits) \
- union n { \
- uint8_t _b_##n[(bits)/8]; \
- uint16_t _w_##n[(bits)/16]; \
- uint32_t _l_##n[(bits)/32]; \
- uint64_t _q_##n[(bits)/64]; \
- float32 _s_##n[(bits)/32]; \
- float64 _d_##n[(bits)/64]; \
- }
+typedef union MMXReg {
+ uint8_t _b_MMXReg[64 / 8];
+ uint16_t _w_MMXReg[64 / 16];
+ uint32_t _l_MMXReg[64 / 32];
+ uint64_t _q_MMXReg[64 / 64];
+ float32 _s_MMXReg[64 / 32];
+ float64 _d_MMXReg[64 / 64];
+} MMXReg;
-typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
-typedef MMREG_UNION(MMXReg, 64) MMXReg;
+typedef union XMMReg {
+ uint64_t _q_XMMReg[128 / 64];
+} XMMReg;
+
+typedef union YMMReg {
+ uint64_t _q_YMMReg[256 / 64];
+ XMMReg _x_YMMReg[256 / 128];
+} YMMReg;
+
+typedef union ZMMReg {
+ uint8_t _b_ZMMReg[512 / 8];
+ uint16_t _w_ZMMReg[512 / 16];
+ uint32_t _l_ZMMReg[512 / 32];
+ uint64_t _q_ZMMReg[512 / 64];
+ float32 _s_ZMMReg[512 / 32];
+ float64 _d_ZMMReg[512 / 64];
+ XMMReg _x_ZMMReg[512 / 128];
+ YMMReg _y_ZMMReg[512 / 256];
+} ZMMReg;
typedef struct BNDReg {
uint64_t lb;
@@ -1267,6 +1283,13 @@ typedef struct BNDCSReg {
#define ZMM_S(n) _s_ZMMReg[15 - (n)]
#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
#define ZMM_D(n) _d_ZMMReg[7 - (n)]
+#define ZMM_X(n) _x_ZMMReg[3 - (n)]
+#define ZMM_Y(n) _y_ZMMReg[1 - (n)]
+
+#define XMM_Q(n) _q_XMMReg[1 - (n)]
+
+#define YMM_Q(n) _q_YMMReg[3 - (n)]
+#define YMM_X(n) _x_YMMReg[1 - (n)]
#define MMX_B(n) _b_MMXReg[7 - (n)]
#define MMX_W(n) _w_MMXReg[3 - (n)]
@@ -1279,6 +1302,13 @@ typedef struct BNDCSReg {
#define ZMM_S(n) _s_ZMMReg[n]
#define ZMM_Q(n) _q_ZMMReg[n]
#define ZMM_D(n) _d_ZMMReg[n]
+#define ZMM_X(n) _x_ZMMReg[n]
+#define ZMM_Y(n) _y_ZMMReg[n]
+
+#define XMM_Q(n) _q_XMMReg[n]
+
+#define YMM_Q(n) _q_YMMReg[n]
+#define YMM_X(n) _x_YMMReg[n]
#define MMX_B(n) _b_MMXReg[n]
#define MMX_W(n) _w_MMXReg[n]
@@ -1556,8 +1586,8 @@ typedef struct CPUArchState {
float_status mmx_status; /* for 3DNow! float ops */
float_status sse_status;
uint32_t mxcsr;
- ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
- ZMMReg xmm_t0;
+ ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
+ ZMMReg xmm_t0 QEMU_ALIGNED(16);
MMXReg mmx_t0;
uint64_t opmask_regs[NB_OPMASK_REGS];
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
2022-09-11 23:03 ` [PATCH 01/37] target/i386: Define XMMReg and access macros, align ZMM registers Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 8:33 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive Paolo Bonzini
` (34 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
ldq takes a pointer to the first byte to load the 64-bit word in;
ldo takes a pointer to the first byte of the ZMMReg. Make them
consistent, which will be useful in the new SSE decoder's
load/writeback routines.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 44 +++++++++++++++++++------------------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 001af76663..9a85010dcd 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2761,28 +2761,29 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index, MO_LEUQ);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(s->tmp0, s->A0, 8);
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
}
static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
+ offset -= offsetof(ZMMReg, ZMM_Q(0));
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index, MO_LEUQ);
tcg_gen_addi_tl(s->tmp0, s->A0, 8);
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
}
static inline void gen_op_movo(DisasContext *s, int d_offset, int s_offset)
{
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, ZMM_Q(0)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, ZMM_Q(0)));
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, ZMM_Q(1)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, ZMM_Q(1)));
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, s_offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, d_offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, s_offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, d_offset + offsetof(XMMReg, XMM_Q(1)));
}
static inline void gen_op_movq(DisasContext *s, int d_offset, int s_offset)
@@ -2804,6 +2805,7 @@ static inline void gen_op_movq_env_0(DisasContext *s, int d_offset)
}
#define ZMM_OFFSET(reg) offsetof(CPUX86State, xmm_regs[reg])
+#define XMM_OFFSET(reg) offsetof(CPUX86State, xmm_regs[reg].ZMM_X(0))
typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg);
@@ -3317,13 +3319,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm);
- gen_sto_env_A0(s, ZMM_OFFSET(reg));
+ gen_sto_env_A0(s, XMM_OFFSET(reg));
break;
case 0x3f0: /* lddqu */
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm);
- gen_ldo_env_A0(s, ZMM_OFFSET(reg));
+ gen_ldo_env_A0(s, XMM_OFFSET(reg));
break;
case 0x22b: /* movntss */
case 0x32b: /* movntsd */
@@ -3392,10 +3394,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x26f: /* movdqu xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- gen_ldo_env_A0(s, ZMM_OFFSET(reg));
+ gen_ldo_env_A0(s, XMM_OFFSET(reg));
} else {
rm = (modrm & 7) | REX_B(s);
- gen_op_movo(s, ZMM_OFFSET(reg), ZMM_OFFSET(rm));
+ gen_op_movo(s, XMM_OFFSET(reg), XMM_OFFSET(rm));
}
break;
case 0x210: /* movss xmm, ea */
@@ -3451,7 +3453,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x212: /* movsldup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- gen_ldo_env_A0(s, ZMM_OFFSET(reg));
+ gen_ldo_env_A0(s, XMM_OFFSET(reg));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(s, offsetof(CPUX86State, xmm_regs[reg].ZMM_L(0)),
@@ -3493,7 +3495,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x216: /* movshdup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- gen_ldo_env_A0(s, ZMM_OFFSET(reg));
+ gen_ldo_env_A0(s, XMM_OFFSET(reg));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(s, offsetof(CPUX86State, xmm_regs[reg].ZMM_L(1)),
@@ -3587,10 +3589,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x27f: /* movdqu ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- gen_sto_env_A0(s, ZMM_OFFSET(reg));
+ gen_sto_env_A0(s, XMM_OFFSET(reg));
} else {
rm = (modrm & 7) | REX_B(s);
- gen_op_movo(s, ZMM_OFFSET(rm), ZMM_OFFSET(reg));
+ gen_op_movo(s, XMM_OFFSET(rm), XMM_OFFSET(reg));
}
break;
case 0x211: /* movss ea, xmm */
@@ -3742,7 +3744,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_helper_enter_mmx(cpu_env);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- op2_offset = offsetof(CPUX86State,xmm_t0);
+ op2_offset = offsetof(CPUX86State,xmm_t0.ZMM_X(0));
gen_ldo_env_A0(s, op2_offset);
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3906,9 +3908,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
if (b1) {
- op1_offset = ZMM_OFFSET(reg);
+ op1_offset = XMM_OFFSET(reg);
if (mod == 3) {
- op2_offset = ZMM_OFFSET(rm | REX_B(s));
+ op2_offset = XMM_OFFSET(rm | REX_B(s));
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
gen_lea_modrm(env, s, modrm);
@@ -4516,7 +4518,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3) {
op2_offset = ZMM_OFFSET(rm | REX_B(s));
} else {
- op2_offset = offsetof(CPUX86State, xmm_t0);
+ op2_offset = offsetof(CPUX86State, xmm_t0.ZMM_X(0));
gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, op2_offset);
}
@@ -4625,7 +4627,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
default:
/* 128 bit access */
- gen_ldo_env_A0(s, op2_offset);
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_X(0)));
break;
}
} else {
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq
2022-09-11 23:03 ` [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
@ 2022-09-12 8:33 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 8:33 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> ldq takes a pointer to the first byte to load the 64-bit word in;
> ldo takes a pointer to the first byte of the ZMMReg. Make them
> consistent, which will be useful in the new SSE decoder's
> load/writeback routines.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/translate.c | 44 +++++++++++++++++++------------------
> 1 file changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
> index 001af76663..9a85010dcd 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -2761,28 +2761,29 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
> {
> int mem_index = s->mem_index;
> tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index, MO_LEUQ);
> - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
> tcg_gen_addi_tl(s->tmp0, s->A0, 8);
> tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
> - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
> }
>
> static inline void gen_sto_env_A0(DisasContext *s, int offset)
> {
> int mem_index = s->mem_index;
> - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
> + offset -= offsetof(ZMMReg, ZMM_Q(0));
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
What is this subtract? You don't have it for ldo or movo, and it looks wrong.
The rest of it looks ok.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
2022-09-11 23:03 ` [PATCH 01/37] target/i386: Define XMMReg and access macros, align ZMM registers Paolo Bonzini
2022-09-11 23:03 ` [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 8:37 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 04/37] target/i386: introduce insn_get_addr Paolo Bonzini
` (33 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
The later prefix wins if both are present, make it show in s->prefix too.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9a85010dcd..f8fd93dae0 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4737,9 +4737,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
switch (b) {
case 0xf3:
prefixes |= PREFIX_REPZ;
+ prefixes &= ~PREFIX_REPNZ;
goto next_byte;
case 0xf2:
prefixes |= PREFIX_REPNZ;
+ prefixes &= ~PREFIX_REPZ;
goto next_byte;
case 0xf0:
prefixes |= PREFIX_LOCK;
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* [PATCH 04/37] target/i386: introduce insn_get_addr
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (2 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 8:39 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 05/37] target/i386: add core of new i386 decoder Paolo Bonzini
` (32 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
The "O" operand type in the Intel SDM needs to load an 8- to 64-bit
unsigned value, while insn_get is limited to 32 bits. Extract the code
out of disas_insn and into a separate function.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 36 ++++++++++++++++++++++++++----------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index f8fd93dae0..f1aa830fcc 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2308,6 +2308,31 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
}
}
+static inline target_ulong insn_get_addr(CPUX86State *env, DisasContext *s, MemOp ot)
+{
+ target_ulong ret;
+
+ switch (ot) {
+ case MO_8:
+ ret = x86_ldub_code(env, s);
+ break;
+ case MO_16:
+ ret = x86_lduw_code(env, s);
+ break;
+ case MO_32:
+ ret = x86_ldl_code(env, s);
+ break;
+#ifdef TARGET_X86_64
+ case MO_64:
+ ret = x86_ldq_code(env, s);
+ break;
+#endif
+ default:
+ tcg_abort();
+ }
+ return ret;
+}
+
static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)
{
uint32_t ret;
@@ -5867,16 +5892,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
target_ulong offset_addr;
ot = mo_b_d(b, dflag);
- switch (s->aflag) {
-#ifdef TARGET_X86_64
- case MO_64:
- offset_addr = x86_ldq_code(env, s);
- break;
-#endif
- default:
- offset_addr = insn_get(env, s, s->aflag);
- break;
- }
+ offset_addr = insn_get_addr(env, s, s->aflag);
tcg_gen_movi_tl(s->A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 04/37] target/i386: introduce insn_get_addr
2022-09-11 23:03 ` [PATCH 04/37] target/i386: introduce insn_get_addr Paolo Bonzini
@ 2022-09-12 8:39 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 8:39 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> The "O" operand type in the Intel SDM needs to load an 8- to 64-bit
> unsigned value, while insn_get is limited to 32 bits. Extract the code
> out of disas_insn and into a separate function.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/translate.c | 36 ++++++++++++++++++++++++++----------
> 1 file changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
> index f8fd93dae0..f1aa830fcc 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -2308,6 +2308,31 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
> }
> }
>
> +static inline target_ulong insn_get_addr(CPUX86State *env, DisasContext *s, MemOp ot)
No need for inline.
> + default:
> + tcg_abort();
Standardize on g_assert_not_reached().
I should probably zap this macro entirely...
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 05/37] target/i386: add core of new i386 decoder
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (3 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 04/37] target/i386: introduce insn_get_addr Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 9:27 ` Richard Henderson
2022-09-12 10:54 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 06/37] target/i386: add ALU load/writeback core Paolo Bonzini
` (31 subsequent siblings)
36 siblings, 2 replies; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
The new decoder is based on three principles:
- use mostly table-driven decoding, using tables derived as much as possible
from the Intel manual. Centralizing the decode the operands makes it
more homogeneous, for example all immediates are signed. All modrm
handling is in one function, and can be shared between SSE and ALU
instructions (including XMM<->GPR instructions). The SSE/AVX decoder
will also not have duplicated code between the 0F, 0F38 and 0F3A tables.
- keep the code as "non-branchy" as possible. Generally, the code for
the new decoder is more verbose, but the control flow is simpler.
Conditionals are not nested and have small bodies. All instruction
groups are resolved even before operands are decoded, and code
generation is separated as much as possible within small functions
that only handle one instruction each.
- keep address generation and (for ALU operands) memory loads and writeback
as much in common code as possible. All ALU operations for example
are implemented as T0=f(T0,T1). For non-ALU instructions,
read-modify-write memory operations are rare, but registers do not
have TCGv equivalents: therefore, the common logic sets up pointer
temporaries with the operands, while load and writeback are handled
by gvec or by helpers.
These principles make future code review and extensibility simpler, at
the cost of having a relatively large amount of code in the form of this
patch. Even EVEX should not be _too_ hard to implement (it's just a crazy
large amount of possibilities).
This patch introduces the main decoder flow, and integrates the old
decoder with the new one. The old decoder takes care of parsing
prefixes and then optionally drops to the new one. The changes to the
old decoder are minimal and allow it to be replaced incrementally with
the new one.
There is a debugging mechanism through a "LIMIT" environment variable.
In user-mode emulation, the variable is the number of instructions
decoded by the new decoder before permanently switching to the old one.
In system emulation, the variable is the highest opcode that is decoded
by the new decoder (this is less friendly, but it's the best that can
be done without requiring deterministic execution).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 752 +++++++++++++++++++++++++++++++
target/i386/tcg/decode-new.h | 181 ++++++++
target/i386/tcg/emit.c.inc | 31 ++
target/i386/tcg/translate.c | 64 ++-
4 files changed, 1021 insertions(+), 7 deletions(-)
create mode 100644 target/i386/tcg/decode-new.c.inc
create mode 100644 target/i386/tcg/decode-new.h
create mode 100644 target/i386/tcg/emit.c.inc
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
new file mode 100644
index 0000000000..de8ef51a2d
--- /dev/null
+++ b/target/i386/tcg/decode-new.c.inc
@@ -0,0 +1,752 @@
+/*
+ * New-style decoder for i386 instructions
+ *
+ * Copyright (c) 2022 Red Hat, Inc.
+ *
+ * Author: Paolo Bonzini <pbonzini@redhat.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * The decoder is mostly based on tables copied from the Intel SDM. As
+ * a result, most operand load and writeback is done entirely in common
+ * table-driven code using the same operand type (X86_TYPE_*) and
+ * size (X86_SIZE_*) codes used in the manual.
+ *
+ * The main difference is that the V, U and W types are extended to
+ * cover MMX as well; if an instruction is like
+ *
+ * por Pq, Qq
+ * 66 por Vx, Hx, Wx
+ *
+ * only the second row is included and the instruction is marked as a
+ * valid MMX instruction. The MMX flag directs the decoder to rewrite
+ * the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing
+ * "x" to "q" if there is no prefix.
+ *
+ * In addition, the ss/ps/sd/pd types are sometimes mushed together as "x"
+ * if the difference is expressed via prefixes. Individual instructions
+ * are separated by prefix in the generator functions.
+ *
+ * There are a couple cases in which instructions (e.g. MOVD) write the
+ * whole XMM or MM register but are established incorrectly in the manual
+ * as "d" or "q". These have to be fixed for the decoder to work correctly.
+ */
+
+#define X86_OP_NONE { 0 },
+
+#define X86_OP_GROUP3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
+ .decode = glue(decode_, op), \
+ .op0 = glue(X86_TYPE_, op0_), \
+ .s0 = glue(X86_SIZE_, s0_), \
+ .op1 = glue(X86_TYPE_, op1_), \
+ .s1 = glue(X86_SIZE_, s1_), \
+ .op2 = glue(X86_TYPE_, op2_), \
+ .s2 = glue(X86_SIZE_, s2_), \
+ .is_decode = true, \
+ ## __VA_ARGS__ \
+}
+
+#define X86_OP_GROUP0(op, ...) \
+ X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__)
+
+#define X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
+ .gen = glue(gen_, op), \
+ .op0 = glue(X86_TYPE_, op0_), \
+ .s0 = glue(X86_SIZE_, s0_), \
+ .op1 = glue(X86_TYPE_, op1_), \
+ .s1 = glue(X86_SIZE_, s1_), \
+ .op2 = glue(X86_TYPE_, op2_), \
+ .s2 = glue(X86_SIZE_, s2_), \
+ ## __VA_ARGS__ \
+}
+
+#define X86_OP_ENTRY4(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) \
+ X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, \
+ .op3 = X86_TYPE_I, .s3 = X86_SIZE_b, \
+ ## __VA_ARGS__)
+
+#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \
+ X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
+#define X86_OP_ENTRY0(op, ...) \
+ X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
+
+#define i64 .special = X86_SPECIAL_i64,
+#define o64 .special = X86_SPECIAL_o64,
+#define xchg .special = X86_SPECIAL_Locked,
+#define mmx .special = X86_SPECIAL_MMX,
+#define zext0 .special = X86_SPECIAL_ZExtOp0,
+#define zext2 .special = X86_SPECIAL_ZExtOp2,
+
+static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
+{
+ if (!s->has_modrm) {
+ s->modrm = x86_ldub_code(env, s);
+ s->has_modrm = true;
+ }
+ return s->modrm;
+}
+
+static const X86OpEntry opcodes_0F38_00toEF[240] = {
+};
+
+/* five rows for no prefix, 66, F3, F2, 66+F2 */
+static X86OpEntry opcodes_0F38_F0toFF[16][5] = {
+};
+
+static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ *b = x86_ldub_code(env, s);
+ if (*b < 0xf0) {
+ *entry = opcodes_0F38_00toEF[*b];
+ } else {
+ int row = 0;
+ if (s->prefix & PREFIX_REPZ) {
+ /* The REPZ (F3) prefix has priority over 66 */
+ row = 2;
+ } else {
+ row += s->prefix & PREFIX_REPNZ ? 3 : 0;
+ row += s->prefix & PREFIX_DATA ? 1 : 0;
+ }
+ *entry = opcodes_0F38_F0toFF[*b & 15][row];
+ }
+}
+
+static const X86OpEntry opcodes_0F3A[256] = {
+};
+
+static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ *b = x86_ldub_code(env, s);
+ *entry = opcodes_0F3A[*b];
+}
+
+static const X86OpEntry opcodes_0F[256] = {
+ [0x38] = X86_OP_GROUP0(0F38),
+ [0x3a] = X86_OP_GROUP0(0F3A),
+};
+
+static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ *entry = opcodes_0F[*b];
+}
+
+static void decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ *b = x86_ldub_code(env, s);
+ do_decode_0F(s, env, entry, b);
+}
+
+static const X86OpEntry opcodes_root[256] = {
+ [0x0F] = X86_OP_GROUP0(0F),
+};
+
+#undef mmx
+
+/*
+ * Decode the fixed part of the opcode and place the last
+ * in b.
+ */
+static void decode_root(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ *entry = opcodes_root[*b];
+}
+
+
+static int decode_modrm(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ X86DecodedOp *op, X86OpType type)
+{
+ int modrm = get_modrm(s, env);
+ if ((modrm >> 6) == 3) {
+ if (s->prefix & PREFIX_LOCK) {
+ decode->e.gen = gen_illegal;
+ return 0xff;
+ }
+ op->n = (modrm & 7);
+ if (type != X86_TYPE_Q && type != X86_TYPE_N) {
+ op->n |= REX_B(s);
+ }
+ } else {
+ op->has_ea = true;
+ op->n = -1;
+ decode->mem = gen_lea_modrm_0(env, s, get_modrm(s, env));
+ }
+ return modrm;
+}
+
+static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot)
+{
+ switch (size) {
+ case X86_SIZE_b: /* byte */
+ *ot = MO_8;
+ return true;
+
+ case X86_SIZE_d: /* 32-bit */
+ case X86_SIZE_ss: /* SSE/AVX scalar single precision */
+ *ot = MO_32;
+ return true;
+
+ case X86_SIZE_p: /* Far pointer, return offset size */
+ case X86_SIZE_s: /* Descriptor, return offset size */
+ case X86_SIZE_v: /* 16/32/64-bit, based on operand size */
+ *ot = s->dflag;
+ return true;
+
+ case X86_SIZE_pi: /* MMX */
+ case X86_SIZE_q: /* 64-bit */
+ case X86_SIZE_sd: /* SSE/AVX scalar double precision */
+ *ot = MO_64;
+ return true;
+
+ case X86_SIZE_w: /* 16-bit */
+ *ot = MO_16;
+ return true;
+
+ case X86_SIZE_y: /* 32/64-bit, based on operand size */
+ *ot = s->dflag == MO_16 ? MO_32 : s->dflag;
+ return true;
+
+ case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */
+ *ot = s->dflag == MO_16 ? MO_16 : MO_32;
+ return true;
+
+ case X86_SIZE_dq: /* SSE/AVX 128-bit */
+ if (e->special == X86_SPECIAL_MMX &&
+ !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
+ *ot = MO_64;
+ return true;
+ }
+ if (s->vex_l && e->s0 != X86_SIZE_qq) {
+ return false;
+ }
+ *ot = MO_128;
+ return true;
+
+ case X86_SIZE_qq: /* AVX 256-bit */
+ if (!s->vex_l) {
+ return false;
+ }
+ *ot = MO_256;
+ return true;
+
+ case X86_SIZE_x: /* 128/256-bit, based on operand size */
+ if (e->special == X86_SPECIAL_MMX &&
+ !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
+ *ot = MO_64;
+ return true;
+ }
+ /* fall through */
+ case X86_SIZE_ps: /* SSE/AVX packed single precision */
+ case X86_SIZE_pd: /* SSE/AVX packed double precision */
+ *ot = s->vex_l ? MO_256 : MO_128;
+ return true;
+
+ case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */
+ *ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag;
+ return true;
+
+ case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */
+ *ot = CODE64(s) ? MO_64 : s->dflag;
+ return true;
+
+ default:
+ *ot = -1;
+ return true;
+ }
+}
+
+static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ X86DecodedOp *op, X86OpType type, int b)
+{
+ int modrm;
+
+ switch (type) {
+ case X86_TYPE_A: /* Implicit */
+ case X86_TYPE_F: /* EFLAGS/RFLAGS */
+ break;
+
+ case X86_TYPE_B: /* VEX.vvvv selects a GPR */
+ op->unit = X86_OP_INT;
+ op->n = s->vex_v;
+ break;
+
+ case X86_TYPE_C: /* REG in the modrm byte selects a control register */
+ op->unit = X86_OP_CR;
+ goto get_reg;
+
+ case X86_TYPE_D: /* REG in the modrm byte selects a debug register */
+ op->unit = X86_OP_DR;
+ goto get_reg;
+
+ case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
+ op->unit = X86_OP_INT;
+ goto get_reg;
+
+ case X86_TYPE_S: /* reg selects a segment register */
+ op->unit = X86_OP_SEG;
+ goto get_reg;
+
+ goto get_reg;
+
+ case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */
+ if (decode->e.special == X86_SPECIAL_MMX &&
+ !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
+ case X86_TYPE_P: /* reg in the modrm byte selects an MMX register */
+ op->unit = X86_OP_MMX;
+ } else {
+ op->unit = X86_OP_SSE;
+ }
+ get_reg:
+ op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s);
+ break;
+
+ case X86_TYPE_E: /* ALU modrm operand */
+ op->unit = X86_OP_INT;
+ goto get_modrm;
+
+ case X86_TYPE_W: /* XMM/YMM modrm operand */
+ if (decode->e.special == X86_SPECIAL_MMX &&
+ !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
+ case X86_TYPE_Q: /* MMX modrm operand */
+ op->unit = X86_OP_MMX;
+ } else {
+ op->unit = X86_OP_SSE;
+ }
+ goto get_modrm;
+
+ case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */
+ if (decode->e.special == X86_SPECIAL_MMX &&
+ !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
+ case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */
+ op->unit = X86_OP_MMX;
+ } else {
+ op->unit = X86_OP_SSE;
+ }
+ goto get_modrm_reg;
+
+ case X86_TYPE_R: /* R/M in the modrm byte selects a register */
+ op->unit = X86_OP_INT;
+ get_modrm_reg:
+ modrm = get_modrm(s, env);
+ if ((modrm >> 6) != 3) {
+ return false;
+ }
+ goto get_modrm;
+
+ case X86_TYPE_M: /* modrm byte selects a memory operand */
+ modrm = get_modrm(s, env);
+ if ((modrm >> 6) == 3) {
+ return false;
+ }
+ get_modrm:
+ decode_modrm(s, env, decode, op, type);
+ break;
+
+ case X86_TYPE_O: /* Absolute address encoded in the instruction */
+ op->unit = X86_OP_INT;
+ op->has_ea = true;
+ op->n = -1;
+ decode->mem = (AddressParts) {
+ .def_seg = R_DS,
+ .base = -1,
+ .index = -1,
+ .disp = insn_get_addr(env, s, s->aflag)
+ };
+ break;
+
+ case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */
+ if ((s->prefix & PREFIX_VEX)) {
+ op->unit = X86_OP_SSE;
+ op->n = s->vex_v;
+ break;
+ e X86_TYPE_J: /* Relative offset for a jump */
+ op->unit = X86_OP_IMM;
+ decode->immediate = insn_get_signed(env, s, op->ot);
+ decode->immediate += s->pc - s->cs_base;
+ if (s->dflag == MO_16) {
+ decode->immediate &= 0xffff;
+ } else if (!CODE64(s)) {
+ decode->immediate &= 0xffffffffu;
+ }
+ break;
+
+ case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */
+ op->n = insn_get(env, s, op->ot) >> 4;
+ break;
+
+ case X86_TYPE_X: /* string source */
+ op->n = -1;
+ decode->mem = (AddressParts) {
+ .def_seg = R_DS,
+ .base = R_ESI,
+ .index = -1,
+ };
+ break;
+
+ case X86_TYPE_Y: /* string destination */
+ op->n = -1;
+ decode->mem = (AddressParts) {
+ .def_seg = R_ES,
+ .base = R_EDI,
+ .index = -1,
+ };
+ break;
+
+ case X86_TYPE_2op:
+ *op = decode->op[0];
+ break;
+
+ case X86_TYPE_LoBits:
+ op->n = (b & 7) | REX_B(s);
+ op->unit = X86_OP_INT;
+ break;
+
+ case X86_TYPE_0 ... X86_TYPE_7:
+ op->n = type - X86_TYPE_0;
+ op->unit = X86_OP_INT;
+ break;
+
+ case X86_TYPE_ES ... X86_TYPE_GS:
+ op->n = type - X86_TYPE_ES;
+ op->unit = X86_OP_SEG;
+ break;
+
+ default:
+ abort();
+ }
+
+ return true;
+}
+
+static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func,
+ X86DecodedInsn *decode)
+{
+ X86OpEntry *e = &decode->e;
+
+ decode_func(s, env, e, &decode->b);
+ while (e->is_decode) {
+ e->is_decode = false;
+ e->decode(s, env, e, &decode->b);
+ }
+
+ /* First compute size of operands in order to initialize s->rip_offset. */
+ if (e->op0 != X86_TYPE_None) {
+ if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
+ return false;
+ }
+ if (e->op0 == X86_TYPE_I) {
+ s->rip_offset += 1 << decode->op[0].ot;
+ }
+ }
+ if (e->op1 != X86_TYPE_None) {
+ if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) {
+ return false;
+ }
+ if (e->op1 == X86_TYPE_I) {
+ s->rip_offset += 1 << decode->op[1].ot;
+ }
+ }
+ if (e->op2 != X86_TYPE_None) {
+ if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) {
+ return false;
+ }
+ if (e->op2 == X86_TYPE_I) {
+ s->rip_offset += 1 << decode->op[2].ot;
+ }
+ }
+ if (e->op3 != X86_TYPE_None) {
+ assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
+ s->rip_offset += 1;
+ }
+
+ if (e->op0 != X86_TYPE_None &&
+ !decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) {
+ return false;
+ }
+
+ if (e->op1 != X86_TYPE_None &&
+ !decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) {
+ return false;
+ }
+
+ if (e->op2 != X86_TYPE_None &&
+ !decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) {
+ return false;
+ }
+
+ if (e->op3 != X86_TYPE_None) {
+ decode->immediate = insn_get_signed(env, s, MO_8);
+ }
+
+ return true;
+}
+
+/* convert one instruction. s->base.is_jmp is set if the translation must
+ be stopped. Return the next pc value */
+static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
+{
+ CPUX86State *env = cpu->env_ptr;
+ bool first = true;
+ X86DecodedInsn decode;
+ X86DecodeFunc decode_func = decode_root;
+
+#ifdef CONFIG_USER_ONLY
+ if (limit) { --limit; }
+#endif
+ s->has_modrm = false;
+#if 0
+ s->pc_start = s->pc = s->base.pc_next;
+ s->override = -1;
+#ifdef TARGET_X86_64
+ s->rex_w = false;
+ s->rex_r = 0;
+ s->rex_x = 0;
+ s->rex_b = 0;
+#endif
+ s->prefix = 0;
+ s->rip_offset = 0; /* for relative ip address */
+ s->vex_l = 0;
+ s->vex_v = 0;
+ if (sigsetjmp(s->jmpbuf, 0) != 0) {
+ gen_exception_gpf(s);
+ return s->pc;
+ }
+#endif
+
+ next_byte:
+ if (first) {
+ first = false;
+ } else {
+ b = x86_ldub_code(env, s);
+ }
+ /* Collect prefixes. */
+ switch (b) {
+ case 0xf3:
+ s->prefix |= PREFIX_REPZ;
+ s->prefix &= ~PREFIX_REPNZ;
+ goto next_byte;
+ case 0xf2:
+ s->prefix |= PREFIX_REPNZ;
+ s->prefix &= ~PREFIX_REPZ;
+ goto next_byte;
+ case 0xf0:
+ s->prefix |= PREFIX_LOCK;
+ goto next_byte;
+ case 0x2e:
+ s->override = R_CS;
+ goto next_byte;
+ case 0x36:
+ s->override = R_SS;
+ goto next_byte;
+ case 0x3e:
+ s->override = R_DS;
+ goto next_byte;
+ case 0x26:
+ s->override = R_ES;
+ goto next_byte;
+ case 0x64:
+ s->override = R_FS;
+ goto next_byte;
+ case 0x65:
+ s->override = R_GS;
+ goto next_byte;
+ case 0x66:
+ s->prefix |= PREFIX_DATA;
+ goto next_byte;
+ case 0x67:
+ s->prefix |= PREFIX_ADR;
+ goto next_byte;
+#ifdef TARGET_X86_64
+ case 0x40 ... 0x4f:
+ if (CODE64(s)) {
+ /* REX prefix */
+ s->prefix |= PREFIX_REX;
+ s->rex_w = (b >> 3) & 1;
+ s->rex_r = (b & 0x4) << 1;
+ s->rex_x = (b & 0x2) << 2;
+ s->rex_b = (b & 0x1) << 3;
+ goto next_byte;
+ }
+ break;
+#endif
+ case 0xc5: /* 2-byte VEX */
+ case 0xc4: /* 3-byte VEX */
+ /* VEX prefixes cannot be used except in 32-bit mode.
+ Otherwise the instruction is LES or LDS. */
+ if (CODE32(s) && !VM86(s)) {
+ static const int pp_prefix[4] = {
+ 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
+ };
+ int vex3, vex2 = x86_ldub_code(env, s);
+
+ if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
+ /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
+ otherwise the instruction is LES or LDS. */
+ s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
+ break;
+ }
+
+ /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
+ if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ
+ | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) {
+ goto illegal_op;
+ }
+#ifdef TARGET_X86_64
+ s->rex_r = (~vex2 >> 4) & 8;
+#endif
+ if (b == 0xc5) {
+ /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */
+ vex3 = vex2;
+ decode_func = decode_0F;
+ } else {
+ /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */
+ vex3 = x86_ldub_code(env, s);
+#ifdef TARGET_X86_64
+ s->rex_x = (~vex2 >> 3) & 8;
+ s->rex_b = (~vex2 >> 2) & 8;
+ s->rex_w = (vex3 >> 7) & 1;
+#endif
+ switch (vex2 & 0x1f) {
+ case 0x01: /* Implied 0f leading opcode bytes. */
+ decode_func = decode_0F;
+ break;
+ case 0x02: /* Implied 0f 38 leading opcode bytes. */
+ decode_func = decode_0F38;
+ break;
+ case 0x03: /* Implied 0f 3a leading opcode bytes. */
+ decode_func = decode_0F3A;
+ break;
+ default: /* Reserved for future use. */
+ goto unknown_op;
+ }
+ }
+ s->vex_v = (~vex3 >> 3) & 0xf;
+ s->vex_l = (vex3 >> 2) & 1;
+ s->prefix |= pp_prefix[vex3 & 3] | PREFIX_VEX;
+ }
+ break;
+ default:
+ if (b >= 0x100) {
+ b -= 0x100;
+ decode_func = do_decode_0F;
+ }
+ break;
+ }
+
+ /* Post-process prefixes. */
+ if (CODE64(s)) {
+ /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
+ data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
+ over 0x66 if both are present. */
+ s->dflag = (REX_W(s) ? MO_64 : s->prefix & PREFIX_DATA ? MO_16 : MO_32);
+ /* In 64-bit mode, 0x67 selects 32-bit addressing. */
+ s->aflag = (s->prefix & PREFIX_ADR ? MO_32 : MO_64);
+ } else {
+ /* In 16/32-bit mode, 0x66 selects the opposite data size. */
+ if (CODE32(s) ^ ((s->prefix & PREFIX_DATA) != 0)) {
+ s->dflag = MO_32;
+ } else {
+ s->dflag = MO_16;
+ }
+ /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
+ if (CODE32(s) ^ ((s->prefix & PREFIX_ADR) != 0)) {
+ s->aflag = MO_32;
+ } else {
+ s->aflag = MO_16;
+ }
+ }
+
+ memset(&decode, 0, sizeof(decode));
+ decode.b = b;
+ if (!decode_insn(s, env, decode_func, &decode)) {
+ goto illegal_op;
+ }
+ if (!decode.e.gen) {
+ goto unknown_op;
+ }
+
+ switch (decode.e.special) {
+ case X86_SPECIAL_None:
+ break;
+
+ case X86_SPECIAL_Locked:
+ if (decode.op[0].has_ea) {
+ s->prefix |= PREFIX_LOCK;
+ }
+ break;
+
+ case X86_SPECIAL_ProtMode:
+ if (!PE(s) || VM86(s)) {
+ goto illegal_op;
+ }
+ break;
+
+ case X86_SPECIAL_i64:
+ if (CODE64(s)) {
+ goto illegal_op;
+ }
+ break;
+ case X86_SPECIAL_o64:
+ if (!CODE64(s)) {
+ goto illegal_op;
+ }
+ break;
+
+ case X86_SPECIAL_ZExtOp0:
+ assert(decode.op[0].unit == X86_OP_INT);
+ if (!decode.op[0].has_ea) {
+ decode.op[0].ot = MO_32;
+ }
+ break;
+
+ case X86_SPECIAL_ZExtOp2:
+ assert(decode.op[2].unit == X86_OP_INT);
+ if (!decode.op[2].has_ea) {
+ decode.op[2].ot = MO_32;
+ }
+ break;
+
+ case X86_SPECIAL_MMX:
+ if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
+ gen_helper_enter_mmx(cpu_env);
+ }
+ break;
+ }
+
+ if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
+ gen_load_ea(s, &decode.mem);
+ }
+ decode.e.gen(s, env, &decode);
+ return s->pc;
+ illegal_op:
+ gen_illegal_opcode(s);
+ return s->pc;
+ unknown_op:
+ gen_unknown_opcode(env, s);
+ return s->pc;
+}
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
new file mode 100644
index 0000000000..fb44560aae
--- /dev/null
+++ b/target/i386/tcg/decode-new.h
@@ -0,0 +1,181 @@
+/*
+ * Decode table flags, mostly based on Intel SDM.
+ *
+ * Copyright (c) 2022 Red Hat, Inc.
+ *
+ * Author: Paolo Bonzini <pbonzini@redhat.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+typedef enum X86OpType {
+ X86_TYPE_None,
+
+ X86_TYPE_A, /* Implicit */
+ X86_TYPE_B, /* VEX.vvvv selects a GPR */
+ X86_TYPE_C, /* REG in the modrm byte selects a control register */
+ X86_TYPE_D, /* REG in the modrm byte selects a debug register */
+ X86_TYPE_E, /* ALU modrm operand */
+ X86_TYPE_F, /* EFLAGS/RFLAGS */
+ X86_TYPE_G, /* REG in the modrm byte selects a GPR */
+ X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */
+ X86_TYPE_I, /* Immediate */
+ X86_TYPE_J, /* Relative offset for a jump */
+ X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
+ X86_TYPE_M, /* modrm byte selects a memory operand */
+ X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */
+ X86_TYPE_O, /* Absolute address encoded in the instruction */
+ X86_TYPE_P, /* reg in the modrm byte selects an MMX register */
+ X86_TYPE_Q, /* MMX modrm operand */
+ X86_TYPE_R, /* R/M in the modrm byte selects a register */
+ X86_TYPE_S, /* reg selects a segment register */
+ X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */
+ X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */
+ X86_TYPE_W, /* XMM/YMM modrm operand */
+ X86_TYPE_X, /* string source */
+ X86_TYPE_Y, /* string destination */
+
+ /* Custom */
+ X86_TYPE_2op, /* 2-operand RMW instruction */
+ X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
+ X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
+ X86_TYPE_1,
+ X86_TYPE_2,
+ X86_TYPE_3,
+ X86_TYPE_4,
+ X86_TYPE_5,
+ X86_TYPE_6,
+ X86_TYPE_7,
+ X86_TYPE_ES, /* Hard-coded segment registers */
+ X86_TYPE_CS,
+ X86_TYPE_SS,
+ X86_TYPE_DS,
+ X86_TYPE_FS,
+ X86_TYPE_GS,
+} X86OpType;
+
+typedef enum X86OpSize {
+ X86_SIZE_None,
+
+ X86_SIZE_a, /* BOUND operand */
+ X86_SIZE_b, /* byte */
+ X86_SIZE_d, /* 32-bit */
+ X86_SIZE_dq, /* SSE/AVX 128-bit */
+ X86_SIZE_p, /* Far pointer */
+ X86_SIZE_pd, /* SSE/AVX packed double precision */
+ X86_SIZE_pi, /* MMX */
+ X86_SIZE_ps, /* SSE/AVX packed single precision */
+ X86_SIZE_q, /* 64-bit */
+ X86_SIZE_qq, /* AVX 256-bit */
+ X86_SIZE_s, /* Descriptor */
+ X86_SIZE_sd, /* SSE/AVX scalar double precision */
+ X86_SIZE_ss, /* SSE/AVX scalar single precision */
+ X86_SIZE_si, /* 32-bit GPR */
+ X86_SIZE_v, /* 16/32/64-bit, based on operand size */
+ X86_SIZE_w, /* 16-bit */
+ X86_SIZE_x, /* 128/256-bit, based on operand size */
+ X86_SIZE_y, /* 32/64-bit, based on operand size */
+ X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */
+
+ /* Custom */
+ X86_SIZE_d64,
+ X86_SIZE_f64,
+} X86OpSize;
+
+/* Execution flags */
+
+typedef enum X86OpUnit {
+ X86_OP_SKIP, /* not valid or managed by emission function */
+ X86_OP_SEG, /* segment selector */
+ X86_OP_CR, /* control register */
+ X86_OP_DR, /* debug register */
+ X86_OP_INT, /* loaded into/stored from s->T0/T1 */
+ X86_OP_IMM, /* immediate */
+ X86_OP_SSE, /* address in either s->ptrX or s->A0 depending on has_ea */
+ X86_OP_MMX, /* address in either s->ptrX or s->A0 depending on has_ea */
+} X86OpUnit;
+
+typedef enum X86InsnSpecial {
+ X86_SPECIAL_None,
+
+ /* Always locked if it has a memory operand (XCHG) */
+ X86_SPECIAL_Locked,
+
+ /* Fault outside protected mode */
+ X86_SPECIAL_ProtMode,
+
+ /*
+ * Register operand 0/2 is zero extended to 32 bits. Rd/Mb or Rd/Mw
+ * in the manual.
+ */
+ X86_SPECIAL_ZExtOp0,
+ X86_SPECIAL_ZExtOp2,
+
+ /*
+ * MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands
+ * become P/P/Q/N, and size "x" becomes "q".
+ */
+ X86_SPECIAL_MMX,
+
+ /* Illegal or exclusive to 64-bit mode */
+ X86_SPECIAL_i64,
+ X86_SPECIAL_o64,
+} X86InsnSpecial;
+
+typedef struct X86OpEntry X86OpEntry;
+typedef struct X86DecodedInsn X86DecodedInsn;
+
+/* Decode function for multibyte opcodes. */
+typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b);
+
+/* Code generation function. */
+typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env,nSpecial special : 8;
+ bool is_decode : 1;
+};
+
+typedef struct X86DecodedOp {
+ int8_t n;
+ MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */
+ X86OpUnit unit;
+ bool has_ea;
+} X86DecodedOp;
+
+struct X86DecodedInsn {
+ X86OpEntry e;
+ X86DecodedOp op[3];
+ target_ulong immediate;
+ AddressParts mem;
+
+ uint8_t b;
+};
+
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
new file mode 100644
index 0000000000..e86364ffc1
--- /dev/null
+++ b/target/i386/tcg/emit.c.inc
@@ -0,0 +1,31 @@
+/*
+ * New-style TCG opcode generator for i386 instructions
+ *
+ * Copyright (c) 2022 Red Hat, Inc.
+ *
+ * Author: Paolo Bonzini <pbonzini@redhat.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static void gen_illegal(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_illegal_opcode(s);
+}
+
+static void gen_load_ea(DisasContext *s, AddressParts *mem)
+{
+ TCGv ea = gen_lea_modrm_1(s, *mem);
+ gen_lea_v_seg(s, s->aflag, ea, mem->def_seg, s->override);
+}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index f1aa830fcc..f66bf2ac79 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -85,6 +85,9 @@ typedef struct DisasContext {
int8_t override; /* -1 if no override, else R_CS, R_DS, etc */
uint8_t prefix;
+ bool has_modrm;
+ uint8_t modrm;
+
#ifndef CONFIG_USER_ONLY
uint8_t cpl; /* code priv level */
uint8_t iopl; /* i/o priv level */
@@ -2356,6 +2359,31 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)
return ret;
}
+static inline target_long insn_get_signed(CPUX86State *env, DisasContext *s, MemOp ot)
+{
+ target_long ret;
+
+ switch (ot) {
+ case MO_8:
+ ret = (int8_t) x86_ldub_code(env, s);
+ break;
+ case MO_16:
+ ret = (int16_t) x86_lduw_code(env, s);
+ break;
+ case MO_32:
+ ret = (int32_t) x86_ldl_code(env, s);
+ break;
+#ifdef TARGET_X86_64
+ case MO_64:
+ ret = x86_ldq_code(env, s);
+ break;
+#endif
+ default:
+ tcg_abort();
+ }
+ return ret;
+}
+
static inline int insn_const_size(MemOp ot)
{
if (ot <= MO_32) {
@@ -2845,6 +2873,11 @@ typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
TCGv val);
+static bool first = true; static unsigned long limit;
+#include "decode-new.h"
+#include "emit.c.inc"
+#include "decode-new.c.inc"
+
#define SSE_OPF_CMP (1 << 1) /* does not write for first operand */
#define SSE_OPF_SPECIAL (1 << 3) /* magic */
#define SSE_OPF_3DNOW (1 << 4) /* 3DNow! instruction */
@@ -4756,10 +4789,33 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
prefixes = 0;
+ if (first) first = false, limit = getenv("LIMIT") ? atol(getenv("LIMIT")) : -1;
+ bool use_new = true;
+#ifdef CONFIG_USER_ONLY
+ use_new &= limit > 0;
+#endif
next_byte:
+ s->prefix = prefixes;
b = x86_ldub_code(env, s);
/* Collect prefixes. */
switch (b) {
+ default:
+#ifndef CONFIG_USER_ONLY
+ use_new &= b <= limit;
+#endif
+ if (use_new && 0) {
+ return disas_insn_new(s, cpu, b);
+ }
+ break;
+ case 0x0f:
+ b = x86_ldub_code(env, s) + 0x100;
+#ifndef CONFIG_USER_ONLY
+ use_new &= b <= limit;
+#endif
+ if (use_new && 0) {
+ return disas_insn_new(s, cpu, b + 0x100);
+ }
+ break;
case 0xf3:
prefixes |= PREFIX_REPZ;
prefixes &= ~PREFIX_REPNZ;
@@ -4810,6 +4866,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#endif
case 0xc5: /* 2-byte VEX */
case 0xc4: /* 3-byte VEX */
+ use_new = false;
/* VEX prefixes cannot be used except in 32-bit mode.
Otherwise the instruction is LES or LDS. */
if (CODE32(s) && !VM86(s)) {
@@ -4894,14 +4951,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
s->dflag = dflag;
/* now check op code */
- reswitch:
switch(b) {
- case 0x0f:
- /**************************/
- /* extended op code */
- b = x86_ldub_code(env, s) | 0x100;
- goto reswitch;
-
/**************************/
/* arith & logic */
case 0x00 ... 0x05:
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 05/37] target/i386: add core of new i386 decoder
2022-09-11 23:03 ` [PATCH 05/37] target/i386: add core of new i386 decoder Paolo Bonzini
@ 2022-09-12 9:27 ` Richard Henderson
2022-09-12 10:54 ` Richard Henderson
1 sibling, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 9:27 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> + case X86_TYPE_B: /* VEX.vvvv selects a GPR */
> + op->unit = X86_OP_INT;
> + op->n = s->vex_v;
> + break;
Could use a comment for where missing vex prefix is diagnosed.
I guess it's one of the "vexN" group markers in the insn table?
> + case X86_TYPE_S: /* reg selects a segment register */
> + op->unit = X86_OP_SEG;
> + goto get_reg;
> +
> + goto get_reg;
Stray goto.
> +
> + case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */
> + if (decode->e.special == X86_SPECIAL_MMX &&
> + !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
> + case X86_TYPE_P: /* reg in the modrm byte selects an MMX register */
> + op->unit = X86_OP_MMX;
> + } else {
> + op->unit = X86_OP_SSE;
> + }
> + get_reg:
Nesting P into the if works, but it's ugly.
Better to separate it out as
case X86_TYPE_P:
op->unit = X86_OP_MMX;
goto get_reg;
> + case X86_TYPE_W: /* XMM/YMM modrm operand */
> + if (decode->e.special == X86_SPECIAL_MMX &&
> + !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
> + case X86_TYPE_Q: /* MMX modrm operand */
> + op->unit = X86_OP_MMX;
> + } else {
> + op->unit = X86_OP_SSE;
> + }
> + goto get_modrm;
Likewise.
> + case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */
> + if (decode->e.special == X86_SPECIAL_MMX &&
> + !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
> + case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */
> + op->unit = X86_OP_MMX;
> + } else {
> + op->unit = X86_OP_SSE;
> + }
> + goto get_modrm_reg;
Likewise.
> + case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */
> + if ((s->prefix & PREFIX_VEX)) {
> + op->unit = X86_OP_SSE;
> + op->n = s->vex_v;
> + break;
Similar to X86_TYPE_B, should this diagnose error if missing VEX?
> + e X86_TYPE_J: /* Relative offset for a jump */
> + op->unit = X86_OP_IMM;
> + decode->immediate = insn_get_signed(env, s, op->ot);
Mailer damage?
> + decode->immediate += s->pc - s->cs_base;
Please consider
https://lore.kernel.org/qemu-devel/20220906100932.343523-1-richard.henderson@linaro.org/
or at least the first half of the patch set, which rationalizes and consolidates the
handing of s->cs_base.
> + default:
> + abort();
g_assert_not_reached().
> +static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func,
> + X86DecodedInsn *decode)
> +{
> + X86OpEntry *e = &decode->e;
> +
> + decode_func(s, env, e, &decode->b);
> + while (e->is_decode) {
> + e->is_decode = false;
> + e->decode(s, env, e, &decode->b);
> + }
> +
> + /* First compute size of operands in order to initialize s->rip_offset. */
> + if (e->op0 != X86_TYPE_None) {
> + if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
> + return false;
> + }
> + if (e->op0 == X86_TYPE_I) {
> + s->rip_offset += 1 << decode->op[0].ot;
> + }
> + }
> + if (e->op1 != X86_TYPE_None) {
> + if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) {
> + return false;
> + }
> + if (e->op1 == X86_TYPE_I) {
> + s->rip_offset += 1 << decode->op[1].ot;
> + }
> + }
> + if (e->op2 != X86_TYPE_None) {
> + if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) {
> + return false;
> + }
> + if (e->op2 == X86_TYPE_I) {
> + s->rip_offset += 1 << decode->op[2].ot;
> + }
> + }
> + if (e->op3 != X86_TYPE_None) {
> + assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
> + s->rip_offset += 1;
> + }
> +
> + if (e->op0 != X86_TYPE_None &&
> + !decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) {
> + return false;
> + }
> +
> + if (e->op1 != X86_TYPE_None &&
> + !decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) {
> + return false;
> + }
> +
> + if (e->op2 != X86_TYPE_None &&
> + !decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) {
> + return false;
> + }
> +
> + if (e->op3 != X86_TYPE_None) {
> + decode->immediate = insn_get_signed(env, s, MO_8);
> + }
> +
> + return true;
> +}
> +
> +/* convert one instruction. s->base.is_jmp is set if the translation must
> + be stopped. Return the next pc value */
> +static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
Note patch 2 from the cs_base cleanup above changes the return type from disas_insn to bool.
> +{
> + CPUX86State *env = cpu->env_ptr;
> + bool first = true;
> + X86DecodedInsn decode;
> + X86DecodeFunc decode_func = decode_root;
> +
> +#ifdef CONFIG_USER_ONLY
> + if (limit) { --limit; }
> +#endif
> + s->has_modrm = false;
> +#if 0
> + s->pc_start = s->pc = s->base.pc_next;
> + s->override = -1;
> +#ifdef TARGET_X86_64
> + s->rex_w = false;
> + s->rex_r = 0;
> + s->rex_x = 0;
> + s->rex_b = 0;
> +#endif
> + s->prefix = 0;
> + s->rip_offset = 0; /* for relative ip address */
> + s->vex_l = 0;
> + s->vex_v = 0;
> + if (sigsetjmp(s->jmpbuf, 0) != 0) {
> + gen_exception_gpf(s);
> + return s->pc;
> + }
Mainline has two longjmp error paths:
(1) insn too long: raise #GP,
(2) insn crosses page boundary, and isn't first in the TB:
undo processing and defer insn to next TB.
> +static inline target_long insn_get_signed(CPUX86State *env, DisasContext *s, MemOp ot)
No need for inline.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 05/37] target/i386: add core of new i386 decoder
2022-09-11 23:03 ` [PATCH 05/37] target/i386: add core of new i386 decoder Paolo Bonzini
2022-09-12 9:27 ` Richard Henderson
@ 2022-09-12 10:54 ` Richard Henderson
1 sibling, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 10:54 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> +/* five rows for no prefix, 66, F3, F2, 66+F2 */
> +static X86OpEntry opcodes_0F38_F0toFF[16][5] = {
const.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 06/37] target/i386: add ALU load/writeback core
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (4 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 05/37] target/i386: add core of new i386 decoder Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 10:02 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext Paolo Bonzini
` (30 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Add generic code generation that takes care of preparing operands
around calls to decode.e.gen in a table-driven manner, so that ALU
operations need not take care of that.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 20 +++-
target/i386/tcg/decode-new.h | 1 +
target/i386/tcg/emit.c.inc | 152 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 24 +++++
4 files changed, 195 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index de8ef51a2d..7f76051b2d 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -228,7 +228,7 @@ static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp
*ot = MO_64;
return true;
}
- if (s->vex_l && e->s0 != X86_SIZE_qq) {
+ if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) {
return false;
}
*ot = MO_128;
@@ -741,7 +741,23 @@ static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
gen_load_ea(s, &decode.mem);
}
- decode.e.gen(s, env, &decode);
+ if (s->prefix & PREFIX_LOCK) {
+ if (decode.op[0].unit != X86_OP_INT || !decode.op[0].has_ea) {
+ goto illegal_op;
+ }
+ gen_load(s, s->T1, NULL, &decode.op[2], decode.immediate);
+ decode.e.gen(s, env, &decode);
+ } else {
+ if (decode.op[0].unit == X86_OP_MMX) {
+ gen_mmx_offset(s->ptr0, &decode.op[0]);
+ } else if (decode.op[0].unit == X86_OP_SSE) {
+ gen_xmm_offset(s->ptr0, &decode.op[0]);
+ }
+ gen_load(s, s->T0, s->ptr1, &decode.op[1], decode.immediate);
+ gen_load(s, s->T1, s->ptr2, &decode.op[2], decode.immediate);
+ decode.e.gen(s, env, &decode);
+ gen_writeback(s, &decode.op[0]);
+ }
return s->pc;
illegal_op:
gen_illegal_opcode(s);
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index fb44560aae..a2d3c3867f 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -168,6 +168,7 @@ typedef struct X86DecodedOp {
MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */
X86OpUnit unit;
bool has_ea;
+ int offset; /* For MMX and SSE */
} X86DecodedOp;
struct X86DecodedInsn {
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index e86364ffc1..6fa0062d6a 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -29,3 +29,155 @@ static void gen_load_ea(DisasContext *s, AddressParts *mem)
TCGv ea = gen_lea_modrm_1(s, *mem);
gen_lea_v_seg(s, s->aflag, ea, mem->def_seg, s->override);
}
+
+static void gen_mmx_offset(TCGv_ptr ptr, X86DecodedOp *op)
+{
+ if (!op->has_ea) {
+ op->offset = offsetof(CPUX86State, fpregs[op->n].mmx);
+ } else {
+ op->offset = offsetof(CPUX86State, mmx_t0);
+ }
+ tcg_gen_addi_ptr(ptr, cpu_env, op->offset);
+
+ /*
+ * ptr is for passing to helpers, and points to the MMXReg; op->offset
+ * is for TCG ops and points to the operand.
+ */
+ if (op->ot == MO_32) {
+ op->offset += offsetof(MMXReg, MMX_L(0));
+ }
+}
+
+static int xmm_offset(MemOp ot)
+{
+ if (ot == MO_8) {
+ return offsetof(ZMMReg, ZMM_B(0));
+ } else if (ot == MO_16) {
+ return offsetof(ZMMReg, ZMM_W(0));
+ } else if (ot == MO_32) {
+ return offsetof(ZMMReg, ZMM_L(0));
+ } else if (ot == MO_64) {
+ return offsetof(ZMMReg, ZMM_Q(0));
+ } else if (ot == MO_128) {
+ return offsetof(ZMMReg, ZMM_X(0));
+ } else if (ot == MO_256) {
+ return offsetof(ZMMReg, ZMM_Y(0));
+ } else {
+ abort();
+ }
+}
+
+static void gen_xmm_offset(TCGv_ptr ptr, X86DecodedOp *op)
+{
+ if (!op->has_ea) {
+ op->offset = ZMM_OFFSET(op->n);
+ } else {
+ op->offset = offsetof(CPUX86State, xmm_t0);
+ }
+ /*
+ * ptr is for passing to helpers, and points to the ZMMReg; op->offset
+ * is for TCG ops (especially gvec) and points to the base of the vector.
+ */
+ tcg_gen_addi_ptr(ptr, cpu_env, op->offset);
+ op->offset += xmm_offset(op->ot);
+}
+
+static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs)
+{
+ if (ot == MO_8) {
+ gen_op_ld_v(s, MO_8, temp, s->A0);
+ tcg_gen_st8_tl(temp, cpu_env, dest_ofs);
+ } else if (ot == MO_16) {
+ gen_op_ld_v(s, MO_16, temp, s->A0);
+ tcg_gen_st16_tl(temp, cpu_env, dest_ofs);
+ } else if (ot == MO_32) {
+ gen_op_ld_v(s, MO_32, temp, s->A0);
+ tcg_gen_st32_tl(temp, cpu_env, dest_ofs);
+ } else if (ot == MO_64) {
+ gen_ldq_env_A0(s, dest_ofs);
+ } else if (ot == MO_128) {
+ gen_ldo_env_A0(s, dest_ofs);
+ } else if (ot == MO_256) {
+ gen_ldy_env_A0(s, dest_ofs);
+ }
+}
+
+static void gen_load(DisasContext *s, TCGv v, TCGv_ptr ptr, X86DecodedOp *op, uint64_t imm)
+{
+ switch (op->unit) {
+ case X86_OP_SKIP:
+ return;
+ case X86_OP_SEG:
+ tcg_gen_ld32u_tl(v, cpu_env,
+ offsetof(CPUX86State,segs[op->n].selector));
+ break;
+ case X86_OP_CR:
+ tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, cr[op->n]));
+ break;
+ case X86_OP_DR:
+ tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, dr[op->n]));
+ break;
+ case X86_OP_INT:
+ if (op->has_ea) {
+ gen_op_ld_v(s, op->ot, v, s->A0);
+ } else {
+ gen_op_mov_v_reg(s, op->ot, v, op->n);
+ }
+ break;
+ case X86_OP_IMM:
+ tcg_gen_movi_tl(v, imm);
+ break;
+
+ case X86_OP_MMX:
+ gen_mmx_offset(ptr, op);
+ goto load_vector;
+
+ case X86_OP_SSE:
+ gen_xmm_offset(ptr, op);
+ load_vector:
+ if (op->has_ea) {
+ gen_load_sse(s, v, op->ot, op->offset);
+ }
+ break;
+
+ default:
+ abort();
+ }
+}
+
+static void gen_writeback(DisasContext *s, X86DecodedOp *op)
+{
+ switch (op->unit) {
+ case X86_OP_SKIP:
+ break;
+ case X86_OP_SEG:
+ /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */
+ gen_movl_seg_T0(s, op->n);
+ if (s->base.is_jmp) {
+ gen_jmp_im(s, s->pc - s->cs_base);
+ if (op->n == R_SS) {
+ s->flags &= ~HF_TF_MASK;
+ gen_eob_inhibit_irq(s, true);
+ } else {
+ gen_eob(s);
+ }
+ }
+ break;
+ case X86_OP_CR:
+ case X86_OP_DR:
+ /* TBD */
+ break;
+ case X86_OP_INT:
+ if (op->has_ea) {
+ gen_op_st_v(s, op->ot, s->T0, s->A0);
+ } else {
+ gen_op_mov_reg_v(s, op->ot, op->n, s->T0);
+ }
+ break;
+ case X86_OP_MMX:
+ case X86_OP_SSE:
+ break;
+ default:
+ abort();
+ }
+}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index f66bf2ac79..7e9920e29c 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2831,6 +2831,30 @@ static inline void gen_sto_env_A0(DisasContext *s, int offset)
tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
}
+static inline void gen_ldy_env_A0(DisasContext *s, int offset)
+{
+ int mem_index = s->mem_index;
+ gen_ldo_env_A0(s, offset);
+ tcg_gen_addi_tl(s->tmp0, s->A0, 16);
+ tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(2)));
+ tcg_gen_addi_tl(s->tmp0, s->A0, 24);
+ tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(3)));
+}
+
+static inline void gen_sty_env_A0(DisasContext *s, int offset)
+{
+ int mem_index = s->mem_index;
+ gen_sto_env_A0(s, offset);
+ tcg_gen_addi_tl(s->tmp0, s->A0, 16);
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(2)));
+ tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
+ tcg_gen_addi_tl(s->tmp0, s->A0, 24);
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(3)));
+ tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
+}
+
static inline void gen_op_movo(DisasContext *s, int d_offset, int s_offset)
{
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, s_offset + offsetof(XMMReg, XMM_Q(0)));
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 06/37] target/i386: add ALU load/writeback core
2022-09-11 23:03 ` [PATCH 06/37] target/i386: add ALU load/writeback core Paolo Bonzini
@ 2022-09-12 10:02 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 10:02 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> Add generic code generation that takes care of preparing operands
> around calls to decode.e.gen in a table-driven manner, so that ALU
> operations need not take care of that.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 20 +++-
> target/i386/tcg/decode-new.h | 1 +
> target/i386/tcg/emit.c.inc | 152 +++++++++++++++++++++++++++++++
> target/i386/tcg/translate.c | 24 +++++
> 4 files changed, 195 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
> index de8ef51a2d..7f76051b2d 100644
> --- a/target/i386/tcg/decode-new.c.inc
> +++ b/target/i386/tcg/decode-new.c.inc
> @@ -228,7 +228,7 @@ static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp
> *ot = MO_64;
> return true;
> }
> - if (s->vex_l && e->s0 != X86_SIZE_qq) {
> + if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) {
> return false;
> }
Squash back?
> diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
> index e86364ffc1..6fa0062d6a 100644
> --- a/target/i386/tcg/emit.c.inc
> +++ b/target/i386/tcg/emit.c.inc
> @@ -29,3 +29,155 @@ static void gen_load_ea(DisasContext *s, AddressParts *mem)
> TCGv ea = gen_lea_modrm_1(s, *mem);
> gen_lea_v_seg(s, s->aflag, ea, mem->def_seg, s->override);
> }
> +
> +static void gen_mmx_offset(TCGv_ptr ptr, X86DecodedOp *op)
> +{
> + if (!op->has_ea) {
> + op->offset = offsetof(CPUX86State, fpregs[op->n].mmx);
> + } else {
> + op->offset = offsetof(CPUX86State, mmx_t0);
> + }
> + tcg_gen_addi_ptr(ptr, cpu_env, op->offset);
It's a shame to generate this so early, when you don't know if you'll need it. Better to
build these in the gen_binary_int_sse helper, immediately before they're required?
> +
> + /*
> + * ptr is for passing to helpers, and points to the MMXReg; op->offset
> + * is for TCG ops and points to the operand.
> + */
> + if (op->ot == MO_32) {
> + op->offset += offsetof(MMXReg, MMX_L(0));
> + }
I guess you'd need an op->offset_base if you do the above...
Switch and g_assert_not_reached on invalid ot?
> +static int xmm_offset(MemOp ot)
> +{
> + if (ot == MO_8) {
> + return offsetof(ZMMReg, ZMM_B(0));
> + } else if (ot == MO_16) {
> + return offsetof(ZMMReg, ZMM_W(0));
> + } else if (ot == MO_32) {
> + return offsetof(ZMMReg, ZMM_L(0));
> + } else if (ot == MO_64) {
> + return offsetof(ZMMReg, ZMM_Q(0));
> + } else if (ot == MO_128) {
> + return offsetof(ZMMReg, ZMM_X(0));
> + } else if (ot == MO_256) {
> + return offsetof(ZMMReg, ZMM_Y(0));
> + } else {
> + abort();
Switch, g_assert_not_reached().
> +static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs)
> +{
> + if (ot == MO_8) {
> + gen_op_ld_v(s, MO_8, temp, s->A0);
> + tcg_gen_st8_tl(temp, cpu_env, dest_ofs);
> + } else if (ot == MO_16) {
> + gen_op_ld_v(s, MO_16, temp, s->A0);
> + tcg_gen_st16_tl(temp, cpu_env, dest_ofs);
> + } else if (ot == MO_32) {
> + gen_op_ld_v(s, MO_32, temp, s->A0);
> + tcg_gen_st32_tl(temp, cpu_env, dest_ofs);
> + } else if (ot == MO_64) {
> + gen_ldq_env_A0(s, dest_ofs);
> + } else if (ot == MO_128) {
> + gen_ldo_env_A0(s, dest_ofs);
> + } else if (ot == MO_256) {
> + gen_ldy_env_A0(s, dest_ofs);
> + }
Likewise.
> +static void gen_writeback(DisasContext *s, X86DecodedOp *op)
> +{
> + switch (op->unit) {
> + case X86_OP_SKIP:
> + break;
> + case X86_OP_SEG:
> + /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */
> + gen_movl_seg_T0(s, op->n);
> + if (s->base.is_jmp) {
> + gen_jmp_im(s, s->pc - s->cs_base);
> + if (op->n == R_SS) {
> + s->flags &= ~HF_TF_MASK;
> + gen_eob_inhibit_irq(s, true);
> + } else {
> + gen_eob(s);
> + }
> + }
> + break;
> + case X86_OP_CR:
> + case X86_OP_DR:
> + /* TBD */
> + break;
Leave these adjacent with default abort until needed?
> + default:
> + abort();
> + }
g_assert_not_reached.
> +static inline void gen_ldy_env_A0(DisasContext *s, int offset)
> +{
> + int mem_index = s->mem_index;
> + gen_ldo_env_A0(s, offset);
> + tcg_gen_addi_tl(s->tmp0, s->A0, 16);
> + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(2)));
> + tcg_gen_addi_tl(s->tmp0, s->A0, 24);
> + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(3)));
> +}
> +
> +static inline void gen_sty_env_A0(DisasContext *s, int offset)
> +{
> + int mem_index = s->mem_index;
> + gen_sto_env_A0(s, offset);
> + tcg_gen_addi_tl(s->tmp0, s->A0, 16);
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(2)));
> + tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
> + tcg_gen_addi_tl(s->tmp0, s->A0, 24);
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(3)));
> + tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
> +}
No need for inline markers.
Note that there's an outstanding patch set that enforces alignment restrictions (for
ldy/sty it would only be for vmovdqa etc):
https://lore.kernel.org/qemu-devel/20220830034816.57091-2-ricky@rzhou.org/
but it's definitely something that ought to build into the new decoder from the start.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (5 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 06/37] target/i386: add ALU load/writeback core Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 10:02 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 08/37] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
` (29 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
TCG will shortly implement VAES instructions, so add the relevant feature
word to the DisasContext.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 7e9920e29c..a92ef61527 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -115,6 +115,7 @@ typedef struct DisasContext {
int cpuid_ext2_features;
int cpuid_ext3_features;
int cpuid_7_0_ebx_features;
+ int cpuid_7_0_ecx_features;
int cpuid_xsave_features;
/* TCG local temps */
@@ -8860,6 +8861,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
+ dc->cpuid_7_0_ecx_features = env->features[FEAT_7_0_ECX];
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* [PATCH 08/37] target/i386: add CPUID feature checks to new decoder
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (6 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 10:05 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 09/37] target/i386: add AVX_EN hflag Paolo Bonzini
` (28 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 51 ++++++++++++++++++++++++++++++++
target/i386/tcg/decode-new.h | 20 +++++++++++++
2 files changed, 71 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 7f76051b2d..a9b8b6c05f 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -83,6 +83,7 @@
#define X86_OP_ENTRY0(op, ...) \
X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
+#define cpuid(feat) .cpuid = X86_FEAT_##feat,
#define i64 .special = X86_SPECIAL_i64,
#define o64 .special = X86_SPECIAL_o64,
#define xchg .special = X86_SPECIAL_Locked,
@@ -506,6 +507,52 @@ static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_
return true;
}
+static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
+{
+ switch (cpuid) {
+ case X86_FEAT_None:
+ return true;
+ case X86_FEAT_MOVBE:
+ return (s->cpuid_ext_features & CPUID_EXT_MOVBE);
+ case X86_FEAT_PCLMULQDQ:
+ return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ);
+ case X86_FEAT_SSE:
+ return (s->cpuid_ext_features & CPUID_SSE);
+ case X86_FEAT_SSE2:
+ return (s->cpuid_ext_features & CPUID_SSE2);
+ case X86_FEAT_SSE3:
+ return (s->cpuid_ext_features & CPUID_EXT_SSE3);
+ case X86_FEAT_SSSE3:
+ return (s->cpuid_ext_features & CPUID_EXT_SSSE3);
+ case X86_FEAT_SSE41:
+ return (s->cpuid_ext_features & CPUID_EXT_SSE41);
+ case X86_FEAT_SSE42:
+ return (s->cpuid_ext_features & CPUID_EXT_SSE42);
+ case X86_FEAT_AES:
+ if (s->vex_l) {
+ return (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES);
+ } else {
+ return (s->cpuid_ext_features & CPUID_EXT_AES);
+ }
+ case X86_FEAT_AVX:
+ return (s->cpuid_ext_features & CPUID_EXT_AVX);
+
+ case X86_FEAT_SSE4A:
+ return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A);
+
+ case X86_FEAT_ADX:
+ return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX);
+ case X86_FEAT_BMI1:
+ return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1);
+ case X86_FEAT_BMI2:
+ return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2);
+ case X86_FEAT_AVX2:
+ return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2);
+ default:
+ abort();
+ }
+}
+
/* convert one instruction. s->base.is_jmp is set if the translation must
be stopped. Return the next pc value */
static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
@@ -690,6 +737,10 @@ static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
goto unknown_op;
}
+ if (!has_cpuid_feature(s, decode.e.cpuid)) {
+ goto illegal_op;
+ }
+
switch (decode.e.special) {
case X86_SPECIAL_None:
break;
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index a2d3c3867f..6fb2d9151e 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -93,6 +93,25 @@ typedef enum X86OpSize {
X86_SIZE_f64,
} X86OpSize;
+typedef enum X86CPUIDFeature {
+ X86_FEAT_None,
+ X86_FEAT_ADX,
+ X86_FEAT_AES,
+ X86_FEAT_AVX,
+ X86_FEAT_AVX2,
+ X86_FEAT_BMI1,
+ X86_FEAT_BMI2,
+ X86_FEAT_MOVBE,
+ X86_FEAT_PCLMULQDQ,
+ X86_FEAT_SSE,
+ X86_FEAT_SSE2,
+ X86_FEAT_SSE3,
+ X86_FEAT_SSSE3,
+ X86_FEAT_SSE41,
+ X86_FEAT_SSE42,
+ X86_FEAT_SSE4A,
+} X86CPUIDFeature;
+
/* Execution flags */
typedef enum X86OpUnit {
@@ -160,6 +179,7 @@ struct X86OpEntry {
X86OpSize s3 : 8;
X86InsnSpecial special : 8;
+ X86CPUIDFeature cpuid : 8;
bool is_decode : 1;
};
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 08/37] target/i386: add CPUID feature checks to new decoder
2022-09-11 23:03 ` [PATCH 08/37] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
@ 2022-09-12 10:05 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 10:05 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 51 ++++++++++++++++++++++++++++++++
> target/i386/tcg/decode-new.h | 20 +++++++++++++
> 2 files changed, 71 insertions(+)
>
> diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
> index 7f76051b2d..a9b8b6c05f 100644
> --- a/target/i386/tcg/decode-new.c.inc
> +++ b/target/i386/tcg/decode-new.c.inc
> @@ -83,6 +83,7 @@
> #define X86_OP_ENTRY0(op, ...) \
> X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
>
> +#define cpuid(feat) .cpuid = X86_FEAT_##feat,
> #define i64 .special = X86_SPECIAL_i64,
> #define o64 .special = X86_SPECIAL_o64,
> #define xchg .special = X86_SPECIAL_Locked,
> @@ -506,6 +507,52 @@ static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_
> return true;
> }
>
> +static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
> +{
> + switch (cpuid) {
> + case X86_FEAT_None:
> + return true;
> + case X86_FEAT_MOVBE:
> + return (s->cpuid_ext_features & CPUID_EXT_MOVBE);
> + case X86_FEAT_PCLMULQDQ:
> + return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ);
> + case X86_FEAT_SSE:
> + return (s->cpuid_ext_features & CPUID_SSE);
> + case X86_FEAT_SSE2:
> + return (s->cpuid_ext_features & CPUID_SSE2);
> + case X86_FEAT_SSE3:
> + return (s->cpuid_ext_features & CPUID_EXT_SSE3);
> + case X86_FEAT_SSSE3:
> + return (s->cpuid_ext_features & CPUID_EXT_SSSE3);
> + case X86_FEAT_SSE41:
> + return (s->cpuid_ext_features & CPUID_EXT_SSE41);
> + case X86_FEAT_SSE42:
> + return (s->cpuid_ext_features & CPUID_EXT_SSE42);
> + case X86_FEAT_AES:
> + if (s->vex_l) {
> + return (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES);
> + } else {
> + return (s->cpuid_ext_features & CPUID_EXT_AES);
> + }
> + case X86_FEAT_AVX:
> + return (s->cpuid_ext_features & CPUID_EXT_AVX);
> +
> + case X86_FEAT_SSE4A:
> + return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A);
> +
> + case X86_FEAT_ADX:
> + return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX);
> + case X86_FEAT_BMI1:
> + return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1);
> + case X86_FEAT_BMI2:
> + return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2);
> + case X86_FEAT_AVX2:
> + return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2);
> + default:
> + abort();
> + }
g_assert_not_reached().
I'll also note that for cases like this, where every case returns, and is intended to be
present, it can be better to leave the default case outside the switch, so that the
compiler can Werror early for missing enumerator entries instead of aborting at runtime.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 09/37] target/i386: add AVX_EN hflag
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (7 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 08/37] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 10:06 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
` (27 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook
From: Paul Brook <paul@nowt.org>
Add a new hflag bit to determine whether AVX instructions are allowed
Signed-off-by: Paul Brook <paul@nowt.org>
Message-Id: <20220424220204.2493824-4-paul@nowt.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.h | 3 +++
target/i386/helper.c | 12 ++++++++++++
target/i386/tcg/fpu_helper.c | 1 +
3 files changed, 16 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8311b69c88..ff1df4ea53 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -169,6 +169,7 @@ typedef enum X86Seg {
#define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
#define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
#define HF_UMIP_SHIFT 27 /* CR4.UMIP */
+#define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */
#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
@@ -195,6 +196,7 @@ typedef enum X86Seg {
#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
#define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
+#define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT)
/* hflags2 */
@@ -2121,6 +2123,7 @@ void host_cpuid(uint32_t function, uint32_t count,
/* helper.c */
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
+void cpu_sync_avx_hflag(CPUX86State *env);
#ifndef CONFIG_USER_ONLY
static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
diff --git a/target/i386/helper.c b/target/i386/helper.c
index fa409e9c44..30083c9cff 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -29,6 +29,17 @@
#endif
#include "qemu/log.h"
+void cpu_sync_avx_hflag(CPUX86State *env)
+{
+ if ((env->cr[4] & CR4_OSXSAVE_MASK)
+ && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK))
+ == (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) {
+ env->hflags |= HF_AVX_EN_MASK;
+ } else{
+ env->hflags &= ~HF_AVX_EN_MASK;
+ }
+}
+
void cpu_sync_bndcs_hflags(CPUX86State *env)
{
uint32_t hflags = env->hflags;
@@ -209,6 +220,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
env->hflags = hflags;
cpu_sync_bndcs_hflags(env);
+ cpu_sync_avx_hflag(env);
}
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 30bc44fcf8..48bf0c5cf8 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -2943,6 +2943,7 @@ void helper_xsetbv(CPUX86State *env, uint32_t ecx, uint64_t mask)
env->xcr0 = mask;
cpu_sync_bndcs_hflags(env);
+ cpu_sync_avx_hflag(env);
return;
do_gpf:
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 09/37] target/i386: add AVX_EN hflag
2022-09-11 23:03 ` [PATCH 09/37] target/i386: add AVX_EN hflag Paolo Bonzini
@ 2022-09-12 10:06 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 10:06 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: Paul Brook
On 9/12/22 00:03, Paolo Bonzini wrote:
> From: Paul Brook<paul@nowt.org>
>
> Add a new hflag bit to determine whether AVX instructions are allowed
>
> Signed-off-by: Paul Brook<paul@nowt.org>
> Message-Id:<20220424220204.2493824-4-paul@nowt.org>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/cpu.h | 3 +++
> target/i386/helper.c | 12 ++++++++++++
> target/i386/tcg/fpu_helper.c | 1 +
> 3 files changed, 16 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (8 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 09/37] target/i386: add AVX_EN hflag Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 10:39 ` Richard Henderson
2022-09-12 10:42 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 11/37] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
` (26 subsequent siblings)
36 siblings, 2 replies; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 160 ++++++++++++++++++++++++++++++-
target/i386/tcg/decode-new.h | 32 +++++++
target/i386/tcg/emit.c.inc | 34 ++++++-
target/i386/tcg/translate.c | 17 ++--
4 files changed, 232 insertions(+), 11 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index a9b8b6c05f..f6c032c694 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -91,6 +91,23 @@
#define zext0 .special = X86_SPECIAL_ZExtOp0,
#define zext2 .special = X86_SPECIAL_ZExtOp2,
+#define vex1 .vex_class = 1,
+#define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar,
+#define vex2 .vex_class = 2,
+#define vex2_rep3 .vex_class = 2, .vex_special = X86_VEX_REPScalar,
+#define vex3 .vex_class = 3,
+#define vex4 .vex_class = 4,
+#define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned,
+#define vex5 .vex_class = 5,
+#define vex6 .vex_class = 6,
+#define vex7 .vex_class = 7,
+#define vex8 .vex_class = 8,
+#define vex11 .vex_class = 11,
+#define vex12 .vex_class = 12,
+#define vex13 .vex_class = 13,
+
+#define avx2_256 .vex_special = X86_VEX_AVX2_256,
+
static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
{
if (!s->has_modrm) {
@@ -155,6 +172,18 @@ static const X86OpEntry opcodes_root[256] = {
};
#undef mmx
+#undef vex1
+#undef vex2
+#undef vex3
+#undef vex4
+#undef vex4_unal
+#undef vex5
+#undef vex6
+#undef vex7
+#undef vex8
+#undef vex11
+#undef vex12
+#undef vex13
/*
* Decode the fixed part of the opcode and place the last
@@ -553,6 +582,132 @@ static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
}
}
+static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
+{
+ X86OpEntry *e = &decode->e;
+
+ switch (e->vex_special) {
+ case X86_VEX_REPScalar:
+ /*
+ * Instructions which differ between 00/66 and F2/F3 in the
+ * exception classification and the size of the memory operand.
+ */
+ assert(e->vex_class == 1 || e->vex_class == 2);
+ if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
+ e->vex_class = 3;
+ if (s->vex_l) {
+ goto illegal;
+ }
+ assert(decode->e.s2 == X86_SIZE_x);
+ if (decode->op[2].has_ea) {
+ decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64;
+ }
+ }
+ break;
+
+ case X86_VEX_SSEUnaligned:
+ /* handled in sse_needs_alignment. */
+ break;
+
+ case X86_VEX_AVX2_256:
+ if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) {
+ goto illegal;
+ }
+ }
+
+ /* TODO: instructions that require VEX.W=0 (Table 2-16) */
+
+ switch (e->vex_class) {
+ case 0:
+ if (s->prefix & PREFIX_VEX) {
+ goto illegal;
+ }
+ return true;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 7:
+ if (s->prefix & PREFIX_VEX) {
+ if (!(s->flags & HF_AVX_EN_MASK)) {
+ goto illegal;
+ }
+ } else {
+ if (!(s->flags & HF_OSFXSR_MASK)) {
+ goto illegal;
+ }
+ }
+ break;
+ case 12:
+ assert(s->has_modrm);
+ /* Must have a VSIB byte and no address prefix. */
+ if ((s->modrm & 7) != 4 || s->aflag == MO_16) {
+ goto illegal;
+ }
+ /* Check no overlap between registers. */
+ if (decode->op[0].unit == decode->op[1].unit && decode->op[0].n == decode->op[1].n) {
+ goto illegal;
+ }
+ if (decode->op[0].unit == X86_OP_SSE && decode->op[0].n == decode->mem.index) {
+ goto illegal;
+ }
+ if (decode->op[1].unit == X86_OP_SSE && decode->op[1].n == decode->mem.index) {
+ goto illegal;
+ }
+ /* fall through */
+ case 6:
+ case 11:
+ if (!(s->prefix & PREFIX_VEX)) {
+ goto illegal;
+ }
+ if (!(s->flags & HF_AVX_EN_MASK)) {
+ goto illegal;
+ }
+ break;
+ case 8:
+ if (!(s->prefix & PREFIX_VEX)) {
+ /* EMMS */
+ return true;
+ }
+ if (!(s->flags & HF_AVX_EN_MASK)) {
+ goto illegal;
+ }
+ break;
+ case 13:
+ if (!(s->prefix & PREFIX_VEX)) {
+ goto illegal;
+ }
+ if (s->vex_l) {
+ goto illegal;
+ }
+ /* All integer instructions use VEX.vvvv, so exit. */
+ return true;
+ }
+
+ if (s->vex_v != 0 &&
+ e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B &&
+ e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B &&
+ e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) {
+ goto illegal;
+ }
+
+ if (s->flags & HF_TS_MASK) {
+ goto nm_exception;
+ }
+ if (s->flags & HF_EM_MASK) {
+ goto illegal;
+ }
+ return true;
+
+nm_exception:
+ gen_NM_exception(s);
+ return false;
+illegal:
+ gen_illegal_opcode(s);
+ return false;
+}
+
/* convert one instruction. s->base.is_jmp is set if the translation must
be stopped. Return the next pc value */
static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
@@ -789,8 +944,11 @@ static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
break;
}
+ if (!validate_vex(s, &decode)) {
+ return s->pc;
+ }
if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
- gen_load_ea(s, &decode.mem);
+ gen_load_ea(s, &decode.mem, decode.e.vex_class == 12);
}
if (s->prefix & PREFIX_LOCK) {
if (decode.op[0].unit != X86_OP_INT || !decode.op[0].has_ea) {
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index 6fb2d9151e..b5299d0dd2 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -152,6 +152,36 @@ typedef enum X86InsnSpecial {
X86_SPECIAL_o64,
} X86InsnSpecial;
+/*
+ * Special cases for instructions that operate on XMM/YMM registers. Intel
+ * retconned all of them to have VEX exception classes other than 0 and 13, so
+ * all these only matter for instructions that have a VEX exception class.
+ * Based on tables in the "AVX and SSE Instruction Exception Specification"
+ * section of the manual.
+ */
+typedef enum X86VEXSpecial {
+ /* Legacy SSE instructions that allow unaligned operands */
+ X86_VEX_SSEUnaligned,
+
+ /*
+ * Used for instructions that distinguish the XMM operand type with an
+ * instruction prefix; legacy SSE encodings will allow unaligned operands
+ * for scalar operands only (identified by a REP prefix). In this case,
+ * the decoding table uses "x" for the vector operands instead of specifying
+ * pd/ps/sd/ss individually.
+ */
+ X86_VEX_REPScalar,
+
+ /*
+ * VEX instructions that only support 256-bit operands with AVX2 (Table 2-17
+ * column 3). Columns 2 and 4 (instructions limited to 256- and 127-bit
+ * operands respectively) are implicit in the presence of dq and qq
+ * operands, and thus handled by decode_op_size.
+ */
+ X86_VEX_AVX2_256,
+} X86VEXSpecial;
+
+
typedef struct X86OpEntry X86OpEntry;
typedef struct X86DecodedInsn X86DecodedInsn;
@@ -180,6 +210,8 @@ struct X86OpEntry {
X86InsnSpecial special : 8;
X86CPUIDFeature cpuid : 8;
+ uint8_t vex_class : 8;
+ X86VEXSpecial vex_special : 8;
bool is_decode : 1;
};
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 6fa0062d6a..ce0205e05a 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -19,14 +19,19 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+static void gen_NM_exception(DisasContext *s)
+{
+ gen_exception(s, EXCP07_PREX, s->pc_start - s->cs_base);
+}
+
static void gen_illegal(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_illegal_opcode(s);
}
-static void gen_load_ea(DisasContext *s, AddressParts *mem)
+static void gen_load_ea(DisasContext *s, AddressParts *mem, bool is_vsib)
{
- TCGv ea = gen_lea_modrm_1(s, *mem);
+ TCGv ea = gen_lea_modrm_1(s, *mem, is_vsib);
gen_lea_v_seg(s, s->aflag, ea, mem->def_seg, s->override);
}
@@ -102,6 +107,25 @@ static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs)
}
}
+static inline bool sse_needs_alignment(DisasContext *s, X86DecodedInsn *decode, X86DecodedOp *op)
+{
+ switch (decode->e.vex_class) {
+ case 2:
+ case 4:
+ if ((s->prefix & PREFIX_VEX) ||
+ decode->e.vex_special == X86_VEX_SSEUnaligned) {
+ /* MOST legacy SSE instructions require aligned memory operands, but not all. */
+ return false;
+ }
+ /* fall through */
+ case 1:
+ return op->has_ea && op->ot >= MO_128;
+
+ default:
+ return false;
+ }
+}
+
static void gen_load(DisasContext *s, TCGv v, TCGv_ptr ptr, X86DecodedOp *op, uint64_t imm)
{
switch (op->unit) {
@@ -175,7 +199,13 @@ static void gen_writeback(DisasContext *s, X86DecodedOp *op)
}
break;
case X86_OP_MMX:
+ break;
case X86_OP_SSE:
+ if ((s->prefix & PREFIX_VEX) && op->ot == MO_128) {
+ tcg_gen_gvec_dup_imm(MO_64,
+ offsetof(CPUX86State, xmm_regs[op->n].ZMM_X(1)),
+ 16, 16, 0);
+ }
break;
default:
abort();
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index a92ef61527..4ecf75ede3 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2217,11 +2217,11 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,
}
/* Compute the address, with a minimum number of TCG ops. */
-static TCGv gen_lea_modrm_1(DisasContext *s, AddressParts a)
+static TCGv gen_lea_modrm_1(DisasContext *s, AddressParts a, bool is_vsib)
{
TCGv ea = NULL;
- if (a.index >= 0) {
+ if (a.index >= 0 && !is_vsib) {
if (a.scale == 0) {
ea = cpu_regs[a.index];
} else {
@@ -2249,7 +2249,7 @@ static TCGv gen_lea_modrm_1(DisasContext *s, AddressParts a)
static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
{
AddressParts a = gen_lea_modrm_0(env, s, modrm);
- TCGv ea = gen_lea_modrm_1(s, a);
+ TCGv ea = gen_lea_modrm_1(s, a, false);
gen_lea_v_seg(s, s->aflag, ea, a.def_seg, s->override);
}
@@ -2262,7 +2262,8 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm,
TCGCond cond, TCGv_i64 bndv)
{
- TCGv ea = gen_lea_modrm_1(s, gen_lea_modrm_0(env, s, modrm));
+ AddressParts a = gen_lea_modrm_0(env, s, modrm);
+ TCGv ea = gen_lea_modrm_1(s, a, false);
tcg_gen_extu_tl_i64(s->tmp1_i64, ea);
if (!CODE64(s)) {
@@ -5953,7 +5954,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
reg = ((modrm >> 3) & 7) | REX_R(s);
{
AddressParts a = gen_lea_modrm_0(env, s, modrm);
- TCGv ea = gen_lea_modrm_1(s, a);
+ TCGv ea = gen_lea_modrm_1(s, a, false);
gen_lea_v_seg(s, s->aflag, ea, -1, -1);
gen_op_mov_reg_v(s, dflag, reg, s->A0);
}
@@ -6180,7 +6181,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
if (mod != 3) {
/* memory op */
AddressParts a = gen_lea_modrm_0(env, s, modrm);
- TCGv ea = gen_lea_modrm_1(s, a);
+ TCGv ea = gen_lea_modrm_1(s, a, false);
TCGv last_addr = tcg_temp_new();
bool update_fdp = true;
@@ -7210,7 +7211,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_exts(ot, s->T1);
tcg_gen_sari_tl(s->tmp0, s->T1, 3 + ot);
tcg_gen_shli_tl(s->tmp0, s->tmp0, ot);
- tcg_gen_add_tl(s->A0, gen_lea_modrm_1(s, a), s->tmp0);
+ tcg_gen_add_tl(s->A0, gen_lea_modrm_1(s, a, false), s->tmp0);
gen_lea_v_seg(s, s->aflag, s->A0, a.def_seg, s->override);
if (!(s->prefix & PREFIX_LOCK)) {
gen_op_ld_v(s, ot, s->T0, s->A0);
@@ -8281,7 +8282,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
/* rip-relative generates #ud */
goto illegal_op;
}
- tcg_gen_not_tl(s->A0, gen_lea_modrm_1(s, a));
+ tcg_gen_not_tl(s->A0, gen_lea_modrm_1(s, a, false));
if (!CODE64(s)) {
tcg_gen_ext32u_tl(s->A0, s->A0);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes
2022-09-11 23:03 ` [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
@ 2022-09-12 10:39 ` Richard Henderson
2022-09-12 10:42 ` Richard Henderson
1 sibling, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 10:39 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> @@ -102,6 +107,25 @@ static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs)
> +static inline bool sse_needs_alignment(DisasContext *s, X86DecodedInsn *decode, X86DecodedOp *op)
> +{
Drop inline. You may require adding G_GNUC_UNUSED temporarily, because it isn't used in
this patch...
> @@ -175,7 +199,13 @@ static void gen_writeback(DisasContext *s, X86DecodedOp *op)
> }
> break;
> case X86_OP_MMX:
> + break;
> case X86_OP_SSE:
> + if ((s->prefix & PREFIX_VEX) && op->ot == MO_128) {
> + tcg_gen_gvec_dup_imm(MO_64,
> + offsetof(CPUX86State, xmm_regs[op->n].ZMM_X(1)),
> + 16, 16, 0);
> + }
So... gvec supports doing this zeroing within the operation. E.g.
static void gen_PADDB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
tcg_gen_gvec_add(MO_8, decode->op[0].offset,
decode->op[1].offset, decode->op[2].offset,
sse_vec_len(s, decode), sse_vec_len_max(s, decode));
}
The only catch is that gvec expects the zeroing to be at the end of the range, so this
requires reorganizing ZMM for big-endian. Instead of reversing the entire ZMM register, we
would keep only each 16-byte lane in host-endian order. Like so:
#if HOST_BIG_ENDIAN
- #define ZMM_B(n) _b_ZMMReg[63 - (n)]
+ #define ZMM_B(n) _b_ZMMReg[(n) ^ 15]
etc.
Ideally this zeroing above would move into each operation. For our current set of
helpers, it should be easy enough to do in gen_binary_int_sse and friends.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes
2022-09-11 23:03 ` [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
2022-09-12 10:39 ` Richard Henderson
@ 2022-09-12 10:42 ` Richard Henderson
1 sibling, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 10:42 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> @@ -180,6 +210,8 @@ struct X86OpEntry {
>
> X86InsnSpecial special : 8;
> X86CPUIDFeature cpuid : 8;
> + uint8_t vex_class : 8;
Since uint8_t expands to 'unsigned char', it's friendlier to use 'unsigned' with
bitfields, so that gdb doesn't try to render the field as a character.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 11/37] target/i386: validate SSE prefixes directly in the decoding table
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (9 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 10:51 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
` (25 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 37 ++++++++++++++++++++++++++++++++
target/i386/tcg/decode-new.h | 1 +
2 files changed, 38 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index f6c032c694..7b4fd9fb54 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -108,6 +108,22 @@
#define avx2_256 .vex_special = X86_VEX_AVX2_256,
+#define P_00 1
+#define P_66 (1 << PREFIX_DATA)
+#define P_F3 (1 << PREFIX_REPZ)
+#define P_F2 (1 << PREFIX_REPNZ)
+
+#define p_00 .valid_prefix = P_00,
+#define p_66 .valid_prefix = P_66,
+#define p_f3 .valid_prefix = P_F3,
+#define p_f2 .valid_prefix = P_F2,
+#define p_00_66 .valid_prefix = P_00|P_66,
+#define p_00_f3 .valid_prefix = P_00|P_F3,
+#define p_66_f2 .valid_prefix = P_66|P_F2,
+#define p_00_66_f3 .valid_prefix = P_00|P_66|P_F3,
+#define p_66_f3_f2 .valid_prefix = P_66|P_F3|P_F2,
+#define p_00_66_f3_f2 .valid_prefix = P_00|P_66|P_F3|P_F2,
+
static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
{
if (!s->has_modrm) {
@@ -473,6 +489,23 @@ static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
return true;
}
+static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e)
+{
+ uint16_t sse_prefixes;
+
+ if (!e->valid_prefix) {
+ return true;
+ }
+ if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
+ /* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */
+ s->prefix &= ~PREFIX_DATA;
+ }
+
+ /* Now, either zero or one bit is set in sse_prefixes. */
+ sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
+ return e->valid_prefix & (1 << sse_prefixes);
+}
+
static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func,
X86DecodedInsn *decode)
{
@@ -484,6 +517,10 @@ static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_
e->decode(s, env, e, &decode->b);
}
+ if (!validate_sse_prefix(s, e)) {
+ return false;
+ }
+
/* First compute size of operands in order to initialize s->rip_offset. */
if (e->op0 != X86_TYPE_None) {
if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index b5299d0dd2..3db7b82506 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -212,6 +212,7 @@ struct X86OpEntry {
X86CPUIDFeature cpuid : 8;
uint8_t vex_class : 8;
X86VEXSpecial vex_special : 8;
+ uint16_t valid_prefix : 16;
bool is_decode : 1;
};
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 11/37] target/i386: validate SSE prefixes directly in the decoding table
2022-09-11 23:03 ` [PATCH 11/37] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
@ 2022-09-12 10:51 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 10:51 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> Many SSE and AVX instructions are only valid with specific prefixes
> (none, 66, F3, F2). Introduce a direct way to encode this in the
> decoding table to avoid using decode groups too much.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 37 ++++++++++++++++++++++++++++++++
> target/i386/tcg/decode-new.h | 1 +
> 2 files changed, 38 insertions(+)
>
> diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
> index f6c032c694..7b4fd9fb54 100644
> --- a/target/i386/tcg/decode-new.c.inc
> +++ b/target/i386/tcg/decode-new.c.inc
> @@ -108,6 +108,22 @@
>
> #define avx2_256 .vex_special = X86_VEX_AVX2_256,
>
> +#define P_00 1
> +#define P_66 (1 << PREFIX_DATA)
> +#define P_F3 (1 << PREFIX_REPZ)
> +#define P_F2 (1 << PREFIX_REPNZ)
These prefixes are already flags. Do you really need to shift the shifted value?
I guess you need to choose a value for "no prefix", but I think you could also (ab,re)use
PREFIX_LOCK or something...
> @@ -212,6 +212,7 @@ struct X86OpEntry {
> X86CPUIDFeature cpuid : 8;
> uint8_t vex_class : 8;
> X86VEXSpecial vex_special : 8;
> + uint16_t valid_prefix : 16;
Anyway, if you did, you'd only need 4 bits instead of 16.
That said, the logic is sound, and saving a few bits doesn't matter much.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (10 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 11/37] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:04 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 13/37] target/i386: remove scalar VEX instructions from old decoder Paolo Bonzini
` (24 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Because these are the only VEX instructions that QEMU supports, the
new decoder is entered on the first byte of a valid VEX prefix, and VEX
decoding only needs to be done in decode-new.c.inc.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 59 +++++++
target/i386/tcg/emit.c.inc | 261 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 49 +-----
3 files changed, 323 insertions(+), 46 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 7b4fd9fb54..b31daecb90 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -133,11 +133,69 @@ static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
return s->modrm;
}
+static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86GenFunc group17_gen[8] = {
+ NULL, gen_BLSR, gen_BLSMSK, gen_BLSI,
+ };
+ int op = (get_modrm(s, env) >> 3) & 7;
+ entry->gen = group17_gen[op];
+}
+
static const X86OpEntry opcodes_0F38_00toEF[240] = {
};
/* five rows for no prefix, 66, F3, F2, 66+F2 */
static X86OpEntry opcodes_0F38_F0toFF[16][5] = {
+ [0] = {
+ X86_OP_ENTRY3(MOVBE, G,y, M,y, None,None, cpuid(MOVBE)),
+ X86_OP_ENTRY3(MOVBE, G,w, M,w, None,None, cpuid(MOVBE)),
+ {},
+ X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
+ X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
+ },
+ [1] = {
+ X86_OP_ENTRY3(MOVBE, M,y, G,y, None,None, cpuid(MOVBE)),
+ X86_OP_ENTRY3(MOVBE, M,w, G,w, None,None, cpuid(MOVBE)),
+ {},
+ X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)),
+ X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)),
+ },
+ [2] = {
+ X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)),
+ {},
+ {},
+ {},
+ {},
+ },
+ [3] = {
+ X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)),
+ {},
+ {},
+ {},
+ {},
+ },
+ [5] = {
+ X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)),
+ {},
+ X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 cpuid(BMI2)),
+ X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 cpuid(BMI2)),
+ {},
+ },
+ [6] = {
+ {},
+ X86_OP_ENTRY2(ADCX, G,y, E,y, cpuid(ADX)),
+ X86_OP_ENTRY2(ADOX, G,y, E,y, cpuid(ADX)),
+ X86_OP_ENTRY3(MULX, /* B,y, */ G,y, E,y, 2,y, vex13 cpuid(BMI2)),
+ {},
+ },
+ [7] = {
+ X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 cpuid(BMI1)),
+ X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
+ X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
+ X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
+ {},
+ },
};
static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
@@ -159,6 +217,7 @@ static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
static const X86OpEntry opcodes_0F3A[256] = {
+ [0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2),
};
static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index ce0205e05a..36b963a0d3 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -211,3 +211,264 @@ static void gen_writeback(DisasContext *s, X86DecodedOp *op)
abort();
}
}
+
+static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
+{
+ TCGv carry_in = NULL;
+ TCGv carry_out = (cc_op == CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2);
+ TCGv zero;
+
+ if (cc_op == s->cc_op || s->cc_op == CC_OP_ADCOX) {
+ /* Re-use the carry-out from a previous round. */
+ carry_in = carry_out;
+ cc_op = s->cc_op;
+ } else if (s->cc_op == CC_OP_ADCX || s->cc_op == CC_OP_ADOX) {
+ /* Merge with the carry-out from the opposite instruction. */
+ cc_op = CC_OP_ADCOX;
+ }
+
+ /* If we don't have a carry-in, get it out of EFLAGS. */
+ if (!carry_in) {
+ if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) {
+ gen_compute_eflags(s);
+ }
+ carry_in = s->tmp0;
+ tcg_gen_extract_tl(carry_in, cpu_cc_src,
+ ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1);
+ }
+
+ switch (ot) {
+#ifdef TARGET_X86_64
+ case MO_32:
+ /* If TL is 64-bit just do everything in 64-bit arithmetic. */
+ tcg_gen_add_i64(s->T0, s->T0, s->T1);
+ tcg_gen_add_i64(s->T0, s->T0, carry_in);
+ tcg_gen_shri_i64(carry_out, s->T0, 32);
+ break;
+#endif
+ default:
+ zero = tcg_const_tl(0);
+ tcg_gen_add2_tl(s->T0, carry_out, s->T0, zero, carry_in, zero);
+ tcg_gen_add2_tl(s->T0, carry_out, s->T0, carry_out, s->T1, zero);
+ tcg_temp_free(zero);
+ break;
+ }
+ set_cc_op(s, cc_op);
+}
+
+static void gen_ADCX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_ADCOX(s, env, decode->op[0].ot, CC_OP_ADCX);
+}
+
+static void gen_ADOX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_ADCOX(s, env, decode->op[0].ot, CC_OP_ADOX);
+}
+
+static void gen_ANDN(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+
+ tcg_gen_andc_tl(s->T0, s->T1, s->T0);
+ gen_op_update1_cc(s);
+ set_cc_op(s, CC_OP_LOGICB + ot);
+}
+
+static void gen_BEXTR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+ TCGv bound, zero;
+
+ /*
+ * Extract START, and shift the operand.
+ * Shifts larger than operand size get zeros.
+ */
+ tcg_gen_ext8u_tl(s->A0, s->T1);
+ tcg_gen_shr_tl(s->T0, s->T0, s->A0);
+
+ bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
+ zero = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound, s->T0, zero);
+ tcg_temp_free(zero);
+
+ /* Extract the LEN into a mask. Lengths larger than
+ * operand size get all ones.
+ */
+ tcg_gen_extract_tl(s->A0, s->T1, 8, 8);
+ tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->A0, bound, s->A0, bound);
+ tcg_temp_free(bound);
+
+ tcg_gen_movi_tl(s->T1, 1);
+ tcg_gen_shl_tl(s->T1, s->T1, s->A0);
+ tcg_gen_subi_tl(s->T1, s->T1, 1);
+ tcg_gen_and_tl(s->T0, s->T0, s->T1);
+
+ gen_op_update1_cc(s);
+ set_cc_op(s, CC_OP_LOGICB + ot);
+}
+
+static void gen_BLSI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+
+ tcg_gen_neg_tl(s->T1, s->T0);
+ tcg_gen_and_tl(s->T0, s->T0, s->T1);
+ tcg_gen_mov_tl(cpu_cc_dst, s->T0);
+ set_cc_op(s, CC_OP_BMILGB + ot);
+}
+
+static void gen_BLSMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+
+ tcg_gen_subi_tl(s->T1, s->T0, 1);
+ tcg_gen_xor_tl(s->T0, s->T0, s->T1);
+ tcg_gen_mov_tl(cpu_cc_dst, s->T0);
+ set_cc_op(s, CC_OP_BMILGB + ot);
+}
+
+static void gen_BLSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+
+ tcg_gen_subi_tl(s->T1, s->T0, 1);
+ tcg_gen_and_tl(s->T0, s->T0, s->T1);
+ tcg_gen_mov_tl(cpu_cc_dst, s->T0);
+ set_cc_op(s, CC_OP_BMILGB + ot);
+}
+
+static void gen_BZHI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+ TCGv bound;
+
+ tcg_gen_ext8u_tl(s->T1, cpu_regs[s->vex_v]);
+ bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
+
+ /*
+ * Note that since we're using BMILG (in order to get O
+ * cleared) we need to store the inverse into C.
+ */
+ tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src, s->T1, bound);
+ tcg_gen_movcond_tl(TCG_COND_GT, s->T1, s->T1, bound, bound, s->T1);
+ tcg_temp_free(bound);
+
+ tcg_gen_movi_tl(s->A0, -1);
+ tcg_gen_shl_tl(s->A0, s->A0, s->T1);
+ tcg_gen_andc_tl(s->T0, s->T0, s->A0);
+
+ gen_op_update1_cc(s);
+ set_cc_op(s, CC_OP_BMILGB + ot);
+}
+
+static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[2].ot;
+
+ tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
+ gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_const_i32(8 << ot));
+}
+
+static void gen_MOVBE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+
+ /* M operand type does not load/store */
+ if (decode->e.op0 == X86_TYPE_M) {
+ tcg_gen_qemu_st_tl(s->T0, s->A0, s->mem_index, ot | MO_BE);
+ } else {
+ tcg_gen_qemu_ld_tl(s->T0, s->A0, s->mem_index, ot | MO_BE);
+ }
+}
+
+static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+
+ /* low part of result in VEX.vvvv, high in MODRM */
+ switch (ot) {
+ default:
+ tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
+ tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
+ tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32,
+ s->tmp2_i32, s->tmp3_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], s->tmp2_i32);
+ tcg_gen_extu_i32_tl(s->T0, s->tmp3_i32);
+ break;
+#ifdef TARGET_X86_64
+ case MO_64:
+ tcg_gen_mulu2_i64(cpu_regs[s->vex_v], s->T0, s->T0, s->T1);
+ break;
+#endif
+ }
+
+}
+
+static void gen_PDEP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[1].ot;
+ if (ot < MO_64) {
+ tcg_gen_ext32u_tl(s->T0, s->T0);
+ }
+ gen_helper_pdep(s->T0, s->T0, s->T1);
+}
+
+static void gen_PEXT(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[1].ot;
+ if (ot < MO_64) {
+ tcg_gen_ext32u_tl(s->T0, s->T0);
+ }
+ gen_helper_pext(s->T0, s->T0, s->T1);
+}
+
+static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+ int b = decode->immediate;
+
+ if (ot == MO_64) {
+ tcg_gen_rotri_tl(s->T0, s->T0, b & 63);
+ } else {
+ tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
+ tcg_gen_rotri_i32(s->tmp2_i32, s->tmp2_i32, b & 31);
+ tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
+ }
+}
+
+static void gen_SARX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+ int mask;
+
+ mask = ot == MO_64 ? 63 : 31;
+ tcg_gen_andi_tl(s->T1, s->T1, mask);
+ if (ot != MO_64) {
+ tcg_gen_ext32s_tl(s->T0, s->T0);
+ }
+ tcg_gen_sar_tl(s->T0, s->T0, s->T1);
+}
+
+static void gen_SHLX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+ int mask;
+
+ mask = ot == MO_64 ? 63 : 31;
+ tcg_gen_andi_tl(s->T1, s->T1, mask);
+ tcg_gen_shl_tl(s->T0, s->T0, s->T1);
+}
+
+static void gen_SHRX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+ int mask;
+
+ mask = ot == MO_64 ? 63 : 31;
+ tcg_gen_andi_tl(s->T1, s->T1, mask);
+ if (ot != MO_64) {
+ tcg_gen_ext32u_tl(s->T0, s->T0);
+ }
+ tcg_gen_shr_tl(s->T0, s->T0, s->T1);
+}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 4ecf75ede3..7eed575f2e 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4892,59 +4892,16 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#endif
case 0xc5: /* 2-byte VEX */
case 0xc4: /* 3-byte VEX */
- use_new = false;
- /* VEX prefixes cannot be used except in 32-bit mode.
- Otherwise the instruction is LES or LDS. */
if (CODE32(s) && !VM86(s)) {
- static const int pp_prefix[4] = {
- 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
- };
- int vex3, vex2 = x86_ldub_code(env, s);
+ int vex2 = x86_ldub_code(env, s);
+ s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
/* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
otherwise the instruction is LES or LDS. */
- s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
break;
}
-
- /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
- if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ
- | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) {
- goto illegal_op;
- }
-#ifdef TARGET_X86_64
- s->rex_r = (~vex2 >> 4) & 8;
-#endif
- if (b == 0xc5) {
- /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */
- vex3 = vex2;
- b = x86_ldub_code(env, s) | 0x100;
- } else {
- /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */
- vex3 = x86_ldub_code(env, s);
-#ifdef TARGET_X86_64
- s->rex_x = (~vex2 >> 3) & 8;
- s->rex_b = (~vex2 >> 2) & 8;
- s->rex_w = (vex3 >> 7) & 1;
-#endif
- switch (vex2 & 0x1f) {
- case 0x01: /* Implied 0f leading opcode bytes. */
- b = x86_ldub_code(env, s) | 0x100;
- break;
- case 0x02: /* Implied 0f 38 leading opcode bytes. */
- b = 0x138;
- break;
- case 0x03: /* Implied 0f 3a leading opcode bytes. */
- b = 0x13a;
- break;
- default: /* Reserved for future use. */
- goto unknown_op;
- }
- }
- s->vex_v = (~vex3 >> 3) & 0xf;
- s->vex_l = (vex3 >> 2) & 1;
- prefixes |= pp_prefix[vex3 & 3] | PREFIX_VEX;
+ return disas_insn_new(s, cpu, b);
}
break;
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder
2022-09-11 23:03 ` [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
@ 2022-09-12 11:04 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 11:04 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> Because these are the only VEX instructions that QEMU supports, the
> new decoder is entered on the first byte of a valid VEX prefix, and VEX
> decoding only needs to be done in decode-new.c.inc.
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 59 +++++++
> target/i386/tcg/emit.c.inc | 261 +++++++++++++++++++++++++++++++
> target/i386/tcg/translate.c | 49 +-----
> 3 files changed, 323 insertions(+), 46 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 13/37] target/i386: remove scalar VEX instructions from old decoder
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (11 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:06 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 14/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
` (23 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
This is all dead code, since the VEX prefix goes straight to the new decoder.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 243 ------------------------------------
1 file changed, 243 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 7eed575f2e..240811bd49 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4119,151 +4119,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
s->mem_index, ot | MO_BE);
}
break;
-
- case 0x0f2: /* andn Gy, By, Ey */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- tcg_gen_andc_tl(s->T0, s->T0, cpu_regs[s->vex_v]);
- gen_op_mov_reg_v(s, ot, reg, s->T0);
- gen_op_update1_cc(s);
- set_cc_op(s, CC_OP_LOGICB + ot);
- break;
-
- case 0x0f7: /* bextr Gy, Ey, By */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- {
- TCGv bound, zero;
-
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- /* Extract START, and shift the operand.
- Shifts larger than operand size get zeros. */
- tcg_gen_ext8u_tl(s->A0, cpu_regs[s->vex_v]);
- tcg_gen_shr_tl(s->T0, s->T0, s->A0);
-
- bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
- zero = tcg_const_tl(0);
- tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound,
- s->T0, zero);
- tcg_temp_free(zero);
-
- /* Extract the LEN into a mask. Lengths larger than
- operand size get all ones. */
- tcg_gen_extract_tl(s->A0, cpu_regs[s->vex_v], 8, 8);
- tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->A0, bound,
- s->A0, bound);
- tcg_temp_free(bound);
- tcg_gen_movi_tl(s->T1, 1);
- tcg_gen_shl_tl(s->T1, s->T1, s->A0);
- tcg_gen_subi_tl(s->T1, s->T1, 1);
- tcg_gen_and_tl(s->T0, s->T0, s->T1);
-
- gen_op_mov_reg_v(s, ot, reg, s->T0);
- gen_op_update1_cc(s);
- set_cc_op(s, CC_OP_LOGICB + ot);
- }
- break;
-
- case 0x0f5: /* bzhi Gy, Ey, By */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- tcg_gen_ext8u_tl(s->T1, cpu_regs[s->vex_v]);
- {
- TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
- /* Note that since we're using BMILG (in order to get O
- cleared) we need to store the inverse into C. */
- tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src,
- s->T1, bound);
- tcg_gen_movcond_tl(TCG_COND_GT, s->T1, s->T1,
- bound, bound, s->T1);
- tcg_temp_free(bound);
- }
- tcg_gen_movi_tl(s->A0, -1);
- tcg_gen_shl_tl(s->A0, s->A0, s->T1);
- tcg_gen_andc_tl(s->T0, s->T0, s->A0);
- gen_op_mov_reg_v(s, ot, reg, s->T0);
- gen_op_update1_cc(s);
- set_cc_op(s, CC_OP_BMILGB + ot);
- break;
-
- case 0x3f6: /* mulx By, Gy, rdx, Ey */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- switch (ot) {
- default:
- tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EDX]);
- tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32,
- s->tmp2_i32, s->tmp3_i32);
- tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], s->tmp2_i32);
- tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp3_i32);
- break;
-#ifdef TARGET_X86_64
- case MO_64:
- tcg_gen_mulu2_i64(s->T0, s->T1,
- s->T0, cpu_regs[R_EDX]);
- tcg_gen_mov_i64(cpu_regs[s->vex_v], s->T0);
- tcg_gen_mov_i64(cpu_regs[reg], s->T1);
- break;
-#endif
- }
- break;
-
- case 0x3f5: /* pdep Gy, By, Ey */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- /* Note that by zero-extending the source operand, we
- automatically handle zero-extending the result. */
- if (ot == MO_64) {
- tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]);
- } else {
- tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]);
- }
- gen_helper_pdep(cpu_regs[reg], s->T1, s->T0);
- break;
-
- case 0x2f5: /* pext Gy, By, Ey */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- /* Note that by zero-extending the source operand, we
- automatically handle zero-extending the result. */
- if (ot == MO_64) {
- tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]);
- } else {
- tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]);
- }
- gen_helper_pext(cpu_regs[reg], s->T1, s->T0);
- break;
-
case 0x1f6: /* adcx Gy, Ey */
case 0x2f6: /* adox Gy, Ey */
CHECK_NO_VEX(s);
@@ -4343,73 +4198,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
break;
- case 0x1f7: /* shlx Gy, Ey, By */
- case 0x2f7: /* sarx Gy, Ey, By */
- case 0x3f7: /* shrx Gy, Ey, By */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- if (ot == MO_64) {
- tcg_gen_andi_tl(s->T1, cpu_regs[s->vex_v], 63);
- } else {
- tcg_gen_andi_tl(s->T1, cpu_regs[s->vex_v], 31);
- }
- if (b == 0x1f7) {
- tcg_gen_shl_tl(s->T0, s->T0, s->T1);
- } else if (b == 0x2f7) {
- if (ot != MO_64) {
- tcg_gen_ext32s_tl(s->T0, s->T0);
- }
- tcg_gen_sar_tl(s->T0, s->T0, s->T1);
- } else {
- if (ot != MO_64) {
- tcg_gen_ext32u_tl(s->T0, s->T0);
- }
- tcg_gen_shr_tl(s->T0, s->T0, s->T1);
- }
- gen_op_mov_reg_v(s, ot, reg, s->T0);
- break;
-
- case 0x0f3:
- case 0x1f3:
- case 0x2f3:
- case 0x3f3: /* Group 17 */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
-
- tcg_gen_mov_tl(cpu_cc_src, s->T0);
- switch (reg & 7) {
- case 1: /* blsr By,Ey */
- tcg_gen_subi_tl(s->T1, s->T0, 1);
- tcg_gen_and_tl(s->T0, s->T0, s->T1);
- break;
- case 2: /* blsmsk By,Ey */
- tcg_gen_subi_tl(s->T1, s->T0, 1);
- tcg_gen_xor_tl(s->T0, s->T0, s->T1);
- break;
- case 3: /* blsi By, Ey */
- tcg_gen_neg_tl(s->T1, s->T0);
- tcg_gen_and_tl(s->T0, s->T0, s->T1);
- break;
- default:
- goto unknown_op;
- }
- tcg_gen_mov_tl(cpu_cc_dst, s->T0);
- gen_op_mov_reg_v(s, ot, s->vex_v, s->T0);
- set_cc_op(s, CC_OP_BMILGB + ot);
- break;
-
- default:
- goto unknown_op;
}
break;
@@ -4625,37 +4413,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
break;
- case 0x33a:
- /* Various integer extensions at 0f 3a f[0-f]. */
- b = modrm | (b1 << 8);
- modrm = x86_ldub_code(env, s);
- reg = ((modrm >> 3) & 7) | REX_R(s);
-
- switch (b) {
- case 0x3f0: /* rorx Gy,Ey, Ib */
- if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
- || !(s->prefix & PREFIX_VEX)
- || s->vex_l != 0) {
- goto illegal_op;
- }
- ot = mo_64_32(s->dflag);
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- b = x86_ldub_code(env, s);
- if (ot == MO_64) {
- tcg_gen_rotri_tl(s->T0, s->T0, b & 63);
- } else {
- tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- tcg_gen_rotri_i32(s->tmp2_i32, s->tmp2_i32, b & 31);
- tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
- }
- gen_op_mov_reg_v(s, ot, reg, s->T0);
- break;
-
- default:
- goto unknown_op;
- }
- break;
-
default:
unknown_op:
gen_unknown_opcode(env, s);
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* [PATCH 14/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (12 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 13/37] target/i386: remove scalar VEX instructions from old decoder Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:09 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 15/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
` (22 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook
From: Paul Brook <paul@nowt.org>
Adjust all #ifdefs to match the ones in ops_sse.h.
Signed-off-by: Paul Brook <paul@nowt.org>
Message-Id: <20220424220204.2493824-23-paul@nowt.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
| 114 +++++++++++++++++++++++------------
1 file changed, 75 insertions(+), 39 deletions(-)
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index d99464afb0..7f57dab496 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -43,7 +43,7 @@ DEF_HELPER_3(glue(pslld, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(psrlq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(psllq, SUFFIX), void, env, Reg, Reg)
-#if SHIFT == 1
+#if SHIFT >= 1
DEF_HELPER_3(glue(psrldq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pslldq, SUFFIX), void, env, Reg, Reg)
#endif
@@ -101,7 +101,7 @@ SSE_HELPER_L(pcmpeql, FCMPEQ)
SSE_HELPER_W(pmullw, FMULLW)
#if SHIFT == 0
-SSE_HELPER_W(pmulhrw, FMULHRW)
+DEF_HELPER_3(glue(pmulhrw, SUFFIX), void, env, Reg, Reg)
#endif
SSE_HELPER_W(pmulhuw, FMULHUW)
SSE_HELPER_W(pmulhw, FMULHW)
@@ -113,7 +113,9 @@ DEF_HELPER_3(glue(pmuludq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmaddwd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(psadbw, SUFFIX), void, env, Reg, Reg)
+#if SHIFT < 2
DEF_HELPER_4(glue(maskmov, SUFFIX), void, env, Reg, Reg, tl)
+#endif
DEF_HELPER_2(glue(movl_mm_T0, SUFFIX), void, Reg, i32)
#ifdef TARGET_X86_64
DEF_HELPER_2(glue(movq_mm_T0, SUFFIX), void, Reg, i64)
@@ -122,38 +124,63 @@ DEF_HELPER_2(glue(movq_mm_T0, SUFFIX), void, Reg, i64)
#if SHIFT == 0
DEF_HELPER_3(glue(pshufw, SUFFIX), void, Reg, Reg, int)
#else
-DEF_HELPER_3(glue(shufps, SUFFIX), void, Reg, Reg, int)
-DEF_HELPER_3(glue(shufpd, SUFFIX), void, Reg, Reg, int)
DEF_HELPER_3(glue(pshufd, SUFFIX), void, Reg, Reg, int)
DEF_HELPER_3(glue(pshuflw, SUFFIX), void, Reg, Reg, int)
DEF_HELPER_3(glue(pshufhw, SUFFIX), void, Reg, Reg, int)
#endif
-#if SHIFT == 1
+#if SHIFT >= 1
/* FPU ops */
/* XXX: not accurate */
-#define SSE_HELPER_S(name, F) \
- DEF_HELPER_3(glue(name ## ps, SUFFIX), void, env, Reg, Reg) \
- DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
- DEF_HELPER_3(glue(name ## pd, SUFFIX), void, env, Reg, Reg) \
+#define SSE_HELPER_P4(name) \
+ DEF_HELPER_3(glue(name ## ps, SUFFIX), void, env, Reg, Reg) \
+ DEF_HELPER_3(glue(name ## pd, SUFFIX), void, env, Reg, Reg)
+
+#define SSE_HELPER_P3(name, ...) \
+ DEF_HELPER_3(glue(name ## ps, SUFFIX), void, env, Reg, Reg) \
+ DEF_HELPER_3(glue(name ## pd, SUFFIX), void, env, Reg, Reg)
+
+#if SHIFT == 1
+#define SSE_HELPER_S4(name) \
+ SSE_HELPER_P4(name) \
+ DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
DEF_HELPER_3(name ## sd, void, env, Reg, Reg)
+#define SSE_HELPER_S3(name) \
+ SSE_HELPER_P3(name) \
+ DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
+ DEF_HELPER_3(name ## sd, void, env, Reg, Reg)
+#else
+#define SSE_HELPER_S4(name, ...) SSE_HELPER_P4(name)
+#define SSE_HELPER_S3(name, ...) SSE_HELPER_P3(name)
+#endif
-SSE_HELPER_S(add, FPU_ADD)
-SSE_HELPER_S(sub, FPU_SUB)
-SSE_HELPER_S(mul, FPU_MUL)
-SSE_HELPER_S(div, FPU_DIV)
-SSE_HELPER_S(min, FPU_MIN)
-SSE_HELPER_S(max, FPU_MAX)
-SSE_HELPER_S(sqrt, FPU_SQRT)
+DEF_HELPER_3(glue(shufps, SUFFIX), void, Reg, Reg, int)
+DEF_HELPER_3(glue(shufpd, SUFFIX), void, Reg, Reg, int)
+SSE_HELPER_S4(add)
+SSE_HELPER_S4(sub)
+SSE_HELPER_S4(mul)
+SSE_HELPER_S4(div)
+SSE_HELPER_S4(min)
+SSE_HELPER_S4(max)
+
+SSE_HELPER_S3(sqrt)
DEF_HELPER_3(glue(cvtps2pd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(cvtpd2ps, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(cvtss2sd, void, env, Reg, Reg)
-DEF_HELPER_3(cvtsd2ss, void, env, Reg, Reg)
DEF_HELPER_3(glue(cvtdq2ps, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(cvtdq2pd, SUFFIX), void, env, Reg, Reg)
+
+DEF_HELPER_3(glue(cvtps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
+DEF_HELPER_3(glue(cvtpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
+
+DEF_HELPER_3(glue(cvttps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
+DEF_HELPER_3(glue(cvttpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
+
+#if SHIFT == 1
+DEF_HELPER_3(cvtss2sd, void, env, Reg, Reg)
+DEF_HELPER_3(cvtsd2ss, void, env, Reg, Reg)
DEF_HELPER_3(cvtpi2ps, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtpi2pd, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtsi2ss, void, env, ZMMReg, i32)
@@ -164,8 +191,6 @@ DEF_HELPER_3(cvtsq2ss, void, env, ZMMReg, i64)
DEF_HELPER_3(cvtsq2sd, void, env, ZMMReg, i64)
#endif
-DEF_HELPER_3(glue(cvtps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(glue(cvtpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(cvtps2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_3(cvtpd2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_2(cvtss2si, s32, env, ZMMReg)
@@ -175,8 +200,6 @@ DEF_HELPER_2(cvtss2sq, s64, env, ZMMReg)
DEF_HELPER_2(cvtsd2sq, s64, env, ZMMReg)
#endif
-DEF_HELPER_3(glue(cvttps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(glue(cvttpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(cvttps2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_3(cvttpd2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_2(cvttss2si, s32, env, ZMMReg)
@@ -185,27 +208,24 @@ DEF_HELPER_2(cvttsd2si, s32, env, ZMMReg)
DEF_HELPER_2(cvttss2sq, s64, env, ZMMReg)
DEF_HELPER_2(cvttsd2sq, s64, env, ZMMReg)
#endif
+#endif
DEF_HELPER_3(glue(rsqrtps, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(rsqrtss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(rcpps, SUFFIX), void, env, ZMMReg, ZMMReg)
+#if SHIFT == 1
+DEF_HELPER_3(rsqrtss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(rcpss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(extrq_r, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(extrq_i, void, env, ZMMReg, int, int)
DEF_HELPER_3(insertq_r, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(insertq_i, void, env, ZMMReg, int, int)
-DEF_HELPER_3(glue(haddps, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(glue(haddpd, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(glue(hsubps, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(glue(hsubpd, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(glue(addsubps, SUFFIX), void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(glue(addsubpd, SUFFIX), void, env, ZMMReg, ZMMReg)
+#endif
-#define SSE_HELPER_CMP(name, F, C) \
- DEF_HELPER_3(glue(name ## ps, SUFFIX), void, env, Reg, Reg) \
- DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
- DEF_HELPER_3(glue(name ## pd, SUFFIX), void, env, Reg, Reg) \
- DEF_HELPER_3(name ## sd, void, env, Reg, Reg)
+SSE_HELPER_P4(hadd)
+SSE_HELPER_P4(hsub)
+SSE_HELPER_P4(addsub)
+
+#define SSE_HELPER_CMP(name, F, C) SSE_HELPER_S4(name)
SSE_HELPER_CMP(cmpeq, FPU_CMPQ, FPU_EQ)
SSE_HELPER_CMP(cmplt, FPU_CMPS, FPU_LT)
@@ -216,10 +236,13 @@ SSE_HELPER_CMP(cmpnlt, FPU_CMPS, !FPU_LT)
SSE_HELPER_CMP(cmpnle, FPU_CMPS, !FPU_LE)
SSE_HELPER_CMP(cmpord, FPU_CMPQ, !FPU_UNORD)
+#if SHIFT == 1
DEF_HELPER_3(ucomiss, void, env, Reg, Reg)
DEF_HELPER_3(comiss, void, env, Reg, Reg)
DEF_HELPER_3(ucomisd, void, env, Reg, Reg)
DEF_HELPER_3(comisd, void, env, Reg, Reg)
+#endif
+
DEF_HELPER_2(glue(movmskps, SUFFIX), i32, env, Reg)
DEF_HELPER_2(glue(movmskpd, SUFFIX), i32, env, Reg)
#endif
@@ -236,7 +259,7 @@ DEF_HELPER_3(glue(packssdw, SUFFIX), void, env, Reg, Reg)
UNPCK_OP(l, 0)
UNPCK_OP(h, 1)
-#if SHIFT == 1
+#if SHIFT >= 1
DEF_HELPER_3(glue(punpcklqdq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(punpckhqdq, SUFFIX), void, env, Reg, Reg)
#endif
@@ -283,7 +306,7 @@ DEF_HELPER_3(glue(psignd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(palignr, SUFFIX), void, env, Reg, Reg, s32)
/* SSE4.1 op helpers */
-#if SHIFT == 1
+#if SHIFT >= 1
DEF_HELPER_3(glue(pblendvb, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(blendvps, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(blendvpd, SUFFIX), void, env, Reg, Reg)
@@ -312,22 +335,30 @@ DEF_HELPER_3(glue(pmaxsd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmaxuw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmaxud, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmulld, SUFFIX), void, env, Reg, Reg)
+#if SHIFT == 1
DEF_HELPER_3(glue(phminposuw, SUFFIX), void, env, Reg, Reg)
+#endif
DEF_HELPER_4(glue(roundps, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(roundpd, SUFFIX), void, env, Reg, Reg, i32)
+#if SHIFT == 1
DEF_HELPER_4(glue(roundss, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(roundsd, SUFFIX), void, env, Reg, Reg, i32)
+#endif
DEF_HELPER_4(glue(blendps, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(blendpd, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(pblendw, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(dpps, SUFFIX), void, env, Reg, Reg, i32)
+#if SHIFT == 1
DEF_HELPER_4(glue(dppd, SUFFIX), void, env, Reg, Reg, i32)
+#endif
DEF_HELPER_4(glue(mpsadbw, SUFFIX), void, env, Reg, Reg, i32)
#endif
/* SSE4.2 op helpers */
-#if SHIFT == 1
+#if SHIFT >= 1
DEF_HELPER_3(glue(pcmpgtq, SUFFIX), void, env, Reg, Reg)
+#endif
+#if SHIFT == 1
DEF_HELPER_4(glue(pcmpestri, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(pcmpestrm, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(pcmpistri, SUFFIX), void, env, Reg, Reg, i32)
@@ -336,13 +367,15 @@ DEF_HELPER_3(crc32, tl, i32, tl, i32)
#endif
/* AES-NI op helpers */
-#if SHIFT == 1
+#if SHIFT >= 1
DEF_HELPER_3(glue(aesdec, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(aesdeclast, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(aesenc, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(aesenclast, SUFFIX), void, env, Reg, Reg)
+#if SHIFT == 1
DEF_HELPER_3(glue(aesimc, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(aeskeygenassist, SUFFIX), void, env, Reg, Reg, i32)
+#endif
DEF_HELPER_4(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, i32)
#endif
@@ -354,6 +387,9 @@ DEF_HELPER_4(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, i32)
#undef SSE_HELPER_W
#undef SSE_HELPER_L
#undef SSE_HELPER_Q
-#undef SSE_HELPER_S
+#undef SSE_HELPER_S3
+#undef SSE_HELPER_S4
+#undef SSE_HELPER_P3
+#undef SSE_HELPER_P4
#undef SSE_HELPER_CMP
#undef UNPCK_OP
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 14/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX
2022-09-11 23:03 ` [PATCH 14/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
@ 2022-09-12 11:09 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 11:09 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: Paul Brook
On 9/12/22 00:03, Paolo Bonzini wrote:
> From: Paul Brook<paul@nowt.org>
>
> Adjust all #ifdefs to match the ones in ops_sse.h.
>
> Signed-off-by: Paul Brook<paul@nowt.org>
> Message-Id:<20220424220204.2493824-23-paul@nowt.org>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/ops_sse_header.h | 114 +++++++++++++++++++++++------------
> 1 file changed, 75 insertions(+), 39 deletions(-)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 15/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (13 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 14/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:11 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 16/37] target/i386: support operand merging in binary scalar helpers Paolo Bonzini
` (21 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Add to the helpers all the operands that are needed to implement AVX.
Extracted from a patch by Paul Brook <paul@nowt.org>.
Message-Id: <20220424220204.2493824-26-paul@nowt.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 173 +++++++++++++--------------------
| 149 ++++++++++++++--------------
target/i386/tcg/translate.c | 181 ++++++++++++++++++++++++-----------
3 files changed, 265 insertions(+), 238 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index c0766de18d..fb8733f509 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -48,9 +48,8 @@
#define FPSLL(x, c) ((x) << shift)
#endif
-void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 15) {
for (int i = 0; i < 1 << SHIFT; i++) {
@@ -64,9 +63,8 @@ void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 15) {
for (int i = 0; i < 1 << SHIFT; i++) {
@@ -80,9 +78,8 @@ void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 15) {
shift = 15;
@@ -94,9 +91,8 @@ void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 31) {
for (int i = 0; i < 1 << SHIFT; i++) {
@@ -110,9 +106,8 @@ void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_pslld, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_pslld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 31) {
for (int i = 0; i < 1 << SHIFT; i++) {
@@ -126,9 +121,8 @@ void glue(helper_pslld, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_psrad, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psrad, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 31) {
shift = 31;
@@ -140,9 +134,8 @@ void glue(helper_psrad, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_psrlq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psrlq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 63) {
for (int i = 0; i < 1 << SHIFT; i++) {
@@ -156,9 +149,8 @@ void glue(helper_psrlq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_psllq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psllq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift;
if (c->Q(0) > 63) {
for (int i = 0; i < 1 << SHIFT; i++) {
@@ -173,9 +165,8 @@ void glue(helper_psllq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
#if SHIFT >= 1
-void glue(helper_psrldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_psrldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift, i, j;
shift = c->L(0);
@@ -192,9 +183,8 @@ void glue(helper_psrldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
}
-void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
+void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, Reg *c)
{
- Reg *s = d;
int shift, i, j;
shift = c->L(0);
@@ -222,9 +212,8 @@ void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *c)
}
#define SSE_HELPER_2(name, elem, num, F) \
- void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
+ void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
int n = num; \
for (int i = 0; i < n; i++) { \
d->elem(i) = F(v->elem(i), s->elem(i)); \
@@ -362,18 +351,24 @@ SSE_HELPER_W(helper_pcmpeqw, FCMPEQ)
SSE_HELPER_L(helper_pcmpeql, FCMPEQ)
SSE_HELPER_W(helper_pmullw, FMULLW)
-#if SHIFT == 0
-SSE_HELPER_W(helper_pmulhrw, FMULHRW)
-#endif
SSE_HELPER_W(helper_pmulhuw, FMULHUW)
SSE_HELPER_W(helper_pmulhw, FMULHW)
+#if SHIFT == 0
+void glue(helper_pmulhrw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+{
+ d->W(0) = FMULHRW(d->W(0), s->W(0));
+ d->W(1) = FMULHRW(d->W(1), s->W(1));
+ d->W(2) = FMULHRW(d->W(2), s->W(2));
+ d->W(3) = FMULHRW(d->W(3), s->W(3));
+}
+#endif
+
SSE_HELPER_B(helper_pavgb, FAVG)
SSE_HELPER_W(helper_pavgw, FAVG)
-void glue(helper_pmuludq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_pmuludq, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
for (i = 0; i < (1 << SHIFT); i++) {
@@ -381,9 +376,8 @@ void glue(helper_pmuludq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
}
-void glue(helper_pmaddwd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_pmaddwd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
for (i = 0; i < (2 << SHIFT); i++) {
@@ -402,10 +396,8 @@ static inline int abs1(int a)
}
}
#endif
-
-void glue(helper_psadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_psadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
for (i = 0; i < (1 << SHIFT); i++) {
@@ -478,9 +470,8 @@ void glue(helper_pshufw, SUFFIX)(Reg *d, Reg *s, int order)
SHUFFLE4(W, s, s, 0);
}
#else
-void glue(helper_shufps, SUFFIX)(Reg *d, Reg *s, int order)
+void glue(helper_shufps, SUFFIX)(Reg *d, Reg *v, Reg *s, int order)
{
- Reg *v = d;
uint32_t r0, r1, r2, r3;
int i;
@@ -489,9 +480,8 @@ void glue(helper_shufps, SUFFIX)(Reg *d, Reg *s, int order)
}
}
-void glue(helper_shufpd, SUFFIX)(Reg *d, Reg *s, int order)
+void glue(helper_shufpd, SUFFIX)(Reg *d, Reg *v, Reg *s, int order)
{
- Reg *v = d;
uint64_t r0, r1;
int i;
@@ -543,9 +533,8 @@ void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order)
#define SSE_HELPER_P(name, F) \
void glue(helper_ ## name ## ps, SUFFIX)(CPUX86State *env, \
- Reg *d, Reg *s) \
+ Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
int i; \
for (i = 0; i < 2 << SHIFT; i++) { \
d->ZMM_S(i) = F(32, v->ZMM_S(i), s->ZMM_S(i)); \
@@ -553,9 +542,8 @@ void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order)
} \
\
void glue(helper_ ## name ## pd, SUFFIX)(CPUX86State *env, \
- Reg *d, Reg *s) \
+ Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
int i; \
for (i = 0; i < 1 << SHIFT; i++) { \
d->ZMM_D(i) = F(64, v->ZMM_D(i), s->ZMM_D(i)); \
@@ -567,15 +555,13 @@ void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order)
#define SSE_HELPER_S(name, F) \
SSE_HELPER_P(name, F) \
\
- void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s)\
+ void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *v, Reg *s)\
{ \
- Reg *v = d; \
d->ZMM_S(0) = F(32, v->ZMM_S(0), s->ZMM_S(0)); \
} \
\
- void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s)\
+ void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *v, Reg *s)\
{ \
- Reg *v = d; \
d->ZMM_D(0) = F(64, v->ZMM_D(0), s->ZMM_D(0)); \
}
@@ -958,9 +944,8 @@ void helper_insertq_i(CPUX86State *env, ZMMReg *d, int index, int length)
#endif
#define SSE_HELPER_HPS(name, F) \
-void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
+void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
float32 r[2 << SHIFT]; \
int i, j, k; \
for (k = 0; k < 2 << SHIFT; k += LANE_WIDTH / 4) { \
@@ -980,9 +965,8 @@ SSE_HELPER_HPS(haddps, float32_add)
SSE_HELPER_HPS(hsubps, float32_sub)
#define SSE_HELPER_HPD(name, F) \
-void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
+void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
float64 r[1 << SHIFT]; \
int i, j, k; \
for (k = 0; k < 1 << SHIFT; k += LANE_WIDTH / 8) { \
@@ -1001,9 +985,8 @@ void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
SSE_HELPER_HPD(haddpd, float64_add)
SSE_HELPER_HPD(hsubpd, float64_sub)
-void glue(helper_addsubps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_addsubps, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
for (i = 0; i < 2 << SHIFT; i += 2) {
d->ZMM_S(i) = float32_sub(v->ZMM_S(i), s->ZMM_S(i), &env->sse_status);
@@ -1011,9 +994,8 @@ void glue(helper_addsubps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
}
-void glue(helper_addsubpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_addsubpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
for (i = 0; i < 1 << SHIFT; i += 2) {
d->ZMM_D(i) = float64_sub(v->ZMM_D(i), s->ZMM_D(i), &env->sse_status);
@@ -1023,9 +1005,8 @@ void glue(helper_addsubpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
#define SSE_HELPER_CMP_P(name, F, C) \
void glue(helper_ ## name ## ps, SUFFIX)(CPUX86State *env, \
- Reg *d, Reg *s) \
+ Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
int i; \
for (i = 0; i < 2 << SHIFT; i++) { \
d->ZMM_L(i) = C(F(32, v->ZMM_S(i), s->ZMM_S(i))) ? -1 : 0; \
@@ -1033,9 +1014,8 @@ void glue(helper_addsubpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
} \
\
void glue(helper_ ## name ## pd, SUFFIX)(CPUX86State *env, \
- Reg *d, Reg *s) \
+ Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
int i; \
for (i = 0; i < 1 << SHIFT; i++) { \
d->ZMM_Q(i) = C(F(64, v->ZMM_D(i), s->ZMM_D(i))) ? -1 : 0; \
@@ -1045,15 +1025,13 @@ void glue(helper_addsubpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
#if SHIFT == 1
#define SSE_HELPER_CMP(name, F, C) \
SSE_HELPER_CMP_P(name, F, C) \
- void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \
+ void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
d->ZMM_L(0) = C(F(32, v->ZMM_S(0), s->ZMM_S(0))) ? -1 : 0; \
} \
\
- void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \
+ void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
d->ZMM_Q(0) = C(F(64, v->ZMM_D(0), s->ZMM_D(0))) ? -1 : 0; \
}
@@ -1179,9 +1157,8 @@ uint32_t glue(helper_pmovmskb, SUFFIX)(CPUX86State *env, Reg *s)
#define PACK_HELPER_B(name, F) \
void glue(helper_pack ## name, SUFFIX)(CPUX86State *env, \
- Reg *d, Reg *s) \
+ Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
uint8_t r[PACK_WIDTH * 2]; \
int j, k; \
for (j = 0; j < 4 << SHIFT; j += PACK_WIDTH) { \
@@ -1200,9 +1177,8 @@ void glue(helper_pack ## name, SUFFIX)(CPUX86State *env, \
PACK_HELPER_B(sswb, satsb)
PACK_HELPER_B(uswb, satub)
-void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
uint16_t r[PACK_WIDTH];
int j, k;
@@ -1222,9 +1198,8 @@ void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
#define UNPCK_OP(base_name, base) \
- Reg *v = d; \
uint8_t r[PACK_WIDTH * 2]; \
int j, i; \
\
@@ -1241,9 +1216,8 @@ void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
} \
\
void glue(helper_punpck ## base_name ## wd, SUFFIX)(CPUX86State *env,\
- Reg *d, Reg *s) \
+ Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
uint16_t r[PACK_WIDTH]; \
int j, i; \
\
@@ -1260,9 +1234,8 @@ void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
} \
\
void glue(helper_punpck ## base_name ## dq, SUFFIX)(CPUX86State *env,\
- Reg *d, Reg *s) \
+ Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
uint32_t r[PACK_WIDTH / 2]; \
int j, i; \
\
@@ -1280,9 +1253,8 @@ void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
\
XMM_ONLY( \
void glue(helper_punpck ## base_name ## qdq, SUFFIX)( \
- CPUX86State *env, Reg *d, Reg *s) \
+ CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
uint64_t r[2]; \
int i; \
\
@@ -1453,9 +1425,8 @@ void helper_pswapd(CPUX86State *env, MMXReg *d, MMXReg *s)
#endif
/* SSSE3 op helpers */
-void glue(helper_pshufb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_pshufb, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
#if SHIFT == 0
uint8_t r[8];
@@ -1480,9 +1451,8 @@ void glue(helper_pshufb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
#define SSE_HELPER_HW(name, F) \
-void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
+void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
uint16_t r[4 << SHIFT]; \
int i, j, k; \
for (k = 0; k < 4 << SHIFT; k += LANE_WIDTH / 2) { \
@@ -1499,9 +1469,8 @@ void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
}
#define SSE_HELPER_HL(name, F) \
-void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
+void glue(helper_ ## name, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
- Reg *v = d; \
uint32_t r[2 << SHIFT]; \
int i, j, k; \
for (k = 0; k < 2 << SHIFT; k += LANE_WIDTH / 4) { \
@@ -1527,9 +1496,8 @@ SSE_HELPER_HL(phsubd, FSUB)
#undef SSE_HELPER_HW
#undef SSE_HELPER_HL
-void glue(helper_pmaddubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_pmaddubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
for (i = 0; i < 4 << SHIFT; i++) {
d->W(i) = satsw((int8_t)s->B(i * 2) * (uint8_t)v->B(i * 2) +
@@ -1554,10 +1522,9 @@ SSE_HELPER_B(helper_psignb, FSIGNB)
SSE_HELPER_W(helper_psignw, FSIGNW)
SSE_HELPER_L(helper_psignd, FSIGNL)
-void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
+void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
int32_t shift)
{
- Reg *v = d;
int i;
/* XXX could be checked during translation */
@@ -1594,10 +1561,9 @@ void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
#if SHIFT >= 1
#define SSE_HELPER_V(name, elem, num, F) \
- void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
+ void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s, \
+ Reg *m) \
{ \
- Reg *v = d; \
- Reg *m = &env->xmm_regs[0]; \
int i; \
for (i = 0; i < num; i++) { \
d->elem(i) = F(v->elem(i), s->elem(i), m->elem(i)); \
@@ -1605,10 +1571,9 @@ void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
#define SSE_HELPER_I(name, elem, num, F) \
- void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, \
+ void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s, \
uint32_t imm) \
{ \
- Reg *v = d; \
int i; \
for (i = 0; i < num; i++) { \
int j = i & 7; \
@@ -1660,9 +1625,8 @@ SSE_HELPER_F(helper_pmovzxwq, Q, 1 << SHIFT, s->W)
SSE_HELPER_F(helper_pmovzxdq, Q, 1 << SHIFT, s->L)
#endif
-void glue(helper_pmuldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_pmuldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
int i;
for (i = 0; i < 1 << SHIFT; i++) {
@@ -1673,9 +1637,8 @@ void glue(helper_pmuldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
#define FCMPEQQ(d, s) (d == s ? -1 : 0)
SSE_HELPER_Q(helper_pcmpeqq, FCMPEQQ)
-void glue(helper_packusdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_packusdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
- Reg *v = d;
uint16_t r[8];
int i, j, k;
@@ -1893,10 +1856,9 @@ SSE_HELPER_I(helper_blendps, L, 2 << SHIFT, FBLENDP)
SSE_HELPER_I(helper_blendpd, Q, 1 << SHIFT, FBLENDP)
SSE_HELPER_I(helper_pblendw, W, 4 << SHIFT, FBLENDP)
-void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
+void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
uint32_t mask)
{
- Reg *v = d;
float32 prod1, prod2, temp2, temp3, temp4;
int i;
@@ -1939,9 +1901,8 @@ void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
#if SHIFT == 1
/* Oddly, there is no ymm version of dppd */
void glue(helper_dppd, SUFFIX)(CPUX86State *env,
- Reg *d, Reg *s, uint32_t mask)
+ Reg *d, Reg *v, Reg *s, uint32_t mask)
{
- Reg *v = d;
float64 prod1, prod2, temp2;
if (mask & (1 << 4)) {
@@ -1960,10 +1921,9 @@ void glue(helper_dppd, SUFFIX)(CPUX86State *env,
}
#endif
-void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
+void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
uint32_t offset)
{
- Reg *v = d;
int i, j;
uint16_t r[8];
@@ -2236,10 +2196,9 @@ static void clmulq(uint64_t *dest_l, uint64_t *dest_h,
}
#endif
-void glue(helper_pclmulqdq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
+void glue(helper_pclmulqdq, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
uint32_t ctrl)
{
- Reg *v = d;
uint64_t a, b;
int i;
@@ -2250,10 +2209,10 @@ void glue(helper_pclmulqdq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
}
-void glue(helper_aesdec, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_aesdec, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
- Reg st = *d;
+ Reg st = *v;
Reg rk = *s;
for (i = 0 ; i < 2 << SHIFT ; i++) {
@@ -2265,10 +2224,10 @@ void glue(helper_aesdec, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
}
-void glue(helper_aesdeclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_aesdeclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
- Reg st = *d;
+ Reg st = *v;
Reg rk = *s;
for (i = 0; i < 8 << SHIFT; i++) {
@@ -2276,10 +2235,10 @@ void glue(helper_aesdeclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
}
-void glue(helper_aesenc, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_aesenc, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
- Reg st = *d;
+ Reg st = *v;
Reg rk = *s;
for (i = 0 ; i < 2 << SHIFT ; i++) {
@@ -2291,10 +2250,10 @@ void glue(helper_aesenc, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
}
-void glue(helper_aesenclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+void glue(helper_aesenclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
- Reg st = *d;
+ Reg st = *v;
Reg rk = *s;
for (i = 0; i < 8 << SHIFT; i++) {
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 7f57dab496..21fed7fa05 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -34,31 +34,31 @@
#define dh_typecode_ZMMReg dh_typecode_ptr
#define dh_typecode_MMXReg dh_typecode_ptr
-DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psrld, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psrad, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pslld, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psrlq, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psllq, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(psrlw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psraw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psllw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psrld, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psrad, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pslld, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psrlq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psllq, SUFFIX), void, env, Reg, Reg, Reg)
#if SHIFT >= 1
-DEF_HELPER_3(glue(psrldq, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pslldq, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(psrldq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pslldq, SUFFIX), void, env, Reg, Reg, Reg)
#endif
#define SSE_HELPER_B(name, F)\
- DEF_HELPER_3(glue(name, SUFFIX), void, env, Reg, Reg)
+ DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
#define SSE_HELPER_W(name, F)\
- DEF_HELPER_3(glue(name, SUFFIX), void, env, Reg, Reg)
+ DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
#define SSE_HELPER_L(name, F)\
- DEF_HELPER_3(glue(name, SUFFIX), void, env, Reg, Reg)
+ DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
#define SSE_HELPER_Q(name, F)\
- DEF_HELPER_3(glue(name, SUFFIX), void, env, Reg, Reg)
+ DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
SSE_HELPER_B(paddb, FADD)
SSE_HELPER_W(paddw, FADD)
@@ -109,10 +109,10 @@ SSE_HELPER_W(pmulhw, FMULHW)
SSE_HELPER_B(pavgb, FAVG)
SSE_HELPER_W(pavgw, FAVG)
-DEF_HELPER_3(glue(pmuludq, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmaddwd, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(pmuludq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pmaddwd, SUFFIX), void, env, Reg, Reg, Reg)
-DEF_HELPER_3(glue(psadbw, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(psadbw, SUFFIX), void, env, Reg, Reg, Reg)
#if SHIFT < 2
DEF_HELPER_4(glue(maskmov, SUFFIX), void, env, Reg, Reg, tl)
#endif
@@ -134,8 +134,8 @@ DEF_HELPER_3(glue(pshufhw, SUFFIX), void, Reg, Reg, int)
/* XXX: not accurate */
#define SSE_HELPER_P4(name) \
- DEF_HELPER_3(glue(name ## ps, SUFFIX), void, env, Reg, Reg) \
- DEF_HELPER_3(glue(name ## pd, SUFFIX), void, env, Reg, Reg)
+ DEF_HELPER_4(glue(name ## ps, SUFFIX), void, env, Reg, Reg, Reg) \
+ DEF_HELPER_4(glue(name ## pd, SUFFIX), void, env, Reg, Reg, Reg)
#define SSE_HELPER_P3(name, ...) \
DEF_HELPER_3(glue(name ## ps, SUFFIX), void, env, Reg, Reg) \
@@ -144,8 +144,8 @@ DEF_HELPER_3(glue(pshufhw, SUFFIX), void, Reg, Reg, int)
#if SHIFT == 1
#define SSE_HELPER_S4(name) \
SSE_HELPER_P4(name) \
- DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
- DEF_HELPER_3(name ## sd, void, env, Reg, Reg)
+ DEF_HELPER_4(name ## ss, void, env, Reg, Reg, Reg) \
+ DEF_HELPER_4(name ## sd, void, env, Reg, Reg, Reg)
#define SSE_HELPER_S3(name) \
SSE_HELPER_P3(name) \
DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
@@ -155,8 +155,8 @@ DEF_HELPER_3(glue(pshufhw, SUFFIX), void, Reg, Reg, int)
#define SSE_HELPER_S3(name, ...) SSE_HELPER_P3(name)
#endif
-DEF_HELPER_3(glue(shufps, SUFFIX), void, Reg, Reg, int)
-DEF_HELPER_3(glue(shufpd, SUFFIX), void, Reg, Reg, int)
+DEF_HELPER_4(glue(shufps, SUFFIX), void, Reg, Reg, Reg, int)
+DEF_HELPER_4(glue(shufpd, SUFFIX), void, Reg, Reg, Reg, int)
SSE_HELPER_S4(add)
SSE_HELPER_S4(sub)
@@ -212,6 +212,7 @@ DEF_HELPER_2(cvttsd2sq, s64, env, ZMMReg)
DEF_HELPER_3(glue(rsqrtps, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(rcpps, SUFFIX), void, env, ZMMReg, ZMMReg)
+
#if SHIFT == 1
DEF_HELPER_3(rsqrtss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(rcpss, void, env, ZMMReg, ZMMReg)
@@ -248,20 +249,20 @@ DEF_HELPER_2(glue(movmskpd, SUFFIX), i32, env, Reg)
#endif
DEF_HELPER_2(glue(pmovmskb, SUFFIX), i32, env, Reg)
-DEF_HELPER_3(glue(packsswb, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(packuswb, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(packssdw, SUFFIX), void, env, Reg, Reg)
-#define UNPCK_OP(base_name, base) \
- DEF_HELPER_3(glue(punpck ## base_name ## bw, SUFFIX), void, env, Reg, Reg) \
- DEF_HELPER_3(glue(punpck ## base_name ## wd, SUFFIX), void, env, Reg, Reg) \
- DEF_HELPER_3(glue(punpck ## base_name ## dq, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(packsswb, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(packuswb, SUFFIX)# name ## dq, SUFFIX), void, env, Reg, Reg, Reg)
UNPCK_OP(l, 0)
UNPCK_OP(h, 1)
#if SHIFT >= 1
-DEF_HELPER_3(glue(punpcklqdq, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(punpckhqdq, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(punpcklqdq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(punpckhqdq, SUFFIX), void, env, Reg, Reg, Reg)
#endif
/* 3DNow! float ops */
@@ -288,28 +289,28 @@ DEF_HELPER_3(pswapd, void, env, MMXReg, MMXReg)
#endif
/* SSSE3 op helpers */
-DEF_HELPER_3(glue(phaddw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(phaddd, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(phaddsw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(phsubw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(phsubd, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(phsubsw, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(phaddw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(phaddd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(phaddsw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(phsubw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(phsubd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(phsubsw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_3(glue(pabsb, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pabsw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pabsd, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmaddubsw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmulhrsw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pshufb, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psignb, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psignw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(psignd, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_4(glue(palignr, SUFFIX), void, env, Reg, Reg, s32)
+DEF_HELPER_4(glue(pmaddubsw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pmulhrsw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pshufb, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psignb, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psignw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(psignd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_5(glue(palignr, SUFFIX), void, env, Reg, Reg, Reg, s32)
/* SSE4.1 op helpers */
#if SHIFT >= 1
-DEF_HELPER_3(glue(pblendvb, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(blendvps, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(blendvpd, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_5(glue(pblendvb, SUFFIX), void, env, Reg, Reg, Reg, Reg)
+DEF_HELPER_5(glue(blendvps, SUFFIX), void, env, Reg, Reg, Reg, Reg)
+DEF_HELPER_5(glue(blendvpd, SUFFIX), void, env, Reg, Reg, Reg, Reg)
DEF_HELPER_3(glue(ptest, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxbw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxbd, SUFFIX), void, env, Reg, Reg)
@@ -323,40 +324,40 @@ DEF_HELPER_3(glue(pmovzxbq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxwd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxwq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxdq, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmuldq, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pcmpeqq, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(packusdw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pminsb, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pminsd, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pminuw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pminud, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmaxsb, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmaxsd, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmaxuw, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmaxud, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(pmulld, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(pmuldq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pcmpeqq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(packusdw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pminsb, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pminsd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pminuw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pminud, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pmaxsb, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pmaxsd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pmaxuw, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pmaxud, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(pmulld, SUFFIX), void, env, Reg, Reg, Reg)
#if SHIFT == 1
DEF_HELPER_3(glue(phminposuw, SUFFIX), void, env, Reg, Reg)
#endif
DEF_HELPER_4(glue(roundps, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(roundpd, SUFFIX), void, env, Reg, Reg, i32)
#if SHIFT == 1
-DEF_HELPER_4(glue(roundss, SUFFIX), void, env, Reg, Reg, i32)
-DEF_HELPER_4(glue(roundsd, SUFFIX), void, env, Reg, Reg, i32)
+DEF_HELPER_4(roundss_xmm, void, env, Reg, Reg, i32)
+DEF_HELPER_4(roundsd_xmm, void, env, Reg, Reg, i32)
#endif
-DEF_HELPER_4(glue(blendps, SUFFIX), void, env, Reg, Reg, i32)
-DEF_HELPER_4(glue(blendpd, SUFFIX), void, env, Reg, Reg, i32)
-DEF_HELPER_4(glue(pblendw, SUFFIX), void, env, Reg, Reg, i32)
-DEF_HELPER_4(glue(dpps, SUFFIX), void, env, Reg, Reg, i32)
+DEF_HELPER_5(glue(blendps, SUFFIX), void, env, Reg, Reg, Reg, i32)
+DEF_HELPER_5(glue(blendpd, SUFFIX), void, env, Reg, Reg, Reg, i32)
+DEF_HELPER_5(glue(pblendw, SUFFIX), void, env, Reg, Reg, Reg, i32)
+DEF_HELPER_5(glue(dpps, SUFFIX), void, env, Reg, Reg, Reg, i32)
#if SHIFT == 1
-DEF_HELPER_4(glue(dppd, SUFFIX), void, env, Reg, Reg, i32)
+DEF_HELPER_5(glue(dppd, SUFFIX), void, env, Reg, Reg, Reg, i32)
#endif
-DEF_HELPER_4(glue(mpsadbw, SUFFIX), void, env, Reg, Reg, i32)
+DEF_HELPER_5(glue(mpsadbw, SUFFIX), void, env, Reg, Reg, Reg, i32)
#endif
/* SSE4.2 op helpers */
#if SHIFT >= 1
-DEF_HELPER_3(glue(pcmpgtq, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(pcmpgtq, SUFFIX), void, env, Reg, Reg, Reg)
#endif
#if SHIFT == 1
DEF_HELPER_4(glue(pcmpestri, SUFFIX), void, env, Reg, Reg, i32)
@@ -368,15 +369,15 @@ DEF_HELPER_3(crc32, tl, i32, tl, i32)
/* AES-NI op helpers */
#if SHIFT >= 1
-DEF_HELPER_3(glue(aesdec, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(aesdeclast, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(aesenc, SUFFIX), void, env, Reg, Reg)
-DEF_HELPER_3(glue(aesenclast, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(aesdec, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(aesdeclast, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(aesenc, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(aesenclast, SUFFIX), void, env, Reg, Reg, Reg)
#if SHIFT == 1
DEF_HELPER_3(glue(aesimc, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(aeskeygenassist, SUFFIX), void, env, Reg, Reg, i32)
#endif
-DEF_HELPER_4(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, i32)
+DEF_HELPER_5(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, Reg, i32)
#endif
#undef SHIFT
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 240811bd49..e996aab541 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -129,6 +129,7 @@ typedef struct DisasContext {
TCGv tmp4;
TCGv_ptr ptr0;
TCGv_ptr ptr1;
+ TCGv_ptr ptr2;
TCGv_i32 tmp2_i32;
TCGv_i32 tmp3_i32;
TCGv_i64 tmp1_i64;
@@ -2893,18 +2894,28 @@ typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val);
typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b);
typedef void (*SSEFunc_0_eppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
TCGv_ptr reg_c);
+typedef void (*SSEFunc_0_epppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
+ TCGv_ptr reg_c, TCGv_ptr reg_d);
typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
TCGv_i32 val);
+typedef void (*SSEFunc_0_epppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
+ TCGv_ptr reg_c, TCGv_i32 val);
typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
+typedef void (*SSEFunc_0_pppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_ptr reg_c,
+ TCGv_i32 val);
typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
TCGv val);
+typedef void (*SSEFunc_0_epppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
+ TCGv_ptr reg_c, TCGv val);
static bool first = true; static unsigned long limit;
#include "decode-new.h"
#include "emit.c.inc"
#include "decode-new.c.inc"
+#define SSE_OPF_V0 (1 << 0) /* vex.v must be 1111b (only 2 operands) */
#define SSE_OPF_CMP (1 << 1) /* does not write for first operand */
+#define SSE_OPF_BLENDV (1 << 2) /* blendv* instruction */
#define SSE_OPF_SPECIAL (1 << 3) /* magic */
#define SSE_OPF_3DNOW (1 << 4) /* 3DNow! instruction */
#define SSE_OPF_MMX (1 << 5) /* MMX/integer/AVX2 instruction */
@@ -2914,10 +2925,10 @@ static bool first = true; static unsigned long limit;
#define OP(op, flags, a, b, c, d) \
{flags, {{.op = a}, {.op = b}, {.op = c}, {.op = d} } }
-#define MMX_OP(x) OP(op1, SSE_OPF_MMX, \
+#define MMX_OP(x) OP(op2, SSE_OPF_MMX, \
gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm, NULL, NULL)
-#define SSE_FOP(name) OP(op1, SSE_OPF_SCALAR, \
+#define SSE_FOP(name) OP(op2, SSE_OPF_SCALAR, \
gen_helper_##name##ps##_xmm, gen_helper_##name##pd##_xmm, \
gen_helper_##name##ss, gen_helper_##name##sd)
#define SSE_OP(sname, dname, op, flags) OP(op, flags, \
@@ -2927,6 +2938,9 @@ typedef union SSEFuncs {
SSEFunc_0_epp op1;
SSEFunc_0_ppi op1i;
SSEFunc_0_eppt op1t;
+ SSEFunc_0_eppp op2;
+ SSEFunc_0_pppi op2i;
+ SSEFunc_0_epppp op3;
} SSEFuncs;
struct SSEOpHelper_table1 {
@@ -2946,8 +2960,8 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x11] = SSE_SPECIAL, /* movups, movupd, movss, movsd */
[0x12] = SSE_SPECIAL, /* movlps, movlpd, movsldup, movddup */
[0x13] = SSE_SPECIAL, /* movlps, movlpd */
- [0x14] = SSE_OP(punpckldq, punpcklqdq, op1, 0), /* unpcklps, unpcklpd */
- [0x15] = SSE_OP(punpckhdq, punpckhqdq, op1, 0), /* unpckhps, unpckhpd */
+ [0x14] = SSE_OP(punpckldq, punpcklqdq, op2, 0), /* unpcklps, unpcklpd */
+ [0x15] = SSE_OP(punpckhdq, punpckhqdq, op2, 0), /* unpckhps, unpckhpd */
[0x16] = SSE_SPECIAL, /* movhps, movhpd, movshdup */
[0x17] = SSE_SPECIAL, /* movhps, movhpd */
@@ -2957,28 +2971,28 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x2b] = SSE_SPECIAL, /* movntps, movntpd, movntss, movntsd */
[0x2c] = SSE_SPECIAL, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
[0x2d] = SSE_SPECIAL, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
- [0x2e] = OP(op1, SSE_OPF_CMP | SSE_OPF_SCALAR,
+ [0x2e] = OP(op1, SSE_OPF_CMP | SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_ucomiss, gen_helper_ucomisd, NULL, NULL),
- [0x2f] = OP(op1, SSE_OPF_CMP | SSE_OPF_SCALAR,
+ [0x2f] = OP(op1, SSE_OPF_CMP | SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_comiss, gen_helper_comisd, NULL, NULL),
[0x50] = SSE_SPECIAL, /* movmskps, movmskpd */
- [0x51] = OP(op1, SSE_OPF_SCALAR,
+ [0x51] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_sqrtps_xmm, gen_helper_sqrtpd_xmm,
gen_helper_sqrtss, gen_helper_sqrtsd),
- [0x52] = OP(op1, SSE_OPF_SCALAR,
+ [0x52] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_rsqrtps_xmm, NULL, gen_helper_rsqrtss, NULL),
- [0x53] = OP(op1, SSE_OPF_SCALAR,
+ [0x53] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_rcpps_xmm, NULL, gen_helper_rcpss, NULL),
- [0x54] = SSE_OP(pand, pand, op1, 0), /* andps, andpd */
- [0x55] = SSE_OP(pandn, pandn, op1, 0), /* andnps, andnpd */
- [0x56] = SSE_OP(por, por, op1, 0), /* orps, orpd */
- [0x57] = SSE_OP(pxor, pxor, op1, 0), /* xorps, xorpd */
+ [0x54] = SSE_OP(pand, pand, op2, 0), /* andps, andpd */
+ [0x55] = SSE_OP(pandn, pandn, op2, 0), /* andnps, andnpd */
+ [0x56] = SSE_OP(por, por, op2, 0), /* orps, orpd */
+ [0x57] = SSE_OP(pxor, pxor, op2, 0), /* xorps, xorpd */
[0x58] = SSE_FOP(add),
[0x59] = SSE_FOP(mul),
- [0x5a] = OP(op1, SSE_OPF_SCALAR,
+ [0x5a] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_cvtps2pd_xmm, gen_helper_cvtpd2ps_xmm,
gen_helper_cvtss2sd, gen_helper_cvtsd2ss),
- [0x5b] = OP(op1, 0,
+ [0x5b] = OP(op1, SSE_OPF_V0,
gen_helper_cvtdq2ps_xmm, gen_helper_cvtps2dq_xmm,
gen_helper_cvttps2dq_xmm, NULL),
[0x5c] = SSE_FOP(sub),
@@ -2987,7 +3001,7 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x5f] = SSE_FOP(max),
[0xc2] = SSE_FOP(cmpeq), /* sse_op_table4 */
- [0xc6] = SSE_OP(shufps, shufpd, op1i, SSE_OPF_SHUF),
+ [0xc6] = SSE_OP(shufps, shufpd, op2i, SSE_OPF_SHUF),
/* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
[0x38] = SSE_SPECIAL,
@@ -3006,13 +3020,13 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x69] = MMX_OP(punpckhwd),
[0x6a] = MMX_OP(punpckhdq),
[0x6b] = MMX_OP(packssdw),
- [0x6c] = OP(op1, SSE_OPF_MMX,
+ [0x6c] = OP(op2, SSE_OPF_MMX,
NULL, gen_helper_punpcklqdq_xmm, NULL, NULL),
- [0x6d] = OP(op1, SSE_OPF_MMX,
+ [0x6d] = OP(op2, SSE_OPF_MMX,
NULL, gen_helper_punpckhqdq_xmm, NULL, NULL),
[0x6e] = SSE_SPECIAL, /* movd mm, ea */
[0x6f] = SSE_SPECIAL, /* movq, movdqa, , movqdu */
- [0x70] = OP(op1i, SSE_OPF_SHUF | SSE_OPF_MMX,
+ [0x70] = OP(op1i, SSE_OPF_SHUF | SSE_OPF_MMX | SSE_OPF_V0,
gen_helper_pshufw_mmx, gen_helper_pshufd_xmm,
gen_helper_pshufhw_xmm, gen_helper_pshuflw_xmm),
[0x71] = SSE_SPECIAL, /* shiftw */
@@ -3023,17 +3037,17 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x76] = MMX_OP(pcmpeql),
[0x77] = SSE_SPECIAL, /* emms */
[0x78] = SSE_SPECIAL, /* extrq_i, insertq_i (sse4a) */
- [0x79] = OP(op1, 0,
+ [0x79] = OP(op1, SSE_OPF_V0,
NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r),
- [0x7c] = OP(op1, 0,
+ [0x7c] = OP(op2, 0,
NULL, gen_helper_haddpd_xmm, NULL, gen_helper_haddps_xmm),
- [0x7d] = OP(op1, 0,
+ [0x7d] = OP(op2, 0,
NULL, gen_helper_hsubpd_xmm, NULL, gen_helper_hsubps_xmm),
[0x7e] = SSE_SPECIAL, /* movd, movd, , movq */
[0x7f] = SSE_SPECIAL, /* movq, movdqa, movdqu */
[0xc4] = SSE_SPECIAL, /* pinsrw */
[0xc5] = SSE_SPECIAL, /* pextrw */
- [0xd0] = OP(op1, 0,
+ [0xd0] = OP(op2, 0,
NULL, gen_helper_addsubpd_xmm, NULL, gen_helper_addsubps_xmm),
[0xd1] = MMX_OP(psrlw),
[0xd2] = MMX_OP(psrld),
@@ -3056,7 +3070,7 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0xe3] = MMX_OP(pavgw),
[0xe4] = MMX_OP(pmulhuw),
[0xe5] = MMX_OP(pmulhw),
- [0xe6] = OP(op1, 0,
+ [0xe6] = OP(op1, SSE_OPF_V0,
NULL, gen_helper_cvttpd2dq_xmm,
gen_helper_cvtdq2pd_xmm, gen_helper_cvtpd2dq_xmm),
[0xe7] = SSE_SPECIAL, /* movntq, movntq */
@@ -3075,7 +3089,7 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0xf4] = MMX_OP(pmuludq),
[0xf5] = MMX_OP(pmaddwd),
[0xf6] = MMX_OP(psadbw),
- [0xf7] = OP(op1t, SSE_OPF_MMX,
+ [0xf7] = OP(op1t, SSE_OPF_MMX | SSE_OPF_V0,
gen_helper_maskmov_mmx, gen_helper_maskmov_xmm, NULL, NULL),
[0xf8] = MMX_OP(psubb),
[0xf9] = MMX_OP(psubw),
@@ -3093,7 +3107,7 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
#define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
-static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
+static const SSEFunc_0_eppp sse_op_table2[3 * 8][2] = {
[0 + 2] = MMX_OP2(psrlw), = {
+static const SSEFunc_0_eppp sse_op_table4[8][4] = {
SSE_CMP(cmpeq),
SSE_CMP(cmplt),
SSE_CMP(cmple),
@@ -3149,6 +3163,11 @@ static const SSEFunc_0_epp sse_op_table4[8][4] = {
};
#undef SSE_CMP
+static void gen_helper_pavgusb(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b)
+{
+ gen_helper_pavgb_mmx(env, reg_a, reg_a, reg_b);
+}
+
static const SSEFunc_0_epp sse_op_table5[256] = {
[0x0c] = gen_helper_pi2fw,
[0x0d] = gen_helper_pi2fd,
@@ -3173,7 +3192,7 @@ static const SSEFunc_0_epp sse_op_table5[256] = {
[0xb6] = gen_helper_movq, /* pfrcpit2 */
[0xb7] = gen_helper_pmulhrw_mmx,
[0xbb] = gen_helper_pswapd,
- [0xbf] = gen_helper_pavgb_mmx,
+ [0xbf] = gen_helper_pavgusb,
};
struct SSEOpHelper_table6 {
@@ -3185,6 +3204,8 @@ struct SSEOpHelper_table6 {
struct SSEOpHelper_table7 {
union {
SSEFunc_0_eppi op1;
+ SSEFunc_0_epppi op2;
+ SSEFunc_0_epppp op3;
} fn[2];
uint32_t ext_mask;
int flags;
@@ -3196,15 +3217,15 @@ struct SSEOpHelper_table7 {
{{{.op = mmx_name}, {.op = gen_helper_ ## name ## _xmm} }, \
CPUID_EXT_ ## ext, flags}
#define BINARY_OP_MMX(name, ext) \
- OP(name, op1, SSE_OPF_MMX, ext, gen_helper_ ## name ## _mmx)
+ OP(name, op2, SSE_OPF_MMX, ext, gen_helper_ ## name ## _mmx)
#define BINARY_OP(name, ext, flags) \
- OP(name, op1, flags, ext, NULL)
+ OP(name, op2, flags, ext, NULL)
#define UNARY_OP_MMX(name, ext) \
- OP(name, op1, SSE_OPF_MMX, ext, gen_helper_ ## name ## _mmx)
+ OP(name, op1, SSE_OPF_V0 | SSE_OPF_MMX, ext, gen_helper_ ## name ## _mmx)
#define UNARY_OP(name, ext, flags) \
- OP(name, op1, flags, ext, NULL)
-#define BLENDV_OP(name, ext, flags) OP(name, op1, 0, ext, NULL)
-#define CMP_OP(name, ext) OP(name, op1, SSE_OPF_CMP, ext, NULL)
+ OP(name, op1, SSE_OPF_V0 | flags, ext, NULL)
+#define BLENDV_OP(name, ext, flags) OP(name, op3, SSE_OPF_BLENDV, ext, NULL)
+#define CMP_OP(name, ext) OP(name, op1, SSE_OPF_CMP | SSE_OPF_V0, ext, NULL)
#define SPECIAL_OP(ext) OP(special, op1, SSE_OPF_SPECIAL, ext, NULL)
/* prefix [66] 0f 38 */
@@ -3748,7 +3769,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op1_offset = offsetof(CPUX86State,mmx_t0);
}
assert(b1 < 2);
- SSEFunc_0_epp fn = sse_op_table2[((b - 1) & 3) * 8 +
+ SSEFunc_0_eppp fn = sse_op_table2[((b - 1) & 3) * 8 +
(((modrm >> 3)) & 7)][b1];
if (!fn) {
goto unknown_op;
@@ -3761,8 +3782,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
}
tcg_gen_addi_ptr(s->ptr0, cpu_env, op2_offset);
- tcg_gen_addi_ptr(s->ptr1, cpu_env, op1_offset);
- fn(cpu_env, s->ptr0, s->ptr1);
+ tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
+ tcg_gen_addi_ptr(s->ptr2, cpu_env, op1_offset);
+ fn(cpu_env, s->ptr0, s->ptr1, s->ptr2);
break;
case 0x050: /* movmskps */
rm = (modrm & 7) | REX_B(s);
@@ -4030,7 +4052,21 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
- op6->fn[b1].op1(cpu_env, s->ptr0, s->ptr1);
+ if (op6->flags & SSE_OPF_V0) {
+ op6->fn[b1].op1(cpu_env, s->ptr0, s->ptr1);
+ } else {
+ tcg_gen_addi_ptr(s->ptr2, cpu_env, op1_offset);
+ if (op6->flags & SSE_OPF_BLENDV) {
+ TCGv_ptr mask = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(mask, cpu_env, ZMM_OFFSET(0));
+ op6->fn[b1].op3(cpu_env, s->ptr0, s->ptr2, s->ptr1,
+ mask);
+ tcg_temp_free_ptr(mask);
+ } else {
+ SSEFunc_0_eppp fn = op6->fn[b1].op2;
+ fn(cpu_env, s->ptr0, s->ptr2, s->ptr1);
+ }
+ }
} else {
CHECK_NO_VEX(s);
if ((op6->flags & SSE_OPF_MMX) == 0) {
@@ -4046,7 +4082,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
- op6->fn[0].op1(cpu_env, s->ptr0, s->ptr1);
+ if (op6->flags & SSE_OPF_V0) {
+ op6->fn[0].op1(cpu_env, s->ptr0, s->ptr1);
+ } else {
+ op6->fn[0].op2(cpu_env, s->ptr0, s->ptr0, s->ptr1);
+ }
}
if (op6->flags & SSE_OPF_CMP) {
@@ -4380,7 +4420,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* We only actually have one MMX instuction (palignr) */
assert(b == 0x0f);
- op7->fn[0].op1(cpu_env, s->ptr0, s->ptr1,
+ op7->fn[0].op2(cpu_env, s->ptr0, s->ptr0, s->ptr1,
tcg_const_i32(val));
break;
}
@@ -4407,7 +4447,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
- op7->fn[b1].op1(cpu_env, s->ptr0, s->ptr1, tcg_const_i32(val));
+ if (op7->flags & SSE_OPF_V0) {
+ op7->fn[b1].op1(cpu_env, s->ptr0, s->ptr1, tcg_const_i32(val));
+ } else {
+ tcg_gen_addi_ptr(s->ptr2, cpu_env, op1_offset);
+ op7->fn[b1].op2(cpu_env, s->ptr0, s->ptr2, s->ptr1,
+ tcg_const_i32(val));
+ }
if (op7->flags & SSE_OPF_CMP) {
set_cc_op(s, CC_OP_EFLAGS);
}
@@ -4499,26 +4545,46 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
return;
}
}
+
+
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
- if (sse_op_flags & SSE_OPF_SHUF) {
- val = x86_ldub_code(env, s);
- sse_op_fn.op1i(s->ptr0, s->ptr1, tcg_const_i32(val));
- } else if (b == 0xf7) {
- /* maskmov : we must prepare A0 */
- if (mod != 3) {
- goto illegal_op;
+ if (sse_op_flags & SSE_OPF_V0) {
+ if (sse_op_flags & SSE_OPF_SHUF) {
+ val = x86_ldub_code(env, s);
+ sse_op_fn.op1i(s->ptr0, s->ptr1, tcg_const_i32(val));
+ } else if (b == 0xf7) {
+ /* maskmov : we must prepare A0 */
+ if (mod != 3) {
+ goto illegal_op;
+ }
+ tcg_gen_mov_tl(s->A0, cpu_regs[R_EDI]);
+ gen_extu(s->aflag, s->A0);
+ gen_add_A0_ds_seg(s);
+
+ tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
+ tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
+ sse_op_fn.op1t(cpu_env, s->ptr0, s->ptr1, s->A0);
+ /* Does not write to the fist operand */
+ return;
+ } else {
+ sse_op_fn.op1(cpu_env, s->ptr0, s->ptr1);
}
- tcg_gen_mov_tl(s->A0, cpu_regs[R_EDI]);
- gen_extu(s->aflag, s->A0);
- gen_add_A0_ds_seg(s);
- sse_op_fn.op1t(cpu_env, s->ptr0, s->ptr1, s->A0);
- } else if (b == 0xc2) {
- /* compare insns, bits 7:3 (7:5 for AVX) are ignored */
- val = x86_ldub_code(env, s) & 7;
- sse_op_table4[val][b1](cpu_env, s->ptr0, s->ptr1);
} else {
- sse_op_fn.op1(cpu_env, s->ptr0, s->ptr1);
+ tcg_gen_addi_ptr(s->ptr2, cpu_env, op1_offset);
+ if (sse_op_flags & SSE_OPF_SHUF) {
+ val = x86_ldub_code(env, s);
+ sse_op_fn.op2i(s->ptr0, s->ptr2, s->ptr1,
+ tcg_const_i32(val));
+ } else {
+ SSEFunc_0_eppp fn = sse_op_fn.op2;
+ if (b == 0xc2) {
+ /* compare insns */
+ val = x86_ldub_code(env, s) & 7;
+ fn = sse_op_table4[val][b1];
+ }
+ fn(cpu_env, s->ptr0, s->ptr2, s->ptr1);
+ }
}
if (sse_op_flags & SSE_OPF_CMP) {
@@ -8598,6 +8664,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->tmp4 = tcg_temp_new();
dc->ptr0 = tcg_temp_new_ptr();
dc->ptr1 = tcg_temp_new_ptr();
+ dc->ptr2 = tcg_temp_new_ptr();
dc->cc_srcT = tcg_temp_local_new();
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 15/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings
2022-09-11 23:03 ` [PATCH 15/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
@ 2022-09-12 11:11 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 11:11 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> Add to the helpers all the operands that are needed to implement AVX.
>
> Extracted from a patch by Paul Brook<paul@nowt.org>.
>
> Message-Id:<20220424220204.2493824-26-paul@nowt.org>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/ops_sse.h | 173 +++++++++++++--------------------
> target/i386/ops_sse_header.h | 149 ++++++++++++++--------------
> target/i386/tcg/translate.c | 181 ++++++++++++++++++++++++-----------
> 3 files changed, 265 insertions(+), 238 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 16/37] target/i386: support operand merging in binary scalar helpers
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (14 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 15/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:11 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 17/37] target/i386: provide 3-operand versions of unary " Paolo Bonzini
` (20 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
helpers to provide this functionality.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index fb8733f509..527da59299 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -557,12 +557,20 @@ void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order)
\
void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *v, Reg *s)\
{ \
+ int i; \
d->ZMM_S(0) = F(32, v->ZMM_S(0), s->ZMM_S(0)); \
+ for (i = 1; i < 2 << SHIFT; i++) { \
+ d->ZMM_L(i) = v->ZMM_L(i); \
+ } \
} \
\
void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *v, Reg *s)\
{ \
+ int i; \
d->ZMM_D(0) = F(64, v->ZMM_D(0), s->ZMM_D(0)); \
+ for (i = 1; i < 1 << SHIFT; i++) { \
+ d->ZMM_Q(i) = v->ZMM_Q(i); \
+ } \
}
#else
@@ -1027,12 +1035,20 @@ void glue(helper_addsubpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
SSE_HELPER_CMP_P(name, F, C) \
void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
+ int i; \
d->ZMM_L(0) = C(F(32, v->ZMM_S(0), s->ZMM_S(0))) ? -1 : 0; \
+ for (i = 1; i < 2 << SHIFT; i++) { \
+ d->ZMM_L(i) = v->ZMM_L(i); \
+ } \
} \
\
void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *v, Reg *s) \
{ \
+ int i; \
d->ZMM_Q(0) = C(F(64, v->ZMM_D(0), s->ZMM_D(0))) ? -1 : 0; \
+ for (i = 1; i < 1 << SHIFT; i++) { \
+ d->ZMM_Q(i) = v->ZMM_Q(i); \
+ } \
}
#define FPU_EQ(x) (x == float_relation_equal)
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* [PATCH 17/37] target/i386: provide 3-operand versions of unary scalar helpers
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (15 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 16/37] target/i386: support operand merging in binary scalar helpers Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:14 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 18/37] target/i386: implement additional AVX comparison operators Paolo Bonzini
` (19 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
old SSE decoder to be compatible with new-style helpers.
The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 48 ++++++++++++++++++++++++++++++------
| 16 ++++++------
target/i386/tcg/translate.c | 22 ++++++++++-------
3 files changed, 61 insertions(+), 25 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 527da59299..0d56f0949b 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -617,14 +617,22 @@ void glue(helper_sqrtpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
#if SHIFT == 1
-void helper_sqrtss(CPUX86State *env, Reg *d, Reg *s)
+void helper_sqrtss(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
+ int i;
d->ZMM_S(0) = float32_sqrt(s->ZMM_S(0), &env->sse_status);
+ for (i = 1; i < 2 << SHIFT; i++) {
+ d->ZMM_L(i) = v->ZMM_L(i);
+ }
}
-void helper_sqrtsd(CPUX86State *env, Reg *d, Reg *s)
+void helper_sqrtsd(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
+ int i;
d->ZMM_D(0) = float64_sqrt(s->ZMM_D(0), &env->sse_status);
+ for (i = 1; i < 1 << SHIFT; i++) {
+ d->ZMM_Q(i) = v->ZMM_Q(i);
+ }
}
#endif
@@ -649,14 +657,22 @@ void glue(helper_cvtpd2ps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
#if SHIFT == 1
-void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s)
+void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
+ int i;
d->ZMM_D(0) = float32_to_float64(s->ZMM_S(0), &env->sse_status);
+ for (i = 1; i < 1 << SHIFT; i++) {
+ d->ZMM_Q(i) = v->ZMM_Q(i);
+ }
}
-void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s)
+void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
+ int i;
d->ZMM_S(0) = float64_to_float32(s->ZMM_D(0), &env->sse_status);
+ for (i = 1; i < 2 << SHIFT; i++) {
+ d->ZMM_L(i) = v->ZMM_L(i);
+ }
}
#endif
@@ -876,13 +892,17 @@ void glue(helper_rsqrtps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s)
}
#if SHIFT == 1
-void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
+void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
+ int i;
d->ZMM_S(0) = float32_div(float32_one,
float32_sqrt(s->ZMM_S(0), &env->sse_status),
&env->sse_status);
set_float_exception_flags(old_flags, &env->sse_status);
+ for (i = 1; i < 2 << SHIFT; i++) {
+ d->ZMM_L(i) = v->ZMM_L(i);
+ }
}
#endif
@@ -897,10 +917,14 @@ void glue(helper_rcpps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s)
}
#if SHIFT == 1
-void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
+void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
+ int i;
d->ZMM_S(0) = float32_div(float32_one, s->ZMM_S(0), &env->sse_status);
+ for (i = 1; i < 2 << SHIFT; i++) {
+ d->ZMM_L(i) = v->ZMM_L(i);
+ }
set_float_exception_flags(old_flags, &env->sse_status);
}
#endif
@@ -1798,11 +1822,12 @@ void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
#if SHIFT == 1
-void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
+void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
uint32_t mode)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
signed char prev_rounding_mode;
+ int i;
prev_rounding_mode = env->sse_status.float_rounding_mode;
if (!(mode & (1 << 2))) {
@@ -1823,6 +1848,9 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
d->ZMM_S(0) = float32_round_to_int(s->ZMM_S(0), &env->sse_status);
+ for (i = 1; i < 2 << SHIFT; i++) {
+ d->ZMM_L(i) = v->ZMM_L(i);
+ }
if (mode & (1 << 3) && !(old_flags & float_flag_inexact)) {
set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
@@ -1832,11 +1860,12 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
env->sse_status.float_rounding_mode = prev_rounding_mode;
}
-void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
+void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
uint32_t mode)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
signed char prev_rounding_mode;
+ int i;
prev_rounding_mode = env->sse_status.float_rounding_mode;
if (!(mode & (1 << 2))) {
@@ -1857,6 +1886,9 @@ void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
d->ZMM_D(0) = float64_round_to_int(s->ZMM_D(0), &env->sse_status);
+ for (i = 1; i < 1 << SHIFT; i++) {
+ d->ZMM_Q(i) = v->ZMM_Q(i);
+ }
if (mode & (1 << 3) && !(old_flags & float_flag_inexact)) {
set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 21fed7fa05..5d17146049 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -148,8 +148,8 @@ DEF_HELPER_3(glue(pshufhw, SUFFIX), void, Reg, Reg, int)
DEF_HELPER_4(name ## sd, void, env, Reg, Reg, Reg)
#define SSE_HELPER_S3(name) \
SSE_HELPER_P3(name) \
- DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
- DEF_HELPER_3(name ## sd, void, env, Reg, Reg)
+ DEF_HELPER_4(name ## ss, void, env, Reg, Reg, Reg) \
+ DEF_HELPER_4(name ## sd, void, env, Reg, Reg, Reg)
#else
#define SSE_HELPER_S4(name, ...) SSE_HELPER_P4(name)
#define SSE_HELPER_S3(name, ...) SSE_HELPER_P3(name)
@@ -179,8 +179,8 @@ DEF_HELPER_3(glue(cvttps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(cvttpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
#if SHIFT == 1
-DEF_HELPER_3(cvtss2sd, void, env, Reg, Reg)
-DEF_HELPER_3(cvtsd2ss, void, env, Reg, Reg)
+DEF_HELPER_4(cvtss2sd, void, env, Reg, Reg, Reg)
+DEF_HELPER_4(cvtsd2ss, void, env, Reg, Reg, Reg)
DEF_HELPER_3(cvtpi2ps, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtpi2pd, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtsi2ss, void, env, ZMMReg, i32)
@@ -214,8 +214,8 @@ DEF_HELPER_3(glue(rsqrtps, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(rcpps, SUFFIX), void, env, ZMMReg, ZMMReg)
#if SHIFT == 1
-DEF_HELPER_3(rsqrtss, void, env, ZMMReg, ZMMReg)
-DEF_HELPER_3(rcpss, void, env, ZMMReg, ZMMReg)
+DEF_HELPER_4(rsqrtss, void, env, ZMMReg, ZMMReg, ZMMReg)
+DEF_HELPER_4(rcpss, void, env, ZMMReg, ZMMReg, ZMMReg)
DEF_HELPER_3(extrq_r, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(extrq_i, void, env, ZMMReg, int, int)
DEF_HELPER_3(insertq_r, void, env, ZMMReg, ZMMReg)
@@ -342,8 +342,8 @@ DEF_HELPER_3(glue(phminposuw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(roundps, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(roundpd, SUFFIX), void, env, Reg, Reg, i32)
#if SHIFT == 1
-DEF_HELPER_4(roundss_xmm, void, env, Reg, Reg, i32)
-DEF_HELPER_4(roundsd_xmm, void, env, Reg, Reg, i32)
+DEF_HELPER_5(roundss_xmm, void, env, Reg, Reg, Reg, i32)
+DEF_HELPER_5(roundsd_xmm, void, env, Reg, Reg, Reg, i32)
#endif
DEF_HELPER_5(glue(blendps, SUFFIX), void, env, Reg, Reg, Reg, i32)
DEF_HELPER_5(glue(blendpd, SUFFIX), void, env, Reg, Reg, Reg, i32)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e996aab541..e147a95c5f 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2934,6 +2934,9 @@ static bool first = true; static unsigned long limit;
#define SSE_OP(sname, dname, op, flags) OP(op, flags, \
gen_helper_##sname##_xmm, gen_helper_##dname##_xmm, NULL, NULL)
+#define SSE_OP_UNARY(a, b, c, d) \
+ {SSE_OPF_SCALAR | SSE_OPF_V0, {{.op1 = a}, {.op1 = b}, {.op2 = c}, {.op2 = d} } }
+
typedef union SSEFuncs {
SSEFunc_0_epp op1;
SSEFunc_0_ppi op1i;
@@ -2976,12 +2979,12 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x2f] = OP(op1, SSE_OPF_CMP | SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_comiss, gen_helper_comisd, NULL, NULL),
[0x50] = SSE_SPECIAL, /* movmskps, movmskpd */
- [0x51] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
+ [0x51] = SSE_OP_UNARY(
gen_helper_sqrtps_xmm, gen_helper_sqrtpd_xmm,
gen_helper_sqrtss, gen_helper_sqrtsd),
- [0x52] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
+ [0x52] = SSE_OP_UNARY(
gen_helper_rsqrtps_xmm, NULL, gen_helper_rsqrtss, NULL),
- [0x53] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
+ [0x53] = SSE_OP_UNARY(
gen_helper_rcpps_xmm, NULL, gen_helper_rcpss, NULL),
[0x54] = SSE_OP(pand, pand, op2, 0), /* andps, andpd */
[0x55] = SSE_OP(pandn, pandn, op2, 0), /* andnps, andnpd */
@@ -2989,9 +2992,9 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x57] = SSE_OP(pxor, pxor, op2, 0), /* xorps, xorpd */
[0x58] = SSE_FOP(add),
[0x59] = SSE_FOP(mul),
- [0x5a] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
- gen_helper_cvtps2pd_xmm, gen_helper_cvtpd2ps_xmm,
- gen_helper_cvtss2sd, gen_helper_cvtsd2ss),
+ [0x5a] = SSE_OP_UNARY(
+ gen_helper_cvtps2pd_xmm, gen_helper_cvtpd2ps_xmm,
+ gen_helper_cvtss2sd, gen_helper_cvtsd2ss),
[0x5b] = OP(op1, SSE_OPF_V0,
gen_helper_cvtdq2ps_xmm, gen_helper_cvtps2dq_xmm,
gen_helper_cvttps2dq_xmm, NULL),
@@ -3287,8 +3290,8 @@ static const struct SSEOpHelper_table6 sse_op_table6[256] = {
static const struct SSEOpHelper_table7 sse_op_table7[256] = {
[0x08] = UNARY_OP(roundps, SSE41, 0),
[0x09] = UNARY_OP(roundpd, SSE41, 0),
- [0x0a] = UNARY_OP(roundss, SSE41, SSE_OPF_SCALAR),
- [0x0b] = UNARY_OP(roundsd, SSE41, SSE_OPF_SCALAR),
+ [0x0a] = BINARY_OP(roundss, SSE41, SSE_OPF_SCALAR),
+ [0x0b] = BINARY_OP(roundsd, SSE41, SSE_OPF_SCALAR),
[0x0c] = BINARY_OP(blendps, SSE41, 0),
[0x0d] = BINARY_OP(blendpd, SSE41, 0),
[0x0e] = BINARY_OP(pblendw, SSE41, SSE_OPF_MMX),
@@ -4549,7 +4552,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
- if (sse_op_flags & SSE_OPF_V0) {
+ if ((sse_op_flags & SSE_OPF_V0) &&
+ !((sse_op_flags & SSE_OPF_SCALAR) && b1 >= 2)) {
if (sse_op_flags & SSE_OPF_SHUF) {
val = x86_ldub_code(env, s);
sse_op_fn.op1i(s->ptr0, s->ptr1, tcg_const_i32(val));
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 17/37] target/i386: provide 3-operand versions of unary scalar helpers
2022-09-11 23:03 ` [PATCH 17/37] target/i386: provide 3-operand versions of unary " Paolo Bonzini
@ 2022-09-12 11:14 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 11:14 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> Compared to Paul's implementation, the new decoder will use a different approach
> to implement AVX's merging of dst with src1 on scalar operations. Adjust the
> old SSE decoder to be compatible with new-style helpers.
>
> The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx.
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/ops_sse.h | 48 ++++++++++++++++++++++++++++++------
> target/i386/ops_sse_header.h | 16 ++++++------
> target/i386/tcg/translate.c | 22 ++++++++++-------
> 3 files changed, 61 insertions(+), 25 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 18/37] target/i386: implement additional AVX comparison operators
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (16 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 17/37] target/i386: provide 3-operand versions of unary " Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:19 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 19/37] target/i386: Introduce 256-bit vector helpers Paolo Bonzini
` (18 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
The new implementation of SSE will cover AVX from the get go, so include
the 24 extra comparison operators that are only available with the VEX
prefix.
Based on a patch by Paul Brook <paul@nowt.org>.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 38 ++++++++++++++++++++++++++++++++++++
| 27 +++++++++++++++++++++++++
2 files changed, 65 insertions(+)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 0d56f0949b..93cee330d2 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -1075,10 +1075,21 @@ void glue(helper_addsubpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
} \
}
+static inline bool FPU_EQU(FloatRelation x)
+{
+ return (x == float_relation_equal || x == float_relation_unordered);
+}
+static inline bool FPU_GE(FloatRelation x)
+{
+ return (x == float_relation_equal || x == float_relation_greater);
+}
#define FPU_EQ(x) (x == float_relation_equal)
#define FPU_LT(x) (x == float_relation_less)
#define FPU_LE(x) (x <= float_relation_equal)
+#define FPU_GT(x) (x == float_relation_greater)
#define FPU_UNORD(x) (x == float_relation_unordered)
+// We must make sure we evaluate the argument in case it is a signalling NAN
+#define FPU_FALSE(x) (x == float_relation_equal && 0)
#define FPU_CMPQ(size, a, b) \
float ## size ## _compare_quiet(a, b, &env->sse_status)
@@ -1098,6 +1109,33 @@ SSE_HELPER_CMP(cmpnlt, FPU_CMPS, !FPU_LT)
SSE_HELPER_CMP(cmpnle, FPU_CMPS, !FPU_LE)
SSE_HELPER_CMP(cmpord, FPU_CMPQ, !FPU_UNORD)
+SSE_HELPER_CMP(cmpequ, FPU_CMPQ, FPU_EQU)
+SSE_HELPER_CMP(cmpnge, FPU_CMPS, !FPU_GE)
+SSE_HELPER_CMP(cmpngt, FPU_CMPS, !FPU_GT)
+SSE_HELPER_CMP(cmpfalse, FPU_CMPQ, FPU_FALSE)
+SSE_HELPER_CMP(cmpnequ, FPU_CMPQ, !FPU_EQU)
+SSE_HELPER_CMP(cmpge, FPU_CMPS, FPU_GE)
+SSE_HELPER_CMP(cmpgt, FPU_CMPS, FPU_GT)
+SSE_HELPER_CMP(cmptrue, FPU_CMPQ, !FPU_FALSE)
+
+SSE_HELPER_CMP(cmpeqs, FPU_CMPS, FPU_EQ)
+SSE_HELPER_CMP(cmpltq, FPU_CMPQ, FPU_LT)
+SSE_HELPER_CMP(cmpleq, FPU_CMPQ, FPU_LE)
+SSE_HELPER_CMP(cmpunords, FPU_CMPS, FPU_UNORD)
+SSE_HELPER_CMP(cmpneqq, FPU_CMPS, !FPU_EQ)
+SSE_HELPER_CMP(cmpnltq, FPU_CMPQ, !FPU_LT)
+SSE_HELPER_CMP(cmpnleq, FPU_CMPQ, !FPU_LE)
+SSE_HELPER_CMP(cmpords, FPU_CMPS, !FPU_UNORD)
+
+SSE_HELPER_CMP(cmpequs, FPU_CMPS, FPU_EQU)
+SSE_HELPER_CMP(cmpngeq, FPU_CMPQ, !FPU_GE)
+SSE_HELPER_CMP(cmpngtq, FPU_CMPQ, !FPU_GT)
+SSE_HELPER_CMP(cmpfalses, FPU_CMPS, FPU_FALSE)
+SSE_HELPER_CMP(cmpnequs, FPU_CMPS, !FPU_EQU)
+SSE_HELPER_CMP(cmpgeq, FPU_CMPQ, FPU_GE)
+SSE_HELPER_CMP(cmpgtq, FPU_CMPQ, FPU_GT)
+SSE_HELPER_CMP(cmptrues, FPU_CMPS, !FPU_FALSE)
+
#undef SSE_HELPER_CMP
#if SHIFT == 1
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 5d17146049..4bef536edb 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -237,6 +237,33 @@ SSE_HELPER_CMP(cmpnlt, FPU_CMPS, !FPU_LT)
SSE_HELPER_CMP(cmpnle, FPU_CMPS, !FPU_LE)
SSE_HELPER_CMP(cmpord, FPU_CMPQ, !FPU_UNORD)
+SSE_HELPER_CMP(cmpequ, FPU_CMPQ, FPU_EQU)
+SSE_HELPER_CMP(cmpnge, FPU_CMPS, !FPU_GE)
+SSE_HELPER_CMP(cmpngt, FPU_CMPS, !FPU_GT)
+SSE_HELPER_CMP(cmpfalse, FPU_CMPQ, FPU_FALSE)
+SSE_HELPER_CMP(cmpnequ, FPU_CMPQ, !FPU_EQU)
+SSE_HELPER_CMP(cmpge, FPU_CMPS, FPU_GE)
+SSE_HELPER_CMP(cmpgt, FPU_CMPS, FPU_GT)
+SSE_HELPER_CMP(cmptrue, FPU_CMPQ, !FPU_FALSE)
+
+SSE_HELPER_CMP(cmpeqs, FPU_CMPS, FPU_EQ)
+SSE_HELPER_CMP(cmpltq, FPU_CMPQ, FPU_LT)
+SSE_HELPER_CMP(cmpleq, FPU_CMPQ, FPU_LE)
+SSE_HELPER_CMP(cmpunords, FPU_CMPS, FPU_UNORD)
+SSE_HELPER_CMP(cmpneqq, FPU_CMPS, !FPU_EQ)
+SSE_HELPER_CMP(cmpnltq, FPU_CMPQ, !FPU_LT)
+SSE_HELPER_CMP(cmpnleq, FPU_CMPQ, !FPU_LE)
+SSE_HELPER_CMP(cmpords, FPU_CMPS, !FPU_UNORD)
+
+SSE_HELPER_CMP(cmpequs, FPU_CMPS, FPU_EQU)
+SSE_HELPER_CMP(cmpngeq, FPU_CMPQ, !FPU_GE)
+SSE_HELPER_CMP(cmpngtq, FPU_CMPQ, !FPU_GT)
+SSE_HELPER_CMP(cmpfalses, FPU_CMPS, FPU_FALSE)
+SSE_HELPER_CMP(cmpnequs, FPU_CMPS, !FPU_EQU)
+SSE_HELPER_CMP(cmpgeq, FPU_CMPQ, FPU_GE)
+SSE_HELPER_CMP(cmpgtq, FPU_CMPQ, FPU_GT)
+SSE_HELPER_CMP(cmptrues, FPU_CMPS, !FPU_FALSE)
+
#if SHIFT == 1
DEF_HELPER_3(ucomiss, void, env, Reg, Reg)
DEF_HELPER_3(comiss, void, env, Reg, Reg)
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 18/37] target/i386: implement additional AVX comparison operators
2022-09-11 23:03 ` [PATCH 18/37] target/i386: implement additional AVX comparison operators Paolo Bonzini
@ 2022-09-12 11:19 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 11:19 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> The new implementation of SSE will cover AVX from the get go, so include
> the 24 extra comparison operators that are only available with the VEX
> prefix.
>
> Based on a patch by Paul Brook<paul@nowt.org>.
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/ops_sse.h | 38 ++++++++++++++++++++++++++++++++++++
> target/i386/ops_sse_header.h | 27 +++++++++++++++++++++++++
> 2 files changed, 65 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 19/37] target/i386: Introduce 256-bit vector helpers
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (17 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 18/37] target/i386: implement additional AVX comparison operators Paolo Bonzini
@ 2022-09-11 23:03 ` Paolo Bonzini
2022-09-12 11:19 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
` (17 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:03 UTC (permalink / raw)
To: qemu-devel
The new implementation of SSE will cover AVX from the get go, because
all the work for the helper functions is already done. We just need to
build them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/helper.h | 2 ++
target/i386/ops_sse.h | 5 +++++
| 4 ++++
target/i386/tcg/fpu_helper.c | 3 +++
4 files changed, 14 insertions(+)
diff --git a/target/i386/helper.h b/target/i386/helper.h
index ac3b4d1ee3..3da5df98b9 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -218,6 +218,8 @@ DEF_HELPER_3(movq, void, env, ptr, ptr)
#include "ops_sse_header.h"
#define SHIFT 1
#include "ops_sse_header.h"
+#define SHIFT 2
+#include "ops_sse_header.h"
DEF_HELPER_3(rclb, tl, env, tl, tl)
DEF_HELPER_3(rclw, tl, env, tl, tl)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 93cee330d2..4f72164c0f 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -35,7 +35,11 @@
#define W(n) ZMM_W(n)
#define L(n) ZMM_L(n)
#define Q(n) ZMM_Q(n)
+#if SHIFT == 1
#define SUFFIX _xmm
+#else
+#define SUFFIX _ymm
+#endif
#endif
#define LANE_WIDTH (SHIFT ? 16 : 8)
@@ -2379,6 +2383,7 @@ void glue(helper_aeskeygenassist, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
#undef SSE_HELPER_S
+#undef LANE_WIDTH
#undef SHIFT
#undef XMM_ONLY
#undef Reg
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 4bef536edb..4041816945 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -21,7 +21,11 @@
#define SUFFIX _mmx
#else
#define Reg ZMMReg
+#if SHIFT == 1
#define SUFFIX _xmm
+#else
+#define SUFFIX _ymm
+#endif
#endif
#define dh_alias_Reg ptr
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 48bf0c5cf8..819e920ec6 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -3053,3 +3053,6 @@ void helper_movq(CPUX86State *env, void *d, void *s)
#define SHIFT 1
#include "ops_sse.h"
+
+#define SHIFT 2
+#include "ops_sse.h"
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 19/37] target/i386: Introduce 256-bit vector helpers
2022-09-11 23:03 ` [PATCH 19/37] target/i386: Introduce 256-bit vector helpers Paolo Bonzini
@ 2022-09-12 11:19 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 11:19 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> The new implementation of SSE will cover AVX from the get go, because
> all the work for the helper functions is already done. We just need to
> build them.
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/helper.h | 2 ++
> target/i386/ops_sse.h | 5 +++++
> target/i386/ops_sse_header.h | 4 ++++
> target/i386/tcg/fpu_helper.c | 3 +++
> 4 files changed, 14 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (18 preceding siblings ...)
2022-09-11 23:03 ` [PATCH 19/37] target/i386: Introduce 256-bit vector helpers Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-12 11:41 ` Richard Henderson
2022-09-12 13:01 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 21/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
` (16 subsequent siblings)
36 siblings, 2 replies; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
These are both MMX and SSE/AVX instructions, except for vmovdqu. In both
cases the inputs and output is in s->ptr{0,1,2}, so the only difference
between MMX, SSE, and AVX is which helper to call.
PCMPGT, MOVD and MOVQ are implemented using gvec.
The amount of macro magic for generating functions is kept to the minimum.
In particular, the gvec cases are easy enough and have no duplication within
each function, so they are spelled out one by one.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 35 ++++++++
target/i386/tcg/emit.c.inc | 148 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 3 +-
3 files changed, 185 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index b31daecb90..f20587c096 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -142,6 +142,23 @@ static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
entry->gen = group17_gen[op];
}
+static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ if (s->prefix & PREFIX_REPNZ) {
+ entry->gen = NULL;
+ } else if (s->prefix & PREFIX_REPZ) {
+ /* movdqu */
+ entry->gen = gen_MOVDQ;
+ entry->vex_class = 4;
+ entry->vex_special = X86_VEX_SSEUnaligned;
+ } else {
+ /* MMX movq, movdqa */
+ entry->gen = gen_MOVDQ;
+ entry->vex_class = 1;
+ entry->special = X86_SPECIAL_MMX;
+ }
+}
+
static const X86OpEntry opcodes_0F38_00toEF[240] = {
};
@@ -227,8 +244,26 @@ static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
static const X86OpEntry opcodes_0F[256] = {
+ [0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),
+
+ [0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
+ [0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
+ [0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
+ [0x6f] = X86_OP_GROUP3(0F6F, V,x, None,None, W,x, vex5 mmx p_00_66_f3),
};
static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 36b963a0d3..3f89d3cf50 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -212,6 +212,97 @@ static void gen_writeback(DisasContext *s, X86DecodedOp *op)
}
}
+static inline int sse_vec_len(DisasContext *s, X86DecodedInsn *decode)
+{
+ if (decode->e.special == X86_SPECIAL_MMX &&
+ !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
+ return 8;
+ }
+ return s->vex_l ? 32 : 16;
+}
+
+static void gen_store_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode, int src_ofs)
+{
+ MemOp ot = decode->op[0].ot;
+ int vec_len = sse_vec_len(s, decode);
+
+ if (!decode->op[0].has_ea) {
+ tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, vec_len, vec_len);
+ return;
+ }
+
+ switch (ot) {
+ case MO_64:
+ gen_stq_env_A0(s, src_ofs);
+ break;
+ case MO_128:
+ gen_sto_env_A0(s, src_ofs);
+ break;
+ case MO_256:
+ gen_sty_env_A0(s, src_ofs);
+ break;
+ default:
+ abort();
+ }
+}
+
+/*
+ * 00 = p* Pq, Qq (if mmx not NULL; no VEX)
+ * 66 = vp* Vx, Hx, Wx
+ *
+ * These are really the same encoding, because 1) V is the same as P when VEX.V
+ * is not present 2) P and Q are the same as H and W apart from MM/XMM
+ */
+static inline void gen_binary_int_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm)
+{
+ assert (!!mmx == !!(decode->e.special == X86_SPECIAL_MMX));
+
+ if (mmx && (s->prefix & PREFIX_VEX) && !(s->prefix & PREFIX_DATA)) {
+ /* VEX encoding is not applicable to MMX instructions. */
+ gen_illegal_opcode(s);
+ return;
+ }
+ if (!(s->prefix & PREFIX_DATA)) {
+ mmx(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+ } else if (!s->vex_l) {
+ xmm(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+ } else {
+ ymm(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+ }
+}
+
+#define BINARY_INT_MMX(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_binary_int_sse(s, env, decode, \
+ gen_helper_##lname##_mmx, \
+ gen_helper_##lname##_xmm, \
+ gen_helper_##lname##_ymm); \
+}
+BINARY_INT_MMX(PUNPCKLBW, punpcklbw)
+BINARY_INT_MMX(PUNPCKLWD, punpcklwd)
+BINARY_INT_MMX(PUNPCKLDQ, punpckldq)
+BINARY_INT_MMX(PACKSSWB, packsswb)
+BINARY_INT_MMX(PACKUSWB, packuswb)
+BINARY_INT_MMX(PUNPCKHBW, punpckhbw)
+BINARY_INT_MMX(PUNPCKHWD, punpckhwd)
+BINARY_INT_MMX(PUNPCKHDQ, punpckhdq)
+BINARY_INT_MMX(PACKSSDW, packssdw)
+
+/* Instructions with no MMX equivalent. */
+#define BINARY_INT_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_binary_int_sse(s, env, decode, \
+ NULL, \
+ gen_helper_##lname##_xmm, \
+ gen_helper_##lname##_ymm); \
+}
+
+BINARY_INT_SSE(PUNPCKLQDQ, punpcklqdq)
+BINARY_INT_SSE(PUNPCKHQDQ, punpckhqdq)
+
static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
{
TCGv carry_in = NULL;
@@ -382,6 +473,36 @@ static void gen_MOVBE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
}
}
+static void gen_MOVD_to(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[2].ot;
+ int vec_len = sse_vec_len(s, decode);
+ int lo_ofs = decode->op[0].offset
+ - xmm_offset(decode->op[0].ot)
+ + xmm_offset(ot);
+
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+
+ switch (ot) {
+ case MO_32:
+#ifdef TARGET_X86_64
+ tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
+ tcg_gen_st_i32(s->tmp3_i32, cpu_env, lo_ofs);
+ break;
+ case MO_64:
+#endif
+ tcg_gen_st_tl(s->T1, cpu_env, lo_ofs);
+ break;
+ default:
+ abort();
+ }
+}
+
+static void gen_MOVDQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_store_sse(s, env, decode, decode->op[2].offset);
+}
+
static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[0].ot;
@@ -405,6 +526,33 @@ static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
}
+static void gen_PCMPGTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_GT, MO_8,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PCMPGTW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_GT, MO_16,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PCMPGTD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_GT, MO_32,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
static void gen_PDEP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[1].ot;
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e147a95c5f..cf18e12d38 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -23,6 +23,7 @@
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
#include "exec/cpu_ldst.h"
#include "exec/translator.h"
@@ -4665,7 +4666,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#ifndef CONFIG_USER_ONLY
use_new &= b <= limit;
#endif
- if (use_new && 0) {
+ if (use_new && (b >= 0x160 && b <= 0x16f)) {
return disas_insn_new(s, cpu, b + 0x100);
}
break;
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX
2022-09-11 23:04 ` [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
@ 2022-09-12 11:41 ` Richard Henderson
2022-09-13 10:56 ` Paolo Bonzini
2022-09-12 13:01 ` Richard Henderson
1 sibling, 1 reply; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 11:41 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> +/*
> + * 00 = p* Pq, Qq (if mmx not NULL; no VEX)
> + * 66 = vp* Vx, Hx, Wx
> + *
> + * These are really the same encoding, because 1) V is the same as P when VEX.V
> + * is not present 2) P and Q are the same as H and W apart from MM/XMM
> + */
> +static inline void gen_binary_int_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> + SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm)
No need to inline.
> +{
> + assert (!!mmx == !!(decode->e.special == X86_SPECIAL_MMX));
> +
> + if (mmx && (s->prefix & PREFIX_VEX) && !(s->prefix & PREFIX_DATA)) {
> + /* VEX encoding is not applicable to MMX instructions. */
> + gen_illegal_opcode(s);
> + return;
> + }
> + if (!(s->prefix & PREFIX_DATA)) {
> + mmx(cpu_env, s->ptr0, s->ptr1, s->ptr2);
> + } else if (!s->vex_l) {
> + xmm(cpu_env, s->ptr0, s->ptr1, s->ptr2);
> + } else {
> + ymm(cpu_env, s->ptr0, s->ptr1, s->ptr2);
> + }
And a reminder from earlier patches that generating the pointers here would be better, as
well as zeroing the high ymm bits for vex xmm insns.
> +static void gen_MOVD_to(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + MemOp ot = decode->op[2].ot;
> + int vec_len = sse_vec_len(s, decode);
> + int lo_ofs = decode->op[0].offset
> + - xmm_offset(decode->op[0].ot)
> + + xmm_offset(ot);
> +
> + tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
> +
> + switch (ot) {
> + case MO_32:
> +#ifdef TARGET_X86_64
> + tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
> + tcg_gen_st_i32(s->tmp3_i32, cpu_env, lo_ofs);
> + break;
Use tcg_gen_st32_tl and omit the trunc.
Alternately, zero extend in T1 and fall through...
> + case MO_64:
> +#endif
> + tcg_gen_st_tl(s->T1, cpu_env, lo_ofs);
This could also be
tcg_gen_gvec_dup_i64(MO_64, offset, 8, sse_vec_max_len, s->T1);
to do the store and clear in one call.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX
2022-09-12 11:41 ` Richard Henderson
@ 2022-09-13 10:56 ` Paolo Bonzini
2022-09-13 11:35 ` Richard Henderson
0 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-13 10:56 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Mon, Sep 12, 2022 at 1:41 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/12/22 00:04, Paolo Bonzini wrote:
> > +/*
> > + * 00 = p* Pq, Qq (if mmx not NULL; no VEX)
> > + * 66 = vp* Vx, Hx, Wx
> > + *
> > + * These are really the same encoding, because 1) V is the same as P when VEX.V
> > + * is not present 2) P and Q are the same as H and W apart from MM/XMM
> > + */
> > +static inline void gen_binary_int_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> > + SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm)
>
> No need to inline.
Yes and no, the compiler should indeed be able to figure it out, but
both the assert() and the calls are meant to be optimized out by
inlining. So this kind of function would be even an always_inline
candidate.
> > +{
> > + assert (!!mmx == !!(decode->e.special == X86_SPECIAL_MMX));
> > +
> > + if (mmx && (s->prefix & PREFIX_VEX) && !(s->prefix & PREFIX_DATA)) {
> > + /* VEX encoding is not applicable to MMX instructions. */
> > + gen_illegal_opcode(s);
> > + return;
> > + }
> > + if (!(s->prefix & PREFIX_DATA)) {
> > + mmx(cpu_env, s->ptr0, s->ptr1, s->ptr2);
> > + } else if (!s->vex_l) {
> > + xmm(cpu_env, s->ptr0, s->ptr1, s->ptr2);
> > + } else {
> > + ymm(cpu_env, s->ptr0, s->ptr1, s->ptr2);
> > + }
>
> And a reminder from earlier patches that generating the pointers here would be better, as
> well as zeroing the high ymm bits for vex xmm insns.
I'm not sure about that, because there are quite a few cases handled
by more complex gen_* functions, which are helper-based (so not simple
calls to gvec functions where you have maxsz/oprsz) and are not
handled by the common gen_*_sse. For example gen_CVTPI2Px,
gen_MASKMOV, gen_PSRLDQ_i, gen_SSE4a_I, gen_VCVTSI2Sx, ... All of
these would have to add extra code to set the pointers and to clear
the high ymm bits.
For gen_load, however, i can delay the generation using something like
static inline TCGv_ptr get_ptr0(DisasContext *s)
{
if (s->ptr0) {
return s->ptr0;
}
s->ptr0 = tcg_temp_new_ptr();
tcg_gen_add(s->ptr0, cpu_env, ...);
return s->ptr0;
}
Most of the changes to this series are mechanical, so if you dislike
relying on DCE then why not.
For gen_writeback, keeping gen_writeback eliminates duplicated code
and keeps the phases of disas_insn_new separated, so I prefer it
slightly. For now I'd rather leave it as is; with the above get_ptr0()
function that creates s->ptr0 lazily, perhaps gen_writeback() could do
it only if s->ptr0 is set (suggesting that a helper was used), while
gvec helpers would use the oprsz<maxsz feature. There's something to
be said for keeping the initial implementation simple of course,
especially since it's already slightly better than the code produced
by the existing decoder.
> > + switch (ot) {
> > + case MO_32:
> > +#ifdef TARGET_X86_64
> > + tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
> > + tcg_gen_st_i32(s->tmp3_i32, cpu_env, lo_ofs);
> > + break;
>
> This could also be
>
> tcg_gen_gvec_dup_i64(MO_64, offset, 8, sse_vec_max_len, s->T1);
Yeah, it can be something like
case MO_32:
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
tcg_gen_gvec_dup_i32(MO_32, decode->op[0].offset, 4, vec_len,
s->tmp3_i32);
break;
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_gvec_dup_i64(MO_64, decode->op[0].offset, 8, vec_len, s->T1);
break;
#endif
and in this case of course it's not possible to use st32_tl.
Paolo
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX
2022-09-13 10:56 ` Paolo Bonzini
@ 2022-09-13 11:35 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 11:35 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
On 9/13/22 11:56, Paolo Bonzini wrote:
> On Mon, Sep 12, 2022 at 1:41 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 9/12/22 00:04, Paolo Bonzini wrote:
>>> +/*
>>> + * 00 = p* Pq, Qq (if mmx not NULL; no VEX)
>>> + * 66 = vp* Vx, Hx, Wx
>>> + *
>>> + * These are really the same encoding, because 1) V is the same as P when VEX.V
>>> + * is not present 2) P and Q are the same as H and W apart from MM/XMM
>>> + */
>>> +static inline void gen_binary_int_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
>>> + SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm)
>>
>> No need to inline.
>
> Yes and no, the compiler should indeed be able to figure it out, but
> both the assert() and the calls are meant to be optimized out by
> inlining. So this kind of function would be even an always_inline
> candidate.
Yes, I get that, I just prefer by default to allow the compiler to figure it out.
Obviously there are parts of the code base where we use always_inline and more, but this
part is never going to be performance critical.
Over-use of inline generally leads to Werror from clang, for the unused function case.
> I'm not sure about that, because there are quite a few cases handled
> by more complex gen_* functions, which are helper-based (so not simple
> calls to gvec functions where you have maxsz/oprsz) and are not
> handled by the common gen_*_sse. For example gen_CVTPI2Px,
> gen_MASKMOV, gen_PSRLDQ_i, gen_SSE4a_I, gen_VCVTSI2Sx, ... All of
> these would have to add extra code to set the pointers and to clear
> the high ymm bits.
Fair.
> For gen_load, however, i can delay the generation using something like
>
> static inline TCGv_ptr get_ptr0(DisasContext *s)
> {
> if (s->ptr0) {
> return s->ptr0;
> }
> s->ptr0 = tcg_temp_new_ptr();
> tcg_gen_add(s->ptr0, cpu_env, ...);
> return s->ptr0;
> }
Sure.
> For gen_writeback, keeping gen_writeback eliminates duplicated code
> and keeps the phases of disas_insn_new separated, so I prefer it
> slightly. For now I'd rather leave it as is; with the above get_ptr0()
> function that creates s->ptr0 lazily, perhaps gen_writeback() could do
> it only if s->ptr0 is set (suggesting that a helper was used), while
> gvec helpers would use the oprsz<maxsz feature. There's something to
> be said for keeping the initial implementation simple of course,
> especially since it's already slightly better than the code produced
> by the existing decoder.
Also fair. Let's ignore the max argument for now, and address it in a subsequent phase,
where we also convert more operations to gvec.
>> This could also be
>>
>> tcg_gen_gvec_dup_i64(MO_64, offset, 8, sse_vec_max_len, s->T1);
>
> Yeah, it can be something like
>
> case MO_32:
> tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
> tcg_gen_gvec_dup_i32(MO_32, decode->op[0].offset, 4, vec_len,
> s->tmp3_i32);
> break;
Actually, this doesn't work, because minimum vector size is 8.
This will hit the assert in check_size_align().
I've just realized that we can't just extend i32 to i64, as I was suggesting, because that
will fall foul of big-endian host (L(0) is at the top half of Q(0)). So best to keep your
zero + store.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX
2022-09-11 23:04 ` [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
2022-09-12 11:41 ` Richard Henderson
@ 2022-09-12 13:01 ` Richard Henderson
1 sibling, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 13:01 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> +static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
> +{
> + if (s->prefix & PREFIX_REPNZ) {
> + entry->gen = NULL;
Are these lines really required with the p_00_66_f3 spec on the group entry?
> + } else if (s->prefix & PREFIX_REPZ) {
> + /* movdqu */
> + entry->gen = gen_MOVDQ;
> + entry->vex_class = 4;
> + entry->vex_special = X86_VEX_SSEUnaligned;
> + } else {
> + /* MMX movq, movdqa */
> + entry->gen = gen_MOVDQ;
> + entry->vex_class = 1;
> + entry->special = X86_SPECIAL_MMX;
> + }
Also, you're overriding vex_class for both valid entries, so why does the group speicfy
vex5? Clearer to use X86_OP_ENTRY3 within this function and copy from static const data
instead of overriding individual fields?
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 21/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (19 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-12 13:19 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 22/37] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
` (15 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
These are more simple integer instructions present in both MMX and SSE/AVX,
with no holes that were later occupied by newer instructions.
Simple, non-saturating operations are implemented using gvec; apart
from this, there is not much to talk about.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 28 ++++++++
target/i386/tcg/emit.c.inc | 113 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 4 +-
3 files changed, 144 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index f20587c096..59f5637583 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -264,6 +264,34 @@ static const X86OpEntry opcodes_0F[256] = {
[0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
[0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
[0x6f] = X86_OP_GROUP3(0F6F, V,x, None,None, W,x, vex5 mmx p_00_66_f3),
+
+ /* Incorrectly missing from 2-17 */
+ [0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xda] = X86_OP_ENTRY3(PMINUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xdb] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xdc] = X86_OP_ENTRY3(PADDUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xdd] = X86_OP_ENTRY3(PADDUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xde] = X86_OP_ENTRY3(PMAXUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xdf] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+
+ [0xe8] = X86_OP_ENTRY3(PSUBSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xe9] = X86_OP_ENTRY3(PSUBSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xea] = X86_OP_ENTRY3(PMINSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xec] = X86_OP_ENTRY3(PADDSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xed] = X86_OP_ENTRY3(PADDSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xee] = X86_OP_ENTRY3(PMAXSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xef] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+
+ [0xf8] = X86_OP_ENTRY3(PSUBB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xf9] = X86_OP_ENTRY3(PSUBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xfa] = X86_OP_ENTRY3(PSUBD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xfb] = X86_OP_ENTRY3(PSUBQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xfc] = X86_OP_ENTRY3(PADDB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xfd] = X86_OP_ENTRY3(PADDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xfe] = X86_OP_ENTRY3(PADDD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ /* 0xff = UD0 */
};
static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 3f89d3cf50..1ba7a45668 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -290,6 +290,20 @@ BINARY_INT_MMX(PUNPCKHWD, punpckhwd)
BINARY_INT_MMX(PUNPCKHDQ, punpckhdq)
BINARY_INT_MMX(PACKSSDW, packssdw)
+BINARY_INT_MMX(PSUBUSB, psubusb)
+BINARY_INT_MMX(PSUBUSW, psubusw)
+BINARY_INT_MMX(PMINUB, pminub)
+BINARY_INT_MMX(PADDUSB, paddusb)
+BINARY_INT_MMX(PADDUSW, paddusw)
+BINARY_INT_MMX(PMAXUB, pmaxub)
+
+BINARY_INT_MMX(PSUBSB, psubsb)
+BINARY_INT_MMX(PSUBSW, psubsw)
+BINARY_INT_MMX(PMINSW, pminsw)
+BINARY_INT_MMX(PADDSB, paddsb)
+BINARY_INT_MMX(PADDSW, paddsw)
+BINARY_INT_MMX(PMAXSW, pmaxsw)
+
/* Instructions with no MMX equivalent. */
#define BINARY_INT_SSE(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
@@ -526,6 +540,51 @@ static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
}
+static void gen_PADDB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_add(MO_8,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PADDW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_add(MO_16,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PADDD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_add(MO_32,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PAND(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_and(MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PANDN(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_andc(MO_64,
+ decode->op[0].offset, decode->op[2].offset,
+ decode->op[1].offset, vec_len, vec_len);
+}
+
static void gen_PCMPGTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
@@ -571,6 +630,60 @@ static void gen_PEXT(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_helper_pext(s->T0, s->T0, s->T1);
}
+static void gen_POR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_or(MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PXOR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_xor(MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PSUBB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_sub(MO_8,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PSUBW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_sub(MO_16,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PSUBD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_sub(MO_32,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PSUBQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_sub(MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[0].ot;
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index cf18e12d38..11c17258eb 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4666,7 +4666,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#ifndef CONFIG_USER_ONLY
use_new &= b <= limit;
#endif
- if (use_new && (b >= 0x160 && b <= 0x16f)) {
+ if (use_new &&
+ ((b >= 0x160 && b <= 0x16f) ||
+ (b >= 0x1d8 && b <= 0x1ff && (b & 8)))) {
return disas_insn_new(s, cpu, b + 0x100);
}
break;
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 21/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX
2022-09-11 23:04 ` [PATCH 21/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
@ 2022-09-12 13:19 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 13:19 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> --- a/target/i386/tcg/emit.c.inc
> +++ b/target/i386/tcg/emit.c.inc
> @@ -290,6 +290,20 @@ BINARY_INT_MMX(PUNPCKHWD, punpckhwd)
> BINARY_INT_MMX(PUNPCKHDQ, punpckhdq)
> BINARY_INT_MMX(PACKSSDW, packssdw)
>
> +BINARY_INT_MMX(PSUBUSB, psubusb)
> +BINARY_INT_MMX(PSUBUSW, psubusw)
tcg_gen_gvec_ussub
> +BINARY_INT_MMX(PMINUB, pminub)
tcg_gen_gvec_umin
> +BINARY_INT_MMX(PADDUSB, paddusb)
> +BINARY_INT_MMX(PADDUSW, paddusw)
tcg_gen_gvec_usadd
> +BINARY_INT_MMX(PMAXUB, pmaxub)
tcg_gen_gvec_umax
> +BINARY_INT_MMX(PSUBSB, psubsb)
> +BINARY_INT_MMX(PSUBSW, psubsw)
tcg_gen_gvec_sssub
> +BINARY_INT_MMX(PMINSW, pminsw)
tcg_gen_gvec_smin
> +BINARY_INT_MMX(PADDSB, paddsb)
> +BINARY_INT_MMX(PADDSW, paddsw)
tcg_gen_gvec_ssadd
> +BINARY_INT_MMX(PMAXSW, pmaxsw)
tcg_gen_gvec_smax
> +static void gen_PADDB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> +
> + tcg_gen_gvec_add(MO_8,
> + decode->op[0].offset, decode->op[1].offset,
> + decode->op[2].offset, vec_len, vec_len);
> +}
Worth the creation of a helper and/or macro to reduce duplication?
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 22/37] target/i386: reimplement 0x0f 0x50-0x5f, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (20 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 21/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-12 13:46 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
` (14 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
These are mostly floating-point SSE operations. The odd ones out
are MOVMSK and CVTxx2yy, the others are straightforward.
Unary operations are a bit special in AVX because they have 2 operands
for PD/PS operands (VEX.vvvv must be 1111b), and 3 operands for SD/SS.
They are handled using X86_OP_GROUP3 for compactness.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 32 ++++++
target/i386/tcg/emit.c.inc | 175 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 2 +-
3 files changed, 208 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 59f5637583..5a94e05d71 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -243,7 +243,30 @@ static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
*entry = opcodes_0F3A[*b];
}
+static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
+ entry->op1 = X86_TYPE_None;
+ entry->s1 = X86_SIZE_None;
+ }
+ switch (*b) {
+ case 0x51: entry->gen = gen_VSQRT; break;
+ case 0x52: entry->gen = gen_VRSQRT; break;
+ case 0x53: entry->gen = gen_VRCP; break;
+ case 0x5A: entry->gen = gen_VCVTfp2fp; break;
+ }
+}
+
static const X86OpEntry opcodes_0F[256] = {
+ [0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
+ [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
+ [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
+ [0x54] = X86_OP_ENTRY3(VAND, V,x, H,x, W,x, vex4 p_00_66),
+ [0x55] = X86_OP_ENTRY3(VANDN, V,x, H,x, W,x, vex4 p_00_66),
+ [0x56] = X86_OP_ENTRY3(VOR, V,x, H,x, W,x, vex4 p_00_66),
+ [0x57] = X86_OP_ENTRY3(VXOR, V,x, H,x, W,x, vex4 p_00_66),
+
[0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
@@ -256,6 +279,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),
+ [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex3 p_00_66_f3_f2),
+ [0x5b] = X86_OP_ENTRY2(VCVTps_dq, V,x, W,x, vex2 p_00_66_f3),
+ [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0x5e] = X86_OP_ENTRY3(VDIV, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0x5f] = X86_OP_ENTRY3(VMAX, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+
[0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 1ba7a45668..5feb50efdb 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -246,6 +246,140 @@ static void gen_store_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
}
}
+static inline int sse_prefix(DisasContext *s)
+{
+ if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
+ return s->prefix & PREFIX_REPZ ? 0xf3 : 0xf2;
+ } else {
+ return s->prefix & PREFIX_DATA ? 0x66 : 0x00;
+ }
+}
+
+/*
+ * 00 = v*ps Vps, Hps, Wpd
+ * 66 = v*pd Vpd, Hpd, Wps
+ * f3 = v*ss Vss, Hss, Wps
+ * f2 = v*sd Vsd, Hsd, Wps
+ */
+static inline void gen_unary_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_epp pd_xmm, SSEFunc_0_epp ps_xmm,
+ SSEFunc_0_epp pd_ymm, SSEFunc_0_epp ps_ymm,
+ SSEFunc_0_eppp sd, SSEFunc_0_eppp ss)
+{
+ if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) {
+ SSEFunc_0_eppp fn = s->prefix & PREFIX_REPZ ? ss : sd;
+ if (!fn) {
+ gen_illegal_opcode(s);
+ return;
+ }
+ fn(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+ } else {
+ SSEFunc_0_epp ps, pd, fn;
+ ps = s->vex_l ? ps_ymm : ps_xmm;
+ pd = s->vex_l ? pd_ymm : pd_xmm;
+ fn = s->prefix & PREFIX_DATA ? pd : ps;
+ if (!fn) {
+ gen_illegal_opcode(s);
+ return;
+ }
+ fn(cpu_env, s->ptr0, s->ptr2);
+ }
+}
+#define UNARY_FP_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_unary_fp_sse(s, env, decode, \
+ gen_helper_##lname##pd_xmm, \
+ gen_helper_##lname##ps_xmm, \
+ gen_helper_##lname##pd_ymm, \
+ gen_helper_##lname##ps_ymm, \
+ gen_helper_##lname##sd, \
+ gen_helper_##lname##ss); \
+}
+UNARY_FP_SSE(VSQRT, sqrt)
+
+/*
+ * 00 = v*ps Vps, Hps, Wpd
+ * 66 = v*pd Vpd, Hpd, Wps
+ * f3 = v*ss Vss, Hss, Wps
+ * f2 = v*sd Vsd, Hsd, Wps
+ */
+static inline void gen_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm,
+ SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm,
+ SSEFunc_0_eppp sd, SSEFunc_0_eppp ss)
+{
+ SSEFunc_0_eppp ps, pd, fn;
+ if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) {
+ fn = s->prefix & PREFIX_REPZ ? ss : sd;
+ } else {
+ ps = s->vex_l ? ps_ymm : ps_xmm;
+ pd = s->vex_l ? pd_ymm : pd_xmm;
+ fn = s->prefix & PREFIX_DATA ? pd : ps;
+ }
+ if (fn) {
+ fn(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+ } else {
+ gen_illegal_opcode(s);
+ }
+}
+#define FP_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_fp_sse(s, env, decode, \
+ gen_helper_##lname##pd_xmm, \
+ gen_helper_##lname##ps_xmm, \
+ gen_helper_##lname##pd_ymm, \
+ gen_helper_##lname##ps_ymm, \
+ gen_helper_##lname##sd, \
+ gen_helper_##lname##ss); \
+}
+FP_SSE(VADD, add)
+FP_SSE(VMUL, mul)
+FP_SSE(VSUB, sub)
+FP_SSE(VMIN, min)
+FP_SSE(VDIV, div)
+FP_SSE(VMAX, max)
+
+/*
+ * 00 = v*ps Vps, Wpd
+ * f3 = v*ss Vss, Wps
+ */
+static inline void gen_unary_fp32_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_epp ps_xmm,
+ SSEFunc_0_epp ps_ymm,
+ SSEFunc_0_eppp ss)
+{
+ if ((s->prefix & (PREFIX_DATA | PREFIX_REPNZ)) != 0) {
+ goto illegal_op;
+ } else if (s->prefix & PREFIX_REPZ) {
+ if (!ss) {
+ goto illegal_op;
+ }
+ ss(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+ } else {
+ SSEFunc_0_epp fn = s->vex_l ? ps_ymm : ps_xmm;
+ if (!fn) {
+ goto illegal_op;
+ }
+ fn(cpu_env, s->ptr0, s->ptr2);
+ }
+ return;
+
+illegal_op:
+ gen_illegal_opcode(s);
+}
+#define UNARY_FP32_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_unary_fp32_sse(s, env, decode, \
+ gen_helper_##lname##ps_xmm, \
+ gen_helper_##lname##ps_ymm, \
+ gen_helper_##lname##ss); \
+}
+UNARY_FP32_SSE(VRSQRT, rsqrt)
+UNARY_FP32_SSE(VRCP, rcp)
+
/*
* 00 = p* Pq, Qq (if mmx not NULL; no VEX)
* 66 = vp* Vx, Hx, Wx
@@ -517,6 +651,16 @@ static void gen_MOVDQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_store_sse(s, env, decode, decode->op[2].offset);
}
+static void gen_MOVMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ typeof(gen_helper_movmskps_ymm) *ps, *pd, *fn;
+ ps = s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm;
+ pd = s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm;
+ fn = s->prefix & PREFIX_DATA ? pd : ps;
+ fn(s->tmp2_i32, cpu_env, s->ptr2);
+ tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
+}
+
static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[0].ot;
@@ -733,3 +877,34 @@ static void gen_SHRX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
}
tcg_gen_shr_tl(s->T0, s->T0, s->T1);
}
+
+#define gen_VAND gen_PAND
+#define gen_VANDN gen_PANDN
+
+static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_unary_fp_sse(s, env, decode,
+ gen_helper_cvtpd2ps_xmm, gen_helper_cvtps2pd_xmm,
+ gen_helper_cvtpd2ps_ymm, gen_helper_cvtps2pd_ymm,
+ gen_helper_cvtsd2ss, gen_helper_cvtss2sd);
+}
+
+static void gen_VCVTps_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ SSEFunc_0_epp fn = NULL;
+ switch (sse_prefix(s)) {
+ case 0x00:
+ fn = s->vex_l ? gen_helper_cvtdq2ps_ymm : gen_helper_cvtdq2ps_xmm;
+ break;
+ case 0x66:
+ fn = s->vex_l ? gen_helper_cvtps2dq_ymm : gen_helper_cvtps2dq_xmm;
+ break;
+ case 0xf3:
+ fn = s->vex_l ? gen_helper_cvttps2dq_ymm : gen_helper_cvttps2dq_xmm;
+ break;
+ }
+ fn(cpu_env, s->ptr0, s->ptr2);
+}
+
+#define gen_VOR gen_POR
+#define gen_VXOR gen_PXOR
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 11c17258eb..8ef419dd59 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4667,7 +4667,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
use_new &= b <= limit;
#endif
if (use_new &&
- ((b >= 0x160 && b <= 0x16f) ||
+ ((b >= 0x150 && b <= 0x16f) ||
(b >= 0x1d8 && b <= 0x1ff && (b & 8)))) {
return disas_insn_new(s, cpu, b + 0x100);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 22/37] target/i386: reimplement 0x0f 0x50-0x5f, add AVX
2022-09-11 23:04 ` [PATCH 22/37] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
@ 2022-09-12 13:46 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 13:46 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> These are mostly floating-point SSE operations. The odd ones out
> are MOVMSK and CVTxx2yy, the others are straightforward.
>
> Unary operations are a bit special in AVX because they have 2 operands
> for PD/PS operands (VEX.vvvv must be 1111b), and 3 operands for SD/SS.
> They are handled using X86_OP_GROUP3 for compactness.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 32 ++++++
> target/i386/tcg/emit.c.inc | 175 +++++++++++++++++++++++++++++++
> target/i386/tcg/translate.c | 2 +-
> 3 files changed, 208 insertions(+), 1 deletion(-)
>
> diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
> index 59f5637583..5a94e05d71 100644
> --- a/target/i386/tcg/decode-new.c.inc
> +++ b/target/i386/tcg/decode-new.c.inc
> @@ -243,7 +243,30 @@ static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
> *entry = opcodes_0F3A[*b];
> }
>
> +static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
> +{
> + if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
> + entry->op1 = X86_TYPE_None;
> + entry->s1 = X86_SIZE_None;
> + }
> + switch (*b) {
> + case 0x51: entry->gen = gen_VSQRT; break;
> + case 0x52: entry->gen = gen_VRSQRT; break;
> + case 0x53: entry->gen = gen_VRCP; break;
> + case 0x5A: entry->gen = gen_VCVTfp2fp; break;
> + }
> +}
I wonder if a .special would be cleaner here, but I guess this isn't horrible.
> + [0x54] = X86_OP_ENTRY3(VAND, V,x, H,x, W,x, vex4 p_00_66),
> + [0x55] = X86_OP_ENTRY3(VANDN, V,x, H,x, W,x, vex4 p_00_66),
> + [0x56] = X86_OP_ENTRY3(VOR, V,x, H,x, W,x, vex4 p_00_66),
> + [0x57] = X86_OP_ENTRY3(VXOR, V,x, H,x, W,x, vex4 p_00_66),
Just reuse PAND et al with a comment? I see there's a define later, but why?
> +static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + gen_unary_fp_sse(s, env, decode,
> + gen_helper_cvtpd2ps_xmm, gen_helper_cvtps2pd_xmm,
> + gen_helper_cvtpd2ps_ymm, gen_helper_cvtps2pd_ymm,
> + gen_helper_cvtsd2ss, gen_helper_cvtss2sd);
> +}
> +
> +static void gen_VCVTps_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + SSEFunc_0_epp fn = NULL;
> + switch (sse_prefix(s)) {
> + case 0x00:
> + fn = s->vex_l ? gen_helper_cvtdq2ps_ymm : gen_helper_cvtdq2ps_xmm;
> + break;
> + case 0x66:
> + fn = s->vex_l ? gen_helper_cvtps2dq_ymm : gen_helper_cvtps2dq_xmm;
> + break;
> + case 0xf3:
> + fn = s->vex_l ? gen_helper_cvttps2dq_ymm : gen_helper_cvttps2dq_xmm;
> + break;
> + }
> + fn(cpu_env, s->ptr0, s->ptr2);
> +}
Only use of sse_prefix? We directly look at prefix bits elsewhere...
Also, while these are all coverts, it doesn't seem conceptually different from
decode_group_twobyte_6F. Why are we waiting until generation in this case?
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (21 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 22/37] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-12 13:56 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
` (13 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
These are a mixed match, including the first two horizontal
(66 and F2 only) operations, more moves, and SSE4a extract/insert.
Because SSE4a is pretty rare, I chose to leave the helper as they are,
but it is possible to unify them by loading index and length from the
source XMM register.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 23 +++++++++
target/i386/tcg/emit.c.inc | 81 ++++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 1 +
3 files changed, 105 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 5a94e05d71..6aa8bac74f 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -159,6 +159,22 @@ static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
}
+static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry movd_from_vec =
+ X86_OP_ENTRY3(MOVD_from, E,y, None,None, V,y, vex5 mmx);
+ static const X86OpEntry movq =
+ X86_OP_ENTRY3(MOVQ, V,x, None,None, W,q, vex5); /* wrong dest Vy on SDM! */
+
+ if (s->prefix & PREFIX_REPNZ) {
+ entry->gen = NULL;
+ } else if (s->prefix & PREFIX_REPZ) {
+ *entry = movq;
+ } else {
+ *entry = movd_from_vec;
+ }
+}
+
static const X86OpEntry opcodes_0F38_00toEF[240] = {
};
@@ -297,6 +313,13 @@ static const X86OpEntry opcodes_0F[256] = {
[0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
[0x6f] = X86_OP_GROUP3(0F6F, V,x, None,None, W,x, vex5 mmx p_00_66_f3),
+ [0x78] = X86_OP_ENTRY2(SSE4a_I, V,x, I,w, cpuid(SSE4A) p_66_f2),
+ [0x79] = X86_OP_ENTRY2(SSE4a_R, V,x, W,x, cpuid(SSE4A) p_66_f2),
+ [0x7c] = X86_OP_ENTRY3(VHADD, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
+ [0x7d] = X86_OP_ENTRY3(VHSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
+ [0x7e] = X86_OP_GROUP0(0F7E),
+ [0x7f] = X86_OP_GROUP3(0F6F, W,x, None,None, V,x, vex5 mmx p_00_66_f3),
+
/* Incorrectly missing from 2-17 */
[0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 5feb50efdb..2053c9d8fb 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -380,6 +380,30 @@ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
UNARY_FP32_SSE(VRSQRT, rsqrt)
UNARY_FP32_SSE(VRCP, rcp)
+/*
+ * 66 = v*pd Vpd, Hpd, Wpd
+ * f2 = v*ps Vps, Hps, Wps
+ */
+static inline void gen_horizontal_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm,
+ SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm)
+{
+ SSEFunc_0_eppp ps, pd, fn;
+ ps = s->vex_l ? ps_ymm : ps_xmm;
+ pd = s->vex_l ? pd_ymm : pd_xmm;
+ fn = s->prefix & PREFIX_DATA ? pd : ps;
+ fn(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+}
+#define HORIZONTAL_FP_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_horizontal_fp_sse(s, env, decode, \
+ gen_helper_##lname##pd_xmm, gen_helper_##lname##ps_xmm, \
+ gen_helper_##lname##pd_ymm, gen_helper_##lname##ps_ymm); \
+}
+HORIZONTAL_FP_SSE(VHADD, hadd)
+HORIZONTAL_FP_SSE(VHSUB, hsub)
+
/*
* 00 = p* Pq, Qq (if mmx not NULL; no VEX)
* 66 = vp* Vx, Hx, Wx
@@ -621,6 +645,28 @@ static void gen_MOVBE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
}
}
+static void gen_MOVD_from(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[2].ot;
+ int lo_ofs = decode->op[2].offset
+ - xmm_offset(decode->op[2].ot)
+ + xmm_offset(ot);
+
+ switch (ot) {
+ case MO_32:
+#ifdef TARGET_X86_64
+ tcg_gen_ld_i32(s->tmp2_i32, cpu_env, lo_ofs);
+ tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
+ break;
+ case MO_64:
+#endif
+ tcg_gen_ld_tl(s->T0, cpu_env, lo_ofs);
+ break;
+ default:
+ abort();
+ }
+}
+
static void gen_MOVD_to(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[2].ot;
@@ -661,6 +707,18 @@ static void gen_MOVMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode
tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
}
+static void gen_MOVQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+ int lo_ofs = decode->op[0].offset
+ - xmm_offset(decode->op[0].ot)
+ + xmm_offset(MO_64);
+
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset);
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, lo_ofs);
+}
+
static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[0].ot;
@@ -878,6 +936,29 @@ static void gen_SHRX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
tcg_gen_shr_tl(s->T0, s->T0, s->T1);
}
+static void gen_SSE4a_I(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 length = tcg_const_i32(decode->immediate & 255);
+ TCGv_i32 index = tcg_const_i32(decode->immediate >> 8);
+
+ if (s->prefix & PREFIX_DATA) {
+ gen_helper_extrq_i(cpu_env, s->ptr0, index, length);
+ } else {
+ gen_helper_insertq_i(cpu_env, s->ptr0, index, length);
+ }
+ tcg_temp_free_i32(length);
+ tcg_temp_free_i32(index);
+}
+
+static void gen_SSE4a_R(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (s->prefix & PREFIX_DATA) {
+ gen_helper_extrq_r(cpu_env, s->ptr0, s->ptr2);
+ } else {
+ gen_helper_insertq_r(cpu_env, s->ptr0, s->ptr2);
+ }
+}
+
#define gen_VAND gen_PAND
#define gen_VANDN gen_PANDN
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 8ef419dd59..53d693279a 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4668,6 +4668,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#endif
if (use_new &&
((b >= 0x150 && b <= 0x16f) ||
+ (b >= 0x178 && b <= 0x17f) ||
(b >= 0x1d8 && b <= 0x1ff && (b & 8)))) {
return disas_insn_new(s, cpu, b + 0x100);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX
2022-09-11 23:04 ` [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
@ 2022-09-12 13:56 ` Richard Henderson
2022-09-14 16:17 ` Paolo Bonzini
0 siblings, 1 reply; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 13:56 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> +static void gen_MOVD_from(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + MemOp ot = decode->op[2].ot;
> + int lo_ofs = decode->op[2].offset
> + - xmm_offset(decode->op[2].ot)
> + + xmm_offset(ot);
> +
> + switch (ot) {
> + case MO_32:
> +#ifdef TARGET_X86_64
> + tcg_gen_ld_i32(s->tmp2_i32, cpu_env, lo_ofs);
> + tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
tcg_gen_ld32u_tl(s->T0, cpu_env, lo_ofs);
> +static void gen_MOVQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> + int lo_ofs = decode->op[0].offset
> + - xmm_offset(decode->op[0].ot)
> + + xmm_offset(MO_64);
> +
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset);
> + tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, lo_ofs);
tcg_gen_gvec_dup_i64(MO_64, offset, 8, sse_vec_max_len, s->tmp1_i64);
> +static void gen_SSE4a_I(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv_i32 length = tcg_const_i32(decode->immediate & 255);
> + TCGv_i32 index = tcg_const_i32(decode->immediate >> 8);
> +
> + if (s->prefix & PREFIX_DATA) {
> + gen_helper_extrq_i(cpu_env, s->ptr0, index, length);
> + } else {
> + gen_helper_insertq_i(cpu_env, s->ptr0, index, length);
> + }
> + tcg_temp_free_i32(length);
> + tcg_temp_free_i32(index);
Again, why the choice of delayed decode? I guess it doesn't matter, but it's odd.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX
2022-09-12 13:56 ` Richard Henderson
@ 2022-09-14 16:17 ` Paolo Bonzini
0 siblings, 0 replies; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-14 16:17 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Mon, Sep 12, 2022 at 3:56 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> > +static void gen_SSE4a_I(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> > +{
> > + TCGv_i32 length = tcg_const_i32(decode->immediate & 255);
> > + TCGv_i32 index = tcg_const_i32(decode->immediate >> 8);
> > +
> > + if (s->prefix & PREFIX_DATA) {
> > + gen_helper_extrq_i(cpu_env, s->ptr0, index, length);
> > + } else {
> > + gen_helper_insertq_i(cpu_env, s->ptr0, index, length);
> > + }
> > + tcg_temp_free_i32(length);
> > + tcg_temp_free_i32(index);
>
> Again, why the choice of delayed decode? I guess it doesn't matter, but it's odd.
Mostly because I wasn't sure of which would be preferable so I tried
different things. I think now I have a better picture.
I will mostly switch to decode_by_prefix.
Paolo
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (22 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-12 14:29 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
` (12 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
This includes shifts by immediate, which use bits 3-5 of the ModRM byte
as an opcode extension. With the exception of 128-bit shifts, they are
implemented using gvec.
This also covers VZEROALL and VZEROUPPER, which use the same opcode
as EMMS. If we were wanting to optimize out gen_clear_ymmh then this
would be one of the starting points. The implementation of the VZEROALL
and VZEROUPPER helpers is by Paul Brook.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/helper.h | 7 +
target/i386/tcg/decode-new.c.inc | 76 ++++++++++
target/i386/tcg/emit.c.inc | 232 +++++++++++++++++++++++++++++++
target/i386/tcg/fpu_helper.c | 46 ++++++
target/i386/tcg/translate.c | 3 +-
5 files changed, 362 insertions(+), 2 deletions(-)
diff --git a/target/i386/helper.h b/target/i386/helper.h
index 3da5df98b9..d7e6878263 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -221,6 +221,13 @@ DEF_HELPER_3(movq, void, env, ptr, ptr)
#define SHIFT 2
#include "ops_sse_header.h"
+DEF_HELPER_1(vzeroall, void, env)
+DEF_HELPER_1(vzeroupper, void, env)
+#ifdef TARGET_X86_64
+DEF_HELPER_1(vzeroall_hi8, void, env)
+DEF_HELPER_1(vzeroupper_hi8, void, env)
+#endif
+
DEF_HELPER_3(rclb, tl, env, tl, tl)
DEF_HELPER_3(rclw, tl, env, tl, tl)
DEF_HELPER_3(rcll, tl, env, tl, tl)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 6aa8bac74f..0e2da85934 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -133,6 +133,19 @@ static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
return s->modrm;
}
+static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4])
+{
+ if (s->prefix & PREFIX_REPNZ) {
+ return &entries[3];
+ } else if (s->prefix & PREFIX_REPZ) {
+ return &entries[2];
+ } else if (s->prefix & PREFIX_DATA) {
+ return &entries[1];
+ } else {
+ return &entries[0];
+ }
+}
+
static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86GenFunc group17_gen[8] = {
@@ -142,6 +155,48 @@ static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
entry->gen = group17_gen[op];
}
+static void decode_group12_13_14(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry group[3][8] = {
+ {
+ /* grp12 */
+ {},
+ {},
+ X86_OP_ENTRY3(PSRLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ {},
+ X86_OP_ENTRY3(PSRAW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ {},
+ X86_OP_ENTRY3(PSLLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ {},
+ },
+ {
+ /* grp13 */
+ {},
+ {},
+ X86_OP_ENTRY3(PSRLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ {},
+ X86_OP_ENTRY3(PSRAD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ {},
+ X86_OP_ENTRY3(PSLLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ {},
+ },
+ {
+ /* grp14 */
+ {},
+ {},
+ X86_OP_ENTRY3(PSRLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ X86_OP_ENTRY3(PSRLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
+ {},
+ {},
+ X86_OP_ENTRY3(PSLLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
+ X86_OP_ENTRY3(PSLLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
+ }
+ };
+
+ int op = (get_modrm(s, env) >> 3) & 7;
+ *entry = group[*b - 0x71][op];
+}
+
static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
if (s->prefix & PREFIX_REPNZ) {
@@ -159,6 +214,18 @@ static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
}
+static void decode_0F70(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry pshufw[4] = {
+ X86_OP_ENTRY3(PSHUFW, P,q, Q,q, I,b, vex4),
+ X86_OP_ENTRY3(PSHUFD, V,x, W,x, I,b, vex4 avx2_256),
+ X86_OP_ENTRY3(PSHUFHW, V,x, W,x, I,b, vex4 avx2_256),
+ X86_OP_ENTRY3(PSHUFLW, V,x, W,x, I,b, vex4 avx2_256),
+ };
+
+ *entry = *decode_by_prefix(s, pshufw);
+}
+
static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry movd_from_vec =
@@ -292,6 +359,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x70] = X86_OP_GROUP0(0F70),
+ [0x71] = X86_OP_GROUP0(group12_13_14),
+ [0x72] = X86_OP_GROUP0(group12_13_14),
+ [0x73] = X86_OP_GROUP0(group12_13_14),
+ [0x74] = X86_OP_ENTRY3(PCMPEQB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x75] = X86_OP_ENTRY3(PCMPEQW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0x77] = X86_OP_ENTRY0(EMMS_VZERO, vex8),
+
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 2053c9d8fb..fb01035d06 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -475,6 +475,30 @@ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
BINARY_INT_SSE(PUNPCKLQDQ, punpcklqdq)
BINARY_INT_SSE(PUNPCKHQDQ, punpckhqdq)
+static inline void gen_unary_imm_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_ppi xmm, SSEFunc_0_ppi ymm)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ if (!s->vex_l) {
+ xmm(s->ptr0, s->ptr1, imm);
+ } else {
+ ymm(s->ptr0, s->ptr1, imm);
+ }
+ tcg_temp_free_i32(imm);
+}
+
+#define UNARY_IMM_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_unary_imm_sse(s, env, decode, \
+ gen_helper_##lname##_xmm, \
+ gen_helper_##lname##_ymm); \
+}
+
+UNARY_IMM_SSE(PSHUFD, pshufd)
+UNARY_IMM_SSE(PSHUFHW, pshufhw)
+UNARY_IMM_SSE(PSHUFLW, pshuflw)
+
static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
{
TCGv carry_in = NULL;
@@ -633,6 +657,29 @@ static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_const_i32(8 << ot));
}
+static void gen_EMMS_VZERO(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (!(s->prefix & PREFIX_VEX)) {
+ gen_helper_emms(cpu_env);
+ return;
+ }
+ if (s->vex_l) {
+ gen_helper_vzeroall(cpu_env);
+#ifdef TARGET_X86_64
+ if (CODE64(s)) {
+ gen_helper_vzeroall_hi8(cpu_env);
+ }
+#endif
+ } else {
+ gen_helper_vzeroupper(cpu_env);
+#ifdef TARGET_X86_64
+ if (CODE64(s)) {
+ gen_helper_vzeroupper_hi8(cpu_env);
+ }
+#endif
+ }
+}
+
static void gen_MOVBE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[0].ot;
@@ -787,6 +834,33 @@ static void gen_PANDN(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
decode->op[1].offset, vec_len, vec_len);
}
+static void gen_PCMPEQB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_EQ, MO_8,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PCMPEQW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_EQ, MO_16,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PCMPEQD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_EQ, MO_32,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
static void gen_PCMPGTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
@@ -841,6 +915,164 @@ static void gen_POR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
decode->op[2].offset, vec_len, vec_len);
}
+static void gen_PSHUFW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ gen_helper_pshufw_mmx(s->ptr0, s->ptr1, imm);
+ tcg_temp_free_i32(imm);
+}
+
+static void gen_PSRLW_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 16) {
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ } else {
+ tcg_gen_gvec_shri(MO_16,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+ }
+}
+
+static void gen_PSLLW_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 16) {
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ } else {
+ tcg_gen_gvec_shli(MO_16,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+ }
+}
+
+static void gen_PSRAW_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 16) {
+ decode->immediate = 15;
+ }
+ tcg_gen_gvec_sari(MO_16,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+}
+
+static void gen_PSRLD_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 32) {
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ } else {
+ tcg_gen_gvec_shri(MO_32,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+ }
+}
+
+static void gen_PSLLD_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 32) {
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ } else {
+ tcg_gen_gvec_shli(MO_32,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+ }
+}
+
+static void gen_PSRAD_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 32) {
+ decode->immediate = 31;
+ }
+ tcg_gen_gvec_sari(MO_32,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+}
+
+static void gen_PSRLQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 64) {
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ } else {
+ tcg_gen_gvec_shri(MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+ }
+}
+
+static void gen_PSLLQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ if (decode->immediate >= 64) {
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ } else {
+ tcg_gen_gvec_shli(MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->immediate, vec_len, vec_len);
+ }
+}
+
+static inline TCGv_ptr make_imm_mmx_vec(uint32_t imm)
+{
+ TCGv_i64 imm_v = tcg_const_i64(imm);
+ TCGv_ptr ptr = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, mmx_t0));
+ tcg_gen_st_i64(imm_v, ptr, offsetof(MMXReg, MMX_Q(0)));
+ return ptr;
+}
+
+static inline TCGv_ptr make_imm_xmm_vec(uint32_t imm, int vec_len)
+{
+ MemOp ot = vec_len == 16 ? MO_128 : MO_256;
+ TCGv_i32 imm_v = tcg_const_i32(imm);
+ TCGv_ptr ptr = tcg_temp_new_ptr();
+
+ tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset(ot),
+ vec_len, vec_len, 0);
+
+ tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0));
+ tcg_gen_st_i32(imm_v, ptr, offsetof(ZMMReg, ZMM_L(0)));
+ return ptr;
+}
+
+static void gen_PSRLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+ TCGv_ptr imm_vec = make_imm_xmm_vec(decode->immediate, vec_len);
+
+ if (s->vex_l) {
+ gen_helper_psrldq_ymm(cpu_env, s->ptr0, s->ptr1, imm_vec);
+ } else {
+ gen_helper_psrldq_xmm(cpu_env, s->ptr0, s->ptr1, imm_vec);
+ }
+ tcg_temp_free_ptr(imm_vec);
+}
+
+static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+ TCGv_ptr imm_vec = make_imm_xmm_vec(decode->immediate, vec_len);
+
+ if (s->vex_l) {
+ gen_helper_pslldq_ymm(cpu_env, s->ptr0, s->ptr1, imm_vec);
+ } else {
+ gen_helper_pslldq_xmm(cpu_env, s->ptr0, s->ptr1, imm_vec);
+ }
+ tcg_temp_free_ptr(imm_vec);
+}
+
static void gen_PXOR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 819e920ec6..230907bc5c 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -3056,3 +3056,49 @@ void helper_movq(CPUX86State *env, void *d, void *s)
#define SHIFT 2
#include "ops_sse.h"
+
+void helper_vzeroall(CPUX86State *env)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ env->xmm_regs[i].ZMM_Q(0) = 0;
+ env->xmm_regs[i].ZMM_Q(1) = 0;
+ env->xmm_regs[i].ZMM_Q(2) = 0;
+ env->xmm_regs[i].ZMM_Q(3) = 0;
+ }
+}
+
+void helper_vzeroupper(CPUX86State *env)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ env->xmm_regs[i].ZMM_Q(2) = 0;
+ env->xmm_regs[i].ZMM_Q(3) = 0;
+ }
+}
+
+#ifdef TARGET_X86_64
+void helper_vzeroall_hi8(CPUX86State *env)
+{
+ int i;
+
+ for (i = 8; i < 16; i++) {
+ env->xmm_regs[i].ZMM_Q(0) = 0;
+ env->xmm_regs[i].ZMM_Q(1) = 0;
+ env->xmm_regs[i].ZMM_Q(2) = 0;
+ env->xmm_regs[i].ZMM_Q(3) = 0;
+ }
+}
+
+void helper_vzeroupper_hi8(CPUX86State *ense_new &&
- ((b >= 0x150 && b <= 0x16f) ||
- (b >= 0x178 && b <= 0x17f) ||
+ ((b >= 0x150 && b <= 0x17f) ||
(b >= 0x1d8 && b <= 0x1ff && (b & 8)))) {
return disas_insn_new(s, cpu, b + 0x100);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, add AVX
2022-09-11 23:04 ` [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
@ 2022-09-12 14:29 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 14:29 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> This includes shifts by immediate, which use bits 3-5 of the ModRM byte
> as an opcode extension. With the exception of 128-bit shifts, they are
> implemented using gvec.
>
> This also covers VZEROALL and VZEROUPPER, which use the same opcode
> as EMMS. If we were wanting to optimize out gen_clear_ymmh then this
> would be one of the starting points. The implementation of the VZEROALL
> and VZEROUPPER helpers is by Paul Brook.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/helper.h | 7 +
> target/i386/tcg/decode-new.c.inc | 76 ++++++++++
> target/i386/tcg/emit.c.inc | 232 +++++++++++++++++++++++++++++++
> target/i386/tcg/fpu_helper.c | 46 ++++++
> target/i386/tcg/translate.c | 3 +-
> 5 files changed, 362 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/helper.h b/target/i386/helper.h
> index 3da5df98b9..d7e6878263 100644
> --- a/target/i386/helper.h
> +++ b/target/i386/helper.h
> @@ -221,6 +221,13 @@ DEF_HELPER_3(movq, void, env, ptr, ptr)
> #define SHIFT 2
> #include "ops_sse_header.h"
>
> +DEF_HELPER_1(vzeroall, void, env)
> +DEF_HELPER_1(vzeroupper, void, env)
> +#ifdef TARGET_X86_64
> +DEF_HELPER_1(vzeroall_hi8, void, env)
> +DEF_HELPER_1(vzeroupper_hi8, void, env)
> +#endif
> +
> DEF_HELPER_3(rclb, tl, env, tl, tl)
> DEF_HELPER_3(rclw, tl, env, tl, tl)
> DEF_HELPER_3(rcll, tl, env, tl, tl)
> diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
> index 6aa8bac74f..0e2da85934 100644
> --- a/target/i386/tcg/decode-new.c.inc
> +++ b/target/i386/tcg/decode-new.c.inc
> @@ -133,6 +133,19 @@ static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
> return s->modrm;
> }
>
> +static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4])
> +{
> + if (s->prefix & PREFIX_REPNZ) {
> + return &entries[3];
> + } else if (s->prefix & PREFIX_REPZ) {
> + return &entries[2];
> + } else if (s->prefix & PREFIX_DATA) {
> + return &entries[1];
> + } else {
> + return &entries[0];
> + }
> +}
This is the sort of thing I would have expected for some of the other insns for which the
distiction was delayed until generation, like SSE4a_{R,I}.
> +static void decode_group12_13_14(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
> +{
> + static const X86OpEntry group[3][8] = {
> + {
> + /* grp12 */
> + {},
> + {},
> + X86_OP_ENTRY3(PSRLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
> + {},
> + X86_OP_ENTRY3(PSRAW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
> + {},
> + X86_OP_ENTRY3(PSLLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
> + {},
> + },
Why combine these 3 groups?
> + *entry = group[*b - 0x71][op];
Split them and you avoid this magic number.
> +static inline void gen_unary_imm_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> + SSEFunc_0_ppi xmm, SSEFunc_0_ppi ymm)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
Use tcg_constant_i32, which need not be freed.
> +static void gen_EMMS_VZERO(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + if (!(s->prefix & PREFIX_VEX)) {
> + gen_helper_emms(cpu_env);
> + return;
> + }
Split in decode? That would make vex8 simpler too.
> +static inline TCGv_ptr make_imm_mmx_vec(uint32_t imm)
Unused? Please do drop all of the inline markers, and/or do build testing with clang,
which will Werror on this.
> +static inline TCGv_ptr make_imm_xmm_vec(uint32_t imm, int vec_len)
> +{
> + MemOp ot = vec_len == 16 ? MO_128 : MO_256;
> + TCGv_i32 imm_v = tcg_const_i32(imm);
tcg_constant_i32, however I think this use can go away too.
> +static void gen_PSRLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> + TCGv_ptr imm_vec = make_imm_xmm_vec(decode->immediate, vec_len);
> +
> + if (s->vex_l) {
> + gen_helper_psrldq_ymm(cpu_env, s->ptr0, s->ptr1, imm_vec);
> + } else {
> + gen_helper_psrldq_xmm(cpu_env, s->ptr0, s->ptr1, imm_vec);
> + }
> + tcg_temp_free_ptr(imm_vec);
Let's just do this inline:
int shift = decode->immediate * 8;
if (shift >= 128) {
zero;
return;
}
for (lane = 0; lane <= s->vex_l; lane++) {
TCGv_i64 q0 = tcg_temp_new_i64();
TCGv_i64 q1 = tcg_temp_new_i64();
tcg_gen_ld_i64(q0, cpu_env, offset + lane * 16 + offsetof(XMMReg, MMX_Q(0));
tcg_gen_ld_i64(q1, ...);
if (shift >= 64) {
tcg_gen_shri_i64(q0, q1, shift - 64);
tcg_gen_movi_i64(q1, 0);
} else {
tcg_gen_extract2_i64(q0, q0, q1, shift);
tcg_gen_shri_i64(q1, q1, shift);
}
tcg_gen_st_i64(q0, cpu_env, offset + lane * 16 + offsetof(XMMReg, MMX_Q(0));
tcg_gen_st_i64(q1, ...);
}
> +static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> + TCGv_ptr imm_vec = make_imm_xmm_vec(decode->immediate, vec_len);
> +
> + if (s->vex_l) {
> + gen_helper_pslldq_ymm(cpu_env, s->ptr0, s->ptr1, imm_vec);
> + } else {
> + gen_helper_pslldq_xmm(cpu_env, s->ptr0, s->ptr1, imm_vec);
> + }
> + tcg_temp_free_ptr(imm_vec);
> +}
Similar, but the extract2 becomes
tcg_gen_extract2_i64(q1, q0, q1, 64 - shift);
> +void helper_vzeroall(CPUX86State *env)
> +{
> + int i;
> +
> + for (i = 0; i < 8; i++) {
> + env->xmm_regs[i].ZMM_Q(0) = 0;
> + env->xmm_regs[i].ZMM_Q(1) = 0;
> + env->xmm_regs[i].ZMM_Q(2) = 0;
> + env->xmm_regs[i].ZMM_Q(3) = 0;
> + }
> +}
Better with memset, I think, available as gen_helper_memset().
> +#ifdef TARGET_X86_64
> +void helper_vzeroall_hi8(CPUX86State *env)
> +{
> + int i;
> +
> + for (i = 8; i < 16; i++) {
> + env->xmm_regs[i].ZMM_Q(0) = 0;
> + env->xmm_regs[i].ZMM_Q(1) = 0;
> + env->xmm_regs[i].ZMM_Q(2) = 0;
> + env->xmm_regs[i].ZMM_Q(3) = 0;
> + }
> +}
Likewise.
> +
> +void helper_vzeroupper_hi8(CPUX86State *ense_new &&
> - ((b >= 0x150 && b <= 0x16f) ||
> - (b >= 0x178 && b <= 0x17f) ||
> + ((b >= 0x150 && b <= 0x17f) ||
> (b >= 0x1d8 && b <= 0x1ff && (b & 8)))) {
> return disas_insn_new(s, cpu, b + 0x100);
> }
More mailer lossage?
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (23 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-12 15:06 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, " Paolo Bonzini
` (11 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
The more complicated ones here are d6-d7, e6-e7, f7. The others
are trivial.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 39 +++++++++++++
target/i386/tcg/emit.c.inc | 99 +++++++++++++++++++++++++++++---
target/i386/tcg/translate.c | 4 +-
3 files changed, 133 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 0e2da85934..e9a9981a7f 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -242,6 +242,18 @@ static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
}
+static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry movq[4] = {
+ {},
+ X86_OP_ENTRY3(MOVQ, W,x, None, None, V,q, vex5),
+ X86_OP_ENTRY3(MOVq_dq, V,dq, None, None, N,q),
+ X86_OP_ENTRY3(MOVq_dq, P,q, None, None, U,q),
+ };
+
+ *entry = *decode_by_prefix(s, movq);
+}
+
static const X86OpEntry opcodes_0F38_00toEF[240] = {
};
@@ -396,6 +408,33 @@ static const X86OpEntry opcodes_0F[256] = {
[0x7e] = X86_OP_GROUP0(0F7E),
[0x7f] = X86_OP_GROUP3(0F6F, W,x, None,None, V,x, vex5 mmx p_00_66_f3),
+ [0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
+ [0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xd6] = X86_OP_GROUP0(0FD6),
+ [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256 p_00_66), /* MOVNTQ/MOVNTDQ */
+
+ [0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
+ [0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
+ [0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xe6] = X86_OP_ENTRY2(VCVTpd_dq, V,x, W,x, vex2 p_66_f3_f2),
+ [0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66), /* MOVNTQ/MOVNTDQ */
+
+ [0xf0] = X86_OP_ENTRY3(LDDQU, V,x, None,None, M,x, vex4_unal cpuid(SSE3) p_f2),
+ [0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
+ [0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
+ [0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
+ [0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
+ [0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256 mmx p_00_66),
+
/* Incorrectly missing from 2-17 */
[0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index fb01035d06..c90f933093 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -403,6 +403,7 @@ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
}
HORIZONTAL_FP_SSE(VHADD, hadd)
HORIZONTAL_FP_SSE(VHSUB, hsub)
+HORIZONTAL_FP_SSE(VADDSUB, addsub)
/*
* 00 = p* Pq, Qq (if mmx not NULL; no VEX)
@@ -462,6 +463,24 @@ BINARY_INT_MMX(PADDSB, paddsb)
BINARY_INT_MMX(PADDSW, paddsw)
BINARY_INT_MMX(PMAXSW, pmaxsw)
+BINARY_INT_MMX(PAVGB, pavgb)
+BINARY_INT_MMX(PAVGW, pavgw)
+BINARY_INT_MMX(PMADDWD, pmaddwd)
+BINARY_INT_MMX(PMULHUW, pmulhuw)
+BINARY_INT_MMX(PMULHW, pmulhw)
+BINARY_INT_MMX(PMULLW, pmullw)
+BINARY_INT_MMX(PMULUDQ, pmuludq)
+BINARY_INT_MMX(PSADBW, psadbw)
+
+BINARY_INT_MMX(PSLLW_r, psllw)
+BINARY_INT_MMX(PSLLD_r, pslld)
+BINARY_INT_MMX(PSLLQ_r, psllq)
+BINARY_INT_MMX(PSRLW_r, psrlw)
+BINARY_INT_MMX(PSRLD_r, psrld)
+BINARY_INT_MMX(PSRLQ_r, psrlq)
+BINARY_INT_MMX(PSRAW_r, psraw)
+BINARY_INT_MMX(PSRAD_r, psrad)
+
/* Instructions with no MMX equivalent. */
#define BINARY_INT_SSE(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
@@ -680,6 +699,24 @@ static void gen_EMMS_VZERO(DisasContext *s, CPUX86State *env, X86DecodedInsn *de
}
}
+static void gen_LDDQU(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_load_sse(s, s->T0, decode->op[0].ot, decode->op[0].offset);
+}
+
+static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_mov_tl(s->A0, cpu_regs[R_EDI]);
+ gen_extu(s->aflag, s->A0);
+ gen_add_A0_ds_seg(s);
+
+ if (s->prefix & PREFIX_DATA) {
+ gen_helper_maskmov_xmm(cpu_env, s->ptr1, s->ptr2, s->A0);
+ } else {
+ gen_helper_maskmov_mmx(cpu_env, s->ptr1, s->ptr2, s->A0);
+ }
+}
+
static void gen_MOVBE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[0].ot;
@@ -756,14 +793,26 @@ static void gen_MOVMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode
static void gen_MOVQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- int vec_len = sse_vec_len(s, decode);
- int lo_ofs = decode->op[0].offset
- - xmm_offset(decode->op[0].ot)
- + xmm_offset(MO_64);
-
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset);
- tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, lo_ofs);
+
+ if (decode->op[0].has_ea) {
+ gen_op_st_v(s, MO_64, s->tmp1_i64, s->A0);
+ } else {
+ int vec_len = sse_vec_len(s, decode);
+ int lo_ofs = decode->op[0].offset
+ - xmm_offset(decode->op[0].ot)
+ + xmm_offset(MO_64);
+
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, lo_ofs);
+ }
+}
+
+static void gen_MOVq_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_helper_enter_mmx(cpu_env);
+ /* Otherwise the same as any other movq. */
+ return gen_MOVQ(s, env, decode);
}
static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@@ -816,6 +865,15 @@ static void gen_PADDD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
decode->op[2].offset, vec_len, vec_len);
}
+static void gen_PADDQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_add(MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
static void gen_PAND(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
@@ -906,6 +964,16 @@ static void gen_PEXT(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_helper_pext(s->T0, s->T0, s->T1);
}
+static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (s->prefix & PREFIX_DATA) {
+ gen_helper_pmovmskb_xmm(s->tmp2_i32, cpu_env, s->ptr2);
+ } else {
+ gen_helper_pmovmskb_mmx(s->tmp2_i32, cpu_env, s->ptr2);
+ }
+ tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
+}
+
static void gen_POR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
@@ -1202,6 +1270,23 @@ static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
gen_helper_cvtsd2ss, gen_helper_cvtss2sd);
}
+static void gen_VCVTpd_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ SSEFunc_0_epp fn = NULL;
+ switch (sse_prefix(s)) {
+ case 0x66:
+ fn = s->vex_l ? gen_helper_cvttpd2dq_ymm : gen_helper_cvttpd2dq_xmm;
+ break;
+ case 0xf3:
+ fn = s->vex_l ? gen_helper_cvtdq2pd_ymm : gen_helper_cvtdq2pd_xmm;
+ break;
+ case 0xf2:
+ fn = s->vex_l ? gen_helper_cvtpd2dq_ymm : gen_helper_cvtpd2dq_xmm;
+ break;
+ }
+ fn(cpu_env, s->ptr0, s->ptr2);
+}
+
static void gen_VCVTps_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
SSEFunc_0_epp fn = NULL;
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 45287dfea2..d15e988891 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4668,8 +4668,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#endif
if (use_new &&
((b >= 0x150 && b <= 0x17f) ||
- (b >= 0x1d8 && b <= 0x1ff && (b & 8)))) {
- return disas_insn_new(s, cpu, b + 0x100);
+ (b >= 0x1d0 && b <= 0x1ff))) {
+ return disas_insn_new(s, cpu, b);
}
break;
case 0xf3:
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX
2022-09-11 23:04 ` [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
@ 2022-09-12 15:06 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 15:06 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> + [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256 p_00_66), /* MOVNTQ/MOVNTDQ */
Cut and paste comment?
> +BINARY_INT_MMX(PMULLW, pmullw)
tcg_gen_gvec_mul
> +static void gen_VCVTpd_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + SSEFunc_0_epp fn = NULL;
> + switch (sse_prefix(s)) {
> + case 0x66:
> + fn = s->vex_l ? gen_helper_cvttpd2dq_ymm : gen_helper_cvttpd2dq_xmm;
> + break;
> + case 0xf3:
> + fn = s->vex_l ? gen_helper_cvtdq2pd_ymm : gen_helper_cvtdq2pd_xmm;
> + break;
> + case 0xf2:
> + fn = s->vex_l ? gen_helper_cvtpd2dq_ymm : gen_helper_cvtpd2dq_xmm;
> + break;
> + }
> + fn(cpu_env, s->ptr0, s->ptr2);
> +}
Earlier decode?
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (24 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-12 15:33 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
` (10 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
The more complicated operations here are insertions and extractions.
Otherwise, there are just more entries than usual because the PS/PD/SS/SD
variations are encoded in the opcode rater than in the prefixes.
These three-byte opcodes also include AVX new instructions, whose
implementation in the helpers was originally done by Paul Brook
<paul@nowt.org>.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 95 +++++++++
| 10 +
target/i386/tcg/decode-new.c.inc | 75 +++++++
target/i386/tcg/emit.c.inc | 323 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 3 +-
5 files changed, 505 insertions(+), 1 deletion(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 4f72164c0f..7eba1cf0f1 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -2381,6 +2381,101 @@ void glue(helper_aeskeygenassist, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
#endif
#endif
+#if SHIFT >= 1
+void glue(helper_vpermilpd_imm, SUFFIX)(Reg *d, Reg *s, uint32_t order)
+{
+ uint64_t r0, r1;
+ int i;
+
+ for (i = 0; i < 1 << SHIFT; i += 2) {
+ r0 = s->Q(i + ((order >> 0) & 1));
+ r1 = s->Q(i + ((order >> 1) & 1));
+ d->Q(i) = r0;
+ d->Q(i+1) = r1;
+
+ order >>= 2;
+ }
+}
+
+void glue(helper_vpermilps_imm, SUFFIX)(Reg *d, Reg *s, uint32_t order)
+{
+ uint32_t r0, r1, r2, r3;
+ int i;
+
+ for (i = 0; i < 2 << SHIFT; i += 4) {
+ r0 = s->L(i + ((order >> 0) & 3));
+ r1 = s->L(i + ((order >> 2) & 3));
+ r2 = s->L(i + ((order >> 4) & 3));
+ r3 = s->L(i + ((order >> 6) & 3));
+ d->L(i) = r0;
+ d->L(i+1) = r1;
+ d->L(i+2) = r2;
+ d->L(i+3) = r3;
+ }
+}
+
+#if SHIFT >= 2
+void helper_vpermdq_ymm(Reg *d, Reg *v, Reg *s, uint32_t order)
+{
+ uint64_t r0, r1, r2, r3;
+
+ switch (order & 3) {
+ case 0:
+ r0 = v->Q(0);
+ r1 = v->Q(1);
+ break;
+ case 1:
+ r0 = v->Q(2);
+ r1 = v->Q(3);
+ break;
+ case 2:
+ r0 = s->Q(0);
+ r1 = s->Q(1);
+ break;
+ case 3:
+ r0 = s->Q(2);
+ r1 = s->Q(3);
+ break;
+ }
+ switch ((order >> 4) & 3) {
+ case 0:
+ r2 = v->Q(0);
+ r3 = v->Q(1);
+ break;
+ case 1:
+ r2 = v->Q(2);
+ r3 = v->Q(3);
+ break;
+ case 2:
+ r2 = s->Q(0);
+ r3 = s->Q(1);
+ break;
+ case 3:
+ r2 = s->Q(2);
+ r3 = s->Q(3);
+ break;
+ }
+ d->Q(0) = r0;
+ d->Q(1) = r1;
+ d->Q(2) = r2;
+ d->Q(3) = r3;
+}
+
+void helper_vpermq_ymm(Reg *d, Reg *s, uint32_t order)
+{
+ uint64_t r0, r1, r2, r3;
+ r0 = s->Q(order & 3);
+ r1 = s->Q((order >> 2) & 3);
+ r2 = s->Q((order >> 4) & 3);
+ r3 = s->Q((order >> 6) & 3);
+ d->Q(0) = r0;
+ d->Q(1) = r1;
+ d->Q(2) = r2;
+ d->Q(3) = r3;
+}
+#endif
+#endif
+
#undef SSE_HELPER_S
#undef LANE_WIDTH
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 4041816945..6b70d90734 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -411,6 +411,16 @@ DEF_HELPER_4(glue(aeskeygenassist, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_5(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, Reg, i32)
#endif
+/* AVX helpers */
+#if SHIFT >= 1
+DEF_HELPER_3(glue(vpermilpd_imm, SUFFIX), void, Reg, Reg, i32)
+DEF_HELPER_3(glue(vpermilps_imm, SUFFIX), void, Reg, Reg, i32)
+#if SHIFT == 2
+DEF_HELPER_4(vpermdq_ymm, void, Reg, Reg, Reg, i32)
+DEF_HELPER_3(vpermq_ymm, void, Reg, Reg, i32)
+#endif
+#endif
+
#undef SHIFT
#undef Reg
#undef SUFFIX
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index e9a9981a7f..e7b406ff80 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -328,7 +328,78 @@ static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
}
+static void decode_VINSERTPS(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry
+ vinsertps_reg = X86_OP_ENTRY4(VINSERTPS_r, V,dq, H,dq, U,dq, vex5 cpuid(SSE41) p_66),
+ vinsertps_mem = X86_OP_ENTRY4(VINSERTPS_m, V,dq, H,dq, M,d, vex5 cpuid(SSE41) p_66);
+
+ int modrm = get_modrm(s, env);
+ *entry = (modrm >> 6) == 3 ? vinsertps_reg : vinsertps_mem;
+}
+
static const X86OpEntry opcodes_0F3A[256] = {
+ /*
+ * These are VEX-only, but incorrectly listed in the manual as exception type 4.
+ * Also the "qq" instructions are sometimes omitted by Table 2-17, but are VEX256
+ * only.
+ */
+ [0x00] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 cpuid(AVX2) p_66),
+ [0x01] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 cpuid(AVX2) p_66), /* VPERMPD */
+ [0x02] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66), /* VPBLENDD */
+ [0x04] = X86_OP_ENTRY3(VPERMILPS_i, V,x, W,x, I,b, vex6 cpuid(AVX) p_66),
+ [0x05] = X86_OP_ENTRY3(VPERMILPD_i, V,x, W,x, I,b, vex6 cpuid(AVX) p_66),
+ [0x06] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 cpuid(AVX) p_66),
+
+ [0x14] = X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
+ [0x15] = X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
+ [0x16] = X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE41) p_66),
+ [0x17] = X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE41) p_66),
+
+ [0x20] = X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE41) zext2 p_66),
+ [0x21] = X86_OP_GROUP0(VINSERTPS),
+ [0x22] = X86_OP_ENTRY4(PINSR, V,dq, H,dq, E,y, vex5 cpuid(SSE41) p_66),
+
+ [0x40] = X86_OP_ENTRY4(VDDPS, V,x, H,x, W,x, vex2 cpuid(SSE41) p_66),
+ [0x41] = X86_OP_ENTRY4(VDDPD, V,dq, H,dq, W,dq, vex2 cpuid(SSE41) p_66),
+ [0x42] = X86_OP_ENTRY4(VMPSADBW, V,x, H,x, W,x, vex2 cpuid(SSE41) avx2_256 p_66),
+ [0x44] = X86_OP_ENTRY4(PCLMULQDQ, V,dq, H,dq, W,dq, vex4 cpuid(PCLMULQDQ) p_66),
+ [0x46] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
+
+ [0x60] = X86_OP_ENTRY4(PCMPESTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
+ [0x61] = X86_OP_ENTRY4(PCMPESTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
+ [0x62] = X86_OP_ENTRY4(PCMPISTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
+ [0x63] = X86_OP_ENTRY4(PCMPISTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
+
+ [0x08] = X86_OP_ENTRY3(VROUNDPS, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
+ [0x09] = X86_OP_ENTRY3(VROUNDPD, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
+ /*
+ * Not listed as four operand in the manual. Also writes and reads 128-bits
+ * from the first two operands due to the V operand picking higher entries of
+ * the H operand; the "Vss,Hss,Wss" description from the manual is incorrect.
+ * For other unary operations such as VSQRTSx this is hidden by the "REPScalar"
+ * value of vex_special, because the table lists the operand types of VSQRTPx.
+ */
+ [0x0a] = X86_OP_ENTRY4(VROUNDSS, V,x, H,x, W,ss, vex3 cpuid(SSE41) p_66),
+ [0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66),
+ [0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
+ [0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
+ [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
+ [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx p_00_66),
+
+ [0x18] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 cpuid(AVX) p_66),
+ [0x19] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 cpuid(AVX) p_66),
+
+ [0x38] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
+ [0x39] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 cpuid(AVX2) p_66),
+
+ /* Listed incorrectly as type 4 */
+ [0x4a] = X86_OP_ENTRY4(VBLENDVPS, V,x, H,x, W,x, vex6 cpuid(AVX) p_66),
+ [0x4b] = X86_OP_ENTRY4(VBLENDVPD, V,x, H,x, W,x, vex6 cpuid(AVX) p_66),
+ [0x4c] = X86_OP_ENTRY4(VPBLENDVB, V,x, H,x, W,x, vex6 cpuid(AVX) p_66 avx2_256),
+
+ [0xdf] = X86_OP_ENTRY3(VAESKEYGEN, V,dq, W,dq, I,b, vex4 cpuid(AES) p_66),
+
[0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2),
};
@@ -839,6 +910,10 @@ static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_
}
}
if (e->op3 != X86_TYPE_None) {
+ /*
+ * A couple instructions actually use the extra immediate byte for an Lx
+ * register operand; those are handled in the gen_* functions as one off.
+ */
assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
s->rip_offset += 1;
}
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index c90f933093..dbf2c05e16 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -405,6 +405,56 @@ HORIZONTAL_FP_SSE(VHADD, hadd)
HORIZONTAL_FP_SSE(VHSUB, hsub)
HORIZONTAL_FP_SSE(VADDSUB, addsub)
+static inline void gen_ternary_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ int op3, SSEFunc_0_epppp xmm, SSEFunc_0_epppp ymm)
+{
+ SSEFunc_0_epppp fn = s->vex_l ? ymm : xmm;
+ TCGv_ptr ptr3 = tcg_temp_new_ptr();
+
+ /* The format of the fourth input is Lx */
+ tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3));
+ fn(cpu_env, s->ptr0, s->ptr1, s->ptr2, ptr3);
+ tcg_temp_free_ptr(ptr3);
+}
+#define TERNARY_SSE(uvname, lname) \
+static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_ternary_sse(s, env, decode, (uint8_t)decode->immediate >> 4, \
+ gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \
+}
+TERNARY_SSE(VBLENDVPS, blendvps)
+TERNARY_SSE(VBLENDVPD, blendvpd)
+TERNARY_SSE(VPBLENDVB, pblendvb)
+
+static inline void gen_binary_imm_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_epppi xmm, SSEFunc_0_epppi ymm)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ if (!s->vex_l) {
+ xmm(cpu_env, s->ptr0, s->ptr1, s->ptr2, imm);
+ } else {
+ ymm(cpu_env, s->ptr0, s->ptr1, s->ptr2, imm);
+ }
+ tcg_temp_free_i32(imm);
+}
+
+#define BINARY_IMM_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_binary_imm_sse(s, env, decode, \
+ gen_helper_##lname##_xmm, \
+ gen_helper_##lname##_ymm); \
+}
+
+BINARY_IMM_SSE(VBLENDPD, blendpd)
+BINARY_IMM_SSE(VBLENDPS, blendps)
+BINARY_IMM_SSE(VPBLENDW, pblendw)
+BINARY_IMM_SSE(VDDPS, dpps)
+#define gen_helper_dppd_ymm NULL
+BINARY_IMM_SSE(VDDPD, dppd)
+BINARY_IMM_SSE(VMPSADBW, mpsadbw)
+BINARY_IMM_SSE(PCLMULQDQ, pclmulqdq)
+
/*
* 00 = p* Pq, Qq (if mmx not NULL; no VEX)
* 66 = vp* Vx, Hx, Wx
@@ -517,6 +567,33 @@ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
UNARY_IMM_SSE(PSHUFD, pshufd)
UNARY_IMM_SSE(PSHUFHW, pshufhw)
UNARY_IMM_SSE(PSHUFLW, pshuflw)
+#define gen_helper_vpermq_xmm NULL
+UNARY_IMM_SSE(VPERMQ, vpermq)
+UNARY_IMM_SSE(VPERMILPS_i, vpermilps_imm)
+UNARY_IMM_SSE(VPERMILPD_i, vpermilpd_imm)
+
+static inline void gen_unary_imm_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_eppi xmm, SSEFunc_0_eppi ymm)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ if (!s->vex_l) {
+ xmm(cpu_env, s->ptr0, s->ptr1, imm);
+ } else {
+ ymm(cpu_env, s->ptr0, s->ptr1, imm);
+ }
+ tcg_temp_free_i32(imm);
+}
+
+#define UNARY_IMM_FP_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_unary_imm_fp_sse(s, env, decode, \
+ gen_helper_##lname##_xmm, \
+ gen_helper_##lname##_ymm); \
+}
+
+UNARY_IMM_FP_SSE(VROUNDPS, roundps)
+UNARY_IMM_FP_SSE(VROUNDPD, roundpd)
static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
{
@@ -874,6 +951,19 @@ static void gen_PADDQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
decode->op[2].offset, vec_len, vec_len);
}
+static void gen_PALIGNR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ if (!(s->prefix & PREFIX_DATA)) {
+ gen_helper_palignr_mmx(cpu_env, s->ptr0, s->ptr1, s->ptr2, imm);
+ } else if (!s->vex_l) {
+ gen_helper_palignr_xmm(cpu_env, s->ptr0, s->ptr1, s->ptr2, imm);
+ } else {
+ gen_helper_palignr_ymm(cpu_env, s->ptr0, s->ptr1, s->ptr2, imm);
+ }
+ tcg_temp_free_i32(imm);
+}
+
static void gen_PAND(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
@@ -919,6 +1009,46 @@ static void gen_PCMPEQD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
decode->op[2].offset, vec_len, vec_len);
}
+static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ gen_helper_pcmpestri_xmm(cpu_env, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+ set_cc_op(s, CC_OP_EFLAGS);
+}
+
+static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ gen_helper_pcmpestrm_xmm(cpu_env, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+ set_cc_op(s, CC_OP_EFLAGS);
+ if ((s->prefix & PREFIX_VEX) && !s->vex_l) {
+ tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)),
+ 16, 16, 0);
+ }
+}
+
+static void gen_PCMPISTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ gen_helper_pcmpistri_xmm(cpu_env, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+ set_cc_op(s, CC_OP_EFLAGS);
+}
+
+static void gen_PCMPISTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ gen_helper_pcmpistrm_xmm(cpu_env, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+ set_cc_op(s, CC_OP_EFLAGS);
+ if ((s->prefix & PREFIX_VEX) && !s->vex_l) {
+ tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)),
+ 16, 16, 0);
+ }
+}
+
static void gen_PCMPGTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
tcg_gen_ld8u_tl(s->T0, s->ptr1, offsetof(ZMMReg, ZMM_B(val)));
+ break;
+ case MO_16:
+ tcg_gen_ld16u_tl(s->T0, s->ptr1, offsetof(ZMMReg, ZMM_W(val)));
+ break;
+ case MO_32:
+ tcg_gen_ld_i32(s->tmp2_i32, s->ptr1, offsetof(ZMMReg, ZMM_L(val)));
+ tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
+ break;
+#ifdef TARGET_X86_64
+ case MO_64:
+ tcg_gen_ld_tl(s->T0, s->ptr1, offsetof(ZMMReg, ZMM_Q(val)));
+ break;
+#endif
+ default:
+ abort();
+ }
+}
+
+static void gen_PEXTRB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_pextr(s, env, decode, MO_8);
+}
+
+static void gen_PEXTRW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_pextr(s, env, decode, MO_16);
+}
+
+static void gen_PEXTR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[0].ot;
+ gen_pextr(s, env, decode, ot);
+}
+
+static inline void gen_pinsr(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode, MemOp ot)
+{
+ int vec_len = sse_vec_len(s, decode);
+ int mask = (vec_len >> ot) - 1;
+ int val = decode->immediate & mask;
+
+ if (decode->op[1].offset != decode->op[0].offset) {
+ assert(vec_len == 16);
+ gen_store_sse(s, env, decode, decode->op[1].offset);
+ }
+
+ switch(ot) {
+ case MO_8:
+ tcg_gen_st8_tl(s->T1, s->ptr0, offsetof(ZMMReg, ZMM_B(val)));
+ break;
+ case MO_16:
+ tcg_gen_st16_tl(s->T1, s->ptr0, offsetof(ZMMReg, ZMM_W(val)));
+ break;
+ case MO_32:
+ tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1);
+ tcg_gen_st_i32(s->tmp2_i32, s->ptr0, offsetof(ZMMReg, ZMM_L(val)));
+ break;
+#ifdef TARGET_X86_64
+ case MO_64:
+ tcg_gen_st_i64(s->T1, s->ptr0, offsetof(ZMMReg, ZMM_Q(val)));
+ break;
+#endif
+ default:
+ abort();
+ }
+}
+
+static void gen_PINSRB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_pinsr(s, env, decode, MO_8);
+}
+
+static void gen_PINSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_pinsr(s, env, decode, decode->op[2].ot);
+}
+
static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
if (s->prefix & PREFIX_DATA) {
@@ -1259,6 +1474,14 @@ static void gen_SSE4a_R(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
}
}
+static inline void gen_VAESKEYGEN(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ assert(!s->vex_l);
+ gen_helper_aeskeygenassist_xmm(cpu_env, s->ptr0, s->ptr1, imm);
+ tcg_temp_free_i32(imm);
+}
+
#define gen_VAND gen_PAND
#define gen_VANDN gen_PANDN
@@ -1304,5 +1527,105 @@ static void gen_VCVTps_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
fn(cpu_env, s->ptr0, s->ptr2);
}
+static void gen_VEXTRACTx128(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int mask = decode->immediate & 1;
+ int src_ofs = decode->op[1].offset + offsetof(YMMReg, YMM_X(mask));
+ if (decode->op[0].has_ea) {
+ gen_sto_env_A0(s, src_ofs);
+ } else {
+ tcg_gen_gvec_mov(MO_64, decode->op[0].offset + offsetof(YMMReg, YMM_X(0)), src_ofs, 16, 16);
+ }
+}
+
+static void gen_VEXTRACTPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_pextr(s, env, decode, MO_32);
+}
+
+static void gen_vinsertps(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 zero = tcg_const_i32(0); /* float32_zero */
+ int val = decode->immediate;
+ int dest_word = (val >> 4) & 3;
+ int new_mask = (val & 15) | (1 << dest_word);
+ int vec_len = 16;
+
+ assert(!s->vex_l);
+
+ if (new_mask == 15) {
+ /* All zeroes plus possibly from the inserted element */
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ } else if (decode->op[1].offset != decode->op[0].offset) {
+ gen_store_sse(s, env, decode, decode->op[1].offset);
+ }
+
+ if (new_mask != (val & 15)) {
+ tcg_gen_st_i32(s->tmp2_i32, s->ptr0, offsetof(ZMMReg, ZMM_L(dest_word)));
+ }
+
+ if (new_mask != 15) {
+ if ((val >> 0) & 1)
+ tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(0)));
+ if ((val >> 1) & 1)
+ tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(1)));
+ if ((val >> 2) & 1)
+ tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(2)));
+ if ((val >> 3) & 1)
+ tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(3)));
+ }
+
+ tcg_temp_free_i32(zero);
+}
+
+static void gen_VINSERTPS_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int val = decode->immediate;
+ tcg_gen_ld_i32(s->tmp2_i32, s->ptr2, offsetof(ZMMReg, ZMM_L((val >> 6) & 3)));
+ gen_vinsertps(s, env, decode);
+}
+
+static void gen_VINSERTPS_m(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL);
+ gen_vinsertps(s, env, decode);
+}
+
+static void gen_VINSERTx128(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int mask = decode->immediate & 1;
+ tcg_gen_gvec_mov(MO_64,
+ decode->op[0].offset + offsetof(YMMReg, YMM_X(mask)),
+ decode->op[2].offset + offsetof(YMMReg, YMM_X(0)), 16, 16);
+ tcg_gen_gvec_mov(MO_64,
+ decode->op[0].offset + offsetof(YMMReg, YMM_X(!mask)),
+ decode->op[1].offset + offsetof(YMMReg, YMM_X(!mask)), 16, 16);
+}
+
#define gen_VOR gen_POR
+
+static inline void gen_VPERM2x128(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ assert(s->vex_l);
+ gen_helper_vpermdq_ymm(s->ptr0, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+}
+
+static inline void gen_VROUNDSD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ assert(!s->vex_l);
+ gen_helper_roundsd_xmm(cpu_env, s->ptr0, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+}
+
+static inline void gen_VROUNDSS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ assert(!s->vex_l);
+ gen_helper_roundss_xmm(cpu_env, s->ptr0, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+}
+
#define gen_VXOR gen_PXOR
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index d15e988891..556087b1e9 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4667,7 +4667,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
use_new &= b <= limit;
#endif
if (use_new &&
- ((b >= 0x150 && b <= 0x17f) ||
+ (b == 0x13a ||
+ (b >= 0x150 && b <= 0x17f) ||
(b >= 0x1d0 && b <= 0x1ff))) {
return disas_insn_new(s, cpu, b);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, add AVX
2022-09-11 23:04 ` [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, " Paolo Bonzini
@ 2022-09-12 15:33 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-12 15:33 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> @@ -839,6 +910,10 @@ static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_
> }
> }
> if (e->op3 != X86_TYPE_None) {
> + /*
> + * A couple instructions actually use the extra immediate byte for an Lx
> + * register operand; those are handled in the gen_* functions as one off.
> + */
> assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
> s->rip_offset += 1;
> }
Comment should be squashed back with the code.
> +static inline void gen_binary_imm_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> + SSEFunc_0_epppi xmm, SSEFunc_0_epppi ymm)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
tcg_constant_i32.
> +static inline void gen_unary_imm_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> + SSEFunc_0_eppi xmm, SSEFunc_0_eppi ymm)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
Likewise.
> +static void gen_PALIGNR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
Likewise, but could simply be implemented with inline with extract2.
> +static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
tcg_constant_i32.
> +static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
Likewise.
> static void gen_PCMPGTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> {
> int vec_len = sse_vec_len(s, decode);
> tcg_gen_ld8u_tl(s->T0, s->ptr1, offsetof(ZMMReg, ZMM_B(val)));
> + break;
> + case MO_16:
> + tcg_gen_ld16u_tl(s->T0, s->ptr1, offsetof(ZMMReg, ZMM_W(val)));
> + break;
Mailer breakage?
> + if (new_mask != 15) {
> + if ((val >> 0) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(0)));
> + if ((val >> 1) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(1)));
> + if ((val >> 2) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(2)));
> + if ((val >> 3) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(3)));
> + }
Missing braces.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (25 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 8:16 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
` (9 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson
From: Richard Henderson <richard.henderson@linaro.org>
As pmovmskb is used by strlen et al, this is the third
highest overhead sse operation at %0.8.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[Reorganize to generate code for any vector size. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/emit.c.inc | 65 +++++++++++++++++++++++++++++++++++---
1 file changed, 60 insertions(+), 5 deletions(-)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index dbf2c05e16..52c0a7fbe0 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1179,14 +1179,69 @@ static void gen_PINSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_pinsr(s, env, decode, decode->op[2].ot);
}
+static void gen_pmovmskb_i64(TCGv_i64 d, TCGv_i64 s)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(d, s, 0x8080808080808080ull);
+
+ /*
+ * After each shift+or pair:
+ * 0: a.......b.......c.......d.......e.......f.......g.......h.......
+ * 7: ab......bc......cd......de......ef......fg......gh......h.......
+ * 14: abcd....bcde....cdef....defg....efgh....fgh.....gh......h.......
+ * 28: abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h.......
+ * The result is left in the high bits of the word.
+ */
+ tcg_gen_shli_i64(t, d, 7);
+ tcg_gen_or_i64(d, d, t);
+ tcg_gen_shli_i64(t, d, 14);
+ tcg_gen_or_i64(d, d, t);
+ tcg_gen_shli_i64(t, d, 28);
+ tcg_gen_or_i64(d, d, t);
+}
+
+static void gen_pmovmskb_vec(unsigned vece, TCGv_vec d, TCGv_vec s)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_constant_vec_matching(d, MO_8, 0x80);
+
+ /* See above */
+ tcg_gen_and_vec(vece, d, s, m);
+ tcg_gen_shli_vec(vece, t, d, 7);
+ tcg_gen_or_vec(vece, d, d, t);
+ tcg_gen_shli_vec(vece, t, d, 14);
+ tcg_gen_or_vec(vece, d, d, t);
+ if (vece == MO_64) {
+ tcg_gen_shli_vec(vece, t, d, 28);
+ tcg_gen_or_vec(vece, d, d, t);
+ }
+}
+
static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- if (s->prefix & PREFIX_DATA) {
- gen_helper_pmovmskb_xmm(s->tmp2_i32, cpu_env, s->ptr2);
- } else {
- gen_helper_pmovmskb_mmx(s->tmp2_i32, cpu_env, s->ptr2);
+ static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 };
+ static const GVecGen2 g = {
+ .fni8 = gen_pmovmskb_i64,
+ .fniv = gen_pmovmskb_vec,
+ .opt_opc = vecop_list,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64
+ };
+ MemOp ot = decode->op[0].ot;
+ int vec_len = sse_vec_len(s, decode);
+ TCGv t = tcg_temp_new();
+
+ tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset,
+ vec_len, vec_len, &g);
+ tcg_gen_ld8u_tl(s->T0, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
+ while (vec_len > 8) {
+ vec_len -= 8;
+ tcg_gen_shli_tl(s->T0, s->T0, 8);
+ tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
+ tcg_gen_or_tl(s->T0, s->T0, t);
}
- tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
+ tcg_temp_free(t);
}
static void gen_POR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb
2022-09-11 23:04 ` [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
@ 2022-09-13 8:16 ` Richard Henderson
2022-09-14 22:59 ` Paolo Bonzini
0 siblings, 1 reply; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 8:16 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> + while (vec_len > 8) {
> + vec_len -= 8;
> + tcg_gen_shli_tl(s->T0, s->T0, 8);
> + tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
> + tcg_gen_or_tl(s->T0, s->T0, t);
> }
The shl + or is deposit, for those hosts that have it,
and will be re-expanded to shl + or for those that don't:
tcg_gen_ld8u_tl(t, ...);
tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
r~
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb
2022-09-13 8:16 ` Richard Henderson
@ 2022-09-14 22:59 ` Paolo Bonzini
2022-09-15 6:48 ` Richard Henderson
0 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-14 22:59 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, Sep 13, 2022 at 10:17 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/12/22 00:04, Paolo Bonzini wrote:
> > + while (vec_len > 8) {
> > + vec_len -= 8;
> > + tcg_gen_shli_tl(s->T0, s->T0, 8);
> > + tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
> > + tcg_gen_or_tl(s->T0, s->T0, t);
> > }
>
> The shl + or is deposit, for those hosts that have it,
> and will be re-expanded to shl + or for those that don't:
>
> tcg_gen_ld8u_tl(t, ...);
> tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
What you get from that is an shl(t, 56) followed by extract2 (i.e.
SHRD). Yeah there are targets with a native deposit (x86 itself could
add PDEP/PEXT support I guess) but I find it hard to believe that it
outperforms a simple shl + or.
If we want to get clever, I should instead load ZMM_B(vec_len - 1)
directly into the *high* byte of t, using ZMM_L or ZMM_Q, and then
issue the extract2 myself.
Paolo
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb
2022-09-14 22:59 ` Paolo Bonzini
@ 2022-09-15 6:48 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-15 6:48 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
On 9/14/22 23:59, Paolo Bonzini wrote:
> On Tue, Sep 13, 2022 at 10:17 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 9/12/22 00:04, Paolo Bonzini wrote:
>>> + while (vec_len > 8) {
>>> + vec_len -= 8;
>>> + tcg_gen_shli_tl(s->T0, s->T0, 8);
>>> + tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
>>> + tcg_gen_or_tl(s->T0, s->T0, t);
>>> }
>>
>> The shl + or is deposit, for those hosts that have it,
>> and will be re-expanded to shl + or for those that don't:
>>
>> tcg_gen_ld8u_tl(t, ...);
>> tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
>
> What you get from that is an shl(t, 56) followed by extract2 (i.e.
> SHRD). Yeah there are targets with a native deposit (x86 itself could
> add PDEP/PEXT support I guess) but I find it hard to believe that it
> outperforms a simple shl + or.
Perhaps the shl+shrd (or shrd+rol if the deposit is slightly different) is over-cleverness
on my part in the expansion, and pdep requires a constant mask.
But for other hosts, deposit is the same cost as shift.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (26 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 9:31 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, " Paolo Bonzini
` (8 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
There are several special cases here:
1) extending moves have different widths for the helpers vs. for the
memory loads, and the width for memory loads depends on VEX.L too.
This is represented by X86_SPECIAL_AVXExtMov.
2) some instructions, such as variable-width shifts, select the vector element
size via REX.W.
3) VSIB instructions (VGATHERxPy, VPGATHERxy) are also part of this group,
and they have (among other things) two output operands.
3) the macros for 4-operand blends (which are under 0x0f 0x3a) have to be
extended to support 2-operand blends. The 2-operand variant actually
came a few years earlier, but it is clearer to implement them in the
opposite order.
4) some helpers accept a Reg* but have a M argument (i.e. a value of 11 in
the ModRM field causes an undefined opcode exception). For these, it is
useful to add a custom X86_TYPE_WM value is added that does call
gen_load() unlike X86_TYPE_M.
These three-byte opcodes also include AVX new instructions, for which
the helpers were originally implemented by Paul Brook <paul@nowt.org>.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 185 +++++++++++++++++++-
| 19 ++
target/i386/tcg/decode-new.c.inc | 115 +++++++++++-
target/i386/tcg/decode-new.h | 7 +
target/i386/tcg/emit.c.inc | 288 ++++++++++++++++++++++++++++++-
target/i386/tcg/translate.c | 2 +-
6 files changed, 608 insertions(+), 8 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 7eba1cf0f1..fbbe82c6e7 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -2382,6 +2382,36 @@ void glue(helper_aeskeygenassist, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
#endif
#if SHIFT >= 1
+void glue(helper_vpermilpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
+{
+ uint64_t r0, r1;
+ int i;
+
+ for (i = 0; i < 1 << SHIFT; i += 2) {
+ r0 = v->Q(i + ((s->Q(i) >> 1) & 1));
+ r1 = v->Q(i + ((s->Q(i+1) >> 1) & 1));
+ d->Q(i) = r0;
+ d->Q(i+1) = r1;
+ }
+}
+
+void glue(helper_vpermilps, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
+{
+ uint32_t r0, r1, r2, r3;
+ int i;
+
+ for (i = 0; i < 2 << SHIFT; i += 4) {
+ r0 = v->L(i + (s->L(i) & 3));
+ r1 = v->L(i + (s->L(i+1) & 3));
+ r2 = v->L(i + (s->L(i+2) & 3));
+ r3 = v->L(i + (s->L(i+3) & 3));
+ d->L(i) = r0;
+ d->L(i+1) = r1;
+ d->L(i+2) = r2;
+ d->L(i+3) = r3;
+ }
+}
+
void glue(helper_vpermilpd_imm, SUFFIX)(Reg *d, Reg *s, uint32_t order)
{
uint64_t r0, r1;
@@ -2414,6 +2444,147 @@ void glue(helper_vpermilps_imm, SUFFIX)(Reg *d, Reg *s, uint32_t order)
}
}
+#if SHIFT == 1
+#define FPSRLVD(x, c) (c < 32 ? ((x) >> c) : 0)
+#define FPSRLVQ(x, c) (c < 64 ? ((x) >> c) : 0)
+#define FPSRAVD(x, c) ((int32_t)(x) >> (c < 64 ? c : 31))
+#define FPSRAVQ(x, c) ((int64_t)(x) >> (c < 64 ? c : 63))
+#define FPSLLVD(x, c) (c < 32 ? ((x) << c) : 0)
+#define FPSLLVQ(x, c) (c < 64 ? ((x) << c) : 0)
+#endif
+
+SSE_HELPER_L(helper_vpsrlvd, FPSRLVD)
+SSE_HELPER_L(helper_vpsravd, FPSRAVD)
+SSE_HELPER_L(helper_vpsllvd, FPSLLVD)
+
+SSE_HELPER_Q(helper_vpsrlvq, FPSRLVQ)
+SSE_HELPER_Q(helper_vpsravq, FPSRAVQ)
+SSE_HELPER_Q(helper_vpsllvq, FPSLLVQ)
+
+void glue(helper_vtestps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+{
+ uint64_t zf = 0, cf = 0;
+ int i;
+
+ for (i = 0; i < 2 << SHIFT; i++) {
+ zf |= (s->L(i) & d->L(i));
+ cf |= (s->L(i) & ~d->L(i));
+ }
+ CC_SRC = ((zf >> 31) ? 0 : CC_Z) | ((cf >> 31) ? 0 : CC_C);
+}
+
+void glue(helper_vtestpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
+{
+ uint64_t zf = 0, cf = 0;
+ int i;
+
+ for (i = 0; i < 1 << SHIFT; i++) {
+ zf |= (s->Q(i) & d->Q(i));
+ cf |= (s->Q(i) & ~d->Q(i));
+ }
+ CC_SRC = ((zf >> 63) ? 0 : CC_Z) | ((cf >> 63) ? 0 : CC_C);
+}
+
+void glue(helper_vpmaskmovd_st, SUFFIX)(CPUX86State *env,
+ Reg *v, Reg *s, target_ulong a0)
+{
+ int i;
+
+ for (i = 0; i < (2 << SHIFT); i++) {
+ if (v->L(i) >> 31) {
+ cpu_stl_data_ra(env, a0 + i * 4, s->L(i), GETPC());
+ }
+ }
+}
+
+void glue(helper_vpmaskmovq_st, SUFFIX)(CPUX86State *env,
+ Reg *v, Reg *s, target_ulong a0)
+{
+ int i;
+
+ for (i = 0; i < (1 << SHIFT); i++) {
+ if (v->Q(i) >> 63) {
+ cpu_stq_data_ra(env, a0 + i * 8, s->Q(i), GETPC());
+ }
+ }
+}
+
+void glue(helper_vpmaskmovd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
+{
+ int i;
+
+ for (i = 0; i < (2 << SHIFT); i++) {
+ d->L(i) = (v->L(i) >> 31) ? s->L(i) : 0;
+ }
+}
+
+void glue(helper_vpmaskmovq, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
+{
+ int i;
+
+ for (i = 0; i < (1 << SHIFT); i++) {
+ d->Q(i) = (v->Q(i) >> 63) ? s->Q(i) : 0;
+ }
+}
+
+void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env,
+ Reg *d, Reg *v, Reg *s, target_ulong a0, unsigned scale)
+{
+ int i;
+ for (i = 0; i < (2 << SHIFT); i++) {
+ if (v->L(i) >> 31) {
+ target_ulong addr = a0
+ + ((target_ulong)(int32_t)s->L(i) << scale);
+ d->L(i) = cpu_ldl_data_ra(env, addr, GETPC());
+ }
+ v->L(i) = 0;
+ }
+}
+void glue(helper_vpgatherdq, SUFFIX)(CPUX86State *env,
+ Reg *d, Reg *v, Reg *s, target_ulong a0, unsigned scale)
+{
+ int i;
+ for (i = 0; i < (1 << SHIFT); i++) {
+ if (v->Q(i) >> 63) {
+ target_ulong addr = a0
+ + ((target_ulong)(int32_t)s->L(i) << scale);
+ d->Q(i) = cpu_ldq_data_ra(env, addr, GETPC());
+ }
+ v->Q(i) = 0;
+ }
+}
+void glue(helper_vpgatherqd, SUFFIX)(CPUX86State *env,
+ Reg *d, Reg *v, Reg *s, target_ulong a0, unsigned scale)
+{
+ int i;
+ for (i = 0; i < (1 << SHIFT); i++) {
+ if (v->L(i) >> 31) {
+ target_ulong addr = a0
+ + ((target_ulong)(int64_t)s->Q(i) << scale);
+ d->L(i) = cpu_ldl_data_ra(env, addr, GETPC());
+ }
+ v->L(i) = 0;
+ }
+ for (i /= 2; i < 1 << SHIFT; i++) {
+ d->Q(i) = 0;
+ v->Q(i) = 0;
+ }
+}
+void glue(helper_vpgatherqq, SUFFIX)(CPUX86State *env,
+ Reg *d, Reg *v, Reg *s, target_ulong a0, unsigned scale)
+{
+ int i;
+ for (i = 0; i < (1 << SHIFT); i++) {
+ if (v->Q(i) >> 63) {
+ target_ulong addr = a0
+ + ((target_ulong)(int64_t)s->Q(i) << scale);
+ d->Q(i) = cpu_ldq_data_ra(env, addr, GETPC());
+ }
+ v->Q(i) = 0;
+ }
+}
+#endif
+
#if SHIFT >= 2
void helper_vpermdq_ymm(Reg *d, Reg *v, Reg *s, uint32_t order)
{
@@ -2473,7 +2644,19 @@ void helper_vpermq_ymm(Reg *d, Reg *s, uint32_t order)
d->Q(2) = r2;
d->Q(3) = r3;
}
-#endif
+
+void helper_vpermd_ymm(Reg *d, Reg *v, Reg *s)
+{
+ uint32_t r[8];
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ r[i] = s->L(v->L(i) & 7);
+ }
+ for (i = 0; i < 8; i++) {
+ d->L(i) = r[i];
+ }
+}
#endif
#undef SSE_HELPER_S
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 6b70d90734..e188cbd87d 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -413,9 +413,28 @@ DEF_HELPER_5(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, Reg, i32)
/* AVX helpers */
#if SHIFT >= 1
+DEF_HELPER_4(glue(vpermilpd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(vpermilps, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_3(glue(vpermilpd_imm, SUFFIX), void, Reg, Reg, i32)
DEF_HELPER_3(glue(vpermilps_imm, SUFFIX), void, Reg, Reg, i32)
+DEF_HELPER_4(glue(vpsrlvd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(vpsravd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(vpsllvd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(vpsrlvq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(vpsravq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(vpsllvq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_3(glue(vtestps, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_3(glue(vtestpd, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_4(glue(vpmaskmovd_st, SUFFIX), void, env, Reg, Reg, tl)
+DEF_HELPER_4(glue(vpmaskmovq_st, SUFFIX), void, env, Reg, Reg, tl)
+DEF_HELPER_4(glue(vpmaskmovd, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_4(glue(vpmaskmovq, SUFFIX), void, env, Reg, Reg, Reg)
+DEF_HELPER_6(glue(vpgatherdd, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
+DEF_HELPER_6(glue(vpgatherdq, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
+DEF_HELPER_6(glue(vpgatherqd, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
+DEF_HELPER_6(glue(vpgatherqq, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
#if SHIFT == 2
+DEF_HELPER_3(vpermd_ymm, void, Reg, Reg, Reg)
DEF_HELPER_4(vpermdq_ymm, void, Reg, Reg, Reg, i32)
DEF_HELPER_3(vpermq_ymm, void, Reg, Reg, i32)
#endif
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index e7b406ff80..7feb0eca4e 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -90,6 +90,7 @@
#define mmx .special = X86_SPECIAL_MMX,
#define zext0 .special = X86_SPECIAL_ZExtOp0,
#define zext2 .special = X86_SPECIAL_ZExtOp2,
+#define avx_movx .special = X86_SPECIAL_AVXExtMov,
#define vex1 .vex_class = 1,
#define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar,
@@ -255,6 +256,105 @@ static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
static const X86OpEntry opcodes_0F38_00toEF[240] = {
+ [0x00] = X86_OP_ENTRY3(PSHUFB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x01] = X86_OP_ENTRY3(PHADDW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x02] = X86_OP_ENTRY3(PHADDD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x03] = X86_OP_ENTRY3(PHADDSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x04] = X86_OP_ENTRY3(PMADDUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x05] = X86_OP_ENTRY3(PHSUBW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x06] = X86_OP_ENTRY3(PHSUBD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x07] = X86_OP_ENTRY3(PHSUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+
+ [0x10] = X86_OP_ENTRY3(PBLENDVB, V,x, None,None, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x14] = X86_OP_ENTRY3(BLENDVPS, V,x, None,None, W,x, vex4 cpuid(SSE41) p_66),
+ [0x15] = X86_OP_ENTRY3(BLENDVPD, V,x, None,None, W,x, vex4 cpuid(SSE41) p_66),
+ /* Listed incorrectly as type 4 */
+ [0x16] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
+ [0x17] = X86_OP_ENTRY3(VPTEST, None,None, V,x, W,x, vex4 cpuid(SSE41) p_66),
+
+ /*
+ * Source operand listed as Mq/Ux and similar in the manual; incorrectly listed
+ * as 128-bit only in 2-17.
+ */
+ [0x20] = X86_OP_ENTRY3(VPMOVSXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x21] = X86_OP_ENTRY3(VPMOVSXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x22] = X86_OP_ENTRY3(VPMOVSXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x23] = X86_OP_ENTRY3(VPMOVSXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x24] = X86_OP_ENTRY3(VPMOVSXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x25] = X86_OP_ENTRY3(VPMOVSXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+
+ /* Same as PMOVSX. */
+ [0x30] = X86_OP_ENTRY3(VPMOVZXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x31] = X86_OP_ENTRY3(VPMOVZXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x32] = X86_OP_ENTRY3(VPMOVZXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x33] = X86_OP_ENTRY3(VPMOVZXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x34] = X86_OP_ENTRY3(VPMOVZXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x35] = X86_OP_ENTRY3(VPMOVZXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
+ [0x36] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
+ [0x37] = X86_OP_ENTRY3(PCMPGTQ, V,x, H,x, W,x, vex4 cpuid(SSE42) avx2_256 p_66),
+
+ [0x40] = X86_OP_ENTRY3(VPMULLD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x41] = X86_OP_ENTRY3(VPHMINPOSUW, V,dq, None,None, W,dq, vex4 cpuid(SSE41) p_66),
+ /* Listed incorrectly as type 4 */
+ [0x45] = X86_OP_ENTRY3(VPSRLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
+ [0x46] = X86_OP_ENTRY3(VPSRAV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
+ [0x47] = X86_OP_ENTRY3(VPSLLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
+
+ [0x90] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vpgatherdd/q */
+ [0x91] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vpgatherqd/q */
+ [0x92] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vgatherdps/d */
+ [0x93] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vgatherqps/d */
+
+ [0x08] = X86_OP_ENTRY3(PSIGNB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x09] = X86_OP_ENTRY3(PSIGNW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x0a] = X86_OP_ENTRY3(PSIGND, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x0b] = X86_OP_ENTRY3(PMULHRSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x0c] = X86_OP_ENTRY3(VPERMILPS, V,x, H,x, W,x, vex4 cpuid(AVX) p_00_66),
+ [0x0d] = X86_OP_ENTRY3(VPERMILPD, V,x, H,x, W,x, vex4 cpuid(AVX) p_66),
+ [0x0e] = X86_OP_ENTRY3(VTESTPS, None,None, V,x, W,x, vex4 cpuid(AVX) p_66),
+ [0x0f] = X86_OP_ENTRY3(VTESTPD, None,None, V,x, W,x, vex4 cpuid(AVX) p_66),
+
+ [0x18] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 cpuid(AVX) p_66), /* vbroadcastss */
+ [0x19] = X86_OP_ENTRY3(VPBROADCASTQ, V,qq, None,None, W,q, vex6 cpuid(AVX) p_66), /* vbroadcastsd */
+ [0x1a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 cpuid(AVX) p_66),
+ [0x1c] = X86_OP_ENTRY3(PABSB, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x1d] = X86_OP_ENTRY3(PABSW, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+ [0x1e] = X86_OP_ENTRY3(PABSD, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
+
+ [0x28] = X86_OP_ENTRY3(VPMULDQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x29] = X86_OP_ENTRY3(PCMPEQQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x2a] = X86_OP_ENTRY3(MOVNTDQA, V,x, None,None, M,x, vex1 cpuid(SSE41) avx2_256 p_66),
+ [0x2b] = X86_OP_ENTRY3(VPACKUSDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x2c] = X86_OP_ENTRY3(VMASKMOVPS, V,x, H,x, WM,x, vex6 cpuid(AVX) p_66),
+ [0x2d] = X86_OP_ENTRY3(VMASKMOVPD, V,x, H,x, WM,x, vex6 cpuid(AVX) p_66),
+ /* Incorrectly listed as Mx,Hx,Vx in the manual */
+ [0x2e] = X86_OP_ENTRY3(VMASKMOVPS_st, M,x, V,x, H,x, vex6 cpuid(AVX) p_66),
+ [0x2f] = X86_OP_ENTRY3(,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x3c] = X86_OP_ENTRY3(VPMAXSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x3d] = X86_OP_ENTRY3(VPMAXSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x3e] = X86_OP_ENTRY3(VPMAXUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x3f] = X86_OP_ENTRY3(VPMAXUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+
+ [0x58] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 cpuid(AVX2) p_66),
+ [0x59] = X86_OP_ENTRY3(VPBROADCASTQ, V,x, None,None, W,q, vex6 cpuid(AVX2) p_66),
+ [0x5a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 cpuid(AVX2) p_66),
+
+ [0x78] = X86_OP_ENTRY3(VPBROADCASTB, V,x, None,None, W,b, vex6 cpuid(AVX2) p_66),
+ [0x79] = X86_OP_ENTRY3(VPBROADCASTW, V,x, None,None, W,w, vex6 cpuid(AVX2) p_66),
+
+ [0x8c] = X86_OP_ENTRY3(VPMASKMOV, V,x, H,x, WM,x, vex6 cpuid(AVX2) p_66),
+ [0x8e] = X86_OP_ENTRY3(VPMASKMOV_st, M,x, V,x, H,x, vex6 cpuid(AVX2) p_66),
+
+ [0xdb] = X86_OP_ENTRY3(VAESIMC, V,dq, None,None, W,dq, vex4 cpuid(AES) p_66),
+ [0xdc] = X86_OP_ENTRY3(VAESENC, V,dq, H,dq, W,dq, vex4 cpuid(AES) p_66),
+ [0xdd] = X86_OP_ENTRY3(VAESENCLAST, V,dq, H,dq, W,dq, vex4 cpuid(AES) p_66),
+ [0xde] = X86_OP_ENTRY3(VAESDEC, V,dq, H,dq, W,dq, vex4 cpuid(AES) p_66),
+ [0xdf] = X86_OP_ENTRY3(VAESDECLAST, V,dq, H,dq, W,dq, vex4 cpuid(AES) p_66),
};
/* five rows for no prefix, 66, F3, F2, 66+F2 */
@@ -384,8 +484,8 @@ static const X86OpEntry opcodes_0F3A[256] = {
[0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66),
[0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
[0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
- [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
- [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx p_00_66),
+ [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
+ [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
[0x18] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 cpuid(AVX) p_66),
[0x19] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 cpuid(AVX) p_66),
@@ -754,6 +854,9 @@ static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
}
goto get_modrm;
+ case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */
+ op->unit = X86_OP_SSE;
+ /* fall through */
case X86_TYPE_M: /* modrm byte selects a memory operand */
modrm = get_modrm(s, env);
if ((modrm >> 6) == 3) {
@@ -1341,6 +1444,14 @@ static target_ulong disas_insn_new(DisasContext *s, CPUState *cpu, int b)
}
break;
+ case X86_SPECIAL_AVXExtMov:
+ if (!decode.op[2].has_ea) {
+ decode.op[2].ot = s->vex_l ? MO_128 : MO_256;
+ } else if (s->vex_l) {
+ decode.op[2].ot++;
+ }
+ break;
+
case X86_SPECIAL_MMX:
if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
gen_helper_enter_mmx(cpu_env);
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index 3db7b82506..e86876b9a9 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -47,6 +47,7 @@ typedef enum X86OpType {
X86_TYPE_Y, /* string destination */
/* Custom */
+ X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */
X86_TYPE_2op, /* 2-operand RMW instruction */
X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
@@ -141,6 +142,12 @@ typedef enum X86InsnSpecial {
X86_SPECIAL_ZExtOp0,
X86_SPECIAL_ZExtOp2,
+ /*
+ * Register operand 2 is extended to full width, while a memory operand
+ * is doubled in size if VEX.L=1.
+ */
+ X86_SPECIAL_AVXExtMov,
+
/*
* MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands
* become P/P/Q/N, and size "x" becomes "q".
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 52c0a7fbe0..7084875af6 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -19,6 +19,9 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+typedef void (*SSEFunc_0_epppti)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
+ TCGv_ptr reg_c, TCGv a0, TCGv_i32 scale);
+
static void gen_NM_exception(DisasContext *s)
{
gen_exception(s, EXCP07_PREX, s->pc_start - s->cs_base);
@@ -416,15 +419,21 @@ static inline void gen_ternary_sse(DisasContext *s, CPUX86State *env, X86Decoded
fn(cpu_env, s->ptr0, s->ptr1, s->ptr2, ptr3);
tcg_temp_free_ptr(ptr3);
}
-#define TERNARY_SSE(uvname, lname) \
+#define TERNARY_SSE(uname, uvname, lname) \
static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
{ \
gen_ternary_sse(s, env, decode, (uint8_t)decode->immediate >> 4, \
gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \
+} \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ tcg_gen_mov_ptr(s->ptr1, s->ptr0); \
+ gen_ternary_sse(s, env, decode, 0, \
+ gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \
}
-TERNARY_SSE(VBLENDVPS, blendvps)
-TERNARY_SSE(VBLENDVPD, blendvpd)
-TERNARY_SSE(VPBLENDVB, pblendvb)
+TERNARY_SSE(BLENDVPS, VBLENDVPS, blendvps)
+TERNARY_SSE(BLENDVPD, VBLENDVPD, blendvpd)
+TERNARY_SSE(PBLENDVB, VPBLENDVB, pblendvb)
static inline void gen_binary_imm_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
SSEFunc_0_epppi xmm, SSEFunc_0_epppi ymm)
@@ -531,6 +540,19 @@ BINARY_INT_MMX(PSRLQ_r, psrlq)
BINARY_INT_MMX(PSRAW_r, psraw)
BINARY_INT_MMX(PSRAD_r, psrad)
+BINARY_INT_MMX(PHADDW, phaddw)
+BINARY_INT_MMX(PHADDSW, phaddsw)
+BINARY_INT_MMX(PHADDD, phaddd)
+BINARY_INT_MMX(PHSUBW, phsubw)
+BINARY_INT_MMX(PHSUBSW, phsubsw)
+BINARY_INT_MMX(PHSUBD, phsubd)
+BINARY_INT_MMX(PMADDUBSW, pmaddubsw)
+BINARY_INT_MMX(PSHUFB, pshufb)
+BINARY_INT_MMX(PSIGNB, psignb)
+BINARY_INT_MMX(PSIGNW, psignw)
+BINARY_INT_MMX(PSIGND, psignd)
+BINARY_INT_MMX(PMULHRSW, pmulhrsw)
+
/* Instructions with no MMX equivalent. */
#define BINARY_INT_SSE(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
@@ -541,8 +563,75 @@ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
gen_helper_##lname##_ymm); \
}
+/* Instructions with no MMX equivalent. */
BINARY_INT_SSE(PUNPCKLQDQ, punpcklqdq)
BINARY_INT_SSE(PUNPCKHQDQ, punpckhqdq)
+BINARY_INT_SSE(VPACKUSDW, packusdw)
+BINARY_INT_SSE(VPMINSB, pminsb)
+BINARY_INT_SSE(VPMINUW, pminuw)
+BINARY_INT_SSE(VPMINUD, pminud)
+BINARY_INT_SSE(VPMINSD, pminsd)
+BINARY_INT_SSE(VPMAXSB, pmaxsb)
+BINARY_INT_SSE(VPMAXUW, pmaxuw)
+BINARY_INT_SSE(VPMAXUD, pmaxud)
+BINARY_INT_SSE(VPMAXSD, pmaxsd)
+BINARY_INT_SSE(VPMULLD, pmulld)
+BINARY_INT_SSE(VPMULDQ, pmuldq)
+BINARY_INT_SSE(VPERMILPS, vpermilps)
+BINARY_INT_SSE(VPERMILPD, vpermilpd)
+BINARY_INT_SSE(VMASKMOVPS, vpmaskmovd)
+BINARY_INT_SSE(VMASKMOVPD, vpmaskmovq)
+
+BINARY_INT_SSE(VAESDEC, aesdec)
+BINARY_INT_SSE(VAESDECLAST, aesdeclast)
+BINARY_INT_SSE(VAESENC, aesenc)
+BINARY_INT_SSE(VAESENCLAST, aesenclast)
+
+static inline void gen_unary_int_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_epp xmm, SSEFunc_0_epp ymm)
+{
+ if (!s->vex_l) {
+ xmm(cpu_env, s->ptr0, s->ptr2);
+ } else {
+ ymm(cpu_env, s->ptr0, s->ptr2);
+ }
+}
+
+#define UNARY_INT_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_unary_int_sse(s, env, decode, \
+ gen_helper_##lname##_xmm, \
+ gen_helper_##lname##_ymm); \
+}
+
+UNARY_INT_SSE(VPMOVSXBW, pmovsxbw)
+UNARY_INT_SSE(VPMOVSXBD, pmovsxbd)
+UNARY_INT_SSE(VPMOVSXBQ, pmovsxbq)
+UNARY_INT_SSE(VPMOVSXWD, pmovsxwd)
+UNARY_INT_SSE(VPMOVSXWQ, pmovsxwq)
+UNARY_INT_SSE(VPMOVSXDQ, pmovsxdq)
+
+UNARY_INT_SSE(VPMOVZXBW, pmovzxbw)
+UNARY_INT_SSE(VPMOVZXBD, pmovzxbd)
+UNARY_INT_SSE(VPMOVZXBQ, pmovzxbq)
+UNARY_INT_SSE(VPMOVZXWD, pmovzxwd)
+UNARY_INT_SSE(VPMOVZXWQ, pmovzxwq)
+UNARY_INT_SSE(VPMOVZXDQ, pmovzxdq)
+
+#define UNARY_CMP_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ if (!s->vex_l) { \
+ gen_helper_##lname##_xmm(cpu_env, s->ptr1, s->ptr2); \
+ } else { \
+ gen_helper_##lname##_ymm(cpu_env, s->ptr1, s->ptr2); \
+ } \
+ set_cc_op(s, CC_OP_EFLAGS); \
+}
+UNARY_CMP_SSE(VPTEST, ptest)
+UNARY_CMP_SSE(VTESTPS, vtestps)
+UNARY_CMP_SSE(VTESTPD, vtestpd)
static inline void gen_unary_imm_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
SSEFunc_0_ppi xmm, SSEFunc_0_ppi ymm)
@@ -595,6 +684,66 @@ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
UNARY_IMM_FP_SSE(VROUNDPS, roundps)
UNARY_IMM_FP_SSE(VROUNDPD, roundpd)
+static inline void gen_rexw_avx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_eppp d_xmm, SSEFunc_0_eppp q_xmm,
+ SSEFunc_0_eppp d_ymm, SSEFunc_0_eppp q_ymm)
+{
+ SSEFunc_0_eppp d = s->vex_l ? d_ymm : d_xmm;
+ SSEFunc_0_eppp q = s->vex_l ? q_ymm : q_xmm;
+ SSEFunc_0_eppp fn = s->rex_w ? q : d;
+ fn(cpu_env, s->ptr0, s->ptr1, s->ptr2);
+}
+
+/* REX.W affects whether to operate on 32- or 64-bit elements. */
+#define REXW_AVX(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_rexw_avx(s, env, decode, \
+ gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \
+ gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \
+}
+REXW_AVX(VPSLLV, vpsllv)
+REXW_AVX(VPSRLV, vpsrlv)
+REXW_AVX(VPSRAV, vpsrav)
+REXW_AVX(VPMASKMOV, vpmaskmov)
+
+/* Same as above, but with extra arguments to the helper. */
+static inline void gen_vsib_avx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_epppti d_xmm, SSEFunc_0_epppti q_xmm,
+ SSEFunc_0_epppti d_ymm, SSEFunc_0_epppti q_ymm)
+{
+ SSEFunc_0_epppti d = s->vex_l ? d_ymm : d_xmm;
+ SSEFunc_0_epppti q = s->vex_l ? q_ymm : q_xmm;
+ SSEFunc_0_epppti fn = s->rex_w ? q : d;
+ TCGv_i32 scale = tcg_const_i32(decode->mem.scale);
+ TCGv_ptr index = tcg_temp_new_ptr();
+
+ /* Pass third input as (index, base, scale) */
+ tcg_gen_addi_ptr(index, cpu_env, ZMM_OFFSET(decode->mem.index));
+ fn(cpu_env, s->ptr0, s->ptr1, index, s->A0, scale);
+
+ /*
+ * There are two output operands, so zero OP1's high 128 bits
+ * in the VEX.128 case.
+ */
+ if (!s->vex_l) {
+ tcg_gen_gvec_dup_imm(MO_64,
+ decode->op[1].offset + offsetof(ZMMReg, ZMM_X(1)),
+ 16, 16, 0);
+ }
+ tcg_temp_free_ptr(index);
+ tcg_temp_free_i32(scale);
+}
+#define VSIB_AVX(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ gen_vsib_avx(s, env, decode, \
+ gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \
+ gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \
+}
+VSIB_AVX(VPGATHERD, vpgatherd)
+VSIB_AVX(VPGATHERQ, vpgatherq)
+
static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
{
TCGv carry_in = NULL;
@@ -868,6 +1017,11 @@ static void gen_MOVMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode
tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
}
+static void gen_MOVNTDQA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_load_sse(s, s->T0, decode->op[0].ot, decode->op[0].offset);
+}
+
static void gen_MOVQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset);
@@ -915,6 +1069,27 @@ static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
}
+static void gen_PABSB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_abs(MO_8, decode->op[0].offset, decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PABSW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_abs(MO_16, decode->op[0].offset, decode->op[2].offset, vec_len, vec_len);
+}
+
+static void gen_PABSD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_abs(MO_32, decode->op[0].offset, decode->op[2].offset, vec_len, vec_len);
+}
+
static void gen_PADDB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
@@ -1009,6 +1184,15 @@ static void gen_PCMPEQD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
decode->op[2].offset, vec_len, vec_len);
}
+static void gen_PCMPEQQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_EQ, MO_64,
+ decode->op[0].offset, decode->op[1].offset,
+ decode->op[2].offset, vec_len, vec_len);
+}
+
static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_const_i32(decode->immediate);
@@ -1076,6 +1260,15 @@ static void gen_PCMPGTD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
decode->op[2].offset, vec_len, vec_len);
}
+static void gen_PCMPGTQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_cmp(TCG_COND_GT, MO_64,
+o
tcg_temp_free_ptr(imm_vec);
}
+static void gen_VPBROADCASTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_ld8u_i32(s->tmp2_i32, s->ptr2, 0);
+ tcg_gen_gvec_dup_i32(MO_8, decode->op[0].offset, vec_len, vec_len, s->tmp2_i32);
+}
+
+static void gen_VPBROADCASTW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_ld16u_i32(s->tmp2_i32, s->ptr2, 0);
+ tcg_gen_gvec_dup_i32(MO_16, decode->op[0].offset, vec_len, vec_len, s->tmp2_i32);
+}
+
+static void gen_VPBROADCASTD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_ld_i32(s->tmp2_i32, s->ptr2, 0);
+ tcg_gen_gvec_dup_i32(MO_32, decode->op[0].offset, vec_len, vec_len, s->tmp2_i32);
+}
+
+static void gen_VPBROADCASTQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_ld_i64(s->tmp1_i64, s->ptr2, 0);
+ tcg_gen_gvec_dup_i64(MO_64, decode->op[0].offset, vec_len, vec_len, s->tmp1_i64);
+}
+
static void gen_PXOR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = sse_vec_len(s, decode);
@@ -1529,6 +1754,12 @@ static void gen_SSE4a_R(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
}
}
+static inline void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ assert(!s->vex_l);
+ gen_helper_aesimc_xmm(cpu_env, s->ptr0, s->ptr2);
+}
+
static inline void gen_VAESKEYGEN(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_const_i32(decode->immediate);
@@ -1540,6 +1771,14 @@ static inline void gen_VAESKEYGEN(DisasContext *s, CPUX86State *env, X86DecodedI
#define gen_VAND gen_PAND
#define gen_VANDN gen_PANDN
+static inline void gen_VBROADCASTx128(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_gvec_mov(MO_64, decode->op[0].offset,
+ decode->op[2].offset, 16, 16);
+ tcg_gen_gvec_mov(MO_64, decode->op[0].offset + offsetof(YMMReg, YMM_X(1)),
+ decode->op[2].offset, 16, 16);
+}
+
static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_unary_fp_sse(s, env, decode,
@@ -1657,8 +1896,43 @@ static void gen_VINSERTx128(DisasContext *s, CPUX86State *env, X86DecodedInsn *d
decode->op[1].offset + offsetof(YMMReg, YMM_X(!mask)), 16, 16);
}
+static inline void gen_maskmov(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm)
+{
+ if (!s->vex_l) {
+ xmm(cpu_env, s->ptr2, s->ptr1, s->A0);
+ } else {
+ ymm(cpu_env, s->ptr2, s->ptr1, s->A0);
+ }
+}
+
+static void gen_VMASKMOVPD_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_maskmov(s, env, decode, gen_helper_vpmaskmovq_st_xmm, gen_helper_vpmaskmovq_st_ymm);
+}
+
+static void gen_VMASKMOVPS_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_maskmov(s, env, decode, gen_helper_vpmaskmovd_st_xmm, gen_helper_vpmaskmovd_st_ymm);
+}
+
+static void gen_VPMASKMOV_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (s->rex_w) {
+ gen_VMASKMOVPD_st(s, env, decode);
+ } else {
+ gen_VMASKMOVPS_st(s, env, decode);
+ }
+}
+
#define gen_VOR gen_POR
+static void gen_VPERMD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ assert(s->vex_l);
+ gen_helper_vpermd_ymm(s->ptr0, s->ptr1, s->ptr2);
+}
+
static inline void gen_VPERM2x128(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_const_i32(decode->immediate);
@@ -1667,6 +1941,12 @@ static inline void gen_VPERM2x128(DisasContext *s, CPUX86State *env, X86DecodedI
tcg_temp_free_i32(imm);
}
+static void gen_VPHMINPOSUW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ assert(!s->vex_l);
+ gen_helper_phminposuw_xmm(cpu_env, s->ptr0, s->ptr2);
+}
+
static inline void gen_VROUNDSD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_const_i32(decode->immediate);
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 556087b1e9..e42cb275a1 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4667,7 +4667,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
use_new &= b <= limit;
#endif
if (use_new &&
- (b == 0x13a ||
+ (b == 0x138 || b == 0x13a ||
(b >= 0x150 && b <= 0x17f) ||
(b >= 0x1d0 && b <= 0x1ff))) {
return disas_insn_new(s, cpu, b);
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX
2022-09-11 23:04 ` [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
@ 2022-09-13 9:31 ` Richard Henderson
2022-09-14 17:04 ` Paolo Bonzini
0 siblings, 1 reply; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 9:31 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> +void glue(helper_vtestps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
> +{
> + uint64_t zf = 0, cf = 0;
uint32_t, to match the size of the operation.
> + int i;
> +
> + for (i = 0; i < 2 << SHIFT; i++) {
> + zf |= (s->L(i) & d->L(i));
> + cf |= (s->L(i) & ~d->L(i));
> + }
> +void glue(helper_vpmaskmovd_st, SUFFIX)(CPUX86State *env,
> + Reg *v, Reg *s, target_ulong a0)
> +{
> + int i;
> +
> + for (i = 0; i < (2 << SHIFT); i++) {
> + if (v->L(i) >> 31) {
> + cpu_stl_data_ra(env, a0 + i * 4, s->L(i), GETPC());
> + }
> + }
> +}
> +
> +void glue(helper_vpmaskmovq_st, SUFFIX)(CPUX86State *env,
> + Reg *v, Reg *s, target_ulong a0)
> +{
> + int i;
> +
> + for (i = 0; i < (1 << SHIFT); i++) {
> + if (v->Q(i) >> 63) {
> + cpu_stq_data_ra(env, a0 + i * 8, s->Q(i), GETPC());
> + }
> + }
> +}
Any idea if hw will write incomplete data if the pieces cross page boundaries, and the
second page is invalid? We're not good at that for any other vector sized write, though,
so not critical.
> +void glue(helper_vpmaskmovd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
> +{
> + int i;
> +
> + for (i = 0; i < (2 << SHIFT); i++) {
> + d->L(i) = (v->L(i) >> 31) ? s->L(i) : 0;
> + }
> +}
This is tcg_gen_cmpsel_vec(TCG_COND_LT, d, v, zero, s, zero).
> +void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env,
> + Reg *d, Reg *v, Reg *s, target_ulong a0, unsigned scale)
> +{
> + int i;
> + for (i = 0; i < (2 << SHIFT); i++) {
> + if (v->L(i) >> 31) {
> + target_ulong addr = a0
> + + ((target_ulong)(int32_t)s->L(i) << scale);
> + d->L(i) = cpu_ldl_data_ra(env, addr, GETPC());
> + }
> + v->L(i) = 0;
> + }
> +}
Better to not modify registers until all potential #GP are raised.
Also, some missing whitespace between functions.
> + [0x2f] = X86_OP_ENTRY3(,x, vex4 cpuid(SSE41) avx2_256 p_66),
Whee! Mailer really chomped down on this series.
> @@ -384,8 +484,8 @@ static const X86OpEntry opcodes_0F3A[256] = {
> [0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66),
> [0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
> [0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
> - [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
> - [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx p_00_66),
> + [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
> + [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
Squash back.
> + case X86_SPECIAL_AVXExtMov:
> + if (!decode.op[2].has_ea) {
> + decode.op[2].ot = s->vex_l ? MO_128 : MO_256;
> + } else if (s->vex_l) {
> + decode.op[2].ot++;
> + }
Clever.
> +BINARY_INT_SSE(VPMINSB, pminsb)
> +BINARY_INT_SSE(VPMINUW, pminuw)
> +BINARY_INT_SSE(VPMINUD, pminud)
> +BINARY_INT_SSE(VPMINSD, pminsd)
> +BINARY_INT_SSE(VPMAXSB, pmaxsb)
> +BINARY_INT_SSE(VPMAXUW, pmaxuw)
> +BINARY_INT_SSE(VPMAXUD, pmaxud)
> +BINARY_INT_SSE(VPMAXSD, pmaxsd)
tcg_gen_gvec_{u,s}{min,max}.
> +/* Same as above, but with extra arguments to the helper. */
> +static inline void gen_vsib_avx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> + SSEFunc_0_epppti d_xmm, SSEFunc_0_epppti q_xmm,
> + SSEFunc_0_epppti d_ymm, SSEFunc_0_epppti q_ymm)
> +{
> + SSEFunc_0_epppti d = s->vex_l ? d_ymm : d_xmm;
> + SSEFunc_0_epppti q = s->vex_l ? q_ymm : q_xmm;
> + SSEFunc_0_epppti fn = s->rex_w ? q : d;
> + TCGv_i32 scale = tcg_const_i32(decode->mem.scale);
tcg_constant_i32.
> +static void gen_VPBROADCASTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> +
> + tcg_gen_ld8u_i32(s->tmp2_i32, s->ptr2, 0);
> + tcg_gen_gvec_dup_i32(MO_8, decode->op[0].offset, vec_len, vec_len, s->tmp2_i32);
> +}
This is better done with tcg_gen_gvec_dup_mem, where you pass the cpu_env offset of the
source data. This lets the host use mem->reg broadcast, which turns out to be more
available than reg->reg broadcast.
> +static void gen_VPBROADCASTW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +static void gen_VPBROADCASTD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +static void gen_VPBROADCASTQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
Likewise.
> +static inline void gen_VBROADCASTx128(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + tcg_gen_gvec_mov(MO_64, decode->op[0].offset,
> + decode->op[2].offset, 16, 16);
> + tcg_gen_gvec_mov(MO_64, decode->op[0].offset + offsetof(YMMReg, YMM_X(1)),
> + decode->op[2].offset, 16, 16);
> +}
tcg_gen_dup_mem(MO_128, ...);
r~
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX
2022-09-13 9:31 ` Richard Henderson
@ 2022-09-14 17:04 ` Paolo Bonzini
2022-09-15 6:50 ` Richard Henderson
0 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-14 17:04 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, Sep 13, 2022 at 11:31 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
> > +void glue(helper_vpmaskmovq_st, SUFFIX)(CPUX86State *env,
> > + Reg *v, Reg *s, target_ulong a0)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < (1 << SHIFT); i++) {
> > + if (v->Q(i) >> 63) {
> > + cpu_stq_data_ra(env, a0 + i * 8, s->Q(i), GETPC());
> > + }
> > + }
> > +}
>
> Any idea if hw will write incomplete data if the pieces cross page boundaries, and the
> second page is invalid? We're not good at that for any other vector sized write, though,
> so not critical.
No, I will check.
> > +void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env,
> > + Reg *d, Reg *v, Reg *s, target_ulong a0, unsigned scale)
> > +{
> > + int i;
> > + for (i = 0; i < (2 << SHIFT); i++) {
> > + if (v->L(i) >> 31) {
> > + target_ulong addr = a0
> > + + ((target_ulong)(int32_t)s->L(i) << scale);
> > + d->L(i) = cpu_ldl_data_ra(env, addr, GETPC());
> > + }
> > + v->L(i) = 0;
> > + }
> > +}
>
> Better to not modify registers until all potential #GP are raised.
This is actually intentional: elements of v are zeroes whenever an
element is read successfully, so that values are not reread when the
instruction restarts. The manual says "If a fault is triggered by an
element and delivered, all elements closer to the LSB of the
destination zmm will be completed".
Paolo
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX
2022-09-14 17:04 ` Paolo Bonzini
@ 2022-09-15 6:50 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-15 6:50 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
On 9/14/22 18:04, Paolo Bonzini wrote:
>>> +void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env,
>>> + Reg *d, Reg *v, Reg *s, target_ulong a0, unsigned scale)
>>> +{
>>> + int i;
>>> + for (i = 0; i < (2 << SHIFT); i++) {
>>> + if (v->L(i) >> 31) {
>>> + target_ulong addr = a0
>>> + + ((target_ulong)(int32_t)s->L(i) << scale);
>>> + d->L(i) = cpu_ldl_data_ra(env, addr, GETPC());
>>> + }
>>> + v->L(i) = 0;
>>> + }
>>> +}
>>
>> Better to not modify registers until all potential #GP are raised.
>
> This is actually intentional: elements of v are zeroes whenever an
> element is read successfully, so that values are not reread when the
> instruction restarts. The manual says "If a fault is triggered by an
> element and delivered, all elements closer to the LSB of the
> destination zmm will be completed".
Ooo, I had never noticed that.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (27 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 9:44 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
` (7 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
Nothing special going on here, for once.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 5 +++
target/i386/tcg/emit.c.inc | 76 ++++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 1 +
3 files changed, 82 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 7feb0eca4e..c51b59f721 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -579,6 +579,11 @@ static const X86OpEntry opcodes_0F[256] = {
[0x7e] = X86_OP_GROUP0(0F7E),
[0x7f] = X86_OP_GROUP3(0F6F, W,x, None,None, V,x, vex5 mmx p_00_66_f3),
+ [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
+ [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
+ [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
+
[0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
[0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 7084875af6..d1819f3581 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1367,6 +1367,11 @@ static void gen_PINSRB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode
gen_pinsr(s, env, decode, MO_8);
}
+static void gen_PINSRW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_pinsr(s, env, decode, MO_16);
+}
+
static void gen_PINSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_pinsr(s, env, decode, decode->op[2].ot);
@@ -1779,6 +1784,66 @@ static inline void gen_VBROADCASTx128(DisasContext *s, CPUX86State *env, X86Deco
decode->op[2].offset, 16, 16);
}
+/*
+ * 00 = v*ps Vps, Hps, Wpd
+ * 66 = v*pd Vpd, Hpd, Wps
+ * f3 = v*ss Vss, Hss, Wps
+ * f2 = v*sd Vsd, Hsd, Wps
+ */
+#define SSE_CMP(x) { \
+ gen_helper_ ## x ## ps ## _xmm, gen_helper_ ## x ## pd ## _xmm, \
+ gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, \
+ gen_helper_ ## x ## ps ## _ymm, gen_helper_ ## x ## pd ## _ymm}
+static const SSEFunc_0_eppp gen_helper_cmp_funcs[32][6] = {
+ SSE_CMP(cmpeq),
+ SSE_CMP(cmplt),
+ SSE_CMP(cmple),
+ SSE_CMP(cmpunord),
+ SSE_CMP(cmpneq),
+ SSE_CMP(cmpnlt),
+ SSE_CMP(cmpnle),
+ SSE_CMP(cmpord),
+
+ SSE_CMP(cmpequ),
+ SSE_CMP(cmpnge),
+ SSE_CMP(cmpngt),
+ SSE_CMP(cmpfalse),
+ SSE_CMP(cmpnequ),
+ SSE_CMP(cmpge),
+ SSE_CMP(cmpgt),
+ SSE_CMP(cmptrue),
+
+ SSE_CMP(cmpeqs),
+ SSE_CMP(cmpltq),
+ SSE_CMP(cmpleq),
+ SSE_CMP(cmpunords),
+ SSE_CMP(cmpneqq),
+ SSE_CMP(cmpnltq),
+ SSE_CMP(cmpnleq),
+ SSE_CMP(cmpords),
+
+ SSE_CMP(cmpequs),
+ SSE_CMP(cmpngeq),
+ SSE_CMP(cmpngtq),
+ SSE_CMP(cmpfalses),
+ SSE_CMP(cmpnequs),
+ SSE_CMP(cmpgeq),
+ SSE_CMP(cmpgtq),
+ SSE_CMP(cmptrues),
+};
+#undef SSE_CMP
+
+static inline void gen_VCMP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int index = decode->immediate & (s->prefix & PREFIX_VEX ? 31 : 7);
+ int b =
+ s->prefix & PREFIX_REPZ ? 2 /* ss */ :
+ s->prefix & PREFIX_REPNZ ? 3 /* ss */ :
+ !!(s->prefix & PREFIX_DATA) + (s->vex_l << 2);
+
+ gen_helper_cmp_funcs[index][b](cpu_env, s->ptr0, s->ptr1, s->ptr2);
+}
+
static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_unary_fp_sse(s, env, decode,
@@ -1963,4 +2028,15 @@ static inline void gen_VROUNDSS(DisasContext *s, CPUX86State *env, X86DecodedIns
tcg_temp_free_i32(imm);
}
+static inline void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv_i32 imm = tcg_const_i32(decode->immediate);
+ SSEFunc_0_pppi ps, pd, fn;
+ ps = s->vex_l ? gen_helper_shufps_ymm : gen_helper_shufps_xmm;
+ pd = s->vex_l ? gen_helper_shufpd_ymm : gen_helper_shufpd_xmm;
+ fn = s->prefix & PREFIX_DATA ? pd : ps;
+ fn(s->ptr0, s->ptr1, s->ptr2, imm);
+ tcg_temp_free_i32(imm);
+}
+
#define gen_VXOR gen_PXOR
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e42cb275a1..468867afcf 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4669,6 +4669,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
if (use_new &&
(b == 0x138 || b == 0x13a ||
(b >= 0x150 && b <= 0x17f) ||
+ b == 0x1c2 || (b >= 0x1c4 && b <= 0x1c6) ||
(b >= 0x1d0 && b <= 0x1ff))) {
return disas_insn_new(s, cpu, b);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (28 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 10:14 ` Richard Henderson
2022-09-13 10:38 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
` (6 subsequent siblings)
36 siblings, 2 replies; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
These are mostly moves, and yet are a total pain. The main issue
is that:
1) some instructions are selected by mod==11 (register operand)
vs. mod=00/01/10 (memory operand)
2) stores to memory are two-operand operations, while the 3-register
and load-from-memory versions operate on the entire contents of the
destination; this makes it easier to separate the gen_* function for
the store case
3) it's inefficient to load into xmm_T0 only to move the value out
again, so the gen_* function for the load case is separated too
The manual also has various mistakes in the operands here, for example
the store case of MOVHPS operates on a 128-bit source (albeit discarding
the bottom 64 bits) and therefore should be Mq,Vdq rather than Mq,Vq.
Likewise for the destination and source of MOVHLPS.
VUNPCK?PS and VUNPCK?PD are the same as VUNPCK?DQ and VUNPCK?QDQ,
but encoded as prefixes rather than separate operands. The helpers
can be reused however.
For MOVSLDUP, MOVSHDUP and MOVDDUP I chose to reimplement them as
helpers. I named the helper for MOVDDUP "movdldup" in preparation
for possible future introduction of MOVDHDUP and to clarify the
similarity with MOVSLDUP.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 7 ++
| 3 +
target/i386/tcg/decode-new.c.inc | 121 ++++++++++++++++++++++++++++++
target/i386/tcg/emit.c.inc | 123 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 1 +
5 files changed, 255 insertions(+)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index fbbe82c6e7..52cae7ebe7 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -1683,6 +1683,10 @@ void glue(helper_ptest, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
CC_SRC = (zf ? 0 : CC_Z) | (cf ? 0 : CC_C);
}
+#define FMOVSLDUP(i) s->L((i) & ~1)
+#define FMOVSHDUP(i) s->L((i) | 1)
+#define FMOVDLDUP(i) s->Q((i) & ~1)
+
#define SSE_HELPER_F(name, elem, num, F) \
void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
{ \
@@ -1705,6 +1709,9 @@ SSE_HELPER_F(helper_pmovzxbq, Q, 1 << SHIFT, s->B)
SSE_HELPER_F(helper_pmovzxwd, L, 2 << SHIFT, s->W)
SSE_HELPER_F(helper_pmovzxwq, Q, 1 << SHIFT, s->W)
SSE_HELPER_F(helper_pmovzxdq, Q, 1 << SHIFT, s->L)
+SSE_HELPER_F(helper_pmovsldup, L, 2 << SHIFT, FMOVSLDUP)
+SSE_HELPER_F(helper_pmovshdup, L, 2 << SHIFT, FMOVSHDUP)
+SSE_HELPER_F(helper_pmovdldup, Q, 1 << SHIFT, FMOVDLDUP)
#endif
void glue(helper_pmuldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s)
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index e188cbd87d..ed51f10eef 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -355,6 +355,9 @@ DEF_HELPER_3(glue(pmovzxbq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxwd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxwq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxdq, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_3(glue(pmovsldup, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_3(glue(pmovshdup, SUFFIX), void, env, Reg, Reg)
+DEF_HELPER_3(glue(pmovdldup, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(pmuldq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(pcmpeqq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(packusdw, SUFFIX), void, env, Reg, Reg, Reg)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index c51b59f721..268ccb886f 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -509,6 +509,117 @@ static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
*entry = opcodes_0F3A[*b];
}
+/*
+ * There are some mistakes in the operands in the manual, and the load/store/register
+ * cases are easiest to keep separate, so the entries for 10-17 follow simplicity and
+ * efficiency of implementation rather than copying what the manual says.
+ *
+ * In particular:
+ *
+ * 1) "VMOVSS m32, xmm1" and "VMOVSD m64, xmm1" do not support VEX.vvvv != 1111b,
+ * but this is not mentioned in the tables.
+ *
+ * 2) MOVHLPS, MOVHPS, MOVHPD, MOVLPD, MOVLPS read the high quadword of one of their
+ * operands, which must therefore be dq; MOVLPD and MOVLPS also write the high
+ * quadword of the V operand.
+ */
+static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F10_reg[4] = {
+ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
+ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
+ X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex4),
+ X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex4), /* MOVSD */
+ };
+
+ static const X86OpEntry opcodes_0F10_mem[4] = {
+ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
+ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
+ X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex4),
+ X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex4),
+ };
+
+ if ((get_modrm(s, env) >> 6) == 3) {
+ *entry = *decode_by_prefix(s, opcodes_0F10_reg);
+ } else {
+ *entry = *decode_by_prefix(s, opcodes_0F10_mem);
+ }
+}
+
+static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F11_reg[4] = {
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */
+ X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex4),
+ X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex4), /* MOVSD */
+ };
+
+ static const X86OpEntry opcodes_0F11_mem[4] = {
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */
+ X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4),
+ X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */
+ };
+
+ if ((get_modrm(s, env) >> 6) == 3) {
+ *entry = *decode_by_prefix(s, opcodes_0F11_reg);
+ } else {
+ *entry = *decode_by_prefix(s, opcodes_0F11_mem);
+ }
+}
+
+static void decode_0F12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F12_mem[4] = {
+ /*
+ * Use dq for operand for compatibility with gen_MOVSD and
+ * to allow VEX128 only.
+ */
+ X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPS */
+ X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPD */
+ X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
+ X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex4 cpuid(SSE3)), /* qq if VEX.256 */
+ };
+ static const X86OpEntry opcodes_0F12_reg[4] = {
+ X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex4),
+ X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex4), /* MOVLPD */
+ X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
+ X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
+ };
+
+ if ((get_modrm(s, env) >> 6) == 3) {
+ *entry = *decode_by_prefix(s, opcodes_0F12_reg);
+ } else {
+ *entry = *decode_by_prefix(s, opcodes_0F12_mem);
+ if ((s->prefix & PREFIX_REPNZ) && s->vex_l) {
+ entry->s2 = X86_SIZE_qq;
+ }
+ }
+}
+
+static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F16_mem[4] = {
+ X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,q, M,q, vex4), /* MOVHPS */
+ X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,q, M,q, vex4), /* MOVHPD */
+ X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
+ {},
+ };
+ static const X86OpEntry opcodes_0F16_reg[4] = {
+ X86_OP_ENTRY3(VMOVLHPS, V,dq, H,q, U,q, vex4),
+ X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex4), /* MOVHPD */
+ X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
+ {},
+ };
+
+ if ((get_modrm(s, env) >> 6) == 3) {
+ *entry = *decode_by_prefix(s, opcodes_0F16_reg);
+ } else {
+ *entry = *decode_by_prefix(s, opcodes_0F16_mem);
+ }
+}
+
static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
@@ -524,6 +635,16 @@ static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entr
}
static const X86OpEntry opcodes_0F[256] = {
+ [0x10] = X86_OP_GROUP0(0F10),
+ [0x11] = X86_OP_GROUP0(0F11),
+ [0x12] = X86_OP_GROUP0(0F12),
+ [0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex4 p_00_66),
+ [0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66),
+ [0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66),
+ [0x16] = X86_OP_GROUP0(0F16),
+ /* Incorrectly listed as Mq,Vq in the manual */
+ [0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex4 p_00_66),
+
[0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
[0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index d1819f3581..2319368cb5 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -326,6 +326,7 @@ static inline void gen_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn
gen_illegal_opcode(s);
}
}
+
#define FP_SSE(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
{ \
@@ -344,6 +345,20 @@ FP_SSE(VMIN, min)
FP_SSE(VDIV, div)
FP_SSE(VMAX, max)
+#define FP_UNPACK_SSE(uname, lname) \
+static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
+{ \
+ /* PS maps to the DQ integer instruction, PD maps to QDQ. */ \
+ gen_fp_sse(s, env, decode, \
+ gen_helper_##lname##qdq_xmm, \
+ gen_helper_##lname##dq_xmm, \
+ gen_helper_##lname##qdq_ymm, \
+ gen_helper_##lname##dq_ymm, \
+ NULL, NULL); \
+}
+FP_UNPACK_SSE(VUNPCKLPx, punpckl)
+FP_UNPACK_SSE(VUNPCKHPx, punpckh)
+
/*
* 00 = v*ps Vps, Wpd
* f3 = v*ss Vss, Wps
@@ -619,6 +634,10 @@ UNARY_INT_SSE(VPMOVZXWD, pmovzxwd)
UNARY_INT_SSE(VPMOVZXWQ, pmovzxwq)
UNARY_INT_SSE(VPMOVZXDQ, pmovzxdq)
+UNARY_INT_SSE(VMOVSLDUP, pmovsldup)
+UNARY_INT_SSE(VMOVSHDUP, pmovshdup)
+UNARY_INT_SSE(VMOVDDUP, pmovdldup)
+
#define UNARY_CMP_SSE(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
{ \
@@ -1981,6 +2000,110 @@ static void gen_VMASKMOVPS_st(DisasContext *s, CPUX86State *env, X86DecodedInsn
gen_maskmov(s, env, decode, gen_helper_vpmaskmovd_st_xmm, gen_helper_vpmaskmovd_st_ymm);
}
+static void gen_VMOVHPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (decode->op[0].offset != decode->op[1].offset) {
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ }
+ gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
+}
+
+static void gen_VMOVHPx_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_stq_env_A0(s, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
+}
+
+static void gen_VMOVHPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (decode->op[0].offset != decode->op[1].offset) {
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ }
+ if (decode->op[0].offset != decode->op[2].offset) {
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
+ }
+}
+
+static void gen_VMOVHLPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ if (decode->op[0].offset != decode->op[1].offset) {
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
+ }
+}
+
+static void gen_VMOVLHPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
+ if (decode->op[0].offset != decode->op[1].offset) {
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ }
+}
+
+static void gen_VMOVLPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
+ tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+}
+
+static void gen_VMOVLPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
+ tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_64);
+ tcg_gen_st_i64(s->tmp1_i64, s->ptr0, offsetof(ZMMReg, ZMM_Q(0)));
+}
+
+static void gen_VMOVLPx_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_ld_i64(s->tmp1_i64, s->ptr2, offsetof(ZMMReg, ZMM_Q(0)));
+ tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_64);
+}
+
+static void gen_VMOVSD_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGv zero = tcg_const_i64(0);
+
+ tcg_gen_st_i64(zero, s->ptr0, offsetof(ZMMReg, ZMM_Q(1)));
+ tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_64);
+ tcg_gen_st_i64(s->tmp1_i64, s->ptr0, offsetof(ZMMReg, ZMM_Q(0)));
+ tcg_temp_free_i64(zero);
+}
+
+sL(0)));
+}
+
+static void gen_VMOVSS_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+
+ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
+ tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_32);
+ tcg_gen_st_i32(s->tmp2_i32, s->ptr0, offsetof(ZMMReg, ZMM_L(0)));
+}
+
+static void gen_VMOVSS_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_ld_i32(s->tmp2_i32, s->ptr2, offsetof(ZMMReg, ZMM_L(0)));
+ tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_32);
+}
+
static void gen_VPMASKMOV_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
if (s->rex_w) {
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 468867afcf..bb5f74140c 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4668,6 +4668,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#endif
if (use_new &&
(b == 0x138 || b == 0x13a ||
+ (b >= 0x110 && b <= 0x117) ||
(b >= 0x150 && b <= 0x17f) ||
b == 0x1c2 || (b >= 0x1c4 && b <= 0x1c6) ||
(b >= 0x1d0 && b <= 0x1ff))) {
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX
2022-09-11 23:04 ` [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
@ 2022-09-13 10:14 ` Richard Henderson
2022-09-14 22:45 ` Paolo Bonzini
2022-09-13 10:38 ` Richard Henderson
1 sibling, 1 reply; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 10:14 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> +static void gen_VMOVHPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + if (decode->op[0].offset != decode->op[1].offset) {
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
> + }
> + gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
> +}
Don't modify op0 before the load fault.
> +static void gen_VMOVHLPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
> + if (decode->op[0].offset != decode->op[1].offset) {
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1)));
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
> + }
> +}
> +
> +static void gen_VMOVLHPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
> + if (decode->op[0].offset != decode->op[1].offset) {
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
> + }
> +}
> +
> +static void gen_VMOVLPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> +
> + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
> + tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
> + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
> +}
You've just been moving i64 pieces in the other functions, why is this one different using
a gvec move in the middle? I do wonder if a generic helper moving offset->offset, with
the comparison wouldn't be helpful within these functions, even when you know off1 !=
off2, due to Q(0) vs Q(1).
> +static void gen_VMOVLPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> +
> + tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
> + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_64);
> + tcg_gen_st_i64(s->tmp1_i64, s->ptr0, offsetof(ZMMReg, ZMM_Q(0)));
> +}
Don't modify op0 before load fault.
> +static void gen_VMOVSD_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv zero = tcg_const_i64(0);
> +
> + tcg_gen_st_i64(zero, s->ptr0, offsetof(ZMMReg, ZMM_Q(1)));
> + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_64);
> + tcg_gen_st_i64(s->tmp1_i64, s->ptr0, offsetof(ZMMReg, ZMM_Q(0)));
> + tcg_temp_free_i64(zero);
> +}
Likewise.
> +static void gen_VMOVSS_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + int vec_len = sse_vec_len(s, decode);
> +
> + tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
> + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_32);
> + tcg_gen_st_i32(s->tmp2_i32, s->ptr0, offsetof(ZMMReg, ZMM_L(0)));
> +}
Likewise.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX
2022-09-13 10:14 ` Richard Henderson
@ 2022-09-14 22:45 ` Paolo Bonzini
2022-09-15 6:51 ` Richard Henderson
0 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-14 22:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, Sep 13, 2022 at 12:14 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> > +static void gen_VMOVLPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> > +{
> > + int vec_len = sse_vec_len(s, decode);
> > +
> > + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
> > + tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
> > + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
> > +}
>
> You've just been moving i64 pieces in the other functions, why is this one different using
> a gvec move in the middle? I do wonder if a generic helper moving offset->offset, with
> the comparison wouldn't be helpful within these functions, even when you know off1 !=
> off2, due to Q(0) vs Q(1).
Because this one is the only one that has a VEX.256 version (the
operand is type "x"
rather than "dq" as in MOVHLPS, MOVLHPS, MOVHPx).
Paolo
Paolo
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX
2022-09-14 22:45 ` Paolo Bonzini
@ 2022-09-15 6:51 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-15 6:51 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
On 9/14/22 23:45, Paolo Bonzini wrote:
>> You've just been moving i64 pieces in the other functions, why is this one different using
>> a gvec move in the middle? I do wonder if a generic helper moving offset->offset, with
>> the comparison wouldn't be helpful within these functions, even when you know off1 !=
>> off2, due to Q(0) vs Q(1).
>
> Because this one is the only one that has a VEX.256 version (the
> operand is type "x"
> rather than "dq" as in MOVHLPS, MOVLHPS, MOVHPx).
Ok, then a comment would help.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX
2022-09-11 23:04 ` [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
2022-09-13 10:14 ` Richard Henderson
@ 2022-09-13 10:38 ` Richard Henderson
1 sibling, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 10:38 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_64);
I just noticed this here, but please examine any other direct loads: you've forgotten the
endian specification: MO_64 | MO_LE, or MO_LEUQ for short.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, add AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (29 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 10:24 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers Paolo Bonzini
` (5 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
Here the code is a bit uglier due to the truncation and extension
of registers to and from 32-bit. Otherwise there is nothing special
going on.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 54 ++++++++++++++
target/i386/tcg/emit.c.inc | 120 +++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 1 +
3 files changed, 175 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 268ccb886f..383a425ccd 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -620,6 +620,51 @@ static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
}
+static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F2A[4] = {
+ X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q, vex4),
+ X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q, vex4),
+ X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
+ X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
+ };
+ *entry = *decode_by_prefix(s, opcodes_0F2A);
+}
+
+static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F2B[4] = {
+ X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS */
+ X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD */
+ X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4),
+ X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */
+ };
+
+ *entry = *decode_by_prefix(s, opcodes_0F2B);
+}
+
+static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F2C[4] = {
+ X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,x, vex4),
+ X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,x, vex4),
+ X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,x, vex3),
+ X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,x, vex3),
+ };
+ *entry = *decode_by_prefix(s, opcodes_0F2C);
+}
+
+static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static const X86OpEntry opcodes_0F2D[4] = {
+ X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,x, vex4),
+ X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,x, vex4),
+ X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,x, vex3),
+ X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,x, vex3),
+ };
+ *entry = *decode_by_prefix(s, opcodes_0F2D);
+}
+
static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
@@ -672,6 +717,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x77] = X86_OP_ENTRY0(EMMS_VZERO, vex8),
+ [0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
+ [0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
+ [0x2A] = X86_OP_GROUP0(0F2A),
+ [0x2B] = X86_OP_GROUP0(0F2B),
+ [0x2C] = X86_OP_GROUP0(0F2C),
+ [0x2D] = X86_OP_GROUP0(0F2D),
+ [0x2E] = X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex4 p_00_66),
+ [0x2F] = X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex4 p_00_66),
+
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 2319368cb5..d61b43f21c 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -921,6 +921,36 @@ static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_const_i32(8 << ot));
}
+static void gen_CVTPI2Px(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_helper_enter_mmx(cpu_env);
+ if (s->prefix & PREFIX_DATA) {
+ gen_helper_cvtpi2pd(cpu_env, s->ptr0, s->ptr2);
+ } else {
+ gen_helper_cvtpi2ps(cpu_env, s->ptr0, s->ptr2);
+ }
+}
+
+static void gen_CVTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_helper_enter_mmx(cpu_env);
+ if (s->prefix & PREFIX_DATA) {
+ gen_helper_cvtpd2pi(cpu_env, s->ptr0, s->ptr2);
+ } else {
+ gen_helper_cvtps2pi(cpu_env, s->ptr0, s->ptr2);
+ }
+}
+
+static void gen_CVTTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_helper_enter_mmx(cpu_env);
+ if (s->prefix & PREFIX_DATA) {
+ gen_helper_cvttpd2pi(cpu_env, s->ptr0, s->ptr2);
+ } else {
+ gen_helper_cvttps2pi(cpu_env, s->ptr0, s->ptr2);
+ }
+}
+
static void gen_EMMS_VZERO(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
if (!(s->prefix & PREFIX_VEX)) {
@@ -1863,6 +1893,14 @@ static inline void gen_VCMP(DisasContext *s, CPUX86State *env, X86DecodedInsn *d
gen_helper_cmp_funcs[index][b](cpu_env, s->ptr0, s->ptr1, s->ptr2);
}
+static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ SSEFunc_0_epp fn;
+ fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss;
+ fn(cpu_env, s->ptr1, s->ptr2);
+ set_cc_op(s, CC_OP_EFLAGS);
+}
+
static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_unary_fp_sse(s, env, decode,
@@ -1871,6 +1909,80 @@ static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
gen_helper_cvtsd2ss, gen_helper_cvtss2sd);
}
+static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int vec_len = sse_vec_len(s, decode);
+ MemOp ot = decode->op[2].ot;
+ TCGv_i32 in;
+
+ tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
+#ifdef TARGET_X86_64
+ if (ot == MO_64) {
+ if (s->prefix & PREFIX_REPNZ) {
+ gen_helper_cvtsq2sd(cpu_env, s->ptr0, s->T1);
+ } else {
+ gen_helper_cvtsq2ss(cpu_env, s->ptr0, s->T1);
+ }
+ return;
+ }
+ in = s->tmp2_i32;
+ tcg_gen_trunc_tl_i32(in, s->T1);
+#else
+ in = s->T1;
+#endif
+
+ if (s->prefix & PREFIX_REPNZ) {
+ gen_helper_cvtsi2sd(cpu_env, s->ptr0, in);
+ } else {
+ gen_helper_cvtsi2ss(cpu_env, s->ptr0, in);
+ }
+}
+
+static inline void gen_VCVTtSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
+ SSEFunc_i_ep ss2si, SSEFunc_l_ep ss2sq,
+ SSEFunc_i_ep sd2si, SSEFunc_l_ep sd2sq)
+{
+ MemOp ot = decode->op[0].ot;
+ TCGv_i32 out;
+
+#ifdef TARGET_X86_64
+ if (ot == MO_64) {
+ if (s->prefix & PREFIX_REPNZ) {
+ sd2sq(s->T0, cpu_env, s->ptr2);
+ } else {
+ ss2sq(s->T0, cpu_env, s->ptr2);
+ }
+ return;
+ }
+
+ out = s->tmp2_i32;
+#else
+ out = s->T0;
+#endif
+ if (s->prefix & PREFIX_REPNZ) {
+ sd2si(out, cpu_env, s->ptr2);
+ } else {
+ ss2si(out, cpu_env, s->ptr2);
+ }
+#ifdef TARGET_X86_64
+ tcg_gen_extu_i32_tl(s->T0, out);
+#endif
+}
+
+static void gen_VCVTSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_VCVTtSx2SI(s, env, decode,
+ gen_helper_cvtss2si, gen_helper_cvtss2sq,
+ gen_helper_cvtsd2si, gen_helper_cvtsd2sq);
+}
+
+static void gen_VCVTTSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_VCVTtSx2SI(s, env, decode,
+ gen_helper_cvttss2si, gen_helper_cvttss2sq,
+ gen_helper_cvttsd2si, gen_helper_cvttsd2sq);
+}
+
static void gen_VCVTpd_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
SSEFunc_0_epp fn = NULL;
@@ -2162,4 +2274,12 @@ static inline void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn *
tcg_temp_free_i32(imm);
}
+static void gen_VUCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ SSEFunc_0_epp fn;
+ fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss;
+ fn(cpu_env, s->ptr1, s->ptr2);
+ set_cc_op(s, CC_OP_EFLAGS);
+}
+
#define gen_VXOR gen_PXOR
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index bb5f74140c..f312663110 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4669,6 +4669,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
if (use_new &&
(b == 0x138 || b == 0x13a ||
(b >= 0x110 && b <= 0x117) ||
+ (b >= 0x128 && b <= 0x12f) ||
(b >= 0x150 && b <= 0x17f) ||
b == 0x1c2 || (b >= 0x1c4 && b <= 0x1c6) ||
(b >= 0x1d0 && b <= 0x1ff))) {
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, add AVX
2022-09-11 23:04 ` [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
@ 2022-09-13 10:24 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 10:24 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> +static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
> +{
> + static const X86OpEntry opcodes_0F2B[4] = {
> + X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS */
> + X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD */
> + X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4),
> + X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */
These last two look wrong. And if you don't have those, you use ENTRY3 instead of GROUP0
in the main table?
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (30 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 10:27 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
` (4 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/fpu_helper.c | 84 ++++++++++++++++++++++++++++++++++--
1 file changed, 81 insertions(+), 3 deletions(-)
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 230907bc5c..1be620257e 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -2571,6 +2571,25 @@ static void do_xsave_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
}
}
+static void do_xsave_ymmh(CPUX86State *env, target_ulong ptr, uintptr_t ra)
+{
+ int i, nb_xmm_regs;
+ target_ulong addr;
+
+ if (env->hflags & HF_CS64_MASK) {
+ nb_xmm_regs = 16;
+ } else {
+ nb_xmm_regs = 8;
+ }
+
+ addr = ptr + XO(avx_state);
+ for (i = 0; i < nb_xmm_regs; i++) {
+ cpu_stq_data_ra(env, addr, env->xmm_regs[i].ZMM_Q(2), ra);
+ cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].ZMM_Q(3), ra);
+ addr += 16;
+ }
+}
+
static void do_xsave_bndregs(CPUX86State *env, target_ulong ptr, uintptr_t ra)
{
target_ulong addr = ptr + offsetof(XSaveBNDREG, bnd_regs);
@@ -2663,6 +2682,9 @@ static void do_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm,
if (opt & XSTATE_SSE_MASK) {
do_xsave_sse(env, ptr, ra);
}
+ if (opt & XSTATE_YMM_MASK) {
+ do_xsave_ymmh(env, ptr + XO(avx_state), ra);
+ }
if (opt & XSTATE_BNDREGS_MASK) {
do_xsave_bndregs(env, ptr + XO(bndreg_state), ra);
}
@@ -2737,6 +2759,57 @@ static void do_xrstor_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
}
}
+static void do_clear_sse(CPUX86State *env)
+{
+ int i, nb_xmm_regs;
+
+ if (env->hflags & HF_CS64_MASK) {
+ nb_xmm_regs = 16;
+ } else {
+ nb_xmm_regs = 8;
+ }
+
+ for (i = 0; i < nb_xmm_regs; i++) {
+ env->xmm_regs[i].ZMM_Q(0) = 0;
+ env->xmm_regs[i].ZMM_Q(1) = 0;
+ }
+}
+
+static void do_xrstor_ymmh(CPUX86State *env, target_ulong ptr, uintptr_t ra)
+{
+ int i, nb_xmm_regs;
+ target_ulong addr;
+
+ if (env->hflags & HF_CS64_MASK) {
+ nb_xmm_regs = 16;
+ } else {
+ nb_xmm_regs = 8;
+ }
+
+ addr = ptr + XO(avx_state);
+ for (i = 0; i < nb_xmm_regs; i++) {
+ env->xmm_regs[i].ZMM_Q(2) = cpu_ldq_data_ra(env, addr, ra);
+ env->xmm_regs[i].ZMM_Q(3) = cpu_ldq_data_ra(env, addr + 8, ra);
+ addr += 16;
+ }
+}
+
+static void do_clear_ymmh(CPUX86State *env)
+{
+ int i, nb_xmm_regs;
+
+ if (env->hflags & HF_CS64_MASK) {
+ nb_xmm_regs = 16;
+ } else {
+ nb_xmm_regs = 8;
+ }
+
+ for (i = 0; i < nb_xmm_regs; i++) {
+ env->xmm_regs[i].ZMM_Q(2) = 0;
+ env->xmm_regs[i].ZMM_Q(3) = 0;
+ }
+}
+
static void do_xrstor_bndregs(CPUX86State *env, target_ulong ptr, uintptr_t ra)
{
target_ulong addr = ptr + offsetof(XSaveBNDREG, bnd_regs);
@@ -2856,9 +2929,14 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
if (xstate_bv & XSTATE_SSE_MASK) {
do_xrstor_sse(env, ptr, ra);
} else {
- /* ??? When AVX is implemented, we may have to be more
- selective in the clearing. */
- memset(env->xmm_regs, 0, sizeof(env->xmm_regs));
+ do_clear_sse(env);
+ }
+ }
+ if (rfbm & XSTATE_YMM_MASK) {
+ if (xstate_bv & XSTATE_BNDREGS_MASK) {
+ do_xrstor_ymmh(env, ptr, ra);
+ } else {
+ do_clear_ymmh(env);
}
}
if (rfbm & XSTATE_BNDREGS_MASK) {
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* [PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (31 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 10:28 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
` (3 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook
From: Paul Brook <paul@nowt.org>
Include AVX, AVX2 and VAES in the guest cpuid features supported by TCG.
Signed-off-by: Paul Brook <paul@nowt.org>
Message-Id: <20220424220204.2493824-40-paul@nowt.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1db1278a59..ec0817a61d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -625,12 +625,12 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
- CPUID_EXT_RDRAND)
+ CPUID_EXT_RDRAND | CPUID_EXT_AVX)
/* missing:
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
- CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
+ CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER,
CPUID_EXT_F16C */
#ifdef TARGET_X86_64
@@ -653,14 +653,14 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
- CPUID_7_0_EBX_ERMS)
+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2)
/* missing:
- CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
+ CPUID_7_0_EBX_HLE
CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
CPUID_7_0_EBX_RDSEED */
#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
/* CPUID_7_0_ECX_OSPKE is dynamic */ \
- CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
+ CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES)
#define TCG_7_0_EDX_FEATURES 0
#define TCG_7_1_EAX_FEATURES 0
#define TCG_APM_FEATURES 0
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG
2022-09-11 23:04 ` [PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
@ 2022-09-13 10:28 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 10:28 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: Paul Brook
On 9/12/22 00:04, Paolo Bonzini wrote:
> From: Paul Brook<paul@nowt.org>
>
> Include AVX, AVX2 and VAES in the guest cpuid features supported by TCG.
>
> Signed-off-by: Paul Brook<paul@nowt.org>
> Message-Id:<20220424220204.2493824-40-paul@nowt.org>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/cpu.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (32 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 10:32 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 35/37] tests/tcg: extend SSE tests to AVX Paolo Bonzini
` (2 subsequent siblings)
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
These are exactly the same as the non-VEX version, but one has to be careful
that only VEX.L=0 is allowed.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 25 +++++++++++++++++++++++++
target/i386/tcg/emit.c.inc | 20 ++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 383a425ccd..e468a32787 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -80,6 +80,10 @@
#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \
X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
+#define X86_OP_ENTRYw(op, op0, s0, ...) \
+ X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__)
+#define X86_OP_ENTRYr(op, op0, s0, ...) \
+ X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__)
#define X86_OP_ENTRY0(op, ...) \
X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
@@ -147,6 +151,25 @@ static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEnt
}
}
+static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ /* only includes ldmxcsr and stmxcsr, because they have AVX variants. */
+ static const X86OpEntry group15_reg[8] = {
+ };
+
+ static const X86OpEntry group15_mem[8] = {
+ [2] = X86_OP_ENTRYr(LDMXCSR, E,d, vex5),
+ [3] = X86_OP_ENTRYw(STMXCSR, E,d, vex5),
+ };
+
+ uint8_t modrm = get_modrm(s, env);
+ if ((modrm >> 6) == 3) {
+ *entry = group15_reg[(modrm >> 3) & 7];
+ } else {
+ *entry = group15_mem[(modrm >> 3) & 7];
+ }
+}
+
static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86GenFunc group17_gen[8] = {
@@ -754,6 +777,8 @@ static const X86OpEntry opcodes_0F[256] = {
[0x7e] = X86_OP_GROUP0(0F7E),
[0x7f] = X86_OP_GROUP3(0F6F, W,x, None,None, V,x, vex5 mmx p_00_66_f3),
+ [0xae] = X86_OP_GROUP0(group15),
+
[0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
[0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index d61b43f21c..942766de0f 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -979,6 +979,16 @@ static void gen_LDDQU(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_load_sse(s, s->T0, decode->op[0].ot, decode->op[0].offset);
}
+static void gen_LDMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (s->vex_l) {
+ gen_illegal_opcode(s);
+ return;
+ }
+ tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1);
+ gen_helper_ldmxcsr(cpu_env, s->tmp2_i32);
+}
+
static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
tcg_gen_mov_tl(s->A0, cpu_regs[R_EDI]);
@@ -1808,6 +1818,16 @@ static void gen_SSE4a_R(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
}
}
+static void gen_STMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ if (s->vex_l) {
+ gen_illegal_opcode(s);
+ return;
+ }
+ gen_helper_update_mxcsr(cpu_env);
+ tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr));
+}
+
static inline void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
assert(!s->vex_l);
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR
2022-09-11 23:04 ` [PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
@ 2022-09-13 10:32 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 10:32 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> These are exactly the same as the non-VEX version, but one has to be careful
> that only VEX.L=0 is allowed.
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 25 +++++++++++++++++++++++++
> target/i386/tcg/emit.c.inc | 20 ++++++++++++++++++++
> 2 files changed, 45 insertions(+)
Needs to be sorted before patch 33, enabling AVX.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 35/37] tests/tcg: extend SSE tests to AVX
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (33 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 10:33 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 36/37] target/i386: move 3DNow completely out of gen_sse Paolo Bonzini
2022-09-13 10:39 ` [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Richard Henderson
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
Extracted from a patch by Paul Brook <paul@nowt.org>.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
tests/tcg/i386/Makefile.target | 2 +-
tests/tcg/i386/test-avx.c | 201 ++++++++++++++++++---------------
tests/tcg/i386/test-avx.py | 3 +-
3 files changed, 112 insertions(+), 94 deletions(-)
diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target
index ae71e7f748..4139973255 100644
--- a/tests/tcg/i386/Makefile.target
+++ b/tests/tcg/i386/Makefile.target
@@ -98,5 +98,5 @@ test-3dnow: test-3dnow.h
test-mmx: CFLAGS += -masm=intel -O -I.
test-mmx: test-mmx.h
-test-avx: CFLAGS += -masm=intel -O -I.
+test-avx: CFLAGS += -mavx -masm=intel -O -I.
test-avx: test-avx.h
diff --git a/tests/tcg/i386/test-avx.c b/tests/tcg/i386/test-avx.c
index 23c170dd79..953e2906fe 100644
--- a/tests/tcg/i386/test-avx.c
+++ b/tests/tcg/i386/test-avx.c
@@ -6,18 +6,18 @@
typedef void (*testfn)(void);
typedef struct {
- uint64_t q0, q1;
-} __attribute__((aligned(16))) v2di;
+ uint64_t q0, q1, q2, q3;
+} __attribute__((aligned(32))) v4di;
typedef struct {
uint64_t mm[8];
- v2di xmm[16];
+ v4di ymm[16];
uint64_t r[16];
uint64_t flags;
uint32_t ff;
uint64_t pad;
- v2di mem[4];
- v2di mem0[4];
+ v4di mem[4];
+ v4di mem0[4];
} reg_state;
typedef struct {
@@ -31,20 +31,20 @@ reg_state initI;
reg_state initF32;
reg_state initF64;
-static void dump_xmm(const char *name, int n, const v2di *r, int ff)
+static void dump_ymm(const char *name, int n, const v4di *r, int ff)
{
- printf("%s%d = %016lx %016lx\n",
- name, n, r->q1, r->q0);
+ printf("%s%d = %016lx %016lx %016lx %016lx\n",
+ name, n, r->q3, r->q2, r->q1, r->q0);
if (ff == 64) {
- double v[2];
+ double v[4];
memcpy(v, r, sizeof(v));
- printf(" %16g %16g\n",
- v[1], v[0]);
- } else if (ff == 32) {
- float v[4];
- memcpy(v, r, sizeof(v));
- printf(" %8g %8g %8g %8g\n",
+ printf(" %16g %16g %16g %16g\n",
v[3], v[2], v[1], v[0]);
+ } else if (ff == 32) {
+ float v[8];
+ memcpy(v, r, sizeof(v));
+ printf(" %8g %8g %8g %8g %8g %8g %8g %8g\n",
+ v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
}
}
@@ -53,10 +53,10 @@ static void dump_regs(reg_state *s)
int i;
for (i = 0; i < 16; i++) {
- dump_xmm("xmm", i, &s->xmm[i], 0);
+ dump_ymm("ymm", i, &s->ymm[i], 0);
}
for (i = 0; i < 4; i++) {
- dump_xmm("mem", i, &s->mem0[i], 0);
+ dump_ymm("mem", i, &s->mem0[i], 0);
}
}
@@ -74,13 +74,13 @@ static void compare_state(const reg_state *a, const reg_state *b)
}
}
for (i = 0; i < 16; i++) {
- if (memcmp(&a->xmm[i], &b->xmm[i], 16)) {
- dump_xmm("xmm", i, &b->xmm[i], a->ff);
+ if (memcmp(&a->ymm[i], &b->ymm[i], 32)) {
+ dump_ymm("ymm", i, &b->ymm[i], a->ff);
}
}
for (i = 0; i < 4; i++) {
- if (memcmp(&a->mem0[i], &a->mem[i], 16)) {
- dump_xmm("mem", i, &a->mem[i], a->ff);
+ if (memcmp(&a->mem0[i], &a->mem[i], 32)) {
+ dump_ymm("mem", i, &a->mem[i], a->ff);
}
}
if (a->flags != b->flags) {
@@ -89,9 +89,9 @@ static void compare_state(const reg_state *a, const reg_state *b)
}
#define LOADMM(r, o) "movq " #r ", " #o "[%0]\n\t"
-#define LOADXMM(r, o) "movdqa " #r ", " #o "[%0]\n\t"
+#define LOADYMM(r, o) "vmovdqa " #r ", " #o "[%0]\n\t"
#define STOREMM(r, o) "movq " #o "[%1], " #r "\n\t"
-#define STOREXMM(r, o) "movdqa " #o "[%1], " #r "\n\t"
+#define STOREYMM(r, o) "vmovdqa " #o "[%1], " #r "\n\t"
#define MMREG(F) \
F(mm0, 0x00) \
F(mm1, 0x08) \
@@ -101,39 +101,39 @@ static void compare_state(const reg_state *a, const reg_state *b)
F(mm5, 0x28) \
F(mm6, 0x30) \
F(mm7, 0x38)
-#define XMMREG(F) \
- F(xmm0, 0x040) \
- F(xmm1, 0x050) \
- F(xmm2, 0x060) \
- F(xmm3, 0x070) \
- F(xmm4, 0x080) \
- F(xmm5, 0x090) \
- F(xmm6, 0x0a0) \
- F(xmm7, 0x0b0) \
- F(xmm8, 0x0c0) \
- F(xmm9, 0x0d0) \
- F(xmm10, 0x0e0) \
- F(xmm11, 0x0f0) \
- F(xmm12, 0x100) \
- F(xmm13, 0x110) \
- F(xmm14, 0x120) \
- F(xmm15, 0x130)
+#define YMMREG(F) \
+ F(ymm0, 0x040) \
+ F(ymm1, 0x060) \
+ F(ymm2, 0x080) \
+ F(ymm3, 0x0a0) \
+ F(ymm4, 0x0c0) \
+ F(ymm5, 0x0e0) \
+ F(ymm6, 0x100) \
+ F(ymm7, 0x120) \
+ F(ymm8, 0x140) \
+ F(ymm9, 0x160) \
+ F(ymm10, 0x180) \
+ F(ymm11, 0x1a0) \
+ F(ymm12, 0x1c0) \
+ F(ymm13, 0x1e0) \
+ F(ymm14, 0x200) \
+ F(ymm15, 0x220)
#define LOADREG(r, o) "mov " #r ", " #o "[rax]\n\t"
#define STOREREG(r, o) "mov " #o "[rax], " #r "\n\t"
#define REG(F) \
- F(rbx, 0x148) \
- F(rcx, 0x150) \
- F(rdx, 0x158) \
- F(rsi, 0x160) \
- F(rdi, 0x168) \
- F(r8, 0x180) \
- F(r9, 0x188) \
- F(r10, 0x190) \
- F(r11, 0x198) \
- F(r12, 0x1a0) \
- F(r13, 0x1a8) \
- F(r14, 0x1b0) \
- F(r15, 0x1b8) \
+ F(rbx, 0x248) \
+ F(rcx, 0x250) \
+ F(rdx, 0x258) \
+ F(rsi, 0x260) \
+ F(rdi, 0x268) \
+ F(r8, 0x280) \
+ F(r9, 0x288) \
+ F(r10, 0x290) \
+ F(r11, 0x298) \
+ F(r12, 0x2a0) \
+ F(r13, 0x2a8) \
+ F(r14, 0x2b0) \
+ F(r15, 0x2b8) \
static void run_test(const TestDef *t)
{
@@ -143,7 +143,7 @@ static void run_test(const TestDef *t)
printf("%5d %s\n", t->n, t->s);
asm volatile(
MMREG(LOADMM)
- XMMREG(LOADXMM)
+ YMMREG(LOADYMM)
"sub rsp, 128\n\t"
"push rax\n\t"
"push rbx\n\t"
@@ -156,26 +156,26 @@ static void run_test(const TestDef *t)
"pop rbx\n\t"
"shr rbx, 8\n\t"
"shl rbx, 8\n\t"
- "mov rcx, 0x1c0[rax]\n\t"
+ "mov rcx, 0x2c0[rax]\n\t"
"and rcx, 0xff\n\t"
"or rbx, rcx\n\t"
"push rbx\n\t"
"popf\n\t"
REG(LOADREG)
- "mov rax, 0x140[rax]\n\t"
+ "mov rax, 0x240[rax]\n\t"
"call [rsp]\n\t"
"mov [rsp], rax\n\t"
"mov rax, 8[rsp]\n\t"
REG(STOREREG)
"mov rbx, [rsp]\n\t"
- "mov 0x140[rax], rbx\n\t"
+ "mov 0x240[rax], rbx\n\t"
"mov rbx, 0\n\t"
- "mov 0x170[rax], rbx\n\t"
- "mov 0x178[rax], rbx\n\t"
+ "mov 0x270[rax], rbx\n\t"
+ "mov 0x278[rax], rbx\n\t"
"pushf\n\t"
"pop rbx\n\t"
"and rbx, 0xff\n\t"
- "mov 0x1c0[rax], rbx\n\t"
+ "mov 0x2c0[rax], rbx\n\t"
"add rsp, 16\n\t"
"pop rdx\n\t"
"pop rcx\n\t"
@@ -183,15 +183,15 @@ static void run_test(const TestDef *t)
"pop rax\n\t"
"add rsp, 128\n\t"
MMREG(STOREMM)
- XMMREG(STOREXMM)
+ YMMREG(STOREYMM)
: : "r"(init), "r"(&result), "r"(t->fn)
: "memory", "cc",
"rsi", "rdi",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
- "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5",
- "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11",
- "xmm12", "xmm13", "xmm14", "xmm15"
+ "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5",
+ "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11",
+ "ymm12", "ymm13", "ymm14", "ymm15"
);
compare_state(init, &result);
}
@@ -223,22 +223,30 @@ static void run_all(void)
float val_f32[] = {2.0, -1.0, 4.8, 0.8, 3, -42.0, 5e6, 7.5, 8.3};
double val_f64[] = {2.0, -1.0, 4.8, 0.8, 3, -42.0, 5e6, 7.5};
-v2di val_i64[] = {
- {0x3d6b3b6a9e4118f2lu, 0x355ae76d2774d78clu},
- {0xd851c54a56bf1f29lu, 0x4a84d1d50bf4c4fflu},
- {0x5826475e2c5fd799lu, 0xfd32edc01243f5e9lu},
+v4di val_i64[] = {
+ {0x3d6b3b6a9e4118f2lu, 0x355ae76d2774d78clu,
+ 0xac3ff76c4daa4b28lu, 0xe7fabd204cb54083lu},
+ {0xd851c54a56bf1f29lu, 0x4a84d1d50bf4c4fflu,
+ 0x56621e553d52b56clu, 0xd0069553da8f584alu},
+ {0x5826475e2c5fd799lu, 0xfd32edc01243f5e9lu,
+ 0x738ba2c66d3fe126lu, 0x5707219c6e6c26b4lu},
};
-v2di deadbeef = {0xa5a5a5a5deadbeefull, 0xa5a5a5a5deadbeefull};
-v2di indexq = {0x000000000000001full, 0x000000000000008full};
-v2di indexd = {0x00000002000000efull, 0xfffffff500000010ull};
+v4di deadbeef = {0xa5a5a5a5deadbeefull, 0xa5a5a5a5deadbeefull,
+ 0xa5a5a5a5deadbeefull, 0xa5a5a5a5deadbeefull};
+v4di indexq = {0x000000000000001full, 0x000000000000008full,
+ 0xffffffffffffffffull, 0xffffffffffffff5full};
+v4di indexd = {0x00000002000000efull, 0xfffffff500000010ull,
+ 0x0000000afffffff0ull, 0x000000000000000eull};
-void init_f32reg(v2di *r)
+v4di gather_mem[0x20];
+
+void init_f32reg(v4di *r)
{
static int n;
- float v[4];
+ float v[8];
int i;
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < 8; i++) {
v[i] = val_f32[n++];
if (n == ARRAY_LEN(val_f32)) {
n = 0;
@@ -247,12 +255,12 @@ void init_f32reg(v2di *r)
memcpy(r, v, sizeof(*r));
}
-void init_f64reg(v2di *r)
+void init_f64reg(v4di *r)
{
static int n;
- double v[2];
+ double v[4];
int i;
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < 4; i++) {
v[i] = val_f64[n++];
if (n == ARRAY_LEN(val_f64)) {
n = 0;
@@ -261,13 +269,15 @@ void init_f64reg(v2di *r)
memcpy(r, v, sizeof(*r));
}
-void init_intreg(v2di *r)
+void init_intreg(v4di *r)
{
static uint64_t mask;
static int n;
r->q0 = val_i64[n].q0 ^ mask;
r->q1 = val_i64[n].q1 ^ mask;
+ r->q2 = val_i64[n].q2 ^ mask;
+ r->q3 = val_i64[n].q3 ^ mask;
n++;
if (n == ARRAY_LEN(val_i64)) {
n = 0;
@@ -280,46 +290,53 @@ static void init_all(reg_state *s)
int i;
s->r[3] = (uint64_t)&s->mem[0]; /* rdx */
+ s->r[4] = (uint64_t)&gather_mem[ARRAY_LEN(gather_mem) / 2]; /* rsi */
s->r[5] = (uint64_t)&s->mem[2]; /* rdi */
s->flags = 2;
- for (i = 0; i < 8; i++) {
- s->xmm[i] = deadbeef;
+ for (i = 0; i < 16; i++) {
+ s->ymm[i] = deadbeef;
}
- s->xmm[13] = indexd;
- s->xmm[14] = indexq;
- for (i = 0; i < 2; i++) {
+ s->ymm[13] = indexd;
+ s->ymm[14] = indexq;
+ for (i = 0; i < 4; i++) {
s->mem0[i] = deadbeef;
}
}
int main(int argc, char *argv[])
{
+ int i;
+
init_all(&initI);
- init_intreg(&initI.xmm[10]);
- init_intreg(&initI.xmm[11]);
- init_intreg(&initI.xmm[12]);
+ init_intreg(&initI.ymm[10]);
+ init_intreg(&initI.ymm[11]);
+ init_intreg(&initI.ymm[12]);
init_intreg(&initI.mem0[1]);
printf("Int:\n");
dump_regs(&initI);
init_all(&initF32);
- init_f32reg(&initF32.xmm[10]);
- init_f32reg(&initF32.xmm[11]);
- init_f32reg(&initF32.xmm[12]);
+ init_f32reg(&initF32.ymm[10]);
+ init_f32reg(&initF32.ymm[11]);
+ init_f32reg(&initF32.ymm[12]);
init_f32reg(&initF32.mem0[1]);
initF32.ff = 32;
printf("F32:\n");
dump_regs(&initF32);
init_all(&initF64);
- init_f64reg(&initF64.xmm[10]);
- init_f64reg(&initF64.xmm[11]);
- init_f64reg(&initF64.xmm[12]);
+ init_f64reg(&initF64.ymm[10]);
+ init_f64reg(&initF64.ymm[11]);
+ init_f64reg(&initF64.ymm[12]);
init_f64reg(&initF64.mem0[1]);
initF64.ff = 64;
printf("F64:\n");
dump_regs(&initF64);
+ for (i = 0; i < ARRAY_LEN(gather_mem); i++) {
+ init_intreg(&gather_mem[i]);
+ }
+
if (argc > 1) {
int n = atoi(argv[1]);
run_test(&test_table[n]);
diff --git a/tests/tcg/i386/test-avx.py b/tests/tcg/i386/test-avx.py
index e16a3d8bee..cff3aed138 100755
--- a/tests/tcg/i386/test-avx.py
+++ b/tests/tcg/i386/test-avx.py
@@ -8,6 +8,7 @@
archs = [
"SSE", "SSE2", "SSE3", "SSSE3", "SSE4_1", "SSE4_2",
+ "AVX", "AVX2", "AES+AVX", # "VAES+AVX",
]
ignore = set(["FISTTP",
@@ -85,7 +86,7 @@ def mem_w(w):
else:
raise Exception()
- return t + " PTR 16[rdx]"
+ return t + " PTR 32[rdx]"
class XMMArg():
isxmm = True
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [PATCH 35/37] tests/tcg: extend SSE tests to AVX
2022-09-11 23:04 ` [PATCH 35/37] tests/tcg: extend SSE tests to AVX Paolo Bonzini
@ 2022-09-13 10:33 ` Richard Henderson
0 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 10:33 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:04, Paolo Bonzini wrote:
> Extracted from a patch by Paul Brook<paul@nowt.org>.
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> tests/tcg/i386/Makefile.target | 2 +-
> tests/tcg/i386/test-avx.c | 201 ++++++++++++++++++---------------
> tests/tcg/i386/test-avx.py | 3 +-
> 3 files changed, 112 insertions(+), 94 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH 36/37] target/i386: move 3DNow completely out of gen_sse
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (34 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 35/37] tests/tcg: extend SSE tests to AVX Paolo Bonzini
@ 2022-09-11 23:04 ` Paolo Bonzini
2022-09-13 10:34 ` Richard Henderson
2022-09-13 10:39 ` [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Richard Henderson
36 siblings, 1 reply; 86+ messages in thread
From: Paolo Bonzini @ 2022-09-11 23:04 UTC (permalink / raw)
To: qemu-devel
Everything else has been converted to the new decoder, so separate the
part that survives.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 104 +++++++++++++++++++++++-------------
1 file changed, 68 insertions(+), 36 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index f312663110..0783b1e7ee 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2918,7 +2918,6 @@ static bool first = true; static unsigned long limit;
#define SSE_OPF_CMP (1 << 1) /* does not write for first operand */
#define SSE_OPF_BLENDV (1 << 2) /* blendv* instruction */
#define SSE_OPF_SPECIAL (1 << 3) /* magic */
-#define SSE_OPF_3DNOW (1 << 4) /* 3DNow! instruction */
#define SSE_OPF_MMX (1 << 5) /* MMX/integer/AVX2 instruction */
#define SSE_OPF_SCALAR (1 << 6) /* Has SSE scalar variants */
#define SSE_OPF_SHUF (1 << 9) /* pshufx/shufpx */
@@ -2952,13 +2951,9 @@ struct SSEOpHelper_table1 {
SSEFuncs fn[4];
};
-#define SSE_3DNOW { SSE_OPF_3DNOW }
#define SSE_SPECIAL { SSE_OPF_SPECIAL }
static const struct SSEOpHelper_table1 sse_op_table1[256] = {
- /* 3DNow! extensions */
- [0x0e] = SSE_SPECIAL, /* femms */
- [0x0f] = SSE_3DNOW, /* pf... (sse_op_table5) */
/* pure SSE operations */
[0x10] = SSE_SPECIAL, /* movups, movupd, movss, movsd */
[0x11] = SSE_SPECIAL, /* movups, movupd, movss, movsd */
@@ -3172,7 +3167,7 @@ static void gen_helper_pavgusb(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b)
gen_helper_pavgb_mmx(env, reg_a, reg_a, reg_b);
}
-static const SSEFunc_0_epp sse_op_table5[256] = {
+static const SSEFunc_0_epp op_3dnow[256] = {
[0x0c] = gen_helper_pi2fw,
[0x0d] = gen_helper_pi2fd,
[0x1c] = gen_helper_pf2iw,
@@ -3351,7 +3346,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
b1 = 0;
sse_op_flags = sse_op_table1[b].flags;
sse_op_fn = sse_op_table1[b].fn[b1];
- if ((sse_op_flags & (SSE_OPF_SPECIAL | SSE_OPF_3DNOW)) == 0
+ if ((sse_op_flags & SSE_OPF_SPECIAL) == 0
&& !sse_op_fn.op1) {
goto unknown_op;
}
@@ -3365,11 +3360,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
is_xmm = 1;
}
}
- if (sse_op_flags & SSE_OPF_3DNOW) {
- if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) {
- goto illegal_op;
- }
- }
/* simple MMX/SSE operation */
if (s->flags & HF_TS_MASK) {
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
@@ -3385,15 +3375,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
&& (b != 0x38 && b != 0x3a)) {
goto unknown_op;
}
- if (b == 0x0e) {
- if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) {
- /* If we were fully decoding this we might use illegal_op. */
- goto unknown_op;
- }
- /* femms */
- gen_helper_emms(cpu_env);
- return;
- }
if (b == 0x77) {
/* emms */
gen_helper_emms(cpu_env);
@@ -4536,18 +4517,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
rm = (modrm & 7);
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
}
- if (sse_op_flags & SSE_OPF_3DNOW) {
- /* 3DNow! data insns */
- val = x86_ldub_code(env, s);
- SSEFunc_0_epp op_3dnow = sse_op_table5[val];
- if (!op_3dnow) {
- goto unknown_op;
- }
- tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
- tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
- op_3dnow(cpu_env, s->ptr0, s->ptr1);
- return;
- }
}
@@ -4598,6 +4567,70 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
}
+static void gen_3dnow(CPUX86State *env, DisasContext *s, int b,
+ target_ulong pc_start)
+{
+ int op1_offset, op2_offset, val;
+ int modrm, mod, rm, reg;
+ SSEFunc_0_epp fn;
+
+ /* simple MMX/SSE operation */
+ if (s->flags & HF_TS_MASK) {
+ gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
+ return;
+ }
+ if (s->flags & HF_EM_MASK) {
+ goto illegal_op;
+ return;
+ }
+ if (b == 0x10e) {
+ if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) {
+ /* If we were fully decoding this we might use illegal_op. */
+ goto unknown_op;
+ }
+ /* femms */
+ gen_helper_emms(cpu_env);
+ return;
+ }
+
+ if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) {
+ goto illegal_op;
+ }
+
+ gen_helper_enter_mmx(cpu_env);
+
+ modrm = x86_ldub_code(env, s);
+ reg = ((modrm >> 3) & 7);
+ mod = (modrm >> 6) & 3;
+
+ op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
+ if (mod != 3) {
+ gen_lea_modrm(env, s, modrm);
+ op2_offset = offsetof(CPUX86State,mmx_t0);
+ gen_ldq_env_A0(s, op2_offset);
+ } else {
+ rm = (modrm & 7);
+ op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
+ }
+
+ val = x86_ldub_code(env, s);
+ fn = op_3dnow[val];
+ if (!fn) {
+ goto unknown_op;
+ }
+ tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
+ tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
+ fn(cpu_env, s->ptr0, s->ptr1);
+ return;
+
+illegal_op:
+ gen_illegal_opcode(s);
+ return;
+
+unknown_op:
+ gen_unknown_opcode(env, s);
+}
+
/* convert one instruction. s->base.is_jmp is set if the translation must
be stopped. Return the next pc value */
static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
@@ -8505,9 +8538,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
set_cc_op(s, CC_OP_POPCNT);
break;
case 0x10e ... 0x10f:
- /* 3DNow! instructions, ignore prefixes */
- s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
- /* fall through */
+ gen_3dnow(env, s, b, pc_start);
+ break;
case 0x110 ... 0x117:
case 0x128 ... 0x12f:
case 0x138 ... 0x13a:
--
2.37.2
^ permalink raw reply related [flat|nested] 86+ messages in thread* Re: [RFC PATCH 00/37] target/i386: new decoder + AVX implementation
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
` (35 preceding siblings ...)
2022-09-11 23:04 ` [PATCH 36/37] target/i386: move 3DNow completely out of gen_sse Paolo Bonzini
@ 2022-09-13 10:39 ` Richard Henderson
36 siblings, 0 replies; 86+ messages in thread
From: Richard Henderson @ 2022-09-13 10:39 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 9/12/22 00:03, Paolo Bonzini wrote:
> target/i386: remove old SSE decoder
Patch 37 never arrived, but I can imagine what it looked like. :-)
The series is looking good. All of the nits were minor.
r~
^ permalink raw reply [flat|nested] 86+ messages in thread