* [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
@ 2022-12-15 12:56 Andrzej Hajda
2022-12-15 13:10 ` Jani Nikula
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Andrzej Hajda @ 2022-12-15 12:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Andrzej Hajda, Rodrigo Vivi
The helper makes the code more compact and readable.
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++++++----------------
1 file changed, 44 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 063f1da4f229cf..f62d9a9313498c 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
/* Train 2 */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_PATTERN_2;
- intel_de_write(dev_priv, reg, temp);
-
- reg = FDI_RX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_PATTERN_2;
- intel_de_write(dev_priv, reg, temp);
-
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
+ FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
+ intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
+ FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
+ intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
udelay(150);
reg = FDI_RX_IIR(pipe);
@@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
udelay(150);
for (i = 0; i < 4; i++) {
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
- temp |= snb_b_fdi_train_param[i];
- intel_de_write(dev_priv, reg, temp);
-
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
+ FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
+ intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
udelay(500);
for (retry = 0; retry < 5; retry++) {
@@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
udelay(150);
for (i = 0; i < 4; i++) {
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
- temp |= snb_b_fdi_train_param[i];
- intel_de_write(dev_priv, reg, temp);
-
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
+ FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
+ intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
udelay(500);
for (retry = 0; retry < 5; retry++) {
@@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
}
/* Train 2 */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_LINK_TRAIN_NONE_IVB;
- temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
- intel_de_write(dev_priv, reg, temp);
-
- reg = FDI_RX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
- temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
- intel_de_write(dev_priv, reg, temp);
-
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
+ FDI_LINK_TRAIN_NONE_IVB,
+ FDI_LINK_TRAIN_PATTERN_2_IVB);
+ intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
+ FDI_LINK_TRAIN_PATTERN_MASK_CPT,
+ FDI_LINK_TRAIN_PATTERN_2_CPT);
+ intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
udelay(2); /* should be 1.5us */
for (i = 0; i < 4; i++) {
@@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
udelay(30);
/* Unset FDI_RX_MISC pwrdn lanes */
- temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
- temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
- intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
+ intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
+ FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
/* Wait for FDI auto training time */
@@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
- temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
- temp &= ~DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
+ intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
- temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
- temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
- temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
- intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
+ intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
+ DP_TP_CTL_LINK_TRAIN_PAT1);
intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
intel_wait_ddi_buf_idle(dev_priv, PORT_E);
/* Reset FDI_RX_MISC pwrdn lanes */
- temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
- temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
- temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
- intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
+ intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
+ FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
+ FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
}
@@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
void hsw_fdi_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 val;
/*
* Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
@@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
* step 13 is the correct place for it. Step 18 is where it was
* originally before the BUN.
*/
- val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- val &= ~FDI_RX_ENABLE;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
-
- val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
- val &= ~DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
-
+ intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
+ intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
intel_wait_ddi_buf_idle(dev_priv, PORT_E);
-
intel_ddi_disable_clock(encoder);
-
- val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
- val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
- val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
- intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
-
- val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- val &= ~FDI_PCDCLK;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
-
- val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
- val &= ~FDI_RX_PLL_ENABLE;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
+ intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
+ FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
+ FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
+ intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
+ intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
}
void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
@@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
udelay(200);
/* Switch from Rawclk to PCDclk */
- temp = intel_de_read(dev_priv, reg);
- intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
-
+ intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
intel_de_posting_read(dev_priv, reg);
udelay(200);
@@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
- u32 temp;
/* Switch from PCDclk to Rawclk */
- reg = FDI_RX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
+ intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
/* Disable CPU FDI TX PLL */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
-
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
+ intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
udelay(100);
- reg = FDI_RX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
-
/* Wait for the clocks to turn off. */
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
+ intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
udelay(100);
}
@@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
u32 temp;
/* disable CPU FDI tx and PCH FDI rx */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
+ intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
reg = FDI_RX_CTL(pipe);
temp = intel_de_read(dev_priv, reg);
@@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
FDI_RX_PHASE_SYNC_POINTER_OVR);
/* still set train pattern 1 */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_PATTERN_1;
- intel_de_write(dev_priv, reg, temp);
+ intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
+ FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
reg = FDI_RX_CTL(pipe);
temp = intel_de_read(dev_priv, reg);
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
2022-12-15 12:56 [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible Andrzej Hajda
@ 2022-12-15 13:10 ` Jani Nikula
2022-12-15 15:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2022-12-15 13:10 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Andrzej Hajda, Rodrigo Vivi
On Thu, 15 Dec 2022, Andrzej Hajda <andrzej.hajda@intel.com> wrote:
> The helper makes the code more compact and readable.
>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++++++----------------
> 1 file changed, 44 insertions(+), 104 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 063f1da4f229cf..f62d9a9313498c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
> drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
>
> /* Train 2 */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_PATTERN_2;
> - intel_de_write(dev_priv, reg, temp);
> -
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_PATTERN_2;
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
> udelay(150);
>
> reg = FDI_RX_IIR(pipe);
> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
> udelay(150);
>
> for (i = 0; i < 4; i++) {
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> - temp |= snb_b_fdi_train_param[i];
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
> udelay(500);
>
> for (retry = 0; retry < 5; retry++) {
> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
> udelay(150);
>
> for (i = 0; i < 4; i++) {
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> - temp |= snb_b_fdi_train_param[i];
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
> udelay(500);
>
> for (retry = 0; retry < 5; retry++) {
> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
> }
>
> /* Train 2 */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> - temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
> - intel_de_write(dev_priv, reg, temp);
> -
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> - temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE_IVB,
> + FDI_LINK_TRAIN_PATTERN_2_IVB);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
> + FDI_LINK_TRAIN_PATTERN_MASK_CPT,
> + FDI_LINK_TRAIN_PATTERN_2_CPT);
> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
> udelay(2); /* should be 1.5us */
>
> for (i = 0; i < 4; i++) {
> @@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> udelay(30);
>
> /* Unset FDI_RX_MISC pwrdn lanes */
> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>
> /* Wait for FDI auto training time */
> @@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
> intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
>
> - temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
> - temp &= ~DDI_BUF_CTL_ENABLE;
> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
> intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
>
> /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
> - temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
> - temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> + intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
> + DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
> + DP_TP_CTL_LINK_TRAIN_PAT1);
> intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
>
> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>
> /* Reset FDI_RX_MISC pwrdn lanes */
> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> - temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
> }
>
> @@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> void hsw_fdi_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - u32 val;
>
> /*
> * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
> @@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
> * step 13 is the correct place for it. Step 18 is where it was
> * originally before the BUN.
> */
> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> - val &= ~FDI_RX_ENABLE;
> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> -
> - val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
> - val &= ~DDI_BUF_CTL_ENABLE;
> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
> -
> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> -
> intel_ddi_disable_clock(encoder);
> -
> - val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> - val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> - val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
> -
> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> - val &= ~FDI_PCDCLK;
> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> -
> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> - val &= ~FDI_RX_PLL_ENABLE;
> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
> }
>
> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> @@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> udelay(200);
>
> /* Switch from Rawclk to PCDclk */
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
> -
> + intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
> intel_de_posting_read(dev_priv, reg);
> udelay(200);
>
> @@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum pipe pipe = crtc->pipe;
> - i915_reg_t reg;
> - u32 temp;
>
> /* Switch from PCDclk to Rawclk */
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
>
> /* Disable CPU FDI TX PLL */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
> udelay(100);
>
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
> -
> /* Wait for the clocks to turn off. */
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
> udelay(100);
> }
>
> @@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
> u32 temp;
>
> /* disable CPU FDI tx and PCH FDI rx */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>
> reg = FDI_RX_CTL(pipe);
> temp = intel_de_read(dev_priv, reg);
> @@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
> FDI_RX_PHASE_SYNC_POINTER_OVR);
>
> /* still set train pattern 1 */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_PATTERN_1;
> - intel_de_write(dev_priv, reg, temp);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
>
> reg = FDI_RX_CTL(pipe);
> temp = intel_de_read(dev_priv, reg);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/fdi: use intel_de_rmw if possible
2022-12-15 12:56 [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible Andrzej Hajda
2022-12-15 13:10 ` Jani Nikula
@ 2022-12-15 15:55 ` Patchwork
2022-12-16 13:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-30 8:11 ` [Intel-gfx] [PATCH] " Andrzej Hajda
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-12-15 15:55 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 18789 bytes --]
== Series Details ==
Series: drm/i915/display/fdi: use intel_de_rmw if possible
URL : https://patchwork.freedesktop.org/series/111964/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12510 -> Patchwork_111964v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/index.html
Participating hosts (19 -> 39)
------------------------------
Additional (22): fi-kbl-soraka bat-dg1-6 bat-dg1-5 bat-adlp-6 bat-rpls-1 bat-rpls-2 fi-skl-6600u fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-bwr-2160 bat-adln-1 bat-atsm-1 bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 bat-adlp-9 bat-adlp-4
Missing (2): fi-hsw-4770 fi-rkl-guc
Known issues
------------
Here are the changes found in Patchwork_111964v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-adlp-4: NOTRUN -> [SKIP][1] ([i915#7456])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@debugfs_test@basic-hwmon.html
* igt@gem_exec_gttfill@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +7 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-kbl-soraka/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-bsw-nick: NOTRUN -> [SKIP][6] ([fdo#109271]) +39 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-bsw-nick/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][7] ([fdo#109271]) +20 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4083])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@gem_mmap@basic.html
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4083])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4079]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4077]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@gem_tiled_fence_blits@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4077]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4079]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#3282])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#7561])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
- bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#7561])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#6621])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@i915_pm_rps@basic-api.html
- bat-dg1-5: NOTRUN -> [SKIP][20] ([i915#6621])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@i915_pm_rps@basic-api.html
- bat-adlp-4: NOTRUN -> [SKIP][21] ([i915#6621])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][22] ([i915#1886])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@workarounds:
- bat-adlp-4: NOTRUN -> [INCOMPLETE][23] ([i915#4983])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][24] ([i915#4212]) +7 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][25] ([i915#4215])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg1-6: NOTRUN -> [SKIP][26] ([i915#4215])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6: NOTRUN -> [SKIP][27] ([i915#4212]) +7 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600: NOTRUN -> [SKIP][28] ([fdo#111827])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-rkl-11600/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][29] ([fdo#111827]) +7 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-edid-read:
- fi-bsw-n3050: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +8 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-bsw-n3050/igt@kms_chamelium@dp-edid-read.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6600u: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +8 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-skl-6600u/igt@kms_chamelium@hdmi-crc-fast.html
- bat-dg1-6: NOTRUN -> [SKIP][32] ([fdo#111827]) +8 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-bsw-nick: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +8 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-bsw-nick/igt@kms_chamelium@hdmi-hpd-fast.html
- bat-dg1-5: NOTRUN -> [SKIP][34] ([fdo#111827]) +8 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-kbl-soraka: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +7 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-adlp-4: NOTRUN -> [SKIP][36] ([i915#4103])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
- bat-dg1-5: NOTRUN -> [SKIP][37] ([i915#4103] / [i915#4213])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
- bat-dg1-6: NOTRUN -> [SKIP][38] ([i915#4103] / [i915#4213])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-5: NOTRUN -> [SKIP][39] ([fdo#109285])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-6: NOTRUN -> [SKIP][40] ([fdo#109285])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][41] ([i915#4093]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_psr@primary_mmap_gtt:
- fi-bwr-2160: NOTRUN -> [SKIP][42] ([fdo#109271]) +54 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-bwr-2160/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6: NOTRUN -> [SKIP][43] ([i915#1072] / [i915#4078]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html
- bat-dg1-5: NOTRUN -> [SKIP][44] ([i915#1072] / [i915#4078]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6: NOTRUN -> [SKIP][45] ([i915#3555])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg1-5: NOTRUN -> [SKIP][46] ([i915#3555])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adlp-4: NOTRUN -> [SKIP][47] ([i915#3555] / [i915#4579])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-dg1-5: NOTRUN -> [SKIP][48] ([i915#3708]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-5: NOTRUN -> [SKIP][49] ([i915#3708] / [i915#4077]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@prime_vgem@basic-gtt.html
- bat-dg1-6: NOTRUN -> [SKIP][50] ([i915#3708] / [i915#4077]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-read:
- bat-dg1-6: NOTRUN -> [SKIP][51] ([i915#3708]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][52] ([fdo#109295] / [i915#3301] / [i915#3708])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@prime_vgem@basic-userptr.html
- fi-skl-6600u: NOTRUN -> [SKIP][53] ([fdo#109271]) +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-skl-6600u/igt@prime_vgem@basic-userptr.html
- bat-dg1-5: NOTRUN -> [SKIP][54] ([i915#3708] / [i915#4873])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-5/igt@prime_vgem@basic-userptr.html
- bat-dg1-6: NOTRUN -> [SKIP][55] ([i915#3708] / [i915#4873])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-dg1-6/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][56] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/bat-adlp-4/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][57] ([i915#6298]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
#### Warnings ####
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][59] ([i915#4817]) -> [FAIL][60] ([fdo#103375])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
[i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
[i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
[i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
[i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
[i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7328]: https://gitlab.freedesktop.org/drm/intel/issues/7328
[i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7498]: https://gitlab.freedesktop.org/drm/intel/issues/7498
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
Build changes
-------------
* Linux: CI_DRM_12510 -> Patchwork_111964v1
CI-20190529: 20190529
CI_DRM_12510: e7a0d02714edf5ceac30b8da5ed7151d7dadbd40 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7094: 1763071e9d50c5e992257c9197cb26f166de6fae @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111964v1: e7a0d02714edf5ceac30b8da5ed7151d7dadbd40 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f4395fff6308 drm/i915/display/fdi: use intel_de_rmw if possible
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/index.html
[-- Attachment #2: Type: text/html, Size: 22116 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/fdi: use intel_de_rmw if possible
2022-12-15 12:56 [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible Andrzej Hajda
2022-12-15 13:10 ` Jani Nikula
2022-12-15 15:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2022-12-16 13:59 ` Patchwork
2023-01-30 8:11 ` [Intel-gfx] [PATCH] " Andrzej Hajda
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-12-16 13:59 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 28788 bytes --]
== Series Details ==
Series: drm/i915/display/fdi: use intel_de_rmw if possible
URL : https://patchwork.freedesktop.org/series/111964/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12510_full -> Patchwork_111964v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 14)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_111964v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_endless@dispatch@vecs0:
- shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3778])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-tglb2/igt@gem_exec_endless@dispatch@vecs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-tglb2/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#5566] / [i915#716])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-glk8/igt@gen9_exec_parse@allowed-single.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-glk2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#5334])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-glk7/igt@i915_selftest@live@gt_heartbeat.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-glk2/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#5591])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-tglb5/igt@i915_selftest@live@hangcheck.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-tglb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-apl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-apl2/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2587] / [i915#2672]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#2672]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#3555])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#2672] / [i915#3555])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [PASS][25] -> [SKIP][26] ([i915#5519])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
- shard-iclb: [PASS][27] -> [SKIP][28] ([i915#5519])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][29] -> [INCOMPLETE][30] ([i915#5213])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-glk8/igt@perf@stress-open-close.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-glk8/igt@perf@stress-open-close.html
#### Possible fixes ####
* igt@drm_read@empty-nonblock:
- {shard-rkl}: [SKIP][31] ([i915#4098]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@drm_read@empty-nonblock.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@drm_read@empty-nonblock.html
* igt@fbdev@unaligned-read:
- {shard-rkl}: [SKIP][33] ([i915#2582]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@fbdev@unaligned-read.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@fbdev@unaligned-read.html
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][35] ([i915#658]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb5/igt@feature_discovery@psr2.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_bad_reloc@negative-reloc-lut:
- {shard-rkl}: [SKIP][37] ([i915#3281]) -> [PASS][38] +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-4/igt@gem_bad_reloc@negative-reloc-lut.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-5/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu-10}: [FAIL][39] ([i915#6268]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-tglu-10/igt@gem_ctx_exec@basic-nohangcheck.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-tglu-10/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_shared@q-in-order@rcs0:
- {shard-rkl}: [FAIL][41] ([i915#7672]) -> [PASS][42] +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-4/igt@gem_ctx_shared@q-in-order@rcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-5/igt@gem_ctx_shared@q-in-order@rcs0.html
* igt@gem_eio@suspend:
- {shard-rkl}: [FAIL][43] ([i915#7052]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-4/igt@gem_eio@suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-2/igt@gem_eio@suspend.html
* igt@gem_exec_balancer@fairslice:
- {shard-rkl}: [SKIP][45] ([i915#6259]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-5/igt@gem_exec_balancer@fairslice.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-1/igt@gem_exec_balancer@fairslice.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][47] ([i915#4525]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][49] ([i915#2846]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_softpin@evict-single-offset:
- {shard-rkl}: [FAIL][51] ([i915#4171]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-4/igt@gem_softpin@evict-single-offset.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-3/igt@gem_softpin@evict-single-offset.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- {shard-rkl}: [SKIP][53] ([i915#2527]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-4/igt@gen9_exec_parse@basic-rejected-ctx-param.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-5/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [SKIP][55] ([i915#3361]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-1/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][57] ([i915#3989] / [i915#454]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu-9}: [FAIL][59] ([i915#4275]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}: [SKIP][61] ([i915#1397]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-rkl}: [SKIP][63] ([i915#1845] / [i915#4098]) -> [PASS][64] +20 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][65] ([i915#2346]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_fbcon_fbt@psr-suspend:
- {shard-rkl}: [SKIP][67] ([i915#3955]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@kms_fbcon_fbt@psr-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][69] ([i915#2122]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1:
- shard-glk: [FAIL][71] ([i915#79]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- {shard-rkl}: [SKIP][73] ([i915#1849] / [i915#4098]) -> [PASS][74] +12 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- {shard-rkl}: [SKIP][75] ([i915#3558]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [SKIP][77] ([i915#5235]) -> [PASS][78] +5 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr@primary_mmap_gtt:
- {shard-rkl}: [SKIP][79] ([i915#1072]) -> [PASS][80] +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@kms_psr@primary_mmap_gtt.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [SKIP][81] ([fdo#109441]) -> [PASS][82] +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_gtt.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [SKIP][83] ([i915#5519]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-tglb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-tglb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
- shard-iclb: [SKIP][85] ([i915#5519]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
- {shard-rkl}: [SKIP][87] ([i915#5461]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][89] ([i915#2434]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-rkl-4/igt@perf@mi-rpc.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-rkl-5/igt@perf@mi-rpc.html
#### Warnings ####
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][91] ([i915#2920]) -> [SKIP][92] ([i915#658])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb6/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][93] ([i915#2920]) -> [SKIP][94] ([fdo#111068] / [i915#658]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][95] ([i915#658]) -> [SKIP][96] ([i915#2920])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@runner@aborted:
- shard-apl: ([FAIL][97], [FAIL][98]) ([i915#3002] / [i915#4312]) -> ([FAIL][99], [FAIL][100], [FAIL][101]) ([i915#180] / [i915#3002] / [i915#4312])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-apl8/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12510/shard-apl3/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-apl6/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-apl2/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/shard-apl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4275]: https://gitlab.freedesktop.org/drm/intel/issues/4275
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7672]: https://gitlab.freedesktop.org/drm/intel/issues/7672
[i915#7673]: https://gitlab.freedesktop.org/drm/intel/issues/7673
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7681]: https://gitlab.freedesktop.org/drm/intel/issues/7681
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12510 -> Patchwork_111964v1
CI-20190529: 20190529
CI_DRM_12510: e7a0d02714edf5ceac30b8da5ed7151d7dadbd40 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7094: 1763071e9d50c5e992257c9197cb26f166de6fae @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111964v1: e7a0d02714edf5ceac30b8da5ed7151d7dadbd40 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111964v1/index.html
[-- Attachment #2: Type: text/html, Size: 26382 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
2022-12-15 12:56 [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible Andrzej Hajda
` (2 preceding siblings ...)
2022-12-16 13:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-01-30 8:11 ` Andrzej Hajda
2023-01-30 12:55 ` Jani Nikula
2023-01-30 13:06 ` Jani Nikula
3 siblings, 2 replies; 9+ messages in thread
From: Andrzej Hajda @ 2023-01-30 8:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
Hi all,
Gently ping on merging this and all other intel_de_rmw patches.
All patches reviewed.
drm/i915/display/fdi: use intel_de_rmw if possible
drm/i915/display/vlv: fix pixel overlap register update
drm/i915/display/vlv: use intel_de_rmw if possible
drm/i915/display/dsi: use intel_de_rmw if possible
drm/i915/display/core: use intel_de_rmw if possible
drm/i915/display/power: use intel_de_rmw if possible
drm/i915/display/dpll: use intel_de_rmw if possible
drm/i915/display/phys: use intel_de_rmw if possible
drm/i915/display/pch: use intel_de_rmw if possible
drm/i915/display/hdmi: use intel_de_rmw if possible
drm/i915/display/panel: use intel_de_rmw if possible in panel related code
drm/i915/display/interfaces: use intel_de_rmw if possible
drm/i915/display/misc: use intel_de_rmw if possible
Regards
Andrzej
On 15.12.2022 13:56, Andrzej Hajda wrote:
> The helper makes the code more compact and readable.
>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++++++----------------
> 1 file changed, 44 insertions(+), 104 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 063f1da4f229cf..f62d9a9313498c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
> drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
>
> /* Train 2 */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_PATTERN_2;
> - intel_de_write(dev_priv, reg, temp);
> -
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_PATTERN_2;
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
> udelay(150);
>
> reg = FDI_RX_IIR(pipe);
> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
> udelay(150);
>
> for (i = 0; i < 4; i++) {
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> - temp |= snb_b_fdi_train_param[i];
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
> udelay(500);
>
> for (retry = 0; retry < 5; retry++) {
> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
> udelay(150);
>
> for (i = 0; i < 4; i++) {
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> - temp |= snb_b_fdi_train_param[i];
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
> udelay(500);
>
> for (retry = 0; retry < 5; retry++) {
> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
> }
>
> /* Train 2 */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> - temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
> - intel_de_write(dev_priv, reg, temp);
> -
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> - temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
> - intel_de_write(dev_priv, reg, temp);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE_IVB,
> + FDI_LINK_TRAIN_PATTERN_2_IVB);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
> + FDI_LINK_TRAIN_PATTERN_MASK_CPT,
> + FDI_LINK_TRAIN_PATTERN_2_CPT);
> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
> udelay(2); /* should be 1.5us */
>
> for (i = 0; i < 4; i++) {
> @@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> udelay(30);
>
> /* Unset FDI_RX_MISC pwrdn lanes */
> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>
> /* Wait for FDI auto training time */
> @@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
> intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
>
> - temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
> - temp &= ~DDI_BUF_CTL_ENABLE;
> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
> intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
>
> /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
> - temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
> - temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
> + intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
> + DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
> + DP_TP_CTL_LINK_TRAIN_PAT1);
> intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
>
> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>
> /* Reset FDI_RX_MISC pwrdn lanes */
> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> - temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
> }
>
> @@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> void hsw_fdi_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - u32 val;
>
> /*
> * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
> @@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
> * step 13 is the correct place for it. Step 18 is where it was
> * originally before the BUN.
> */
> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> - val &= ~FDI_RX_ENABLE;
> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> -
> - val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
> - val &= ~DDI_BUF_CTL_ENABLE;
> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
> -
> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> -
> intel_ddi_disable_clock(encoder);
> -
> - val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> - val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> - val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
> -
> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> - val &= ~FDI_PCDCLK;
> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> -
> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
> - val &= ~FDI_RX_PLL_ENABLE;
> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
> }
>
> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> @@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> udelay(200);
>
> /* Switch from Rawclk to PCDclk */
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
> -
> + intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
> intel_de_posting_read(dev_priv, reg);
> udelay(200);
>
> @@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum pipe pipe = crtc->pipe;
> - i915_reg_t reg;
> - u32 temp;
>
> /* Switch from PCDclk to Rawclk */
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
>
> /* Disable CPU FDI TX PLL */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
> -
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
> udelay(100);
>
> - reg = FDI_RX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
> -
> /* Wait for the clocks to turn off. */
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
> udelay(100);
> }
>
> @@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
> u32 temp;
>
> /* disable CPU FDI tx and PCH FDI rx */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
> - intel_de_posting_read(dev_priv, reg);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>
> reg = FDI_RX_CTL(pipe);
> temp = intel_de_read(dev_priv, reg);
> @@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
> FDI_RX_PHASE_SYNC_POINTER_OVR);
>
> /* still set train pattern 1 */
> - reg = FDI_TX_CTL(pipe);
> - temp = intel_de_read(dev_priv, reg);
> - temp &= ~FDI_LINK_TRAIN_NONE;
> - temp |= FDI_LINK_TRAIN_PATTERN_1;
> - intel_de_write(dev_priv, reg, temp);
> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
>
> reg = FDI_RX_CTL(pipe);
> temp = intel_de_read(dev_priv, reg);
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
2023-01-30 8:11 ` [Intel-gfx] [PATCH] " Andrzej Hajda
@ 2023-01-30 12:55 ` Jani Nikula
2023-01-30 13:06 ` Jani Nikula
1 sibling, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2023-01-30 12:55 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Rodrigo Vivi
On Mon, 30 Jan 2023, Andrzej Hajda <andrzej.hajda@intel.com> wrote:
> Hi all,
>
> Gently ping on merging this and all other intel_de_rmw patches.
Pushed this one to din, thanks for the patch.
BR,
Jani.
> All patches reviewed.
> drm/i915/display/fdi: use intel_de_rmw if possible
> drm/i915/display/vlv: fix pixel overlap register update
> drm/i915/display/vlv: use intel_de_rmw if possible
> drm/i915/display/dsi: use intel_de_rmw if possible
> drm/i915/display/core: use intel_de_rmw if possible
> drm/i915/display/power: use intel_de_rmw if possible
> drm/i915/display/dpll: use intel_de_rmw if possible
> drm/i915/display/phys: use intel_de_rmw if possible
> drm/i915/display/pch: use intel_de_rmw if possible
> drm/i915/display/hdmi: use intel_de_rmw if possible
> drm/i915/display/panel: use intel_de_rmw if possible in panel related code
> drm/i915/display/interfaces: use intel_de_rmw if possible
> drm/i915/display/misc: use intel_de_rmw if possible
>
> Regards
> Andrzej
>
> On 15.12.2022 13:56, Andrzej Hajda wrote:
>> The helper makes the code more compact and readable.
>>
>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++++++----------------
>> 1 file changed, 44 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
>> index 063f1da4f229cf..f62d9a9313498c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
>> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>> drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
>>
>> /* Train 2 */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(150);
>>
>> reg = FDI_RX_IIR(pipe);
>> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> - temp |= snb_b_fdi_train_param[i];
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> - temp |= snb_b_fdi_train_param[i];
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>> }
>>
>> /* Train 2 */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE_IVB;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE_IVB,
>> + FDI_LINK_TRAIN_PATTERN_2_IVB);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>> + FDI_LINK_TRAIN_PATTERN_MASK_CPT,
>> + FDI_LINK_TRAIN_PATTERN_2_CPT);
>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(2); /* should be 1.5us */
>>
>> for (i = 0; i < 4; i++) {
>> @@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>> udelay(30);
>>
>> /* Unset FDI_RX_MISC pwrdn lanes */
>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>
>> /* Wait for FDI auto training time */
>> @@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>> intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
>> intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>
>> - temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>> - temp &= ~DDI_BUF_CTL_ENABLE;
>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>> intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>
>> /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
>> - temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
>> - temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>> - temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
>> - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
>> + intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
>> + DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
>> + DP_TP_CTL_LINK_TRAIN_PAT1);
>> intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
>>
>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>>
>> /* Reset FDI_RX_MISC pwrdn lanes */
>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>> - temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> }
>>
>> @@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>> void hsw_fdi_disable(struct intel_encoder *encoder)
>> {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> - u32 val;
>>
>> /*
>> * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
>> @@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
>> * step 13 is the correct place for it. Step 18 is where it was
>> * originally before the BUN.
>> */
>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>> - val &= ~FDI_RX_ENABLE;
>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>> -
>> - val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>> - val &= ~DDI_BUF_CTL_ENABLE;
>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
>> -
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>> -
>> intel_ddi_disable_clock(encoder);
>> -
>> - val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> - val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>> - val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
>> -
>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>> - val &= ~FDI_PCDCLK;
>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>> -
>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>> - val &= ~FDI_RX_PLL_ENABLE;
>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
>> }
>>
>> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>> @@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>> udelay(200);
>>
>> /* Switch from Rawclk to PCDclk */
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
>> -
>> + intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
>> intel_de_posting_read(dev_priv, reg);
>> udelay(200);
>>
>> @@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
>> struct drm_device *dev = crtc->base.dev;
>> struct drm_i915_private *dev_priv = to_i915(dev);
>> enum pipe pipe = crtc->pipe;
>> - i915_reg_t reg;
>> - u32 temp;
>>
>> /* Switch from PCDclk to Rawclk */
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
>>
>> /* Disable CPU FDI TX PLL */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(100);
>>
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
>> -
>> /* Wait for the clocks to turn off. */
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(100);
>> }
>>
>> @@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>> u32 temp;
>>
>> /* disable CPU FDI tx and PCH FDI rx */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>
>> reg = FDI_RX_CTL(pipe);
>> temp = intel_de_read(dev_priv, reg);
>> @@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>> FDI_RX_PHASE_SYNC_POINTER_OVR);
>>
>> /* still set train pattern 1 */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE;
>> - temp |= FDI_LINK_TRAIN_PATTERN_1;
>> - intel_de_write(dev_priv, reg, temp);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
>>
>> reg = FDI_RX_CTL(pipe);
>> temp = intel_de_read(dev_priv, reg);
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
2023-01-30 8:11 ` [Intel-gfx] [PATCH] " Andrzej Hajda
2023-01-30 12:55 ` Jani Nikula
@ 2023-01-30 13:06 ` Jani Nikula
2023-02-06 9:28 ` Andrzej Hajda
1 sibling, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2023-01-30 13:06 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Rodrigo Vivi
On Mon, 30 Jan 2023, Andrzej Hajda <andrzej.hajda@intel.com> wrote:
> Hi all,
>
> Gently ping on merging this and all other intel_de_rmw patches.
> All patches reviewed.
> drm/i915/display/fdi: use intel_de_rmw if possible
> drm/i915/display/vlv: fix pixel overlap register update
> drm/i915/display/vlv: use intel_de_rmw if possible
> drm/i915/display/dsi: use intel_de_rmw if possible
Pushed the above, sorry for the delay.
The below are R-b by Rodrigo in [1], I'll let him deal with them.
Andrzej, looks like you now meet the criteria for commit access
[2]. Please check the documentation and apply for drm-intel commit
access, so you can start pushing your own patches.
Thanks,
Jani.
[1] https://patchwork.freedesktop.org/series/112438/
[2] https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html#drm-intel
> drm/i915/display/core: use intel_de_rmw if possible
> drm/i915/display/power: use intel_de_rmw if possible
> drm/i915/display/dpll: use intel_de_rmw if possible
> drm/i915/display/phys: use intel_de_rmw if possible
> drm/i915/display/pch: use intel_de_rmw if possible
> drm/i915/display/hdmi: use intel_de_rmw if possible
> drm/i915/display/panel: use intel_de_rmw if possible in panel related code
> drm/i915/display/interfaces: use intel_de_rmw if possible
> drm/i915/display/misc: use intel_de_rmw if possible
>
> Regards
> Andrzej
>
> On 15.12.2022 13:56, Andrzej Hajda wrote:
>> The helper makes the code more compact and readable.
>>
>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++++++----------------
>> 1 file changed, 44 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
>> index 063f1da4f229cf..f62d9a9313498c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
>> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>> drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
>>
>> /* Train 2 */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(150);
>>
>> reg = FDI_RX_IIR(pipe);
>> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> - temp |= snb_b_fdi_train_param[i];
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>> udelay(150);
>>
>> for (i = 0; i < 4; i++) {
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>> - temp |= snb_b_fdi_train_param[i];
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(500);
>>
>> for (retry = 0; retry < 5; retry++) {
>> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>> }
>>
>> /* Train 2 */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE_IVB;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>> - temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
>> - intel_de_write(dev_priv, reg, temp);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE_IVB,
>> + FDI_LINK_TRAIN_PATTERN_2_IVB);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>> + FDI_LINK_TRAIN_PATTERN_MASK_CPT,
>> + FDI_LINK_TRAIN_PATTERN_2_CPT);
>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(2); /* should be 1.5us */
>>
>> for (i = 0; i < 4; i++) {
>> @@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>> udelay(30);
>>
>> /* Unset FDI_RX_MISC pwrdn lanes */
>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>
>> /* Wait for FDI auto training time */
>> @@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>> intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
>> intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>
>> - temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>> - temp &= ~DDI_BUF_CTL_ENABLE;
>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>> intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>
>> /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
>> - temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
>> - temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>> - temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
>> - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
>> + intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
>> + DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
>> + DP_TP_CTL_LINK_TRAIN_PAT1);
>> intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
>>
>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>>
>> /* Reset FDI_RX_MISC pwrdn lanes */
>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>> - temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> }
>>
>> @@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>> void hsw_fdi_disable(struct intel_encoder *encoder)
>> {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> - u32 val;
>>
>> /*
>> * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
>> @@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
>> * step 13 is the correct place for it. Step 18 is where it was
>> * originally before the BUN.
>> */
>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>> - val &= ~FDI_RX_ENABLE;
>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>> -
>> - val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>> - val &= ~DDI_BUF_CTL_ENABLE;
>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
>> -
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>> -
>> intel_ddi_disable_clock(encoder);
>> -
>> - val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>> - val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>> - val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
>> -
>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>> - val &= ~FDI_PCDCLK;
>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>> -
>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>> - val &= ~FDI_RX_PLL_ENABLE;
>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
>> }
>>
>> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>> @@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>> udelay(200);
>>
>> /* Switch from Rawclk to PCDclk */
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
>> -
>> + intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
>> intel_de_posting_read(dev_priv, reg);
>> udelay(200);
>>
>> @@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
>> struct drm_device *dev = crtc->base.dev;
>> struct drm_i915_private *dev_priv = to_i915(dev);
>> enum pipe pipe = crtc->pipe;
>> - i915_reg_t reg;
>> - u32 temp;
>>
>> /* Switch from PCDclk to Rawclk */
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
>>
>> /* Disable CPU FDI TX PLL */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
>> -
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>> udelay(100);
>>
>> - reg = FDI_RX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
>> -
>> /* Wait for the clocks to turn off. */
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>> udelay(100);
>> }
>>
>> @@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>> u32 temp;
>>
>> /* disable CPU FDI tx and PCH FDI rx */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
>> - intel_de_posting_read(dev_priv, reg);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>
>> reg = FDI_RX_CTL(pipe);
>> temp = intel_de_read(dev_priv, reg);
>> @@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>> FDI_RX_PHASE_SYNC_POINTER_OVR);
>>
>> /* still set train pattern 1 */
>> - reg = FDI_TX_CTL(pipe);
>> - temp = intel_de_read(dev_priv, reg);
>> - temp &= ~FDI_LINK_TRAIN_NONE;
>> - temp |= FDI_LINK_TRAIN_PATTERN_1;
>> - intel_de_write(dev_priv, reg, temp);
>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
>>
>> reg = FDI_RX_CTL(pipe);
>> temp = intel_de_read(dev_priv, reg);
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
2023-01-30 13:06 ` Jani Nikula
@ 2023-02-06 9:28 ` Andrzej Hajda
2023-02-06 11:43 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Andrzej Hajda @ 2023-02-06 9:28 UTC (permalink / raw)
To: intel-gfx, Rodrigo Vivi; +Cc: Jani Nikula
Hi Rodrigo,
On 30.01.2023 14:06, Jani Nikula wrote:
> On Mon, 30 Jan 2023, Andrzej Hajda <andrzej.hajda@intel.com> wrote:
>> Hi all,
>>
>> Gently ping on merging this and all other intel_de_rmw patches.
>> All patches reviewed.
>> drm/i915/display/fdi: use intel_de_rmw if possible
>> drm/i915/display/vlv: fix pixel overlap register update
>> drm/i915/display/vlv: use intel_de_rmw if possible
>> drm/i915/display/dsi: use intel_de_rmw if possible
> Pushed the above, sorry for the delay.
>
> The below are R-b by Rodrigo in [1], I'll let him deal with them.
Could you push below patches, risk of merge conflicts raises :)
Hopefully I will have commit rights soon, but today is not the case, yet.
Regards
Andrzej
>
> Andrzej, looks like you now meet the criteria for commit access
> [2]. Please check the documentation and apply for drm-intel commit
> access, so you can start pushing your own patches.
>
>
> Thanks,
> Jani.
>
> [1] https://patchwork.freedesktop.org/series/112438/
> [2] https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html#drm-intel
>
>> drm/i915/display/core: use intel_de_rmw if possible
>> drm/i915/display/power: use intel_de_rmw if possible
>> drm/i915/display/dpll: use intel_de_rmw if possible
>> drm/i915/display/phys: use intel_de_rmw if possible
>> drm/i915/display/pch: use intel_de_rmw if possible
>> drm/i915/display/hdmi: use intel_de_rmw if possible
>> drm/i915/display/panel: use intel_de_rmw if possible in panel related code
>> drm/i915/display/interfaces: use intel_de_rmw if possible
>> drm/i915/display/misc: use intel_de_rmw if possible
>>
>> Regards
>> Andrzej
>>
>> On 15.12.2022 13:56, Andrzej Hajda wrote:
>>> The helper makes the code more compact and readable.
>>>
>>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++++++----------------
>>> 1 file changed, 44 insertions(+), 104 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
>>> index 063f1da4f229cf..f62d9a9313498c 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
>>> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>>> drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
>>>
>>> /* Train 2 */
>>> - reg = FDI_TX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - temp &= ~FDI_LINK_TRAIN_NONE;
>>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>>> - intel_de_write(dev_priv, reg, temp);
>>> -
>>> - reg = FDI_RX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - temp &= ~FDI_LINK_TRAIN_NONE;
>>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>>> - intel_de_write(dev_priv, reg, temp);
>>> -
>>> - intel_de_posting_read(dev_priv, reg);
>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>>> udelay(150);
>>>
>>> reg = FDI_RX_IIR(pipe);
>>> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>>> udelay(150);
>>>
>>> for (i = 0; i < 4; i++) {
>>> - reg = FDI_TX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>>> - temp |= snb_b_fdi_train_param[i];
>>> - intel_de_write(dev_priv, reg, temp);
>>> -
>>> - intel_de_posting_read(dev_priv, reg);
>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>> udelay(500);
>>>
>>> for (retry = 0; retry < 5; retry++) {
>>> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>>> udelay(150);
>>>
>>> for (i = 0; i < 4; i++) {
>>> - reg = FDI_TX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>>> - temp |= snb_b_fdi_train_param[i];
>>> - intel_de_write(dev_priv, reg, temp);
>>> -
>>> - intel_de_posting_read(dev_priv, reg);
>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>> udelay(500);
>>>
>>> for (retry = 0; retry < 5; retry++) {
>>> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>>> }
>>>
>>> /* Train 2 */
>>> - reg = FDI_TX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - temp &= ~FDI_LINK_TRAIN_NONE_IVB;
>>> - temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
>>> - intel_de_write(dev_priv, reg, temp);
>>> -
>>> - reg = FDI_RX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>>> - temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
>>> - intel_de_write(dev_priv, reg, temp);
>>> -
>>> - intel_de_posting_read(dev_priv, reg);
>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>> + FDI_LINK_TRAIN_NONE_IVB,
>>> + FDI_LINK_TRAIN_PATTERN_2_IVB);
>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>>> + FDI_LINK_TRAIN_PATTERN_MASK_CPT,
>>> + FDI_LINK_TRAIN_PATTERN_2_CPT);
>>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>>> udelay(2); /* should be 1.5us */
>>>
>>> for (i = 0; i < 4; i++) {
>>> @@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>>> udelay(30);
>>>
>>> /* Unset FDI_RX_MISC pwrdn lanes */
>>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
>>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>>
>>> /* Wait for FDI auto training time */
>>> @@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>>> intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
>>> intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>>
>>> - temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>> - temp &= ~DDI_BUF_CTL_ENABLE;
>>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
>>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>>> intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>>
>>> /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
>>> - temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
>>> - temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>>> - temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
>>> - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
>>> + intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
>>> + DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
>>> + DP_TP_CTL_LINK_TRAIN_PAT1);
>>> intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
>>>
>>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>>>
>>> /* Reset FDI_RX_MISC pwrdn lanes */
>>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>>> - temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>> }
>>>
>>> @@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>>> void hsw_fdi_disable(struct intel_encoder *encoder)
>>> {
>>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> - u32 val;
>>>
>>> /*
>>> * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
>>> @@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
>>> * step 13 is the correct place for it. Step 18 is where it was
>>> * originally before the BUN.
>>> */
>>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>> - val &= ~FDI_RX_ENABLE;
>>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>>> -
>>> - val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>> - val &= ~DDI_BUF_CTL_ENABLE;
>>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
>>> -
>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
>>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>>> -
>>> intel_ddi_disable_clock(encoder);
>>> -
>>> - val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>> - val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>>> - val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
>>> -
>>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>> - val &= ~FDI_PCDCLK;
>>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>>> -
>>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>> - val &= ~FDI_RX_PLL_ENABLE;
>>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
>>> }
>>>
>>> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>>> @@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>>> udelay(200);
>>>
>>> /* Switch from Rawclk to PCDclk */
>>> - temp = intel_de_read(dev_priv, reg);
>>> - intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
>>> -
>>> + intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
>>> intel_de_posting_read(dev_priv, reg);
>>> udelay(200);
>>>
>>> @@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
>>> struct drm_device *dev = crtc->base.dev;
>>> struct drm_i915_private *dev_priv = to_i915(dev);
>>> enum pipe pipe = crtc->pipe;
>>> - i915_reg_t reg;
>>> - u32 temp;
>>>
>>> /* Switch from PCDclk to Rawclk */
>>> - reg = FDI_RX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
>>>
>>> /* Disable CPU FDI TX PLL */
>>> - reg = FDI_TX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
>>> -
>>> - intel_de_posting_read(dev_priv, reg);
>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>> udelay(100);
>>>
>>> - reg = FDI_RX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
>>> -
>>> /* Wait for the clocks to turn off. */
>>> - intel_de_posting_read(dev_priv, reg);
>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
>>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>>> udelay(100);
>>> }
>>>
>>> @@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>>> u32 temp;
>>>
>>> /* disable CPU FDI tx and PCH FDI rx */
>>> - reg = FDI_TX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
>>> - intel_de_posting_read(dev_priv, reg);
>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>>
>>> reg = FDI_RX_CTL(pipe);
>>> temp = intel_de_read(dev_priv, reg);
>>> @@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>>> FDI_RX_PHASE_SYNC_POINTER_OVR);
>>>
>>> /* still set train pattern 1 */
>>> - reg = FDI_TX_CTL(pipe);
>>> - temp = intel_de_read(dev_priv, reg);
>>> - temp &= ~FDI_LINK_TRAIN_NONE;
>>> - temp |= FDI_LINK_TRAIN_PATTERN_1;
>>> - intel_de_write(dev_priv, reg, temp);
>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
>>>
>>> reg = FDI_RX_CTL(pipe);
>>> temp = intel_de_read(dev_priv, reg);
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible
2023-02-06 9:28 ` Andrzej Hajda
@ 2023-02-06 11:43 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2023-02-06 11:43 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx, Rodrigo Vivi
On Mon, 06 Feb 2023, Andrzej Hajda <andrzej.hajda@intel.com> wrote:
> Hi Rodrigo,
>
> On 30.01.2023 14:06, Jani Nikula wrote:
>> On Mon, 30 Jan 2023, Andrzej Hajda <andrzej.hajda@intel.com> wrote:
>>> Hi all,
>>>
>>> Gently ping on merging this and all other intel_de_rmw patches.
>>> All patches reviewed.
>>> drm/i915/display/fdi: use intel_de_rmw if possible
>>> drm/i915/display/vlv: fix pixel overlap register update
>>> drm/i915/display/vlv: use intel_de_rmw if possible
>>> drm/i915/display/dsi: use intel_de_rmw if possible
>> Pushed the above, sorry for the delay.
>>
>> The below are R-b by Rodrigo in [1], I'll let him deal with them.
>
> Could you push below patches, risk of merge conflicts raises :)
Full IGT wasn't run on the last version, I hit retest. Let's see.
BR,
Jani
> Hopefully I will have commit rights soon, but today is not the case, yet.
>
> Regards
> Andrzej
>
>>
>> Andrzej, looks like you now meet the criteria for commit access
>> [2]. Please check the documentation and apply for drm-intel commit
>> access, so you can start pushing your own patches.
>>
>>
>> Thanks,
>> Jani.
>>
>> [1] https://patchwork.freedesktop.org/series/112438/
>> [2] https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html#drm-intel
>>
>>> drm/i915/display/core: use intel_de_rmw if possible
>>> drm/i915/display/power: use intel_de_rmw if possible
>>> drm/i915/display/dpll: use intel_de_rmw if possible
>>> drm/i915/display/phys: use intel_de_rmw if possible
>>> drm/i915/display/pch: use intel_de_rmw if possible
>>> drm/i915/display/hdmi: use intel_de_rmw if possible
>>> drm/i915/display/panel: use intel_de_rmw if possible in panel related code
>>> drm/i915/display/interfaces: use intel_de_rmw if possible
>>> drm/i915/display/misc: use intel_de_rmw if possible
>>>
>>> Regards
>>> Andrzej
>>>
>>> On 15.12.2022 13:56, Andrzej Hajda wrote:
>>>> The helper makes the code more compact and readable.
>>>>
>>>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_fdi.c | 148 +++++++----------------
>>>> 1 file changed, 44 insertions(+), 104 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
>>>> index 063f1da4f229cf..f62d9a9313498c 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
>>>> @@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>>>> drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
>>>>
>>>> /* Train 2 */
>>>> - reg = FDI_TX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - temp &= ~FDI_LINK_TRAIN_NONE;
>>>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>>>> - intel_de_write(dev_priv, reg, temp);
>>>> -
>>>> - reg = FDI_RX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - temp &= ~FDI_LINK_TRAIN_NONE;
>>>> - temp |= FDI_LINK_TRAIN_PATTERN_2;
>>>> - intel_de_write(dev_priv, reg, temp);
>>>> -
>>>> - intel_de_posting_read(dev_priv, reg);
>>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>>>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
>>>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>>>> udelay(150);
>>>>
>>>> reg = FDI_RX_IIR(pipe);
>>>> @@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>>>> udelay(150);
>>>>
>>>> for (i = 0; i < 4; i++) {
>>>> - reg = FDI_TX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>>>> - temp |= snb_b_fdi_train_param[i];
>>>> - intel_de_write(dev_priv, reg, temp);
>>>> -
>>>> - intel_de_posting_read(dev_priv, reg);
>>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>>> udelay(500);
>>>>
>>>> for (retry = 0; retry < 5; retry++) {
>>>> @@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>>>> udelay(150);
>>>>
>>>> for (i = 0; i < 4; i++) {
>>>> - reg = FDI_TX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>>>> - temp |= snb_b_fdi_train_param[i];
>>>> - intel_de_write(dev_priv, reg, temp);
>>>> -
>>>> - intel_de_posting_read(dev_priv, reg);
>>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>>> + FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
>>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>>> udelay(500);
>>>>
>>>> for (retry = 0; retry < 5; retry++) {
>>>> @@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>>>> }
>>>>
>>>> /* Train 2 */
>>>> - reg = FDI_TX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - temp &= ~FDI_LINK_TRAIN_NONE_IVB;
>>>> - temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
>>>> - intel_de_write(dev_priv, reg, temp);
>>>> -
>>>> - reg = FDI_RX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>>>> - temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
>>>> - intel_de_write(dev_priv, reg, temp);
>>>> -
>>>> - intel_de_posting_read(dev_priv, reg);
>>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>>> + FDI_LINK_TRAIN_NONE_IVB,
>>>> + FDI_LINK_TRAIN_PATTERN_2_IVB);
>>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
>>>> + FDI_LINK_TRAIN_PATTERN_MASK_CPT,
>>>> + FDI_LINK_TRAIN_PATTERN_2_CPT);
>>>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>>>> udelay(2); /* should be 1.5us */
>>>>
>>>> for (i = 0; i < 4; i++) {
>>>> @@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>>>> udelay(30);
>>>>
>>>> /* Unset FDI_RX_MISC pwrdn lanes */
>>>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>>>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>>>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>>>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
>>>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>>>
>>>> /* Wait for FDI auto training time */
>>>> @@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>>>> intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
>>>> intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>>>
>>>> - temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>>> - temp &= ~DDI_BUF_CTL_ENABLE;
>>>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
>>>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>>>> intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>>>
>>>> /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
>>>> - temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
>>>> - temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>>>> - temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
>>>> - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
>>>> + intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
>>>> + DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
>>>> + DP_TP_CTL_LINK_TRAIN_PAT1);
>>>> intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
>>>>
>>>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>>>>
>>>> /* Reset FDI_RX_MISC pwrdn lanes */
>>>> - temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>>> - temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>>>> - temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>>>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
>>>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>>>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>>>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>>>> intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>>> }
>>>>
>>>> @@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>>>> void hsw_fdi_disable(struct intel_encoder *encoder)
>>>> {
>>>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>>> - u32 val;
>>>>
>>>> /*
>>>> * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
>>>> @@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
>>>> * step 13 is the correct place for it. Step 18 is where it was
>>>> * originally before the BUN.
>>>> */
>>>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>>> - val &= ~FDI_RX_ENABLE;
>>>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>>>> -
>>>> - val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
>>>> - val &= ~DDI_BUF_CTL_ENABLE;
>>>> - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
>>>> -
>>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
>>>> + intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
>>>> intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>>>> -
>>>> intel_ddi_disable_clock(encoder);
>>>> -
>>>> - val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
>>>> - val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>>>> - val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
>>>> - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
>>>> -
>>>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>>> - val &= ~FDI_PCDCLK;
>>>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>>>> -
>>>> - val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
>>>> - val &= ~FDI_RX_PLL_ENABLE;
>>>> - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>>>> + intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
>>>> + FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
>>>> + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
>>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
>>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
>>>> }
>>>>
>>>> void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>>>> @@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>>>> udelay(200);
>>>>
>>>> /* Switch from Rawclk to PCDclk */
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
>>>> -
>>>> + intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
>>>> intel_de_posting_read(dev_priv, reg);
>>>> udelay(200);
>>>>
>>>> @@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
>>>> struct drm_device *dev = crtc->base.dev;
>>>> struct drm_i915_private *dev_priv = to_i915(dev);
>>>> enum pipe pipe = crtc->pipe;
>>>> - i915_reg_t reg;
>>>> - u32 temp;
>>>>
>>>> /* Switch from PCDclk to Rawclk */
>>>> - reg = FDI_RX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
>>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
>>>>
>>>> /* Disable CPU FDI TX PLL */
>>>> - reg = FDI_TX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
>>>> -
>>>> - intel_de_posting_read(dev_priv, reg);
>>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
>>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>>> udelay(100);
>>>>
>>>> - reg = FDI_RX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
>>>> -
>>>> /* Wait for the clocks to turn off. */
>>>> - intel_de_posting_read(dev_priv, reg);
>>>> + intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
>>>> + intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
>>>> udelay(100);
>>>> }
>>>>
>>>> @@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>>>> u32 temp;
>>>>
>>>> /* disable CPU FDI tx and PCH FDI rx */
>>>> - reg = FDI_TX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
>>>> - intel_de_posting_read(dev_priv, reg);
>>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
>>>> + intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
>>>>
>>>> reg = FDI_RX_CTL(pipe);
>>>> temp = intel_de_read(dev_priv, reg);
>>>> @@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>>>> FDI_RX_PHASE_SYNC_POINTER_OVR);
>>>>
>>>> /* still set train pattern 1 */
>>>> - reg = FDI_TX_CTL(pipe);
>>>> - temp = intel_de_read(dev_priv, reg);
>>>> - temp &= ~FDI_LINK_TRAIN_NONE;
>>>> - temp |= FDI_LINK_TRAIN_PATTERN_1;
>>>> - intel_de_write(dev_priv, reg, temp);
>>>> + intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
>>>> + FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
>>>>
>>>> reg = FDI_RX_CTL(pipe);
>>>> temp = intel_de_read(dev_priv, reg);
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-02-06 11:43 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-15 12:56 [Intel-gfx] [PATCH] drm/i915/display/fdi: use intel_de_rmw if possible Andrzej Hajda
2022-12-15 13:10 ` Jani Nikula
2022-12-15 15:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-12-16 13:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-30 8:11 ` [Intel-gfx] [PATCH] " Andrzej Hajda
2023-01-30 12:55 ` Jani Nikula
2023-01-30 13:06 ` Jani Nikula
2023-02-06 9:28 ` Andrzej Hajda
2023-02-06 11:43 ` Jani Nikula
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