* [PULL 0/2] target/alpha update
@ 2021-10-13 17:37 Richard Henderson
2021-10-13 17:37 ` [PULL 1/2] target/alpha: Reorg fp memory operations Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Richard Henderson @ 2021-10-13 17:37 UTC (permalink / raw)
To: qemu-devel
The following changes since commit ee26ce674a93c824713542cec3b6a9ca85459165:
Merge remote-tracking branch 'remotes/jsnow/tags/python-pull-request' into staging (2021-10-12 16:08:33 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-axp-20211013
for you to fetch changes up to 5ffcb33426aaa2906daea2eee7a5195662a6580f:
target/alpha: Reorg integer memory operations (2021-10-13 09:18:23 -0700)
----------------------------------------------------------------
Cleanup alpha memory ops prior to prctl PR_SET_UNALIGN
----------------------------------------------------------------
Richard Henderson (2):
target/alpha: Reorg fp memory operations
target/alpha: Reorg integer memory operations
target/alpha/translate.c | 173 ++++++++++++++++++++++++-----------------------
1 file changed, 90 insertions(+), 83 deletions(-)
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PULL 1/2] target/alpha: Reorg fp memory operations
2021-10-13 17:37 [PULL 0/2] target/alpha update Richard Henderson
@ 2021-10-13 17:37 ` Richard Henderson
2021-10-13 17:37 ` [PULL 2/2] target/alpha: Reorg integer " Richard Henderson
2021-10-13 18:42 ` [PULL 0/2] target/alpha update Richard Henderson
2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2021-10-13 17:37 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Pass in the context to each mini-helper, instead of an
incorrectly named "flags". Separate gen_load_fp and
gen_store_fp, away from the integer helpers.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/translate.c | 83 +++++++++++++++++++++++++++-------------
1 file changed, 57 insertions(+), 26 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index b034206688..bfdd485508 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -267,30 +267,47 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
return gen_excp(ctx, EXCP_OPCDEC, 0);
}
-static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
+static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
- gen_helper_memory_to_f(t0, tmp32);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ gen_helper_memory_to_f(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
-static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
+static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv tmp = tcg_temp_new();
- tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ);
- gen_helper_memory_to_g(t0, tmp);
+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
+ gen_helper_memory_to_g(dest, tmp);
tcg_temp_free(tmp);
}
-static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
+static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
- gen_helper_memory_to_s(t0, tmp32);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ gen_helper_memory_to_s(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
+static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
+{
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
+}
+
+static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
+ void (*func)(DisasContext *, TCGv, TCGv))
+{
+ /* Loads to $f31 are prefetches, which we can treat as nops. */
+ if (likely(ra != 31)) {
+ TCGv addr = tcg_temp_new();
+ tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
+ func(ctx, cpu_fir[ra], addr);
+ tcg_temp_free(addr);
+ }
+}
+
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
@@ -338,30 +355,44 @@ static inline void gen_load_mem(DisasContext *ctx,
tcg_temp_free(tmp);
}
-static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
+static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- gen_helper_f_to_memory(tmp32, t0);
- tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
+ gen_helper_f_to_memory(tmp32, addr);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
tcg_temp_free_i32(tmp32);
}
-static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
+static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv tmp = tcg_temp_new();
- gen_helper_g_to_memory(tmp, t0);
- tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ);
+ gen_helper_g_to_memory(tmp, src);
+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
tcg_temp_free(tmp);
}
-static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
+static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- gen_helper_s_to_memory(tmp32, t0);
- tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
+ gen_helper_s_to_memory(tmp32, src);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
tcg_temp_free_i32(tmp32);
}
+static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
+{
+ tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
+}
+
+static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
+ void (*func)(DisasContext *, TCGv, TCGv))
+{
+ TCGv addr = tcg_temp_new();
+ tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
+ func(ctx, load_fpr(ctx, ra), addr);
+ tcg_temp_free(addr);
+}
+
static inline void gen_store_mem(DisasContext *ctx,
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
int flags),
@@ -2776,42 +2807,42 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x20:
/* LDF */
REQUIRE_FEN;
- gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_ldf);
break;
case 0x21:
/* LDG */
REQUIRE_FEN;
- gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_ldg);
break;
case 0x22:
/* LDS */
REQUIRE_FEN;
- gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_lds);
break;
case 0x23:
/* LDT */
REQUIRE_FEN;
- gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_ldt);
break;
case 0x24:
/* STF */
REQUIRE_FEN;
- gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_stf);
break;
case 0x25:
/* STG */
REQUIRE_FEN;
- gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_stg);
break;
case 0x26:
/* STS */
REQUIRE_FEN;
- gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_sts);
break;
case 0x27:
/* STT */
REQUIRE_FEN;
- gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_stt);
break;
case 0x28:
/* LDL */
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PULL 2/2] target/alpha: Reorg integer memory operations
2021-10-13 17:37 [PULL 0/2] target/alpha update Richard Henderson
2021-10-13 17:37 ` [PULL 1/2] target/alpha: Reorg fp memory operations Richard Henderson
@ 2021-10-13 17:37 ` Richard Henderson
2021-10-13 18:42 ` [PULL 0/2] target/alpha update Richard Henderson
2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2021-10-13 17:37 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Pass in the MemOp instead of a callback.
Drop the fp argument; add a locked argument.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/translate.c | 104 +++++++++++++++------------------------
1 file changed, 40 insertions(+), 64 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index bfdd485508..0eee3a1bcc 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -308,27 +308,10 @@ static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
}
}
-static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
+static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
+ MemOp op, bool clear, bool locked)
{
- tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
- tcg_gen_mov_i64(cpu_lock_addr, t1);
- tcg_gen_mov_i64(cpu_lock_value, t0);
-}
-
-static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
-{
- tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ);
- tcg_gen_mov_i64(cpu_lock_addr, t1);
- tcg_gen_mov_i64(cpu_lock_value, t0);
-}
-
-static inline void gen_load_mem(DisasContext *ctx,
- void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
- int flags),
- int ra, int rb, int32_t disp16, bool fp,
- bool clear)
-{
- TCGv tmp, addr, va;
+ TCGv addr, dest;
/* LDQ_U with ra $31 is UNOP. Other various loads are forms of
prefetches, which we can treat as nops. No worries about
@@ -337,22 +320,20 @@ static inline void gen_load_mem(DisasContext *ctx,
return;
}
- tmp = tcg_temp_new();
- addr = load_gpr(ctx, rb);
-
- if (disp16) {
- tcg_gen_addi_i64(tmp, addr, disp16);
- addr = tmp;
- }
+ addr = tcg_temp_new();
+ tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
if (clear) {
- tcg_gen_andi_i64(tmp, addr, ~0x7);
- addr = tmp;
+ tcg_gen_andi_i64(addr, addr, ~0x7);
}
- va = (fp ? cpu_fir[ra] : ctx->ir[ra]);
- tcg_gen_qemu_load(va, addr, ctx->mem_idx);
+ dest = ctx->ir[ra];
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, op);
- tcg_temp_free(tmp);
+ if (locked) {
+ tcg_gen_mov_i64(cpu_lock_addr, addr);
+ tcg_gen_mov_i64(cpu_lock_value, dest);
+ }
+ tcg_temp_free(addr);
}
static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
@@ -393,30 +374,21 @@ static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
tcg_temp_free(addr);
}
-static inline void gen_store_mem(DisasContext *ctx,
- void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
- int flags),
- int ra, int rb, int32_t disp16, bool fp,
- bool clear)
+static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
+ MemOp op, bool clear)
{
- TCGv tmp, addr, va;
+ TCGv addr, src;
- tmp = tcg_temp_new();
- addr = load_gpr(ctx, rb);
-
- if (disp16) {
- tcg_gen_addi_i64(tmp, addr, disp16);
- addr = tmp;
- }
+ addr = tcg_temp_new();
+ tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
if (clear) {
- tcg_gen_andi_i64(tmp, addr, ~0x7);
- addr = tmp;
+ tcg_gen_andi_i64(addr, addr, ~0x7);
}
- va = (fp ? load_fpr(ctx, ra) : load_gpr(ctx, ra));
- tcg_gen_qemu_store(va, addr, ctx->mem_idx);
+ src = load_gpr(ctx, ra);
+ tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, op);
- tcg_temp_free(tmp);
+ tcg_temp_free(addr);
}
static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
@@ -1511,30 +1483,30 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x0A:
/* LDBU */
REQUIRE_AMASK(BWX);
- gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
+ gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0);
break;
case 0x0B:
/* LDQ_U */
- gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
+ gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 1, 0);
break;
case 0x0C:
/* LDWU */
REQUIRE_AMASK(BWX);
- gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
+ gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0);
break;
case 0x0D:
/* STW */
REQUIRE_AMASK(BWX);
- gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
+ gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0);
break;
case 0x0E:
/* STB */
REQUIRE_AMASK(BWX);
- gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);
+ gen_store_int(ctx, ra, rb, disp16, MO_UB, 0);
break;
case 0x0F:
/* STQ_U */
- gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1);
+ gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 1);
break;
case 0x10:
@@ -2489,11 +2461,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
- gen_qemu_ldl_l(va, addr, MMU_PHYS_IDX);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
+ tcg_gen_mov_i64(cpu_lock_addr, addr);
+ tcg_gen_mov_i64(cpu_lock_value, va);
break;
case 0x3:
/* Quadword physical access with lock (hw_ldq_l/p) */
- gen_qemu_ldq_l(va, addr, MMU_PHYS_IDX);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEQ);
+ tcg_gen_mov_i64(cpu_lock_addr, addr);
+ tcg_gen_mov_i64(cpu_lock_value, va);
break;
case 0x4:
/* Longword virtual PTE fetch (hw_ldl/v) */
@@ -2846,27 +2822,27 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x28:
/* LDL */
- gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);
+ gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0);
break;
case 0x29:
/* LDQ */
- gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);
+ gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 0);
break;
case 0x2A:
/* LDL_L */
- gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);
+ gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1);
break;
case 0x2B:
/* LDQ_L */
- gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);
+ gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 1);
break;
case 0x2C:
/* STL */
- gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0);
+ gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0);
break;
case 0x2D:
/* STQ */
- gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0);
+ gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 0);
break;
case 0x2E:
/* STL_C */
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PULL 0/2] target/alpha update
2021-10-13 17:37 [PULL 0/2] target/alpha update Richard Henderson
2021-10-13 17:37 ` [PULL 1/2] target/alpha: Reorg fp memory operations Richard Henderson
2021-10-13 17:37 ` [PULL 2/2] target/alpha: Reorg integer " Richard Henderson
@ 2021-10-13 18:42 ` Richard Henderson
2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2021-10-13 18:42 UTC (permalink / raw)
To: qemu-devel
On 10/13/21 10:37 AM, Richard Henderson wrote:
> The following changes since commit ee26ce674a93c824713542cec3b6a9ca85459165:
>
> Merge remote-tracking branch 'remotes/jsnow/tags/python-pull-request' into staging (2021-10-12 16:08:33 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-axp-20211013
>
> for you to fetch changes up to 5ffcb33426aaa2906daea2eee7a5195662a6580f:
>
> target/alpha: Reorg integer memory operations (2021-10-13 09:18:23 -0700)
>
> ----------------------------------------------------------------
> Cleanup alpha memory ops prior to prctl PR_SET_UNALIGN
>
> ----------------------------------------------------------------
> Richard Henderson (2):
> target/alpha: Reorg fp memory operations
> target/alpha: Reorg integer memory operations
>
> target/alpha/translate.c | 173 ++++++++++++++++++++++++-----------------------
> 1 file changed, 90 insertions(+), 83 deletions(-)
Applied, thanks.
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-10-13 18:44 UTC | newest]
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2021-10-13 17:37 [PULL 0/2] target/alpha update Richard Henderson
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2021-10-13 17:37 ` [PULL 2/2] target/alpha: Reorg integer " Richard Henderson
2021-10-13 18:42 ` [PULL 0/2] target/alpha update Richard Henderson
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