From: Christophe Leroy <christophe.leroy@csgroup.eu> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, npiggin@gmail.com, msuchanek@suse.de Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v4 03/23] powerpc/32: On syscall entry, enable instruction translation at the same time as data Date: Mon, 25 Jan 2021 14:48:15 +0000 (UTC) [thread overview] Message-ID: <2dc1a491c32be486d96a0ed6f8979025c17bbb23.1611585031.git.christophe.leroy@csgroup.eu> (raw) In-Reply-To: <cover.1611585031.git.christophe.leroy@csgroup.eu> On 40x and 8xx, kernel text is pinned. On book3s/32, kernel text is mapped by BATs. Enable instruction translation at the same time as data translation, it makes things simpler. MSR_RI can also be set at the same time because srr0/srr1 are already saved and r1 is set properly. On booke, translation is always on, so at the end all PPC32 have translation on early. This reduces null_syscall benchmark by 13 cycles on 8xx (296 ==> 283 cycles). Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> --- arch/powerpc/kernel/head_32.h | 26 +++++++++----------------- arch/powerpc/kernel/head_booke.h | 7 ++----- 2 files changed, 11 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h index fdc07beab844..4029c51dce5d 100644 --- a/arch/powerpc/kernel/head_32.h +++ b/arch/powerpc/kernel/head_32.h @@ -125,9 +125,13 @@ lwz r1,TASK_STACK-THREAD(r12) beq- 99f addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE - LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR | MSR_RI)) /* can take DTLB miss */ - mtmsr r10 - isync + LOAD_REG_IMMEDIATE(r10, MSR_KERNEL) /* can take exceptions */ + mtspr SPRN_SRR1, r10 + lis r10, 1f@h + ori r10, r10, 1f@l + mtspr SPRN_SRR0, r10 + rfi +1: tovirt(r12, r12) stw r11,GPR1(r1) stw r11,0(r1) @@ -141,9 +145,6 @@ stw r10,_CCR(r11) /* save registers */ #ifdef CONFIG_40x rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ -#else - LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~MSR_IR) /* can take exceptions */ - mtmsr r10 /* (except for mach check in rtas) */ #endif lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ stw r2,GPR2(r11) @@ -180,8 +181,6 @@ #endif 3: - lis r11, transfer_to_syscall@h - ori r11, r11, transfer_to_syscall@l #ifdef CONFIG_TRACE_IRQFLAGS /* * If MSR is changing we need to keep interrupts disabled at this point @@ -193,15 +192,8 @@ #else LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE) #endif -#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) - mtspr SPRN_NRI, r0 -#endif - mtspr SPRN_SRR1,r10 - mtspr SPRN_SRR0,r11 - rfi /* jump to handler, enable MMU */ -#ifdef CONFIG_40x - b . /* Prevent prefetch past rfi */ -#endif + mtmsr r10 + b transfer_to_syscall /* jump to handler */ 99: b ret_from_kernel_syscall .endm diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 706cd9368992..b3c502c503a0 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -157,8 +157,6 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) stw r12,4(r11) 3: - lis r11, transfer_to_syscall@h - ori r11, r11, transfer_to_syscall@l #ifdef CONFIG_TRACE_IRQFLAGS /* * If MSR is changing we need to keep interrupts disabled at this point @@ -172,9 +170,8 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) lis r10, (MSR_KERNEL | MSR_EE)@h ori r10, r10, (MSR_KERNEL | MSR_EE)@l #endif - mtspr SPRN_SRR1,r10 - mtspr SPRN_SRR0,r11 - rfi /* jump to handler, enable MMU */ + mtmsr r10 + b transfer_to_syscall /* jump to handler */ 99: b ret_from_kernel_syscall .endm -- 2.25.0
WARNING: multiple messages have this Message-ID (diff)
From: Christophe Leroy <christophe.leroy@csgroup.eu> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, npiggin@gmail.com, msuchanek@suse.de Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/23] powerpc/32: On syscall entry, enable instruction translation at the same time as data Date: Mon, 25 Jan 2021 14:48:15 +0000 (UTC) [thread overview] Message-ID: <2dc1a491c32be486d96a0ed6f8979025c17bbb23.1611585031.git.christophe.leroy@csgroup.eu> (raw) In-Reply-To: <cover.1611585031.git.christophe.leroy@csgroup.eu> On 40x and 8xx, kernel text is pinned. On book3s/32, kernel text is mapped by BATs. Enable instruction translation at the same time as data translation, it makes things simpler. MSR_RI can also be set at the same time because srr0/srr1 are already saved and r1 is set properly. On booke, translation is always on, so at the end all PPC32 have translation on early. This reduces null_syscall benchmark by 13 cycles on 8xx (296 ==> 283 cycles). Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> --- arch/powerpc/kernel/head_32.h | 26 +++++++++----------------- arch/powerpc/kernel/head_booke.h | 7 ++----- 2 files changed, 11 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h index fdc07beab844..4029c51dce5d 100644 --- a/arch/powerpc/kernel/head_32.h +++ b/arch/powerpc/kernel/head_32.h @@ -125,9 +125,13 @@ lwz r1,TASK_STACK-THREAD(r12) beq- 99f addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE - LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR | MSR_RI)) /* can take DTLB miss */ - mtmsr r10 - isync + LOAD_REG_IMMEDIATE(r10, MSR_KERNEL) /* can take exceptions */ + mtspr SPRN_SRR1, r10 + lis r10, 1f@h + ori r10, r10, 1f@l + mtspr SPRN_SRR0, r10 + rfi +1: tovirt(r12, r12) stw r11,GPR1(r1) stw r11,0(r1) @@ -141,9 +145,6 @@ stw r10,_CCR(r11) /* save registers */ #ifdef CONFIG_40x rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ -#else - LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~MSR_IR) /* can take exceptions */ - mtmsr r10 /* (except for mach check in rtas) */ #endif lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ stw r2,GPR2(r11) @@ -180,8 +181,6 @@ #endif 3: - lis r11, transfer_to_syscall@h - ori r11, r11, transfer_to_syscall@l #ifdef CONFIG_TRACE_IRQFLAGS /* * If MSR is changing we need to keep interrupts disabled at this point @@ -193,15 +192,8 @@ #else LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE) #endif -#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) - mtspr SPRN_NRI, r0 -#endif - mtspr SPRN_SRR1,r10 - mtspr SPRN_SRR0,r11 - rfi /* jump to handler, enable MMU */ -#ifdef CONFIG_40x - b . /* Prevent prefetch past rfi */ -#endif + mtmsr r10 + b transfer_to_syscall /* jump to handler */ 99: b ret_from_kernel_syscall .endm diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 706cd9368992..b3c502c503a0 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -157,8 +157,6 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) stw r12,4(r11) 3: - lis r11, transfer_to_syscall@h - ori r11, r11, transfer_to_syscall@l #ifdef CONFIG_TRACE_IRQFLAGS /* * If MSR is changing we need to keep interrupts disabled at this point @@ -172,9 +170,8 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) lis r10, (MSR_KERNEL | MSR_EE)@h ori r10, r10, (MSR_KERNEL | MSR_EE)@l #endif - mtspr SPRN_SRR1,r10 - mtspr SPRN_SRR0,r11 - rfi /* jump to handler, enable MMU */ + mtmsr r10 + b transfer_to_syscall /* jump to handler */ 99: b ret_from_kernel_syscall .endm -- 2.25.0
next prev parent reply other threads:[~2021-01-26 6:44 UTC|newest] Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-25 14:48 [PATCH v4 00/23] powerpc/32: Implement C syscall entry/exit Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 01/23] powerpc/32s: Add missing call to kuep_lock on syscall entry Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 02/23] powerpc/32: Always enable data translation " Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy [this message] 2021-01-25 14:48 ` [PATCH v4 03/23] powerpc/32: On syscall entry, enable instruction translation at the same time as data Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 04/23] powerpc/32: Reorder instructions to avoid using CTR in syscall entry Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 05/23] powerpc/64s: Make kuap_check_amr() and kuap_get_and_check_amr() generic Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 06/23] powerpc/32s: Create C version of kuap_user/kernel_restore() and friends Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 07/23] powerpc/8xx: " Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 08/23] powerpc/irq: Add helper to set regs->softe Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 09/23] powerpc/irq: Rework helpers that manipulate MSR[EE/RI] Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 10/23] powerpc/irq: Add stub irq_soft_mask_return() for PPC32 Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 11/23] powerpc/syscall: Rename syscall_64.c into syscall.c Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-26 10:21 ` Nicholas Piggin 2021-01-26 10:21 ` Nicholas Piggin 2021-01-26 10:28 ` David Laight 2021-01-27 23:50 ` Nicholas Piggin 2021-01-27 23:50 ` Nicholas Piggin 2021-02-02 6:15 ` Christophe Leroy 2021-02-02 6:15 ` Christophe Leroy 2021-02-02 6:38 ` Nicholas Piggin 2021-02-02 6:38 ` Nicholas Piggin 2021-02-02 6:58 ` Christophe Leroy 2021-02-02 6:58 ` Christophe Leroy 2021-02-02 20:10 ` Segher Boessenkool 2021-02-02 20:10 ` Segher Boessenkool 2021-02-08 17:47 ` Christophe Leroy 2021-02-08 17:47 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 12/23] powerpc/syscall: Make syscall.c buildable on PPC32 Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 13/23] powerpc/syscall: Use is_compat_task() Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 14/23] powerpc/syscall: Save r3 in regs->orig_r3 Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-26 10:18 ` Nicholas Piggin 2021-01-26 10:18 ` Nicholas Piggin 2021-02-08 17:47 ` Christophe Leroy 2021-02-08 17:47 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 15/23] powerpc/syscall: Change condition to check MSR_RI Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 16/23] powerpc/32: Always save non volatile GPRs at syscall entry Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 17/23] powerpc/syscall: implement system call entry/exit logic in C for PPC32 Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 18/23] powerpc/32: Remove verification of MSR_PR on syscall in the ASM entry Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 19/23] powerpc/syscall: Avoid stack frame in likely part of system_call_exception() Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-26 10:14 ` Nicholas Piggin 2021-01-26 10:14 ` Nicholas Piggin 2021-01-25 14:48 ` [PATCH v4 20/23] powerpc/syscall: Do not check unsupported scv vector on PPC32 Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-26 10:16 ` Nicholas Piggin 2021-01-26 10:16 ` Nicholas Piggin 2021-02-08 17:45 ` Christophe Leroy 2021-02-08 17:45 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 21/23] powerpc/syscall: Remove FULL_REGS verification in system_call_exception Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 22/23] powerpc/syscall: Optimise checks in beginning of system_call_exception() Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy 2021-01-25 14:48 ` [PATCH v4 23/23] powerpc/syscall: Avoid storing 'current' in another pointer Christophe Leroy 2021-01-25 14:48 ` Christophe Leroy
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