From: Alistair Francis <Alistair.Francis@wdc.com> To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, "alistair23@gmail.com" <alistair23@gmail.com>, "richard.henderson@linaro.org" <richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 17/23] riscv: tcg-target: Add direct load and store instructions Date: Wed, 19 Dec 2018 19:19:20 +0000 [thread overview] Message-ID: <2e047a95c39c007c66cda024c095e29b0ac4c43e.1545246859.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target.inc.c | 158 +++++++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 7216bad086..154315787c 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -1151,3 +1151,161 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_goto(s, l->raddr); } #endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, TCGMemOp opc, bool is_64) +{ + const TCGMemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_UB: + tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + break; + case MO_SB: + tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + break; + case MO_UW: + tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + break; + case MO_SW: + tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + break; + case MO_UL: + if (TCG_TARGET_REG_BITS == 64 && is_64) { + tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + break; + } + /* FALLTHRU */ + case MO_SL: + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + break; + case MO_Q: + /* Prefer to load from offset 0 first, but allow for overlap. */ + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); + } else if (lo != base) { + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + } else { + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + TCGMemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); +#endif +} + +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, TCGMemOp opc) +{ + const TCGMemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_8: + tcg_out_opc_store(s, OPC_SB, base, lo, 0); + break; + case MO_16: + tcg_out_opc_store(s, OPC_SH, base, lo, 0); + break; + case MO_32: + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_store(s, OPC_SD, base, lo, 0); + } else { + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + tcg_out_opc_store(s, OPC_SW, base, hi, 4); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + TCGMemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + add_qemu_ldst_label(s, 0, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); +#endif +} -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <Alistair.Francis@wdc.com> To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, "alistair23@gmail.com" <alistair23@gmail.com>, "richard.henderson@linaro.org" <richard.henderson@linaro.org> Subject: [Qemu-riscv] [PATCH v2 17/23] riscv: tcg-target: Add direct load and store instructions Date: Wed, 19 Dec 2018 19:19:20 +0000 [thread overview] Message-ID: <2e047a95c39c007c66cda024c095e29b0ac4c43e.1545246859.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target.inc.c | 158 +++++++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 7216bad086..154315787c 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -1151,3 +1151,161 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_goto(s, l->raddr); } #endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, TCGMemOp opc, bool is_64) +{ + const TCGMemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_UB: + tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + break; + case MO_SB: + tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + break; + case MO_UW: + tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + break; + case MO_SW: + tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + break; + case MO_UL: + if (TCG_TARGET_REG_BITS == 64 && is_64) { + tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + break; + } + /* FALLTHRU */ + case MO_SL: + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + break; + case MO_Q: + /* Prefer to load from offset 0 first, but allow for overlap. */ + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); + } else if (lo != base) { + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + } else { + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + TCGMemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); +#endif +} + +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, TCGMemOp opc) +{ + const TCGMemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_8: + tcg_out_opc_store(s, OPC_SB, base, lo, 0); + break; + case MO_16: + tcg_out_opc_store(s, OPC_SH, base, lo, 0); + break; + case MO_32: + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_store(s, OPC_SD, base, lo, 0); + } else { + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + tcg_out_opc_store(s, OPC_SW, base, hi, 4); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + TCGMemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + add_qemu_ldst_label(s, 0, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); +#endif +} -- 2.19.1
next prev parent reply other threads:[~2018-12-19 19:19 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-19 19:16 [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support Alistair Francis 2018-12-19 19:16 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis 2018-12-19 19:16 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis 2018-12-19 19:16 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis 2018-12-19 19:16 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 04/23] exec: Add RISC-V GCC poison macro Alistair Francis 2018-12-19 19:16 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 05/23] riscv: Add the tcg-target header file Alistair Francis 2018-12-19 19:17 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 06/23] riscv: Add the tcg target registers Alistair Francis 2018-12-19 19:17 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 07/23] riscv: tcg-target: Add support for the constraints Alistair Francis 2018-12-19 19:17 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 08/23] riscv: tcg-target: Add the immediate encoders Alistair Francis 2018-12-19 19:17 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 09/23] riscv: tcg-target: Add the instruction emitters Alistair Francis 2018-12-19 19:17 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 10/23] riscv: tcg-target: Add the relocation functions Alistair Francis 2018-12-19 19:18 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis 2018-12-19 19:18 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 12/23] riscv: tcg-target: Add the extract instructions Alistair Francis 2018-12-19 19:18 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 13/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis 2018-12-19 19:18 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 14/23] riscv: tcg-target: Add the add2 and sub2 instructions Alistair Francis 2018-12-19 19:18 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis 2018-12-19 19:19 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis 2018-12-19 19:19 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:19 ` Alistair Francis [this message] 2018-12-19 19:19 ` [Qemu-riscv] [PATCH v2 17/23] riscv: tcg-target: Add direct " Alistair Francis 2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis 2018-12-19 19:19 ` [Qemu-riscv] " Alistair Francis 2018-12-20 5:59 ` [Qemu-devel] " Richard Henderson 2018-12-20 5:59 ` [Qemu-riscv] " Richard Henderson 2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 19/23] riscv: tcg-target: Add the prologue generation and register the JIT Alistair Francis 2018-12-19 19:19 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 20/23] riscv: tcg-target: Add the target init code Alistair Francis 2018-12-19 19:19 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis 2018-12-19 19:19 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:20 ` [Qemu-devel] [PATCH v2 22/23] dias: Add RISC-V support Alistair Francis 2018-12-19 19:20 ` [Qemu-riscv] " Alistair Francis 2018-12-19 19:20 ` [Qemu-devel] [PATCH v2 23/23] configure: Add support for building RISC-V host Alistair Francis 2018-12-19 19:20 ` [Qemu-riscv] " Alistair Francis 2018-12-20 6:07 ` [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support Richard Henderson 2018-12-20 6:07 ` [Qemu-riscv] " Richard Henderson 2018-12-20 17:20 ` [Qemu-devel] " Alistair Francis 2018-12-20 17:20 ` [Qemu-riscv] " Alistair Francis 2018-12-20 18:45 ` [Qemu-devel] " Palmer Dabbelt 2018-12-20 18:45 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-20 19:04 ` Alistair Francis 2018-12-20 19:04 ` [Qemu-riscv] " Alistair Francis 2018-12-20 19:10 ` Palmer Dabbelt 2018-12-20 19:10 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-25 14:44 ` no-reply 2018-12-25 14:44 ` [Qemu-riscv] " no-reply
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