All of lore.kernel.org
 help / color / mirror / Atom feed
From: BALATON Zoltan <balaton@eik.bme.hu>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: qemu-devel@nongnu.org, philmd@linaro.org
Subject: Re: [RFC PATCH 2/3] hw/misc: Add MIPS Trickbox device
Date: Fri, 25 Nov 2022 13:57:35 +0100 (CET)	[thread overview]
Message-ID: <2e5de7db-aad1-d133-d777-661bcebf129b@eik.bme.hu> (raw)
In-Reply-To: <20221124212916.723490-3-jiaxun.yang@flygoat.com>

Hello,

I can't review the patch, I can only correct grammar in commit message. 
(Also Philippe has a new preferred email address now.)

On Thu, 24 Nov 2022, Jiaxun Yang wrote:
> MIPS Trickbox is a emulated device present in MIPS's proprietary

an emulated

> simulators for decadeds. It's capable for managing simulator status,

decades, capable of

> signaling interrupts, doing DMA and EJTAG stimulations.

Stimulations? Did you mean simulation or something else?

> For now we just borrow this device and implement power management

Borrow it from where?

Regards,
BALATON Zoltan

> related functions.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> hw/misc/Kconfig                 |  3 +
> hw/misc/meson.build             |  1 +
> hw/misc/mips_trickbox.c         | 97 +++++++++++++++++++++++++++++++++
> hw/misc/trace-events            |  4 ++
> include/hw/misc/mips_trickbox.h | 41 ++++++++++++++
> 5 files changed, 146 insertions(+)
> create mode 100644 hw/misc/mips_trickbox.c
> create mode 100644 include/hw/misc/mips_trickbox.h
>
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index cbabe9f78c..fa92c439ec 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -89,6 +89,9 @@ config STM32F4XX_EXTI
> config MIPS_ITU
>     bool
>
> +config MIPS_TRICKBOX
> +    bool
> +
> config MPS2_FPGAIO
>     bool
>     select LED
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 95268eddc0..116eff8890 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -133,6 +133,7 @@ specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))
>
> specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c'))
> specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
> +specific_ss.add(when: 'CONFIG_MIPS_TRICKBOX', if_true: files('mips_trickbox.c'))
>
> specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
>
> diff --git a/hw/misc/mips_trickbox.c b/hw/misc/mips_trickbox.c
> new file mode 100644
> index 0000000000..20349b774b
> --- /dev/null
> +++ b/hw/misc/mips_trickbox.c
> @@ -0,0 +1,97 @@
> +/*
> + * SPDX-License-Identifier: LGPL-2.0-or-later
> + *
> + * MIPS Trickbox
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "trace.h"
> +#include "sysemu/runstate.h"
> +#include "hw/misc/mips_trickbox.h"
> +
> +static uint64_t mips_trickbox_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> +    uint64_t value = 0;
> +
> +    qemu_log_mask(LOG_UNIMP,
> +                    "%s: unimplemented register read 0x%02"HWADDR_PRIx"\n",
> +                    __func__, addr);
> +    trace_mips_trickbox_read(size, value);
> +
> +    return 0;
> +}
> +
> +static void mips_trickbox_write(void *opaque, hwaddr addr,
> +           uint64_t val64, unsigned int size)
> +{
> +    trace_mips_trickbox_write(size, val64);
> +
> +    switch (addr) {
> +    case REG_SIM_CMD:
> +        switch (val64 & 0xffffffff) {
> +        case TRICK_PANIC:
> +            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_PANIC);
> +            break;
> +        case TRICK_HALT:
> +            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
> +            break;
> +        case TRICK_SUSPEND:
> +            qemu_system_suspend_request();
> +            break;
> +        case TRICK_RESET:
> +            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +            break;
> +        case TRICK_PASS_MIPS:
> +        case TRICK_PASS_NANOMIPS:
> +            exit(EXIT_SUCCESS);
> +            break;
> +        case TRICK_FAIL_MIPS:
> +        case TRICK_FAIL_NANOMIPS:
> +            exit(EXIT_FAILURE);
> +            break;
> +        }
> +        break;
> +    default:
> +        qemu_log_mask(LOG_UNIMP,
> +                      "%s: unimplemented register write 0x%02"HWADDR_PRIx"\n",
> +                      __func__, addr);
> +        break;
> +    }
> +}
> +
> +static const MemoryRegionOps mips_trickbox_ops = {
> +    .read = mips_trickbox_read,
> +    .write = mips_trickbox_write,
> +    .endianness = DEVICE_NATIVE_ENDIAN,
> +    .valid = {
> +        .min_access_size = 2,
> +        .max_access_size = 4
> +    }
> +};
> +
> +static void mips_trickbox_init(Object *obj)
> +{
> +    MIPSTrickboxState *s = MIPS_TRICKBOX(obj);
> +
> +    memory_region_init_io(&s->mmio, obj, &mips_trickbox_ops, s,
> +                          TYPE_MIPS_TRICKBOX, 0x100);
> +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
> +}
> +
> +static const TypeInfo mips_trickbox_info = {
> +    .name          = TYPE_MIPS_TRICKBOX,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(MIPSTrickboxState),
> +    .instance_init = mips_trickbox_init,
> +};
> +
> +static void mips_trickbox_register_types(void)
> +{
> +    type_register_static(&mips_trickbox_info);
> +}
> +
> +type_init(mips_trickbox_register_types)
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index c18bc0605e..6df0e42450 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -274,3 +274,7 @@ virt_ctrl_instance_init(void *dev) "ctrl: %p"
> lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d"
> lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
> lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
> +
> +# mips_trickbox.c
> +mips_trickbox_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
> +mips_trickbox_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
> diff --git a/include/hw/misc/mips_trickbox.h b/include/hw/misc/mips_trickbox.h
> new file mode 100644
> index 0000000000..386a767937
> --- /dev/null
> +++ b/include/hw/misc/mips_trickbox.h
> @@ -0,0 +1,41 @@
> +/*
> + * SPDX-License-Identifier: LGPL-2.0-or-later
> + *
> + * MIPS Trickbox
> + */
> +
> +
> +#ifndef HW_MIPS_TRICKBOX_H
> +#define HW_MIPS_TRICKBOX_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +#define TYPE_MIPS_TRICKBOX "mips.trickbox"
> +
> +typedef struct MIPSTrickboxState MIPSTrickboxState;
> +DECLARE_INSTANCE_CHECKER(MIPSTrickboxState, MIPS_TRICKBOX,
> +                         TYPE_MIPS_TRICKBOX)
> +
> +struct MIPSTrickboxState {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +
> +    /*< public >*/
> +    MemoryRegion mmio;
> +};
> +
> +#define REG_SIM_CMD 0x0
> +
> +enum {
> +    TRICK_PANIC = 1,
> +    TRICK_HALT = 2,
> +    TRICK_SUSPEND = 3,
> +    TRICK_RESET = 4,
> +    TRICK_FAIL_MIPS = 0x2c00abc1,
> +    TRICK_PASS_MIPS = 0x2c00abc2,
> +    TRICK_FAIL_NANOMIPS = 0x80005bc1,
> +    TRICK_PASS_NANOMIPS = 0x80005bc2
> +};
> +
> +#endif
>


  reply	other threads:[~2022-11-25 12:59 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24 21:29 [RFC PATCH 0/3] MIPS VirtIO Machine Jiaxun Yang
2022-11-24 21:29 ` [RFC PATCH 1/3] hw/intc: Add missing include for goldfish_pic.h Jiaxun Yang
2022-11-25 13:28   ` Philippe Mathieu-Daudé
2022-11-24 21:29 ` [RFC PATCH 2/3] hw/misc: Add MIPS Trickbox device Jiaxun Yang
2022-11-25 12:57   ` BALATON Zoltan [this message]
2022-11-24 21:29 ` [RFC PATCH 3/3] hw/mips: Add MIPS VirtIO board Jiaxun Yang
2022-11-25 13:05   ` BALATON Zoltan
2022-11-25 13:25   ` Philippe Mathieu-Daudé
2022-11-25 18:06     ` Jiaxun Yang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2e5de7db-aad1-d133-d777-661bcebf129b@eik.bme.hu \
    --to=balaton@eik.bme.hu \
    --cc=jiaxun.yang@flygoat.com \
    --cc=philmd@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.