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From: Auger Eric <eric.auger@redhat.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: iommu@lists.linux-foundation.org,
	LKML <linux-kernel@vger.kernel.org>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	Raj Ashok <ashok.raj@intel.com>
Subject: Re: [PATCH] iommu/vt-d: Fix PASID cache flush
Date: Tue, 31 Mar 2020 18:19:25 +0200	[thread overview]
Message-ID: <2e9fc0f5-6181-0a10-db59-67e0ffca14cd@redhat.com> (raw)
In-Reply-To: <20200331090843.59961e03@jacob-builder>

Hi Jacob,

On 3/31/20 6:08 PM, Jacob Pan wrote:
> Actually, this is not a bug. The current code has:
> #define QI_PC_PASID_SEL             (QI_PC_TYPE | QI_PC_GRAN(1))
> 
> Which already has the type and shift.
> 
> In my vSVA series, I redefined granu such that I can use them in the 2D
> table lookup.
> 
> -#define QI_PC_ALL_PASIDS       (QI_PC_TYPE | QI_PC_GRAN(0))        
> -#define QI_PC_PASID_SEL                (QI_PC_TYPE | QI_PC_GRAN(1))
> +/* PASID cache invalidation granu */                               
> +#define QI_PC_ALL_PASIDS       0                                   
> +#define QI_PC_PASID_SEL                1                           
> 
> Please ignore this, sorry about the confusion.
OK I missed that as well, sorry. So that's not a fix but the code will
become more readable/consistent in your vSVA series.

Thanks

Eric
> 
> On Tue, 31 Mar 2020 11:28:17 +0200
> Auger Eric <eric.auger@redhat.com> wrote:
> 
>> Hi Jacob,
>>
>> On 3/31/20 1:25 AM, Jacob Pan wrote:
>>> PASID cache type and shift of granularity bits are missing in
>>> the current code.
>>>
>>> Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table
>>> interface")
>>>
>>> Cc: Eric Auger <eric.auger@redhat.com>
>>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>  
>> Reviewed-by: Eric Auger <eric.auger@redhat.com>
>>
>> Thanks
>>
>> Eric
>>
>>> ---
>>>  drivers/iommu/intel-pasid.c | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/iommu/intel-pasid.c
>>> b/drivers/iommu/intel-pasid.c index 22b30f10b396..57d05b0fbafc
>>> 100644 --- a/drivers/iommu/intel-pasid.c
>>> +++ b/drivers/iommu/intel-pasid.c
>>> @@ -365,7 +365,8 @@ pasid_cache_invalidation_with_pasid(struct
>>> intel_iommu *iommu, {
>>>  	struct qi_desc desc;
>>>  
>>> -	desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL |
>>> QI_PC_PASID(pasid);
>>> +	desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) |
>>> +		   QI_PC_PASID(pasid) | QI_PC_TYPE;
>>>  	desc.qw1 = 0;
>>>  	desc.qw2 = 0;
>>>  	desc.qw3 = 0;
>>>   
>>
> 
> [Jacob Pan]
> 


WARNING: multiple messages have this Message-ID (diff)
From: Auger Eric <eric.auger@redhat.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Raj Ashok <ashok.raj@intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	iommu@lists.linux-foundation.org,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH] iommu/vt-d: Fix PASID cache flush
Date: Tue, 31 Mar 2020 18:19:25 +0200	[thread overview]
Message-ID: <2e9fc0f5-6181-0a10-db59-67e0ffca14cd@redhat.com> (raw)
In-Reply-To: <20200331090843.59961e03@jacob-builder>

Hi Jacob,

On 3/31/20 6:08 PM, Jacob Pan wrote:
> Actually, this is not a bug. The current code has:
> #define QI_PC_PASID_SEL             (QI_PC_TYPE | QI_PC_GRAN(1))
> 
> Which already has the type and shift.
> 
> In my vSVA series, I redefined granu such that I can use them in the 2D
> table lookup.
> 
> -#define QI_PC_ALL_PASIDS       (QI_PC_TYPE | QI_PC_GRAN(0))        
> -#define QI_PC_PASID_SEL                (QI_PC_TYPE | QI_PC_GRAN(1))
> +/* PASID cache invalidation granu */                               
> +#define QI_PC_ALL_PASIDS       0                                   
> +#define QI_PC_PASID_SEL                1                           
> 
> Please ignore this, sorry about the confusion.
OK I missed that as well, sorry. So that's not a fix but the code will
become more readable/consistent in your vSVA series.

Thanks

Eric
> 
> On Tue, 31 Mar 2020 11:28:17 +0200
> Auger Eric <eric.auger@redhat.com> wrote:
> 
>> Hi Jacob,
>>
>> On 3/31/20 1:25 AM, Jacob Pan wrote:
>>> PASID cache type and shift of granularity bits are missing in
>>> the current code.
>>>
>>> Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table
>>> interface")
>>>
>>> Cc: Eric Auger <eric.auger@redhat.com>
>>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>  
>> Reviewed-by: Eric Auger <eric.auger@redhat.com>
>>
>> Thanks
>>
>> Eric
>>
>>> ---
>>>  drivers/iommu/intel-pasid.c | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/iommu/intel-pasid.c
>>> b/drivers/iommu/intel-pasid.c index 22b30f10b396..57d05b0fbafc
>>> 100644 --- a/drivers/iommu/intel-pasid.c
>>> +++ b/drivers/iommu/intel-pasid.c
>>> @@ -365,7 +365,8 @@ pasid_cache_invalidation_with_pasid(struct
>>> intel_iommu *iommu, {
>>>  	struct qi_desc desc;
>>>  
>>> -	desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL |
>>> QI_PC_PASID(pasid);
>>> +	desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) |
>>> +		   QI_PC_PASID(pasid) | QI_PC_TYPE;
>>>  	desc.qw1 = 0;
>>>  	desc.qw2 = 0;
>>>  	desc.qw3 = 0;
>>>   
>>
> 
> [Jacob Pan]
> 

_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  reply	other threads:[~2020-03-31 16:19 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-30 23:25 [PATCH] iommu/vt-d: Fix PASID cache flush Jacob Pan
2020-03-30 23:25 ` Jacob Pan
2020-03-31  9:28 ` Auger Eric
2020-03-31  9:28   ` Auger Eric
2020-03-31 16:08   ` Jacob Pan
2020-03-31 16:08     ` Jacob Pan
2020-03-31 16:19     ` Auger Eric [this message]
2020-03-31 16:19       ` Auger Eric

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