* [PATCH v2 00/23] Add driver nodes for MT8192 SoC
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
This series are based on tag: next-20220216, linux-next/master
and apply the below patchs
https://patchwork.kernel.org/project/linux-mediatek/patch/20220207094024.22674-1-allen-kh.cheng@mediatek.com/
https://patchwork.kernel.org/project/linux-mediatek/patch/20220217135620.10559-1-allen-kh.cheng@mediatek.com/
There some patches are missed in PATCH v1.
I resend series again and also add display related nodes in PATCH v2.
changes since v1:
- add usb-phy node for xhci node
- move infracfg_rst patch in front of PCIe patch
- add display nodes, i2c aliases and pwm node.
Allen-KH Cheng (23):
arm64: dts: mt8192: Add power domains controller
arm64: dts: mt8192: Add pwrap node
arm64: dts: mt8192: Add spmi node
arm64: dts: mt8192: Add gce node
arm64: dts: mt8192: Add SCP node
arm64: dts: mt8192: Add usb-phy node
arm64: dts: mt8192: Add xhci node
arm64: dts: mt8192: Add audio-related nodes
arm64: dts: mt8192: Add infracfg_rst node
arm64: dts: mt8192: Add PCIe node
arm64: dts: mt8192: Correct nor_flash status of mt8192
arm64: dts: mt8192: Add efuse node
arm64: dts: mt8192: Add mmc device nodes
arm64: dts: mt8192: Add mipi_tx node
arm64: dts: mt8192: Add m4u and smi nodes
arm64: dts: mt8192: Add H264 venc device node
arm64: dts: mt8192: Add vcodec lat and core nodes
arm64: dts: mt8192: Add dpi node
arm64: dts: mt8192: Add i2c aliases
arm64: dts: mt8192: Add display nodes
arm64: dts: mt8192: Add dsi node
arm64: dts: mt8192: Add gce info for display nodes
arm64: dts: mt8192: Add pwm node
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1000 +++++++++++++++++++++-
1 file changed, 989 insertions(+), 11 deletions(-)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 00/23] Add driver nodes for MT8192 SoC
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
This series are based on tag: next-20220216, linux-next/master
and apply the below patchs
https://patchwork.kernel.org/project/linux-mediatek/patch/20220207094024.22674-1-allen-kh.cheng@mediatek.com/
https://patchwork.kernel.org/project/linux-mediatek/patch/20220217135620.10559-1-allen-kh.cheng@mediatek.com/
There some patches are missed in PATCH v1.
I resend series again and also add display related nodes in PATCH v2.
changes since v1:
- add usb-phy node for xhci node
- move infracfg_rst patch in front of PCIe patch
- add display nodes, i2c aliases and pwm node.
Allen-KH Cheng (23):
arm64: dts: mt8192: Add power domains controller
arm64: dts: mt8192: Add pwrap node
arm64: dts: mt8192: Add spmi node
arm64: dts: mt8192: Add gce node
arm64: dts: mt8192: Add SCP node
arm64: dts: mt8192: Add usb-phy node
arm64: dts: mt8192: Add xhci node
arm64: dts: mt8192: Add audio-related nodes
arm64: dts: mt8192: Add infracfg_rst node
arm64: dts: mt8192: Add PCIe node
arm64: dts: mt8192: Correct nor_flash status of mt8192
arm64: dts: mt8192: Add efuse node
arm64: dts: mt8192: Add mmc device nodes
arm64: dts: mt8192: Add mipi_tx node
arm64: dts: mt8192: Add m4u and smi nodes
arm64: dts: mt8192: Add H264 venc device node
arm64: dts: mt8192: Add vcodec lat and core nodes
arm64: dts: mt8192: Add dpi node
arm64: dts: mt8192: Add i2c aliases
arm64: dts: mt8192: Add display nodes
arm64: dts: mt8192: Add dsi node
arm64: dts: mt8192: Add gce info for display nodes
arm64: dts: mt8192: Add pwm node
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1000 +++++++++++++++++++++-
1 file changed, 989 insertions(+), 11 deletions(-)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add power domains controller node for SoC mt8192.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c1d4030e7e4b..f10a9c75b20c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/power/mt8192-power.h>
/ {
compatible = "mediatek,mt8192";
@@ -301,6 +302,206 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8192-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ power-domain@MT8192_POWER_DOMAIN_AUDIO {
+ reg = <MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&infracfg CLK_INFRA_AUDIO>;
+ clock-names = "audio", "audio1", "audio2";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CONN {
+ reg = <MT8192_POWER_DOMAIN_CONN>;
+ clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
+ clock-names = "conn";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
+ reg = <MT8192_POWER_DOMAIN_MFG0>;
+ clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG1 {
+ reg = <MT8192_POWER_DOMAIN_MFG1>;
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG2 {
+ reg = <MT8192_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG3 {
+ reg = <MT8192_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG4 {
+ reg = <MT8192_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG5 {
+ reg = <MT8192_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG6 {
+ reg = <MT8192_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_DISP {
+ reg = <MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&topckgen CLK_TOP_DISP_SEL>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "disp", "disp-0", "disp-1", "disp-2",
+ "disp-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_IPE {
+ reg = <MT8192_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE_SEL>,
+ <&ipesys CLK_IPE_LARB19>,
+ <&ipesys CLK_IPE_LARB20>,
+ <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_GALS>;
+ clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
+ "ipe-3";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP {
+ reg = <MT8192_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_IMG1_SEL>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "isp", "isp-0", "isp-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP2 {
+ reg = <MT8192_POWER_DOMAIN_ISP2>;
+ clocks = <&topckgen CLK_TOP_IMG2_SEL>,
+ <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_GALS>;
+ clock-names = "isp2", "isp2-0", "isp2-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MDP {
+ reg = <MT8192_POWER_DOMAIN_MDP>;
+ clocks = <&topckgen CLK_TOP_MDP_SEL>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "mdp", "mdp-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VENC {
+ reg = <MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc", "venc-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC {
+ reg = <MT8192_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC2 {
+ reg = <MT8192_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec2-0", "vdec2-1",
+ "vdec2-2";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM {
+ reg = <MT8192_POWER_DOMAIN_CAM>;
+ clocks = <&topckgen CLK_TOP_CAM_SEL>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CCU_GALS>,
+ <&camsys CLK_CAM_CAM2MM_GALS>;
+ clock-names = "cam", "cam-0", "cam-1", "cam-2",
+ "cam-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "cam_rawa-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "cam_rawb-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
+ clock-names = "cam_rawc-0";
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8192-wdt";
reg = <0 0x10007000 0 0x100>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add power domains controller node for SoC mt8192.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c1d4030e7e4b..f10a9c75b20c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/power/mt8192-power.h>
/ {
compatible = "mediatek,mt8192";
@@ -301,6 +302,206 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8192-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ power-domain@MT8192_POWER_DOMAIN_AUDIO {
+ reg = <MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&infracfg CLK_INFRA_AUDIO>;
+ clock-names = "audio", "audio1", "audio2";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CONN {
+ reg = <MT8192_POWER_DOMAIN_CONN>;
+ clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
+ clock-names = "conn";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
+ reg = <MT8192_POWER_DOMAIN_MFG0>;
+ clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG1 {
+ reg = <MT8192_POWER_DOMAIN_MFG1>;
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG2 {
+ reg = <MT8192_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG3 {
+ reg = <MT8192_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG4 {
+ reg = <MT8192_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG5 {
+ reg = <MT8192_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG6 {
+ reg = <MT8192_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_DISP {
+ reg = <MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&topckgen CLK_TOP_DISP_SEL>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "disp", "disp-0", "disp-1", "disp-2",
+ "disp-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_IPE {
+ reg = <MT8192_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE_SEL>,
+ <&ipesys CLK_IPE_LARB19>,
+ <&ipesys CLK_IPE_LARB20>,
+ <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_GALS>;
+ clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
+ "ipe-3";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP {
+ reg = <MT8192_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_IMG1_SEL>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "isp", "isp-0", "isp-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP2 {
+ reg = <MT8192_POWER_DOMAIN_ISP2>;
+ clocks = <&topckgen CLK_TOP_IMG2_SEL>,
+ <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_GALS>;
+ clock-names = "isp2", "isp2-0", "isp2-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MDP {
+ reg = <MT8192_POWER_DOMAIN_MDP>;
+ clocks = <&topckgen CLK_TOP_MDP_SEL>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "mdp", "mdp-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VENC {
+ reg = <MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc", "venc-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC {
+ reg = <MT8192_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC2 {
+ reg = <MT8192_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec2-0", "vdec2-1",
+ "vdec2-2";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM {
+ reg = <MT8192_POWER_DOMAIN_CAM>;
+ clocks = <&topckgen CLK_TOP_CAM_SEL>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CCU_GALS>,
+ <&camsys CLK_CAM_CAM2MM_GALS>;
+ clock-names = "cam", "cam-0", "cam-1", "cam-2",
+ "cam-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "cam_rawa-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "cam_rawb-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
+ clock-names = "cam_rawc-0";
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8192-wdt";
reg = <0 0x10007000 0 0x100>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add power domains controller node for SoC mt8192.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c1d4030e7e4b..f10a9c75b20c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/power/mt8192-power.h>
/ {
compatible = "mediatek,mt8192";
@@ -301,6 +302,206 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8192-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ power-domain@MT8192_POWER_DOMAIN_AUDIO {
+ reg = <MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&infracfg CLK_INFRA_AUDIO>;
+ clock-names = "audio", "audio1", "audio2";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CONN {
+ reg = <MT8192_POWER_DOMAIN_CONN>;
+ clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
+ clock-names = "conn";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
+ reg = <MT8192_POWER_DOMAIN_MFG0>;
+ clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG1 {
+ reg = <MT8192_POWER_DOMAIN_MFG1>;
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG2 {
+ reg = <MT8192_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG3 {
+ reg = <MT8192_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG4 {
+ reg = <MT8192_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG5 {
+ reg = <MT8192_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG6 {
+ reg = <MT8192_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_DISP {
+ reg = <MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&topckgen CLK_TOP_DISP_SEL>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "disp", "disp-0", "disp-1", "disp-2",
+ "disp-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_IPE {
+ reg = <MT8192_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE_SEL>,
+ <&ipesys CLK_IPE_LARB19>,
+ <&ipesys CLK_IPE_LARB20>,
+ <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_GALS>;
+ clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
+ "ipe-3";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP {
+ reg = <MT8192_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_IMG1_SEL>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "isp", "isp-0", "isp-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP2 {
+ reg = <MT8192_POWER_DOMAIN_ISP2>;
+ clocks = <&topckgen CLK_TOP_IMG2_SEL>,
+ <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_GALS>;
+ clock-names = "isp2", "isp2-0", "isp2-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MDP {
+ reg = <MT8192_POWER_DOMAIN_MDP>;
+ clocks = <&topckgen CLK_TOP_MDP_SEL>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "mdp", "mdp-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VENC {
+ reg = <MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc", "venc-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC {
+ reg = <MT8192_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC2 {
+ reg = <MT8192_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec2-0", "vdec2-1",
+ "vdec2-2";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM {
+ reg = <MT8192_POWER_DOMAIN_CAM>;
+ clocks = <&topckgen CLK_TOP_CAM_SEL>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CCU_GALS>,
+ <&camsys CLK_CAM_CAM2MM_GALS>;
+ clock-names = "cam", "cam-0", "cam-1", "cam-2",
+ "cam-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "cam_rawa-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "cam_rawb-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
+ clock-names = "cam_rawc-0";
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8192-wdt";
reg = <0 0x10007000 0 0x100>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add power domains controller node for SoC mt8192.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add power domains controller node for SoC mt8192.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add power domains controller node for SoC mt8192.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 19:18 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:18 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:11PM +0800, Allen-KH Cheng wrote:
> Add power domains controller node for SoC mt8192.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
@ 2022-02-22 19:18 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:18 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:11PM +0800, Allen-KH Cheng wrote:
> Add power domains controller node for SoC mt8192.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller
@ 2022-02-22 19:18 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:18 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:11PM +0800, Allen-KH Cheng wrote:
> Add power domains controller node for SoC mt8192.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add pwrap node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f10a9c75b20c..f58a13b10916 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
clock-names = "clk13m";
};
+ pwrap: pwrap@10026000 {
+ compatible = "mediatek,mt6873-pwrap";
+ reg = <0 0x10026000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add pwrap node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f10a9c75b20c..f58a13b10916 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
clock-names = "clk13m";
};
+ pwrap: pwrap@10026000 {
+ compatible = "mediatek,mt6873-pwrap";
+ reg = <0 0x10026000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add pwrap node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f10a9c75b20c..f58a13b10916 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
clock-names = "clk13m";
};
+ pwrap: pwrap@10026000 {
+ compatible = "mediatek,mt6873-pwrap";
+ reg = <0 0x10026000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add pwrap node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f10a9c75b20c..f58a13b10916 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -523,6 +523,18 @@
> clock-names = "clk13m";
> };
>
> + pwrap: pwrap@10026000 {
> + compatible = "mediatek,mt6873-pwrap";
> + reg = <0 0x10026000 0 0x1000>;
> + reg-names = "pwrap";
> + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> + <&infracfg CLK_INFRA_PMIC_TMR>;
> + clock-names = "spi", "wrap";
> + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> + };
> +
> scp_adsp: clock-controller@10720000 {
> compatible = "mediatek,mt8192-scp_adsp";
> reg = <0 0x10720000 0 0x1000>;
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add pwrap node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f10a9c75b20c..f58a13b10916 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -523,6 +523,18 @@
> clock-names = "clk13m";
> };
>
> + pwrap: pwrap@10026000 {
> + compatible = "mediatek,mt6873-pwrap";
> + reg = <0 0x10026000 0 0x1000>;
> + reg-names = "pwrap";
> + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> + <&infracfg CLK_INFRA_PMIC_TMR>;
> + clock-names = "spi", "wrap";
> + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> + };
> +
> scp_adsp: clock-controller@10720000 {
> compatible = "mediatek,mt8192-scp_adsp";
> reg = <0 0x10720000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add pwrap node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f10a9c75b20c..f58a13b10916 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -523,6 +523,18 @@
> clock-names = "clk13m";
> };
>
> + pwrap: pwrap@10026000 {
> + compatible = "mediatek,mt6873-pwrap";
> + reg = <0 0x10026000 0 0x1000>;
> + reg-names = "pwrap";
> + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> + <&infracfg CLK_INFRA_PMIC_TMR>;
> + clock-names = "spi", "wrap";
> + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> + };
> +
> scp_adsp: clock-controller@10720000 {
> compatible = "mediatek,mt8192-scp_adsp";
> reg = <0 0x10720000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 19:24 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:12PM +0800, Allen-KH Cheng wrote:
> Add pwrap node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
@ 2022-02-22 19:24 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:12PM +0800, Allen-KH Cheng wrote:
> Add pwrap node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node
@ 2022-02-22 19:24 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:12PM +0800, Allen-KH Cheng wrote:
> Add pwrap node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add spmi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f58a13b10916..8635c8a53472 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -535,6 +535,23 @@
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt6873-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST_SEL>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add spmi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f58a13b10916..8635c8a53472 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -535,6 +535,23 @@
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt6873-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST_SEL>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add spmi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f58a13b10916..8635c8a53472 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -535,6 +535,23 @@
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt6873-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST_SEL>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add spmi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add spmi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add spmi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 19:31 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:31 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:13PM +0800, Allen-KH Cheng wrote:
> Add spmi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
@ 2022-02-22 19:31 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:31 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:13PM +0800, Allen-KH Cheng wrote:
> Add spmi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node
@ 2022-02-22 19:31 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:31 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:13PM +0800, Allen-KH Cheng wrote:
> Add spmi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add gce node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8635c8a53472..f92d8d7afa5d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -552,6 +553,15 @@
#size-cells = <0>;
};
+ gce: mailbox@10228000 {
+ compatible = "mediatek,mt8192-gce";
+ reg = <0 0x10228000 0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add gce node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8635c8a53472..f92d8d7afa5d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -552,6 +553,15 @@
#size-cells = <0>;
};
+ gce: mailbox@10228000 {
+ compatible = "mediatek,mt8192-gce";
+ reg = <0 0x10228000 0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add gce node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8635c8a53472..f92d8d7afa5d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -552,6 +553,15 @@
#size-cells = <0>;
};
+ gce: mailbox@10228000 {
+ compatible = "mediatek,mt8192-gce";
+ reg = <0 0x10228000 0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add gce node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add gce node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add gce node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 19:43 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:43 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:14PM +0800, Allen-KH Cheng wrote:
> Add gce node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
@ 2022-02-22 19:43 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:43 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:14PM +0800, Allen-KH Cheng wrote:
> Add gce node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node
@ 2022-02-22 19:43 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 19:43 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:14PM +0800, Allen-KH Cheng wrote:
> Add gce node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add SCP node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f92d8d7afa5d..61aadd7bd397 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -706,6 +706,18 @@
status = "disabled";
};
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8192-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10700000 0 0x8000>,
+ <0 0x10720000 0 0xe0000>;
+ reg-names = "sram", "l1tcm", "cfg";
+ interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_SCPSYS>;
+ clock-names = "main";
+ status = "disabled";
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add SCP node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f92d8d7afa5d..61aadd7bd397 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -706,6 +706,18 @@
status = "disabled";
};
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8192-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10700000 0 0x8000>,
+ <0 0x10720000 0 0xe0000>;
+ reg-names = "sram", "l1tcm", "cfg";
+ interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_SCPSYS>;
+ clock-names = "main";
+ status = "disabled";
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add SCP node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f92d8d7afa5d..61aadd7bd397 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -706,6 +706,18 @@
status = "disabled";
};
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8192-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10700000 0 0x8000>,
+ <0 0x10720000 0 0xe0000>;
+ reg-names = "sram", "l1tcm", "cfg";
+ interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_SCPSYS>;
+ clock-names = "main";
+ status = "disabled";
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add SCP node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f92d8d7afa5d..61aadd7bd397 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
> status = "disabled";
> };
>
> + scp: scp@10500000 {
> + compatible = "mediatek,mt8192-scp";
> + reg = <0 0x10500000 0 0x100000>,
> + <0 0x10700000 0 0x8000>,
> + <0 0x10720000 0 0xe0000>;
Please fix indentation:
reg = <0 0x10500000 0 0x100000>,
<0 0x10700000 0 0x8000>,
<0 0x10720000 0 0xe0000>;
> + reg-names = "sram", "l1tcm", "cfg";
> + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_SCPSYS>;
> + clock-names = "main";
> + status = "disabled";
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add SCP node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f92d8d7afa5d..61aadd7bd397 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
> status = "disabled";
> };
>
> + scp: scp@10500000 {
> + compatible = "mediatek,mt8192-scp";
> + reg = <0 0x10500000 0 0x100000>,
> + <0 0x10700000 0 0x8000>,
> + <0 0x10720000 0 0xe0000>;
Please fix indentation:
reg = <0 0x10500000 0 0x100000>,
<0 0x10700000 0 0x8000>,
<0 0x10720000 0 0xe0000>;
> + reg-names = "sram", "l1tcm", "cfg";
> + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_SCPSYS>;
> + clock-names = "main";
> + status = "disabled";
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add SCP node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f92d8d7afa5d..61aadd7bd397 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
> status = "disabled";
> };
>
> + scp: scp@10500000 {
> + compatible = "mediatek,mt8192-scp";
> + reg = <0 0x10500000 0 0x100000>,
> + <0 0x10700000 0 0x8000>,
> + <0 0x10720000 0 0xe0000>;
Please fix indentation:
reg = <0 0x10500000 0 0x100000>,
<0 0x10700000 0 0x8000>,
<0 0x10720000 0 0xe0000>;
> + reg-names = "sram", "l1tcm", "cfg";
> + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_SCPSYS>;
> + clock-names = "main";
> + status = "disabled";
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
2022-02-18 12:55 ` AngeloGioacchino Del Regno
@ 2022-02-21 12:37 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:37 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add SCP node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f92d8d7afa5d..61aadd7bd397 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -706,6 +706,18 @@
> > status = "disabled";
> > };
> >
> > + scp: scp@10500000 {
> > + compatible = "mediatek,mt8192-scp";
> > + reg = <0 0x10500000 0 0x100000>,
> > + <0 0x10700000 0 0x8000>,
> > + <0 0x10720000 0 0xe0000>;
>
> Please fix indentation:
> reg = <0 0x10500000 0 0x100000>,
> <0 0x10700000 0 0x8000>,
> <0 0x10720000 0 0xe0000>;
>
>
Hi Angelo,
Thanks for your reminding ,I will correct this in next version.
Thanks.
Allen
>
> > + reg-names = "sram", "l1tcm", "cfg";
> > + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&infracfg CLK_INFRA_SCPSYS>;
> > + clock-names = "main";
> > + status = "disabled";
> > + };
> > +
> > nor_flash: spi@11234000 {
> > compatible = "mediatek,mt8192-nor";
> > reg = <0 0x11234000 0 0xe0>;
>
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
@ 2022-02-21 12:37 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:37 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add SCP node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f92d8d7afa5d..61aadd7bd397 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -706,6 +706,18 @@
> > status = "disabled";
> > };
> >
> > + scp: scp@10500000 {
> > + compatible = "mediatek,mt8192-scp";
> > + reg = <0 0x10500000 0 0x100000>,
> > + <0 0x10700000 0 0x8000>,
> > + <0 0x10720000 0 0xe0000>;
>
> Please fix indentation:
> reg = <0 0x10500000 0 0x100000>,
> <0 0x10700000 0 0x8000>,
> <0 0x10720000 0 0xe0000>;
>
>
Hi Angelo,
Thanks for your reminding ,I will correct this in next version.
Thanks.
Allen
>
> > + reg-names = "sram", "l1tcm", "cfg";
> > + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&infracfg CLK_INFRA_SCPSYS>;
> > + clock-names = "main";
> > + status = "disabled";
> > + };
> > +
> > nor_flash: spi@11234000 {
> > compatible = "mediatek,mt8192-nor";
> > reg = <0 0x11234000 0 0xe0>;
>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 61aadd7bd397..ce18d692175f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -875,6 +875,31 @@
#clock-cells = <1>;
};
+ u3phy0: usb-phy@11e40000 {
+ compatible = "mediatek,mt8192-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port0: usb-phy@11e40000 {
+ reg = <0 0x11e40000 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@11e40700 {
+ reg = <0 0x11e40700 0 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 61aadd7bd397..ce18d692175f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -875,6 +875,31 @@
#clock-cells = <1>;
};
+ u3phy0: usb-phy@11e40000 {
+ compatible = "mediatek,mt8192-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port0: usb-phy@11e40000 {
+ reg = <0 0x11e40000 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@11e40700 {
+ reg = <0 0x11e40700 0 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 61aadd7bd397..ce18d692175f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -875,6 +875,31 @@
#clock-cells = <1>;
};
+ u3phy0: usb-phy@11e40000 {
+ compatible = "mediatek,mt8192-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port0: usb-phy@11e40000 {
+ reg = <0 0x11e40000 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@11e40700 {
+ reg = <0 0x11e40700 0 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 61aadd7bd397..ce18d692175f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,31 @@
> #clock-cells = <1>;
> };
>
> + u3phy0: usb-phy@11e40000 {
> + compatible = "mediatek,mt8192-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
This can be better:
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11e40000 0x1000>
> + status = "okay";
> +
> + u2port0: usb-phy@11e40000 {
u2port0: usb-phy@0 {
> + reg = <0 0x11e40000 0 0x700>;
reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@11e40700 {
> + reg = <0 0x11e40700 0 0x900>;
u3port0: usb-phy@700 {
reg = <0x700 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
Thanks,
Angelo
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 61aadd7bd397..ce18d692175f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,31 @@
> #clock-cells = <1>;
> };
>
> + u3phy0: usb-phy@11e40000 {
> + compatible = "mediatek,mt8192-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
This can be better:
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11e40000 0x1000>
> + status = "okay";
> +
> + u2port0: usb-phy@11e40000 {
u2port0: usb-phy@0 {
> + reg = <0 0x11e40000 0 0x700>;
reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@11e40700 {
> + reg = <0 0x11e40700 0 0x900>;
u3port0: usb-phy@700 {
reg = <0x700 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
Thanks,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 61aadd7bd397..ce18d692175f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,31 @@
> #clock-cells = <1>;
> };
>
> + u3phy0: usb-phy@11e40000 {
> + compatible = "mediatek,mt8192-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
This can be better:
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11e40000 0x1000>
> + status = "okay";
> +
> + u2port0: usb-phy@11e40000 {
u2port0: usb-phy@0 {
> + reg = <0 0x11e40000 0 0x700>;
reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@11e40700 {
> + reg = <0 0x11e40700 0 0x900>;
u3port0: usb-phy@700 {
reg = <0x700 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
Thanks,
Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
2022-02-18 12:55 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:00 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:00 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add xhci node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > ++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 61aadd7bd397..ce18d692175f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -875,6 +875,31 @@
> > #clock-cells = <1>;
> > };
> >
> > + u3phy0: usb-phy@11e40000 {
> > + compatible = "mediatek,mt8192-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
>
> This can be better:
> #address-cells = <1>;
>
> #size-cells = <1>;
> ranges = <0 0 0x11e40000 0x1000>
>
>
Hi Angelo,
Thanks for your surgestion, this's good for me,
I will update in next version.
Best regards,
Allen
> > + status = "okay";
> > +
> > + u2port0: usb-phy@11e40000 {
>
> u2port0: usb-phy@0 {
>
> > + reg = <0 0x11e40000 0 0x700>;
>
> reg = <0x0 0x700>;
>
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > +
> > + u3port0: usb-phy@11e40700 {
> > + reg = <0 0x11e40700 0 0x900>;
>
> u3port0: usb-phy@700 {
> reg = <0x700 0x900>;
>
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
>
> Thanks,
> Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-21 13:00 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:00 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add xhci node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > ++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 61aadd7bd397..ce18d692175f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -875,6 +875,31 @@
> > #clock-cells = <1>;
> > };
> >
> > + u3phy0: usb-phy@11e40000 {
> > + compatible = "mediatek,mt8192-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
>
> This can be better:
> #address-cells = <1>;
>
> #size-cells = <1>;
> ranges = <0 0 0x11e40000 0x1000>
>
>
Hi Angelo,
Thanks for your surgestion, this's good for me,
I will update in next version.
Best regards,
Allen
> > + status = "okay";
> > +
> > + u2port0: usb-phy@11e40000 {
>
> u2port0: usb-phy@0 {
>
> > + reg = <0 0x11e40000 0 0x700>;
>
> reg = <0x0 0x700>;
>
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > +
> > + u3port0: usb-phy@11e40700 {
> > + reg = <0 0x11e40700 0 0x900>;
>
> u3port0: usb-phy@700 {
> reg = <0x700 0x900>;
>
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
>
> Thanks,
> Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 20:10 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:10 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 61aadd7bd397..ce18d692175f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,31 @@
> #clock-cells = <1>;
> };
>
> + u3phy0: usb-phy@11e40000 {
According to Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
should be called t-phy. Only the child nodes should be usb-phy.
> + compatible = "mediatek,mt8192-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
"okay" is already the default status, so you can drop this line, as well as the
ones on the child nodes below.
> +
> + u2port0: usb-phy@11e40000 {
> + reg = <0 0x11e40000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@11e40700 {
> + reg = <0 0x11e40700 0 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-22 20:10 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:10 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 61aadd7bd397..ce18d692175f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,31 @@
> #clock-cells = <1>;
> };
>
> + u3phy0: usb-phy@11e40000 {
According to Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
should be called t-phy. Only the child nodes should be usb-phy.
> + compatible = "mediatek,mt8192-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
"okay" is already the default status, so you can drop this line, as well as the
ones on the child nodes below.
> +
> + u2port0: usb-phy@11e40000 {
> + reg = <0 0x11e40000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@11e40700 {
> + reg = <0 0x11e40700 0 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-22 20:10 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:10 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 61aadd7bd397..ce18d692175f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,31 @@
> #clock-cells = <1>;
> };
>
> + u3phy0: usb-phy@11e40000 {
According to Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
should be called t-phy. Only the child nodes should be usb-phy.
> + compatible = "mediatek,mt8192-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
"okay" is already the default status, so you can drop this line, as well as the
ones on the child nodes below.
> +
> + u2port0: usb-phy@11e40000 {
> + reg = <0 0x11e40000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@11e40700 {
> + reg = <0 0x11e40700 0 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
2022-02-22 20:10 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:24 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:24 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 15:10 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> > Add xhci node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > ++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 61aadd7bd397..ce18d692175f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -875,6 +875,31 @@
> > #clock-cells = <1>;
> > };
> >
> > + u3phy0: usb-phy@11e40000 {
>
> According to
> Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
> should be called t-phy. Only the child nodes should be usb-phy.
>
Hi Nícolas,
I think it should be "u3phy0: t-phy@11e40000". am I right?
Many thanks,
Allen
> > + compatible = "mediatek,mt8192-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + status = "okay";
>
> "okay" is already the default status, so you can drop this line, as
> well as the
> ones on the child nodes below.
>
> > +
> > + u2port0: usb-phy@11e40000 {
> > + reg = <0 0x11e40000 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > +
> > + u3port0: usb-phy@11e40700 {
> > + reg = <0 0x11e40700 0 0x900>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-23 13:24 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:24 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 15:10 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> > Add xhci node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > ++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 61aadd7bd397..ce18d692175f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -875,6 +875,31 @@
> > #clock-cells = <1>;
> > };
> >
> > + u3phy0: usb-phy@11e40000 {
>
> According to
> Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
> should be called t-phy. Only the child nodes should be usb-phy.
>
Hi Nícolas,
I think it should be "u3phy0: t-phy@11e40000". am I right?
Many thanks,
Allen
> > + compatible = "mediatek,mt8192-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + status = "okay";
>
> "okay" is already the default status, so you can drop this line, as
> well as the
> ones on the child nodes below.
>
> > +
> > + u2port0: usb-phy@11e40000 {
> > + reg = <0 0x11e40000 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > +
> > + u3port0: usb-phy@11e40700 {
> > + reg = <0 0x11e40700 0 0x900>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
2022-02-23 13:24 ` allen-kh.cheng
(?)
@ 2022-02-23 15:11 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:11 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Wed, Feb 23, 2022 at 09:24:12PM +0800, allen-kh.cheng wrote:
> On Tue, 2022-02-22 at 15:10 -0500, Nícolas F. R. A. Prado wrote:
> > On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> > > Add xhci node for mt8192 SoC.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > > ++++++++++++++++++++++++
> > > 1 file changed, 25 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 61aadd7bd397..ce18d692175f 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -875,6 +875,31 @@
> > > #clock-cells = <1>;
> > > };
> > >
> > > + u3phy0: usb-phy@11e40000 {
> >
> > According to
> > Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
> > should be called t-phy. Only the child nodes should be usb-phy.
> >
> Hi Nícolas,
>
> I think it should be "u3phy0: t-phy@11e40000". am I right?
Yes, that's it.
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-23 15:11 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:11 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Wed, Feb 23, 2022 at 09:24:12PM +0800, allen-kh.cheng wrote:
> On Tue, 2022-02-22 at 15:10 -0500, Nícolas F. R. A. Prado wrote:
> > On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> > > Add xhci node for mt8192 SoC.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > > ++++++++++++++++++++++++
> > > 1 file changed, 25 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 61aadd7bd397..ce18d692175f 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -875,6 +875,31 @@
> > > #clock-cells = <1>;
> > > };
> > >
> > > + u3phy0: usb-phy@11e40000 {
> >
> > According to
> > Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
> > should be called t-phy. Only the child nodes should be usb-phy.
> >
> Hi Nícolas,
>
> I think it should be "u3phy0: t-phy@11e40000". am I right?
Yes, that's it.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node
@ 2022-02-23 15:11 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:11 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Wed, Feb 23, 2022 at 09:24:12PM +0800, allen-kh.cheng wrote:
> On Tue, 2022-02-22 at 15:10 -0500, Nícolas F. R. A. Prado wrote:
> > On Fri, Feb 18, 2022 at 05:16:16PM +0800, Allen-KH Cheng wrote:
> > > Add xhci node for mt8192 SoC.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > > ++++++++++++++++++++++++
> > > 1 file changed, 25 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 61aadd7bd397..ce18d692175f 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -875,6 +875,31 @@
> > > #clock-cells = <1>;
> > > };
> > >
> > > + u3phy0: usb-phy@11e40000 {
> >
> > According to
> > Documentation/devicetree/bindings/phy/mediatek,tphy.yaml, this node
> > should be called t-phy. Only the child nodes should be usb-phy.
> >
> Hi Nícolas,
>
> I think it should be "u3phy0: t-phy@11e40000". am I right?
Yes, that's it.
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ce18d692175f..08c7c1c772f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
/ {
@@ -718,6 +719,30 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt8192-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "host";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg CLK_INFRA_SSUSB>,
+ <&infracfg CLK_INFRA_SSUSB_XHCI>,
+ <&apmixedsys CLK_APMIXED_USBPLL>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ce18d692175f..08c7c1c772f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
/ {
@@ -718,6 +719,30 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt8192-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "host";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg CLK_INFRA_SSUSB>,
+ <&infracfg CLK_INFRA_SSUSB_XHCI>,
+ <&apmixedsys CLK_APMIXED_USBPLL>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ce18d692175f..08c7c1c772f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
/ {
@@ -718,6 +719,30 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt8192-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "host";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg CLK_INFRA_SSUSB>,
+ <&infracfg CLK_INFRA_SSUSB_XHCI>,
+ <&apmixedsys CLK_APMIXED_USBPLL>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index ce18d692175f..08c7c1c772f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
>
> / {
> @@ -718,6 +719,30 @@
> status = "disabled";
> };
>
> + xhci: xhci@11200000 {
> + compatible = "mediatek,mt8192-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "host";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> + <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> + clocks = <&infracfg CLK_INFRA_SSUSB>,
> + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> + <&apmixedsys CLK_APMIXED_USBPLL>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + wakeup-source;
> + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index ce18d692175f..08c7c1c772f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
>
> / {
> @@ -718,6 +719,30 @@
> status = "disabled";
> };
>
> + xhci: xhci@11200000 {
> + compatible = "mediatek,mt8192-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "host";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> + <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> + clocks = <&infracfg CLK_INFRA_SSUSB>,
> + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> + <&apmixedsys CLK_APMIXED_USBPLL>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + wakeup-source;
> + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index ce18d692175f..08c7c1c772f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
>
> / {
> @@ -718,6 +719,30 @@
> status = "disabled";
> };
>
> + xhci: xhci@11200000 {
> + compatible = "mediatek,mt8192-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "host";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> + <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> + clocks = <&infracfg CLK_INFRA_SSUSB>,
> + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> + <&apmixedsys CLK_APMIXED_USBPLL>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + wakeup-source;
> + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 20:28 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:28 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:17PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index ce18d692175f..08c7c1c772f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
>
> / {
> @@ -718,6 +719,30 @@
> status = "disabled";
> };
>
> + xhci: xhci@11200000 {
According to Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml, this
node should be called usb (but the label can be kept as xhci).
> + compatible = "mediatek,mt8192-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "host";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> + <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> + clocks = <&infracfg CLK_INFRA_SSUSB>,
> + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> + <&apmixedsys CLK_APMIXED_USBPLL>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + wakeup-source;
> + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> + #address-cells = <2>;
> + #size-cells = <2>;
This node doesn't have any children, so no need for #address-cells and
#size-cells, just drop them.
Also, let's keep this node disabled by default:
status = "disabled";
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
@ 2022-02-22 20:28 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:28 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:17PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index ce18d692175f..08c7c1c772f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
>
> / {
> @@ -718,6 +719,30 @@
> status = "disabled";
> };
>
> + xhci: xhci@11200000 {
According to Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml, this
node should be called usb (but the label can be kept as xhci).
> + compatible = "mediatek,mt8192-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "host";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> + <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> + clocks = <&infracfg CLK_INFRA_SSUSB>,
> + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> + <&apmixedsys CLK_APMIXED_USBPLL>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + wakeup-source;
> + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> + #address-cells = <2>;
> + #size-cells = <2>;
This node doesn't have any children, so no need for #address-cells and
#size-cells, just drop them.
Also, let's keep this node disabled by default:
status = "disabled";
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
@ 2022-02-22 20:28 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:28 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:17PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index ce18d692175f..08c7c1c772f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
>
> / {
> @@ -718,6 +719,30 @@
> status = "disabled";
> };
>
> + xhci: xhci@11200000 {
According to Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml, this
node should be called usb (but the label can be kept as xhci).
> + compatible = "mediatek,mt8192-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "host";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> + <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> + clocks = <&infracfg CLK_INFRA_SSUSB>,
> + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> + <&apmixedsys CLK_APMIXED_USBPLL>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + wakeup-source;
> + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> + #address-cells = <2>;
> + #size-cells = <2>;
This node doesn't have any children, so no need for #address-cells and
#size-cells, just drop them.
Also, let's keep this node disabled by default:
status = "disabled";
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
2022-02-22 20:28 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:27 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:27 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 15:28 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:17PM +0800, Allen-KH Cheng wrote:
> > Add xhci node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > ++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index ce18d692175f..08c7c1c772f5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -10,6 +10,7 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > +#include <dt-bindings/phy/phy.h>
> > #include <dt-bindings/power/mt8192-power.h>
> >
> > / {
> > @@ -718,6 +719,30 @@
> > status = "disabled";
> > };
> >
> > + xhci: xhci@11200000 {
>
> According to Documentation/devicetree/bindings/usb/mediatek,mtk-
> xhci.yaml, this
> node should be called usb (but the label can be kept as xhci).
Hi Nícolas,
ok, I will fix this. Thanks for suggestion.
> > + compatible = "mediatek,mt8192-xhci",
> > + "mediatek,mtk-xhci";
> > + reg = <0 0x11200000 0 0x1000>,
> > + <0 0x11203e00 0 0x0100>;
> > + reg-names = "mac", "ippc";
> > + interrupts-extended = <&gic GIC_SPI 97
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + interrupt-names = "host";
> > + phys = <&u2port0 PHY_TYPE_USB2>,
> > + <&u3port0 PHY_TYPE_USB3>;
> > + assigned-clocks = <&topckgen
> > CLK_TOP_USB_TOP_SEL>,
> > + <&topckgen
> > CLK_TOP_SSUSB_XHCI_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>,
> > + <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>;
> > + clocks = <&infracfg CLK_INFRA_SSUSB>,
> > + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> > + <&apmixedsys CLK_APMIXED_USBPLL>;
> > + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> > + wakeup-source;
> > + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> This node doesn't have any children, so no need for #address-cells
> and
> #size-cells, just drop them.
>
> Also, let's keep this node disabled by default:
>
> status = "disabled";
>
sure, thanks.
> > + };
> > +
> > nor_flash: spi@11234000 {
> > compatible = "mediatek,mt8192-nor";
> > reg = <0 0x11234000 0 0xe0>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node
@ 2022-02-23 13:27 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:27 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 15:28 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:17PM +0800, Allen-KH Cheng wrote:
> > Add xhci node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
> > ++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index ce18d692175f..08c7c1c772f5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -10,6 +10,7 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > +#include <dt-bindings/phy/phy.h>
> > #include <dt-bindings/power/mt8192-power.h>
> >
> > / {
> > @@ -718,6 +719,30 @@
> > status = "disabled";
> > };
> >
> > + xhci: xhci@11200000 {
>
> According to Documentation/devicetree/bindings/usb/mediatek,mtk-
> xhci.yaml, this
> node should be called usb (but the label can be kept as xhci).
Hi Nícolas,
ok, I will fix this. Thanks for suggestion.
> > + compatible = "mediatek,mt8192-xhci",
> > + "mediatek,mtk-xhci";
> > + reg = <0 0x11200000 0 0x1000>,
> > + <0 0x11203e00 0 0x0100>;
> > + reg-names = "mac", "ippc";
> > + interrupts-extended = <&gic GIC_SPI 97
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + interrupt-names = "host";
> > + phys = <&u2port0 PHY_TYPE_USB2>,
> > + <&u3port0 PHY_TYPE_USB3>;
> > + assigned-clocks = <&topckgen
> > CLK_TOP_USB_TOP_SEL>,
> > + <&topckgen
> > CLK_TOP_SSUSB_XHCI_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>,
> > + <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>;
> > + clocks = <&infracfg CLK_INFRA_SSUSB>,
> > + <&infracfg CLK_INFRA_SSUSB_XHCI>,
> > + <&apmixedsys CLK_APMIXED_USBPLL>;
> > + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> > + wakeup-source;
> > + mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> This node doesn't have any children, so no need for #address-cells
> and
> #size-cells, just drop them.
>
> Also, let's keep this node disabled by default:
>
> status = "disabled";
>
sure, thanks.
> > + };
> > +
> > nor_flash: spi@11234000 {
> > compatible = "mediatek,mt8192-nor";
> > reg = <0 0x11234000 0 0xe0>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add audio-related nodes in audsys for mt8192 SoC.
Move audsys node in ascending order.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 08c7c1c772f5..f93fe3779161 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -743,6 +743,135 @@
#size-cells = <2>;
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
@@ -758,12 +887,6 @@
status = "disable";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add audio-related nodes in audsys for mt8192 SoC.
Move audsys node in ascending order.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 08c7c1c772f5..f93fe3779161 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -743,6 +743,135 @@
#size-cells = <2>;
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
@@ -758,12 +887,6 @@
status = "disable";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add audio-related nodes in audsys for mt8192 SoC.
Move audsys node in ascending order.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 08c7c1c772f5..f93fe3779161 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -743,6 +743,135 @@
#size-cells = <2>;
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
@@ -758,12 +887,6 @@
status = "disable";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add audio-related nodes in audsys for mt8192 SoC.
> Move audsys node in ascending order.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add audio-related nodes in audsys for mt8192 SoC.
> Move audsys node in ascending order.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add audio-related nodes in audsys for mt8192 SoC.
> Move audsys node in ascending order.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 20:35 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:35 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:18PM +0800, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
> Move audsys node in ascending order.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08c7c1c772f5..f93fe3779161 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -743,6 +743,135 @@
> #size-cells = <2>;
> };
>
> + audsys: syscon@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x2000>;
You should mention in the commit message that the address range's length was
increased as well (from 0x1000 to 0x2000).
> + #clock-cells = <1>;
> +
> + afe: mt8192-afe-pcm {
> + compatible = "mediatek,mt8192-audio";
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&watchdog 17>;
> + reset-names = "audiosys";
> + mediatek,apmixedsys = <&apmixedsys>;
> + mediatek,infracfg = <&infracfg>;
> + mediatek,topckgen = <&topckgen>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> + clocks = <&audsys CLK_AUD_AFE>,
> + <&audsys CLK_AUD_DAC>,
> + <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> + "aud_infra_clk",
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> + };
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> @@ -758,12 +887,6 @@
> status = "disable";
> };
>
> - audsys: clock-controller@11210000 {
> - compatible = "mediatek,mt8192-audsys", "syscon";
> - reg = <0 0x11210000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> i2c3: i2c@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
@ 2022-02-22 20:35 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:35 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:18PM +0800, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
> Move audsys node in ascending order.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08c7c1c772f5..f93fe3779161 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -743,6 +743,135 @@
> #size-cells = <2>;
> };
>
> + audsys: syscon@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x2000>;
You should mention in the commit message that the address range's length was
increased as well (from 0x1000 to 0x2000).
> + #clock-cells = <1>;
> +
> + afe: mt8192-afe-pcm {
> + compatible = "mediatek,mt8192-audio";
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&watchdog 17>;
> + reset-names = "audiosys";
> + mediatek,apmixedsys = <&apmixedsys>;
> + mediatek,infracfg = <&infracfg>;
> + mediatek,topckgen = <&topckgen>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> + clocks = <&audsys CLK_AUD_AFE>,
> + <&audsys CLK_AUD_DAC>,
> + <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> + "aud_infra_clk",
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> + };
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> @@ -758,12 +887,6 @@
> status = "disable";
> };
>
> - audsys: clock-controller@11210000 {
> - compatible = "mediatek,mt8192-audsys", "syscon";
> - reg = <0 0x11210000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> i2c3: i2c@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
@ 2022-02-22 20:35 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 20:35 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:18PM +0800, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
> Move audsys node in ascending order.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08c7c1c772f5..f93fe3779161 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -743,6 +743,135 @@
> #size-cells = <2>;
> };
>
> + audsys: syscon@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x2000>;
You should mention in the commit message that the address range's length was
increased as well (from 0x1000 to 0x2000).
> + #clock-cells = <1>;
> +
> + afe: mt8192-afe-pcm {
> + compatible = "mediatek,mt8192-audio";
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&watchdog 17>;
> + reset-names = "audiosys";
> + mediatek,apmixedsys = <&apmixedsys>;
> + mediatek,infracfg = <&infracfg>;
> + mediatek,topckgen = <&topckgen>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> + clocks = <&audsys CLK_AUD_AFE>,
> + <&audsys CLK_AUD_DAC>,
> + <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> + "aud_infra_clk",
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> + };
> + };
> +
> nor_flash: spi@11234000 {
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> @@ -758,12 +887,6 @@
> status = "disable";
> };
>
> - audsys: clock-controller@11210000 {
> - compatible = "mediatek,mt8192-audsys", "syscon";
> - reg = <0 0x11210000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> i2c3: i2c@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
2022-02-22 20:35 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:30 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:30 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 15:35 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:18PM +0800, Allen-KH Cheng wrote:
> > Add audio-related nodes in audsys for mt8192 SoC.
> > Move audsys node in ascending order.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135
> > ++++++++++++++++++++++-
> > 1 file changed, 129 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 08c7c1c772f5..f93fe3779161 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -743,6 +743,135 @@
> > #size-cells = <2>;
> > };
> >
> > + audsys: syscon@11210000 {
> > + compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > + reg = <0 0x11210000 0 0x2000>;
>
> You should mention in the commit message that the address range's
> length was
> increased as well (from 0x1000 to 0x2000).
Hi, I am sorry for missing this thing, I will add info in commit
message in next version.
Many thanks,
Allen
>
> > + #clock-cells = <1>;
> > +
> > + afe: mt8192-afe-pcm {
> > + compatible = "mediatek,mt8192-audio";
> > + interrupts = <GIC_SPI 202
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + resets = <&watchdog 17>;
> > + reset-names = "audiosys";
> > + mediatek,apmixedsys = <&apmixedsys>;
> > + mediatek,infracfg = <&infracfg>;
> > + mediatek,topckgen = <&topckgen>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_AUDIO>;
> > + clocks = <&audsys CLK_AUD_AFE>,
> > + <&audsys CLK_AUD_DAC>,
> > + <&audsys CLK_AUD_DAC_PREDIS>,
> > + <&audsys CLK_AUD_ADC>,
> > + <&audsys CLK_AUD_ADDA6_ADC>,
> > + <&audsys CLK_AUD_22M>,
> > + <&audsys CLK_AUD_24M>,
> > + <&audsys CLK_AUD_APLL_TUNER>,
> > + <&audsys CLK_AUD_APLL2_TUNER>,
> > + <&audsys CLK_AUD_TDM>,
> > + <&audsys CLK_AUD_TML>,
> > + <&audsys CLK_AUD_NLE>,
> > + <&audsys CLK_AUD_DAC_HIRES>,
> > + <&audsys CLK_AUD_ADC_HIRES>,
> > + <&audsys
> > CLK_AUD_ADC_HIRES_TML>,
> > + <&audsys
> > CLK_AUD_ADDA6_ADC_HIRES>,
> > + <&audsys CLK_AUD_3RD_DAC>,
> > + <&audsys
> > CLK_AUD_3RD_DAC_PREDIS>,
> > + <&audsys CLK_AUD_3RD_DAC_TML>,
> > + <&audsys
> > CLK_AUD_3RD_DAC_HIRES>,
> > + <&infracfg CLK_INFRA_AUDIO>,
> > + <&infracfg
> > CLK_INFRA_AUDIO_26M_B>,
> > + <&topckgen CLK_TOP_AUDIO_SEL>,
> > + <&topckgen
> > CLK_TOP_AUD_INTBUS_SEL>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4_D4>,
> > + <&topckgen CLK_TOP_AUD_1_SEL>,
> > + <&topckgen CLK_TOP_APLL1>,
> > + <&topckgen CLK_TOP_AUD_2_SEL>,
> > + <&topckgen CLK_TOP_APLL2>,
> > + <&topckgen
> > CLK_TOP_AUD_ENGEN1_SEL>,
> > + <&topckgen CLK_TOP_APLL1_D4>,
> > + <&topckgen
> > CLK_TOP_AUD_ENGEN2_SEL>,
> > + <&topckgen CLK_TOP_APLL2_D4>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S0_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S1_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S2_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S3_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S4_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S5_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S6_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S7_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S8_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S9_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV0>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV1>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV2>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV3>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV4>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIVB>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV5>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV6>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV7>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV8>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV9>,
> > + <&topckgen
> > CLK_TOP_AUDIO_H_SEL>,
> > + <&clk26m>;
> > + clock-names = "aud_afe_clk",
> > + "aud_dac_clk",
> > + "aud_dac_predis_clk",
> > + "aud_adc_clk",
> > + "aud_adda6_adc_clk",
> > + "aud_apll22m_clk",
> > + "aud_apll24m_clk",
> > + "aud_apll1_tuner_clk",
> > + "aud_apll2_tuner_clk",
> > + "aud_tdm_clk",
> > + "aud_tml_clk",
> > + "aud_nle",
> > + "aud_dac_hires_clk",
> > + "aud_adc_hires_clk",
> > + "aud_adc_hires_tml",
> > + "aud_adda6_adc_hires_clk"
> > ,
> > + "aud_3rd_dac_clk",
> > + "aud_3rd_dac_predis_clk",
> > + "aud_3rd_dac_tml",
> > + "aud_3rd_dac_hires_clk",
> > + "aud_infra_clk",
> > + "aud_infra_26m_clk",
> > + "top_mux_audio",
> > + "top_mux_audio_int",
> > + "top_mainpll_d4_d4",
> > + "top_mux_aud_1",
> > + "top_apll1_ck",
> > + "top_mux_aud_2",
> > + "top_apll2_ck",
> > + "top_mux_aud_eng1",
> > + "top_apll1_d4",
> > + "top_mux_aud_eng2",
> > + "top_apll2_d4",
> > + "top_i2s0_m_sel",
> > + "top_i2s1_m_sel",
> > + "top_i2s2_m_sel",
> > + "top_i2s3_m_sel",
> > + "top_i2s4_m_sel",
> > + "top_i2s5_m_sel",
> > + "top_i2s6_m_sel",
> > + "top_i2s7_m_sel",
> > + "top_i2s8_m_sel",
> > + "top_i2s9_m_sel",
> > + "top_apll12_div0",
> > + "top_apll12_div1",
> > + "top_apll12_div2",
> > + "top_apll12_div3",
> > + "top_apll12_div4",
> > + "top_apll12_divb",
> > + "top_apll12_div5",
> > + "top_apll12_div6",
> > + "top_apll12_div7",
> > + "top_apll12_div8",
> > + "top_apll12_div9",
> > + "top_mux_audio_h",
> > + "top_clk26m_clk";
> > + };
> > + };
> > +
> > nor_flash: spi@11234000 {
> > compatible = "mediatek,mt8192-nor";
> > reg = <0 0x11234000 0 0xe0>;
> > @@ -758,12 +887,6 @@
> > status = "disable";
> > };
> >
> > - audsys: clock-controller@11210000 {
> > - compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > - reg = <0 0x11210000 0 0x1000>;
> > - #clock-cells = <1>;
> > - };
> > -
> > i2c3: i2c@11cb0000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11cb0000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes
@ 2022-02-23 13:30 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:30 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 15:35 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:18PM +0800, Allen-KH Cheng wrote:
> > Add audio-related nodes in audsys for mt8192 SoC.
> > Move audsys node in ascending order.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135
> > ++++++++++++++++++++++-
> > 1 file changed, 129 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 08c7c1c772f5..f93fe3779161 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -743,6 +743,135 @@
> > #size-cells = <2>;
> > };
> >
> > + audsys: syscon@11210000 {
> > + compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > + reg = <0 0x11210000 0 0x2000>;
>
> You should mention in the commit message that the address range's
> length was
> increased as well (from 0x1000 to 0x2000).
Hi, I am sorry for missing this thing, I will add info in commit
message in next version.
Many thanks,
Allen
>
> > + #clock-cells = <1>;
> > +
> > + afe: mt8192-afe-pcm {
> > + compatible = "mediatek,mt8192-audio";
> > + interrupts = <GIC_SPI 202
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + resets = <&watchdog 17>;
> > + reset-names = "audiosys";
> > + mediatek,apmixedsys = <&apmixedsys>;
> > + mediatek,infracfg = <&infracfg>;
> > + mediatek,topckgen = <&topckgen>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_AUDIO>;
> > + clocks = <&audsys CLK_AUD_AFE>,
> > + <&audsys CLK_AUD_DAC>,
> > + <&audsys CLK_AUD_DAC_PREDIS>,
> > + <&audsys CLK_AUD_ADC>,
> > + <&audsys CLK_AUD_ADDA6_ADC>,
> > + <&audsys CLK_AUD_22M>,
> > + <&audsys CLK_AUD_24M>,
> > + <&audsys CLK_AUD_APLL_TUNER>,
> > + <&audsys CLK_AUD_APLL2_TUNER>,
> > + <&audsys CLK_AUD_TDM>,
> > + <&audsys CLK_AUD_TML>,
> > + <&audsys CLK_AUD_NLE>,
> > + <&audsys CLK_AUD_DAC_HIRES>,
> > + <&audsys CLK_AUD_ADC_HIRES>,
> > + <&audsys
> > CLK_AUD_ADC_HIRES_TML>,
> > + <&audsys
> > CLK_AUD_ADDA6_ADC_HIRES>,
> > + <&audsys CLK_AUD_3RD_DAC>,
> > + <&audsys
> > CLK_AUD_3RD_DAC_PREDIS>,
> > + <&audsys CLK_AUD_3RD_DAC_TML>,
> > + <&audsys
> > CLK_AUD_3RD_DAC_HIRES>,
> > + <&infracfg CLK_INFRA_AUDIO>,
> > + <&infracfg
> > CLK_INFRA_AUDIO_26M_B>,
> > + <&topckgen CLK_TOP_AUDIO_SEL>,
> > + <&topckgen
> > CLK_TOP_AUD_INTBUS_SEL>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4_D4>,
> > + <&topckgen CLK_TOP_AUD_1_SEL>,
> > + <&topckgen CLK_TOP_APLL1>,
> > + <&topckgen CLK_TOP_AUD_2_SEL>,
> > + <&topckgen CLK_TOP_APLL2>,
> > + <&topckgen
> > CLK_TOP_AUD_ENGEN1_SEL>,
> > + <&topckgen CLK_TOP_APLL1_D4>,
> > + <&topckgen
> > CLK_TOP_AUD_ENGEN2_SEL>,
> > + <&topckgen CLK_TOP_APLL2_D4>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S0_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S1_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S2_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S3_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S4_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S5_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S6_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S7_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S8_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL_I2S9_M_SEL>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV0>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV1>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV2>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV3>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV4>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIVB>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV5>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV6>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV7>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV8>,
> > + <&topckgen
> > CLK_TOP_APLL12_DIV9>,
> > + <&topckgen
> > CLK_TOP_AUDIO_H_SEL>,
> > + <&clk26m>;
> > + clock-names = "aud_afe_clk",
> > + "aud_dac_clk",
> > + "aud_dac_predis_clk",
> > + "aud_adc_clk",
> > + "aud_adda6_adc_clk",
> > + "aud_apll22m_clk",
> > + "aud_apll24m_clk",
> > + "aud_apll1_tuner_clk",
> > + "aud_apll2_tuner_clk",
> > + "aud_tdm_clk",
> > + "aud_tml_clk",
> > + "aud_nle",
> > + "aud_dac_hires_clk",
> > + "aud_adc_hires_clk",
> > + "aud_adc_hires_tml",
> > + "aud_adda6_adc_hires_clk"
> > ,
> > + "aud_3rd_dac_clk",
> > + "aud_3rd_dac_predis_clk",
> > + "aud_3rd_dac_tml",
> > + "aud_3rd_dac_hires_clk",
> > + "aud_infra_clk",
> > + "aud_infra_26m_clk",
> > + "top_mux_audio",
> > + "top_mux_audio_int",
> > + "top_mainpll_d4_d4",
> > + "top_mux_aud_1",
> > + "top_apll1_ck",
> > + "top_mux_aud_2",
> > + "top_apll2_ck",
> > + "top_mux_aud_eng1",
> > + "top_apll1_d4",
> > + "top_mux_aud_eng2",
> > + "top_apll2_d4",
> > + "top_i2s0_m_sel",
> > + "top_i2s1_m_sel",
> > + "top_i2s2_m_sel",
> > + "top_i2s3_m_sel",
> > + "top_i2s4_m_sel",
> > + "top_i2s5_m_sel",
> > + "top_i2s6_m_sel",
> > + "top_i2s7_m_sel",
> > + "top_i2s8_m_sel",
> > + "top_i2s9_m_sel",
> > + "top_apll12_div0",
> > + "top_apll12_div1",
> > + "top_apll12_div2",
> > + "top_apll12_div3",
> > + "top_apll12_div4",
> > + "top_apll12_divb",
> > + "top_apll12_div5",
> > + "top_apll12_div6",
> > + "top_apll12_div7",
> > + "top_apll12_div8",
> > + "top_apll12_div9",
> > + "top_mux_audio_h",
> > + "top_clk26m_clk";
> > + };
> > + };
> > +
> > nor_flash: spi@11234000 {
> > compatible = "mediatek,mt8192-nor";
> > reg = <0 0x11234000 0 0xe0>;
> > @@ -758,12 +887,6 @@
> > status = "disable";
> > };
> >
> > - audsys: clock-controller@11210000 {
> > - compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > - reg = <0 0x11210000 0 0x1000>;
> > - #clock-cells = <1>;
> > - };
> > -
> > i2c3: i2c@11cb0000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11cb0000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
add infracfg_rst node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f93fe3779161..a935a22babbb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "mediatek,mt8192";
@@ -267,10 +268,23 @@
#clock-cells = <1>;
};
- infracfg: syscon@10001000 {
- compatible = "mediatek,mt8192-infracfg", "syscon";
+ infracfg: infracfg@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+
+ ti,reset-bits = <
+ 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
+ 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
+ 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
+ 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
+ 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
+ >;
+ };
};
pericfg: syscon@10003000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
add infracfg_rst node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f93fe3779161..a935a22babbb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "mediatek,mt8192";
@@ -267,10 +268,23 @@
#clock-cells = <1>;
};
- infracfg: syscon@10001000 {
- compatible = "mediatek,mt8192-infracfg", "syscon";
+ infracfg: infracfg@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+
+ ti,reset-bits = <
+ 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
+ 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
+ 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
+ 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
+ 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
+ >;
+ };
};
pericfg: syscon@10003000 {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
add infracfg_rst node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f93fe3779161..a935a22babbb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "mediatek,mt8192";
@@ -267,10 +268,23 @@
#clock-cells = <1>;
};
- infracfg: syscon@10001000 {
- compatible = "mediatek,mt8192-infracfg", "syscon";
+ infracfg: infracfg@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+
+ ti,reset-bits = <
+ 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
+ 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
+ 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
+ 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
+ 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
+ >;
+ };
};
pericfg: syscon@10003000 {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> add infracfg_rst node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
For v3, please mention that you're adding simple-mfd to allow probing the
ti,syscon-reset node.
After the commit description fix:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f93fe3779161..a935a22babbb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -12,6 +12,7 @@
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>
> / {
> compatible = "mediatek,mt8192";
> @@ -267,10 +268,23 @@
> #clock-cells = <1>;
> };
>
> - infracfg: syscon@10001000 {
> - compatible = "mediatek,mt8192-infracfg", "syscon";
> + infracfg: infracfg@10001000 {
> + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> +
> + infracfg_rst: reset-controller {
> + compatible = "ti,syscon-reset";
> + #reset-cells = <1>;
> +
> + ti,reset-bits = <
> + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> + 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> + 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> + >;
> + };
> };
>
> pericfg: syscon@10003000 {
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> add infracfg_rst node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
For v3, please mention that you're adding simple-mfd to allow probing the
ti,syscon-reset node.
After the commit description fix:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f93fe3779161..a935a22babbb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -12,6 +12,7 @@
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>
> / {
> compatible = "mediatek,mt8192";
> @@ -267,10 +268,23 @@
> #clock-cells = <1>;
> };
>
> - infracfg: syscon@10001000 {
> - compatible = "mediatek,mt8192-infracfg", "syscon";
> + infracfg: infracfg@10001000 {
> + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> +
> + infracfg_rst: reset-controller {
> + compatible = "ti,syscon-reset";
> + #reset-cells = <1>;
> +
> + ti,reset-bits = <
> + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> + 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> + 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> + >;
> + };
> };
>
> pericfg: syscon@10003000 {
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> add infracfg_rst node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
For v3, please mention that you're adding simple-mfd to allow probing the
ti,syscon-reset node.
After the commit description fix:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f93fe3779161..a935a22babbb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -12,6 +12,7 @@
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>
> / {
> compatible = "mediatek,mt8192";
> @@ -267,10 +268,23 @@
> #clock-cells = <1>;
> };
>
> - infracfg: syscon@10001000 {
> - compatible = "mediatek,mt8192-infracfg", "syscon";
> + infracfg: infracfg@10001000 {
> + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> +
> + infracfg_rst: reset-controller {
> + compatible = "ti,syscon-reset";
> + #reset-cells = <1>;
> +
> + ti,reset-bits = <
> + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> + 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> + 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> + >;
> + };
> };
>
> pericfg: syscon@10003000 {
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
2022-02-18 12:55 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:05 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:05 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > add infracfg_rst node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> For v3, please mention that you're adding simple-mfd to allow probing
> the
> ti,syscon-reset node.
>
> After the commit description fix:
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
>
Hi Angelo,
Thanks for reminding, I will update commit message.
Do I need to also change the commit title ?
Best regards,
Allen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> > 1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f93fe3779161..a935a22babbb 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -12,6 +12,7 @@
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > #include <dt-bindings/phy/phy.h>
> > #include <dt-bindings/power/mt8192-power.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> >
> > / {
> > compatible = "mediatek,mt8192";
> > @@ -267,10 +268,23 @@
> > #clock-cells = <1>;
> > };
> >
> > - infracfg: syscon@10001000 {
> > - compatible = "mediatek,mt8192-infracfg",
> > "syscon";
> > + infracfg: infracfg@10001000 {
> > + compatible = "mediatek,mt8192-infracfg",
> > "syscon", "simple-mfd";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > + infracfg_rst: reset-controller {
> > + compatible = "ti,syscon-reset";
> > + #reset-cells = <1>;
> > +
> > + ti,reset-bits = <
> > + 0x120 0 0x124 0 0 0 (ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > + 0x730 12 0x734 12 0 0 (AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > + 0x140 15 0x144 15 0 0 (AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > + 0x730 1 0x734 1 0 0 (ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > + 0x150 5 0x154 5 0 0 (ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > + >;
> > + };
> > };
> >
> > pericfg: syscon@10003000 {
>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-21 13:05 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:05 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > add infracfg_rst node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> For v3, please mention that you're adding simple-mfd to allow probing
> the
> ti,syscon-reset node.
>
> After the commit description fix:
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
>
Hi Angelo,
Thanks for reminding, I will update commit message.
Do I need to also change the commit title ?
Best regards,
Allen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> > 1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f93fe3779161..a935a22babbb 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -12,6 +12,7 @@
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > #include <dt-bindings/phy/phy.h>
> > #include <dt-bindings/power/mt8192-power.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> >
> > / {
> > compatible = "mediatek,mt8192";
> > @@ -267,10 +268,23 @@
> > #clock-cells = <1>;
> > };
> >
> > - infracfg: syscon@10001000 {
> > - compatible = "mediatek,mt8192-infracfg",
> > "syscon";
> > + infracfg: infracfg@10001000 {
> > + compatible = "mediatek,mt8192-infracfg",
> > "syscon", "simple-mfd";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > + infracfg_rst: reset-controller {
> > + compatible = "ti,syscon-reset";
> > + #reset-cells = <1>;
> > +
> > + ti,reset-bits = <
> > + 0x120 0 0x124 0 0 0 (ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > + 0x730 12 0x734 12 0 0 (AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > + 0x140 15 0x144 15 0 0 (AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > + 0x730 1 0x734 1 0 0 (ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > + 0x150 5 0x154 5 0 0 (ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > + >;
> > + };
> > };
> >
> > pericfg: syscon@10003000 {
>
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
2022-02-21 13:05 ` allen-kh.cheng
(?)
@ 2022-02-21 15:20 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-21 15:20 UTC (permalink / raw)
To: allen-kh.cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 21/02/22 14:05, allen-kh.cheng ha scritto:
> On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
>> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
>>> add infracfg_rst node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>
>> For v3, please mention that you're adding simple-mfd to allow probing
>> the
>> ti,syscon-reset node.
>>
>> After the commit description fix:
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
>
> Hi Angelo,
>
> Thanks for reminding, I will update commit message.
>
> Do I need to also change the commit title ?
>
> Best regards,
> Allen
>
Hi Allen,
Please update only the description; the title is fine.
Thank you,
Angelo
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-21 15:20 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-21 15:20 UTC (permalink / raw)
To: allen-kh.cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 21/02/22 14:05, allen-kh.cheng ha scritto:
> On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
>> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
>>> add infracfg_rst node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>
>> For v3, please mention that you're adding simple-mfd to allow probing
>> the
>> ti,syscon-reset node.
>>
>> After the commit description fix:
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
>
> Hi Angelo,
>
> Thanks for reminding, I will update commit message.
>
> Do I need to also change the commit title ?
>
> Best regards,
> Allen
>
Hi Allen,
Please update only the description; the title is fine.
Thank you,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-21 15:20 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-21 15:20 UTC (permalink / raw)
To: allen-kh.cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 21/02/22 14:05, allen-kh.cheng ha scritto:
> On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
>> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
>>> add infracfg_rst node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>
>> For v3, please mention that you're adding simple-mfd to allow probing
>> the
>> ti,syscon-reset node.
>>
>> After the commit description fix:
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
>
> Hi Angelo,
>
> Thanks for reminding, I will update commit message.
>
> Do I need to also change the commit title ?
>
> Best regards,
> Allen
>
Hi Allen,
Please update only the description; the title is fine.
Thank you,
Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
2022-02-21 15:20 ` AngeloGioacchino Del Regno
@ 2022-02-22 5:55 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-22 5:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Mon, 2022-02-21 at 16:20 +0100, AngeloGioacchino Del Regno wrote:
> Il 21/02/22 14:05, allen-kh.cheng ha scritto:
> > On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > > > add infracfg_rst node for mt8192 SoC.
> > > >
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > >
> > > For v3, please mention that you're adding simple-mfd to allow
> > > probing
> > > the
> > > ti,syscon-reset node.
> > >
> > > After the commit description fix:
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > >
> >
> > Hi Angelo,
> >
> > Thanks for reminding, I will update commit message.
> >
> > Do I need to also change the commit title ?
> >
> > Best regards,
> > Allen
> >
>
> Hi Allen,
>
> Please update only the description; the title is fine.
>
> Thank you,
> Angelo
Hi Angelo,
Ok, No problem.
Many thanks,
Allen
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node
@ 2022-02-22 5:55 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-22 5:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Mon, 2022-02-21 at 16:20 +0100, AngeloGioacchino Del Regno wrote:
> Il 21/02/22 14:05, allen-kh.cheng ha scritto:
> > On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > > > add infracfg_rst node for mt8192 SoC.
> > > >
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > >
> > > For v3, please mention that you're adding simple-mfd to allow
> > > probing
> > > the
> > > ti,syscon-reset node.
> > >
> > > After the commit description fix:
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > >
> >
> > Hi Angelo,
> >
> > Thanks for reminding, I will update commit message.
> >
> > Do I need to also change the commit title ?
> >
> > Best regards,
> > Allen
> >
>
> Hi Allen,
>
> Please update only the description; the title is fine.
>
> Thank you,
> Angelo
Hi Angelo,
Ok, No problem.
Many thanks,
Allen
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 10/23] arm64: dts: mt8192: Add PCIe node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add PCIe node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a935a22babbb..4533c794effc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -886,6 +886,44 @@
};
};
+ pcie: pcie@11230000 {
+ compatible = "mediatek,mt8192-pcie";
+ device_type = "pci";
+ reg = <0 0x11230000 0 0x2000>;
+ reg-names = "pcie-mac";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
+ <&infracfg CLK_INFRA_PCIE_TL_96M>,
+ <&infracfg CLK_INFRA_PCIE_TL_32K>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+ <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
+ <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+ "obff_ck0", "axi_ck0", "pipe_ck0";
+ assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+ resets = <&infracfg_rst 2>,
+ <&infracfg_rst 3>;
+ reset-names = "phy", "mac";
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+ <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 10/23] arm64: dts: mt8192: Add PCIe node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add PCIe node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a935a22babbb..4533c794effc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -886,6 +886,44 @@
};
};
+ pcie: pcie@11230000 {
+ compatible = "mediatek,mt8192-pcie";
+ device_type = "pci";
+ reg = <0 0x11230000 0 0x2000>;
+ reg-names = "pcie-mac";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
+ <&infracfg CLK_INFRA_PCIE_TL_96M>,
+ <&infracfg CLK_INFRA_PCIE_TL_32K>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+ <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
+ <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+ "obff_ck0", "axi_ck0", "pipe_ck0";
+ assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+ resets = <&infracfg_rst 2>,
+ <&infracfg_rst 3>;
+ reset-names = "phy", "mac";
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+ <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 10/23] arm64: dts: mt8192: Add PCIe node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add PCIe node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a935a22babbb..4533c794effc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -886,6 +886,44 @@
};
};
+ pcie: pcie@11230000 {
+ compatible = "mediatek,mt8192-pcie";
+ device_type = "pci";
+ reg = <0 0x11230000 0 0x2000>;
+ reg-names = "pcie-mac";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
+ <&infracfg CLK_INFRA_PCIE_TL_96M>,
+ <&infracfg CLK_INFRA_PCIE_TL_32K>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+ <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
+ <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+ "obff_ck0", "axi_ck0", "pipe_ck0";
+ assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+ resets = <&infracfg_rst 2>,
+ <&infracfg_rst 3>;
+ reset-names = "phy", "mac";
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+ <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread
* [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Correct nor_flash status of mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 4533c794effc..f51fd0f6c356 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -936,7 +936,7 @@
assigned-clock-parents = <&clk26m>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disable";
+ status = "disabled";
};
i2c3: i2c@11cb0000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Correct nor_flash status of mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 4533c794effc..f51fd0f6c356 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -936,7 +936,7 @@
assigned-clock-parents = <&clk26m>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disable";
+ status = "disabled";
};
i2c3: i2c@11cb0000 {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Correct nor_flash status of mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 4533c794effc..f51fd0f6c356 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -936,7 +936,7 @@
assigned-clock-parents = <&clk26m>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disable";
+ status = "disabled";
};
i2c3: i2c@11cb0000 {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Correct nor_flash status of mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
The commit message should be:
arm64: dts: mt8192: Fix nor_flash status disable typo
...and it should also have a Fixes: tag.
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 4533c794effc..f51fd0f6c356 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -936,7 +936,7 @@
> assigned-clock-parents = <&clk26m>;
> #address-cells = <1>;
> #size-cells = <0>;
> - status = "disable";
> + status = "disabled";
> };
>
> i2c3: i2c@11cb0000 {
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Correct nor_flash status of mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
The commit message should be:
arm64: dts: mt8192: Fix nor_flash status disable typo
...and it should also have a Fixes: tag.
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 4533c794effc..f51fd0f6c356 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -936,7 +936,7 @@
> assigned-clock-parents = <&clk26m>;
> #address-cells = <1>;
> #size-cells = <0>;
> - status = "disable";
> + status = "disabled";
> };
>
> i2c3: i2c@11cb0000 {
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Correct nor_flash status of mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
The commit message should be:
arm64: dts: mt8192: Fix nor_flash status disable typo
...and it should also have a Fixes: tag.
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 4533c794effc..f51fd0f6c356 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -936,7 +936,7 @@
> assigned-clock-parents = <&clk26m>;
> #address-cells = <1>;
> #size-cells = <0>;
> - status = "disable";
> + status = "disabled";
> };
>
> i2c3: i2c@11cb0000 {
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
2022-02-18 12:55 ` AngeloGioacchino Del Regno
@ 2022-02-21 12:49 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:49 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Correct nor_flash status of mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> The commit message should be:
> arm64: dts: mt8192: Fix nor_flash status disable typo
>
> ...and it should also have a Fixes: tag.
>
Hi Angelo,
Thanks for your reminding, this's my neglect.
I will update commit message.
Best regards,
Allen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 4533c794effc..f51fd0f6c356 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -936,7 +936,7 @@
> > assigned-clock-parents = <&clk26m>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - status = "disable";
> > + status = "disabled";
> > };
> >
> > i2c3: i2c@11cb0000 {
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192
@ 2022-02-21 12:49 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:49 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Correct nor_flash status of mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> The commit message should be:
> arm64: dts: mt8192: Fix nor_flash status disable typo
>
> ...and it should also have a Fixes: tag.
>
Hi Angelo,
Thanks for your reminding, this's my neglect.
I will update commit message.
Best regards,
Allen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 4533c794effc..f51fd0f6c356 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -936,7 +936,7 @@
> > assigned-clock-parents = <&clk26m>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - status = "disable";
> > + status = "disabled";
> > };
> >
> > i2c3: i2c@11cb0000 {
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add efuse node for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f51fd0f6c356..094805db395b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -939,6 +939,20 @@
status = "disabled";
};
+ efuse: efuse@11c10000 {
+ compatible = "mediatek,efuse";
+ reg = <0 0x11c10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ lvts_e_data1: data1 {
+ reg = <0x1C0 0x58>;
+ };
+ svs_calibration: calib@580 {
+ reg = <0x580 0x68>;
+ };
+ };
+
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add efuse node for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f51fd0f6c356..094805db395b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -939,6 +939,20 @@
status = "disabled";
};
+ efuse: efuse@11c10000 {
+ compatible = "mediatek,efuse";
+ reg = <0 0x11c10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ lvts_e_data1: data1 {
+ reg = <0x1C0 0x58>;
+ };
+ svs_calibration: calib@580 {
+ reg = <0x580 0x68>;
+ };
+ };
+
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add efuse node for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f51fd0f6c356..094805db395b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -939,6 +939,20 @@
status = "disabled";
};
+ efuse: efuse@11c10000 {
+ compatible = "mediatek,efuse";
+ reg = <0 0x11c10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ lvts_e_data1: data1 {
+ reg = <0x1C0 0x58>;
+ };
+ svs_calibration: calib@580 {
+ reg = <0x580 0x68>;
+ };
+ };
+
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add efuse node for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f51fd0f6c356..094805db395b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -939,6 +939,20 @@
> status = "disabled";
> };
>
> + efuse: efuse@11c10000 {
> + compatible = "mediatek,efuse";
> + reg = <0 0x11c10000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + lvts_e_data1: data1 {
lvts_e_data1: lvts_data1@1c0 {
reg = <0x1c0 0x58>;
Please write hex with lower case characters.
> + reg = <0x1C0 0x58>;
> + };
> + svs_calibration: calib@580 {
> + reg = <0x580 0x68>;
> + };
> + };
> +
> i2c3: i2c@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add efuse node for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f51fd0f6c356..094805db395b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -939,6 +939,20 @@
> status = "disabled";
> };
>
> + efuse: efuse@11c10000 {
> + compatible = "mediatek,efuse";
> + reg = <0 0x11c10000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + lvts_e_data1: data1 {
lvts_e_data1: lvts_data1@1c0 {
reg = <0x1c0 0x58>;
Please write hex with lower case characters.
> + reg = <0x1C0 0x58>;
> + };
> + svs_calibration: calib@580 {
> + reg = <0x580 0x68>;
> + };
> + };
> +
> i2c3: i2c@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add efuse node for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f51fd0f6c356..094805db395b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -939,6 +939,20 @@
> status = "disabled";
> };
>
> + efuse: efuse@11c10000 {
> + compatible = "mediatek,efuse";
> + reg = <0 0x11c10000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + lvts_e_data1: data1 {
lvts_e_data1: lvts_data1@1c0 {
reg = <0x1c0 0x58>;
Please write hex with lower case characters.
> + reg = <0x1C0 0x58>;
> + };
> + svs_calibration: calib@580 {
> + reg = <0x580 0x68>;
> + };
> + };
> +
> i2c3: i2c@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
2022-02-18 12:55 ` AngeloGioacchino Del Regno
@ 2022-02-21 12:53 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:53 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add efuse node for mt8192 SoC
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f51fd0f6c356..094805db395b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -939,6 +939,20 @@
> > status = "disabled";
> > };
> >
> > + efuse: efuse@11c10000 {
> > + compatible = "mediatek,efuse";
> > + reg = <0 0x11c10000 0 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + lvts_e_data1: data1 {
>
> lvts_e_data1: lvts_data1@1c0 {
> reg = <0x1c0 0x58>;
>
> Please write hex with lower case characters.
Hi Angelo,
Sorry for my neglect and will correct this in next version
Many thanks,
Allen
>
> > + reg = <0x1C0 0x58>;
> > + };
> > + svs_calibration: calib@580 {
> > + reg = <0x580 0x68>;
> > + };
> > + };
> > +
> > i2c3: i2c@11cb0000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11cb0000 0 0x1000>,
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node
@ 2022-02-21 12:53 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:53 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add efuse node for mt8192 SoC
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f51fd0f6c356..094805db395b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -939,6 +939,20 @@
> > status = "disabled";
> > };
> >
> > + efuse: efuse@11c10000 {
> > + compatible = "mediatek,efuse";
> > + reg = <0 0x11c10000 0 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + lvts_e_data1: data1 {
>
> lvts_e_data1: lvts_data1@1c0 {
> reg = <0x1c0 0x58>;
>
> Please write hex with lower case characters.
Hi Angelo,
Sorry for my neglect and will correct this in next version
Many thanks,
Allen
>
> > + reg = <0x1C0 0x58>;
> > + };
> > + svs_calibration: calib@580 {
> > + reg = <0x580 0x68>;
> > + };
> > + };
> > +
> > i2c3: i2c@11cb0000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11cb0000 0 0x1000>,
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add mmc nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++---
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 094805db395b..cfc2db501108 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1154,10 +1154,38 @@
#clock-cells = <1>;
};
- msdc: clock-controller@11f60000 {
- compatible = "mediatek,mt8192-msdc";
- reg = <0 0x11f60000 0 0x1000>;
- #clock-cells = <1>;
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "axi_cg", "ahb_cg", "pclk_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "axi_cg", "ahb_cg", "pclk_cg";
+ status = "disabled";
};
mfgcfg: clock-controller@13fbf000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add mmc nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++---
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 094805db395b..cfc2db501108 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1154,10 +1154,38 @@
#clock-cells = <1>;
};
- msdc: clock-controller@11f60000 {
- compatible = "mediatek,mt8192-msdc";
- reg = <0 0x11f60000 0 0x1000>;
- #clock-cells = <1>;
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "axi_cg", "ahb_cg", "pclk_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "axi_cg", "ahb_cg", "pclk_cg";
+ status = "disabled";
};
mfgcfg: clock-controller@13fbf000 {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add mmc nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++---
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 094805db395b..cfc2db501108 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1154,10 +1154,38 @@
#clock-cells = <1>;
};
- msdc: clock-controller@11f60000 {
- compatible = "mediatek,mt8192-msdc";
- reg = <0 0x11f60000 0 0x1000>;
- #clock-cells = <1>;
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "axi_cg", "ahb_cg", "pclk_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "axi_cg", "ahb_cg", "pclk_cg";
+ status = "disabled";
};
mfgcfg: clock-controller@13fbf000 {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add mmc nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++---
> 1 file changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 094805db395b..cfc2db501108 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1154,10 +1154,38 @@
> #clock-cells = <1>;
> };
>
> - msdc: clock-controller@11f60000 {
> - compatible = "mediatek,mt8192-msdc";
> - reg = <0 0x11f60000 0 0x1000>;
> - #clock-cells = <1>;
> + mmc0: mmc@11f60000 {
> + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11f60000 0 0x1000>,
> + <0 0x11f50000 0 0x1000>;
This fits on a single line:
reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> + <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> + <&msdc_top CLK_MSDC_TOP_AXI>,
> + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> + <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
> + clock-names = "source", "hclk", "source_cg", "sys_cg",
> + "axi_cg", "ahb_cg", "pclk_cg";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11f70000 {
> + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11f70000 0 0x1000>,
> + <0 0x11c70000 0 0x1000>;
Same here.
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> + <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> + <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> + <&msdc_top CLK_MSDC_TOP_AXI>,
> + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> + <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
> + clock-names = "source", "hclk", "source_cg", "sys_cg",
> + "axi_cg", "ahb_cg", "pclk_cg";
> + status = "disabled";
> };
>
> mfgcfg: clock-controller@13fbf000 {
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add mmc nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++---
> 1 file changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 094805db395b..cfc2db501108 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1154,10 +1154,38 @@
> #clock-cells = <1>;
> };
>
> - msdc: clock-controller@11f60000 {
> - compatible = "mediatek,mt8192-msdc";
> - reg = <0 0x11f60000 0 0x1000>;
> - #clock-cells = <1>;
> + mmc0: mmc@11f60000 {
> + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11f60000 0 0x1000>,
> + <0 0x11f50000 0 0x1000>;
This fits on a single line:
reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> + <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> + <&msdc_top CLK_MSDC_TOP_AXI>,
> + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> + <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
> + clock-names = "source", "hclk", "source_cg", "sys_cg",
> + "axi_cg", "ahb_cg", "pclk_cg";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11f70000 {
> + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11f70000 0 0x1000>,
> + <0 0x11c70000 0 0x1000>;
Same here.
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> + <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> + <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> + <&msdc_top CLK_MSDC_TOP_AXI>,
> + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> + <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
> + clock-names = "source", "hclk", "source_cg", "sys_cg",
> + "axi_cg", "ahb_cg", "pclk_cg";
> + status = "disabled";
> };
>
> mfgcfg: clock-controller@13fbf000 {
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add mmc nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++---
> 1 file changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 094805db395b..cfc2db501108 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1154,10 +1154,38 @@
> #clock-cells = <1>;
> };
>
> - msdc: clock-controller@11f60000 {
> - compatible = "mediatek,mt8192-msdc";
> - reg = <0 0x11f60000 0 0x1000>;
> - #clock-cells = <1>;
> + mmc0: mmc@11f60000 {
> + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11f60000 0 0x1000>,
> + <0 0x11f50000 0 0x1000>;
This fits on a single line:
reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> + <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> + <&msdc_top CLK_MSDC_TOP_AXI>,
> + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> + <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
> + clock-names = "source", "hclk", "source_cg", "sys_cg",
> + "axi_cg", "ahb_cg", "pclk_cg";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11f70000 {
> + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11f70000 0 0x1000>,
> + <0 0x11c70000 0 0x1000>;
Same here.
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> + <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> + <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> + <&msdc_top CLK_MSDC_TOP_AXI>,
> + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> + <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
> + clock-names = "source", "hclk", "source_cg", "sys_cg",
> + "axi_cg", "ahb_cg", "pclk_cg";
> + status = "disabled";
> };
>
> mfgcfg: clock-controller@13fbf000 {
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
2022-02-18 12:55 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:08 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:08 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add mmc nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36
> > +++++++++++++++++++++---
> > 1 file changed, 32 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 094805db395b..cfc2db501108 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1154,10 +1154,38 @@
> > #clock-cells = <1>;
> > };
> >
> > - msdc: clock-controller@11f60000 {
> > - compatible = "mediatek,mt8192-msdc";
> > - reg = <0 0x11f60000 0 0x1000>;
> > - #clock-cells = <1>;
> > + mmc0: mmc@11f60000 {
> > + compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11f60000 0 0x1000>,
> > + <0 0x11f50000 0 0x1000>;
>
> This fits on a single line:
> reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0
> 0x1000>;
>
Hi Angelo,
This is my neglect and will correct this in next version.
Many thanks,
Allen
> > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> > + <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> > + <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> > + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > + <&msdc_top CLK_MSDC_TOP_AXI>,
> > + <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> > + <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
> > + clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > + "axi_cg", "ahb_cg", "pclk_cg";
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@11f70000 {
> > + compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11f70000 0 0x1000>,
> > + <0 0x11c70000 0 0x1000>;
>
> Same here.
>
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> > + <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> > + <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> > + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > + <&msdc_top CLK_MSDC_TOP_AXI>,
> > + <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> > + <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
> > + clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > + "axi_cg", "ahb_cg", "pclk_cg";
> > + status = "disabled";
> > };
> >
> > mfgcfg: clock-controller@13fbf000 {
>
>
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes
@ 2022-02-21 13:08 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:08 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add mmc nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36
> > +++++++++++++++++++++---
> > 1 file changed, 32 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 094805db395b..cfc2db501108 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1154,10 +1154,38 @@
> > #clock-cells = <1>;
> > };
> >
> > - msdc: clock-controller@11f60000 {
> > - compatible = "mediatek,mt8192-msdc";
> > - reg = <0 0x11f60000 0 0x1000>;
> > - #clock-cells = <1>;
> > + mmc0: mmc@11f60000 {
> > + compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11f60000 0 0x1000>,
> > + <0 0x11f50000 0 0x1000>;
>
> This fits on a single line:
> reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0
> 0x1000>;
>
Hi Angelo,
This is my neglect and will correct this in next version.
Many thanks,
Allen
> > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> > + <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> > + <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> > + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > + <&msdc_top CLK_MSDC_TOP_AXI>,
> > + <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> > + <&msdc_top CLK_MSDC_TOP_P_MSDC0>;
> > + clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > + "axi_cg", "ahb_cg", "pclk_cg";
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@11f70000 {
> > + compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11f70000 0 0x1000>,
> > + <0 0x11c70000 0 0x1000>;
>
> Same here.
>
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> > + <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> > + <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> > + <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > + <&msdc_top CLK_MSDC_TOP_AXI>,
> > + <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>,
> > + <&msdc_top CLK_MSDC_TOP_P_MSDC1>;
> > + clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > + "axi_cg", "ahb_cg", "pclk_cg";
> > + status = "disabled";
> > };
> >
> > mfgcfg: clock-controller@13fbf000 {
>
>
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add mipi_tx node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cfc2db501108..f5e5af949f19 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1114,6 +1114,16 @@
};
};
+ mipi_tx0: mipi-dphy@11e50000 {
+ compatible = "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11e50000 0 0x1000>;
+ clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ };
+
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add mipi_tx node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cfc2db501108..f5e5af949f19 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1114,6 +1114,16 @@
};
};
+ mipi_tx0: mipi-dphy@11e50000 {
+ compatible = "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11e50000 0 0x1000>;
+ clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ };
+
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add mipi_tx node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cfc2db501108..f5e5af949f19 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1114,6 +1114,16 @@
};
};
+ mipi_tx0: mipi-dphy@11e50000 {
+ compatible = "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11e50000 0 0x1000>;
+ clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ };
+
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add mipi_tx node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cfc2db501108..f5e5af949f19 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1114,6 +1114,16 @@
> };
> };
>
> + mipi_tx0: mipi-dphy@11e50000 {
> + compatible = "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11e50000 0 0x1000>;
> + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
Please, disable this node by default, as this is something that may be
enabled for some machine, but disabled for the other.
status = "disabled";
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add mipi_tx node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cfc2db501108..f5e5af949f19 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1114,6 +1114,16 @@
> };
> };
>
> + mipi_tx0: mipi-dphy@11e50000 {
> + compatible = "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11e50000 0 0x1000>;
> + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
Please, disable this node by default, as this is something that may be
enabled for some machine, but disabled for the other.
status = "disabled";
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-18 12:55 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:55 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add mipi_tx node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cfc2db501108..f5e5af949f19 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1114,6 +1114,16 @@
> };
> };
>
> + mipi_tx0: mipi-dphy@11e50000 {
> + compatible = "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11e50000 0 0x1000>;
> + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
Please, disable this node by default, as this is something that may be
enabled for some machine, but disabled for the other.
status = "disabled";
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
2022-02-18 12:55 ` AngeloGioacchino Del Regno
@ 2022-02-21 12:43 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:43 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add mipi_tx node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> > };
> > };
> >
> > + mipi_tx0: mipi-dphy@11e50000 {
> > + compatible = "mediatek,mt8183-mipi-tx";
> > + reg = <0 0x11e50000 0 0x1000>;
> > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > + clock-names = "ref_clk";
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clock-output-names = "mipi_tx0_pll";
>
> Please, disable this node by default, as this is something that may
> be
> enabled for some machine, but disabled for the other.
>
> status = "disabled";
>
Hi Angelo,
Thank you for your suggestion.
I will add disabled status for mipi_tx node.
Best regards,
Allen
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
>
>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-21 12:43 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 12:43 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add mipi_tx node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> > };
> > };
> >
> > + mipi_tx0: mipi-dphy@11e50000 {
> > + compatible = "mediatek,mt8183-mipi-tx";
> > + reg = <0 0x11e50000 0 0x1000>;
> > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > + clock-names = "ref_clk";
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clock-output-names = "mipi_tx0_pll";
>
> Please, disable this node by default, as this is something that may
> be
> enabled for some machine, but disabled for the other.
>
> status = "disabled";
>
Hi Angelo,
Thank you for your suggestion.
I will add disabled status for mipi_tx node.
Best regards,
Allen
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 21:26 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 21:26 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cfc2db501108..f5e5af949f19 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1114,6 +1114,16 @@
> };
> };
>
> + mipi_tx0: mipi-dphy@11e50000 {
According to Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml, this
node's name should be dsi-phy, not mipi-dphy.
> + compatible = "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11e50000 0 0x1000>;
> + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-22 21:26 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 21:26 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cfc2db501108..f5e5af949f19 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1114,6 +1114,16 @@
> };
> };
>
> + mipi_tx0: mipi-dphy@11e50000 {
According to Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml, this
node's name should be dsi-phy, not mipi-dphy.
> + compatible = "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11e50000 0 0x1000>;
> + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-22 21:26 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 21:26 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cfc2db501108..f5e5af949f19 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1114,6 +1114,16 @@
> };
> };
>
> + mipi_tx0: mipi-dphy@11e50000 {
According to Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml, this
node's name should be dsi-phy, not mipi-dphy.
> + compatible = "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11e50000 0 0x1000>;
> + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
> + };
> +
> i2c0: i2c@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
2022-02-22 21:26 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:32 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:32 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 16:26 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> > };
> > };
> >
> > + mipi_tx0: mipi-dphy@11e50000 {
>
> According to Documentation/devicetree/bindings/phy/mediatek,dsi-
> phy.yaml, this
> node's name should be dsi-phy, not mipi-dphy.
>
Hi Nícolas
I will change to the below
mipi_tx0: dsi-phy@11e50000
Thanks.
> > + compatible = "mediatek,mt8183-mipi-tx";
> > + reg = <0 0x11e50000 0 0x1000>;
> > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > + clock-names = "ref_clk";
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clock-output-names = "mipi_tx0_pll";
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-23 13:32 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:32 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 16:26 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> > };
> > };
> >
> > + mipi_tx0: mipi-dphy@11e50000 {
>
> According to Documentation/devicetree/bindings/phy/mediatek,dsi-
> phy.yaml, this
> node's name should be dsi-phy, not mipi-dphy.
>
Hi Nícolas
I will change to the below
mipi_tx0: dsi-phy@11e50000
Thanks.
> > + compatible = "mediatek,mt8183-mipi-tx";
> > + reg = <0 0x11e50000 0 0x1000>;
> > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > + clock-names = "ref_clk";
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clock-output-names = "mipi_tx0_pll";
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
2022-02-22 21:26 ` Nícolas F. R. A. Prado
(?)
@ 2022-02-25 20:38 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-25 20:38 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, Feb 22, 2022 at 04:27:03PM -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> > };
> > };
> >
> > + mipi_tx0: mipi-dphy@11e50000 {
>
> According to Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml, this
> node's name should be dsi-phy, not mipi-dphy.
>
> > + compatible = "mediatek,mt8183-mipi-tx";
> > + reg = <0 0x11e50000 0 0x1000>;
> > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > + clock-names = "ref_clk";
Also, this clock-names should be dropped [1].
[1] https://lore.kernel.org/all/CAAOTY_84OF71QK6M5JT1M5YAFKED_xWVpx8B8t859OsVxE0cfQ@mail.gmail.com/
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clock-output-names = "mipi_tx0_pll";
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-25 20:38 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-25 20:38 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, Feb 22, 2022 at 04:27:03PM -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> > };
> > };
> >
> > + mipi_tx0: mipi-dphy@11e50000 {
>
> According to Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml, this
> node's name should be dsi-phy, not mipi-dphy.
>
> > + compatible = "mediatek,mt8183-mipi-tx";
> > + reg = <0 0x11e50000 0 0x1000>;
> > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > + clock-names = "ref_clk";
Also, this clock-names should be dropped [1].
[1] https://lore.kernel.org/all/CAAOTY_84OF71QK6M5JT1M5YAFKED_xWVpx8B8t859OsVxE0cfQ@mail.gmail.com/
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clock-output-names = "mipi_tx0_pll";
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
@ 2022-02-25 20:38 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-25 20:38 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, Feb 22, 2022 at 04:27:03PM -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> > };
> > };
> >
> > + mipi_tx0: mipi-dphy@11e50000 {
>
> According to Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml, this
> node's name should be dsi-phy, not mipi-dphy.
>
> > + compatible = "mediatek,mt8183-mipi-tx";
> > + reg = <0 0x11e50000 0 0x1000>;
> > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > + clock-names = "ref_clk";
Also, this clock-names should be dropped [1].
[1] https://lore.kernel.org/all/CAAOTY_84OF71QK6M5JT1M5YAFKED_xWVpx8B8t859OsVxE0cfQ@mail.gmail.com/
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clock-output-names = "mipi_tx0_pll";
> > + };
> > +
> > i2c0: i2c@11f00000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11f00000 0 0x1000>,
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add m4u and smi nodes for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++
1 file changed, 191 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f5e5af949f19..40887120fdb3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
@@ -1210,24 +1211,114 @@
#clock-cells = <1>;
};
+ smi_common: smi@14002000 {
+ compatible = "mediatek,mt8192-smi-common";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb0: larb@14003000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb1: larb@14004000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ iommu0: m4u@1401d000 {
+ compatible = "mediatek,mt8192-m4u";
+ reg = <0 0x1401d000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb1 &larb2
+ &larb4 &larb5 &larb7
+ &larb9 &larb11 &larb13
+ &larb14 &larb16 &larb17
+ &larb18 &larb19 &larb20>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ #iommu-cells = <1>;
+ };
+
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@1502e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1502e000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+ };
+
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
+ larb11: larb@1582e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1582e000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+ };
+
+ larb5: larb@1600d000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1600d000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@1602e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1602e000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+ <&vdecsys CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
@@ -1240,12 +1331,79 @@
#clock-cells = <1>;
};
+ larb7: larb@17010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_SET0_LARB>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@1a001000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB13>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@1a002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@1a00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a00f000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ mediatek,smi-id = <16>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@1a010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb18: larb@1a011000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a011000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+ <&camsys_rawc CLK_CAM_RAWC_CAM>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+ };
+
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
@@ -1270,10 +1428,43 @@
#clock-cells = <1>;
};
+ larb20: larb@1b00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b00f000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB20>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
+ larb19: larb@1b10f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b10f000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB19>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb2: larb@1f002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1f002000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mdpsys CLK_MDP_SMI0>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+ };
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add m4u and smi nodes for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++
1 file changed, 191 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f5e5af949f19..40887120fdb3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
@@ -1210,24 +1211,114 @@
#clock-cells = <1>;
};
+ smi_common: smi@14002000 {
+ compatible = "mediatek,mt8192-smi-common";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb0: larb@14003000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb1: larb@14004000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ iommu0: m4u@1401d000 {
+ compatible = "mediatek,mt8192-m4u";
+ reg = <0 0x1401d000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb1 &larb2
+ &larb4 &larb5 &larb7
+ &larb9 &larb11 &larb13
+ &larb14 &larb16 &larb17
+ &larb18 &larb19 &larb20>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ #iommu-cells = <1>;
+ };
+
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@1502e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1502e000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+ };
+
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
+ larb11: larb@1582e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1582e000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+ };
+
+ larb5: larb@1600d000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1600d000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@1602e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1602e000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+ <&vdecsys CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
@@ -1240,12 +1331,79 @@
#clock-cells = <1>;
};
+ larb7: larb@17010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_SET0_LARB>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@1a001000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB13>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@1a002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@1a00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a00f000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ mediatek,smi-id = <16>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@1a010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb18: larb@1a011000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a011000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+ <&camsys_rawc CLK_CAM_RAWC_CAM>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+ };
+
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
@@ -1270,10 +1428,43 @@
#clock-cells = <1>;
};
+ larb20: larb@1b00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b00f000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB20>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
+ larb19: larb@1b10f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b10f000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB19>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb2: larb@1f002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1f002000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mdpsys CLK_MDP_SMI0>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+ };
};
};
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add m4u and smi nodes for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++
1 file changed, 191 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f5e5af949f19..40887120fdb3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
@@ -1210,24 +1211,114 @@
#clock-cells = <1>;
};
+ smi_common: smi@14002000 {
+ compatible = "mediatek,mt8192-smi-common";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb0: larb@14003000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb1: larb@14004000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ iommu0: m4u@1401d000 {
+ compatible = "mediatek,mt8192-m4u";
+ reg = <0 0x1401d000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb1 &larb2
+ &larb4 &larb5 &larb7
+ &larb9 &larb11 &larb13
+ &larb14 &larb16 &larb17
+ &larb18 &larb19 &larb20>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ #iommu-cells = <1>;
+ };
+
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@1502e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1502e000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+ };
+
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
+ larb11: larb@1582e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1582e000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+ };
+
+ larb5: larb@1600d000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1600d000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@1602e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1602e000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+ <&vdecsys CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
@@ -1240,12 +1331,79 @@
#clock-cells = <1>;
};
+ larb7: larb@17010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_SET0_LARB>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@1a001000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB13>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@1a002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@1a00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a00f000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ mediatek,smi-id = <16>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@1a010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb18: larb@1a011000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a011000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+ <&camsys_rawc CLK_CAM_RAWC_CAM>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+ };
+
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
@@ -1270,10 +1428,43 @@
#clock-cells = <1>;
};
+ larb20: larb@1b00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b00f000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB20>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
+ larb19: larb@1b10f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b10f000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB19>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb2: larb@1f002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1f002000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mdpsys CLK_MDP_SMI0>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+ };
};
};
--
2.18.0
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add m4u and smi nodes for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++
> 1 file changed, 191 insertions(+)
>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add m4u and smi nodes for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++
> 1 file changed, 191 insertions(+)
>
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^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add m4u and smi nodes for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++
> 1 file changed, 191 insertions(+)
>
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 21:48 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 21:48 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> + larb16: larb@1a00f000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a00f000 0 0x1000>;
> + mediatek,larb-id = <16>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> + clock-names = "apb", "smi";
> + mediatek,smi-id = <16>;
This mediatek,smi-id property isn't handled in the driver or mentioned in the
dt-binding, and seems redundant to mediatek,larb-id. So just drop it.
Other than that,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-22 21:48 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 21:48 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> + larb16: larb@1a00f000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a00f000 0 0x1000>;
> + mediatek,larb-id = <16>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> + clock-names = "apb", "smi";
> + mediatek,smi-id = <16>;
This mediatek,smi-id property isn't handled in the driver or mentioned in the
dt-binding, and seems redundant to mediatek,larb-id. So just drop it.
Other than that,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-22 21:48 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 21:48 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> + larb16: larb@1a00f000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a00f000 0 0x1000>;
> + mediatek,larb-id = <16>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> + clock-names = "apb", "smi";
> + mediatek,smi-id = <16>;
This mediatek,smi-id property isn't handled in the driver or mentioned in the
dt-binding, and seems redundant to mediatek,larb-id. So just drop it.
Other than that,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
2022-02-22 21:48 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:34 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:34 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 16:48 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> > + larb16: larb@1a00f000 {
> > + compatible = "mediatek,mt8192-smi-larb";
> > + reg = <0 0x1a00f000 0 0x1000>;
> > + mediatek,larb-id = <16>;
> > + mediatek,smi = <&smi_common>;
> > + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> > + <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> > + clock-names = "apb", "smi";
> > + mediatek,smi-id = <16>;
>
> This mediatek,smi-id property isn't handled in the driver or
> mentioned in the
> dt-binding, and seems redundant to mediatek,larb-id. So just drop it.
>
> Other than that,
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
I will drop this from series. thanks.
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-23 13:34 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:34 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 16:48 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> > + larb16: larb@1a00f000 {
> > + compatible = "mediatek,mt8192-smi-larb";
> > + reg = <0 0x1a00f000 0 0x1000>;
> > + mediatek,larb-id = <16>;
> > + mediatek,smi = <&smi_common>;
> > + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> > + <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> > + clock-names = "apb", "smi";
> > + mediatek,smi-id = <16>;
>
> This mediatek,smi-id property isn't handled in the driver or
> mentioned in the
> dt-binding, and seems redundant to mediatek,larb-id. So just drop it.
>
> Other than that,
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
I will drop this from series. thanks.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-25 23:06 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-25 23:06 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, AngeloGioacchino Del Regno
Hi Allen,
actually there's one other thing, please see below.
On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> + iommu0: m4u@1401d000 {
> + compatible = "mediatek,mt8192-m4u";
> + reg = <0 0x1401d000 0 0x1000>;
> + mediatek,larbs = <&larb0 &larb1 &larb2
> + &larb4 &larb5 &larb7
> + &larb9 &larb11 &larb13
> + &larb14 &larb16 &larb17
> + &larb18 &larb19 &larb20>;
I just sent a patch [1] fixing the formatting of the mediatek,larbs properties
on other Mediatek Devicetrees. So please do the same here so we can avoid
introducing a new warning in dtbs_check.
Thanks,
Nícolas
[1] https://lore.kernel.org/all/20220225225315.80220-1-nfraprado@collabora.com/
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-25 23:06 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-25 23:06 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, AngeloGioacchino Del Regno
Hi Allen,
actually there's one other thing, please see below.
On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> + iommu0: m4u@1401d000 {
> + compatible = "mediatek,mt8192-m4u";
> + reg = <0 0x1401d000 0 0x1000>;
> + mediatek,larbs = <&larb0 &larb1 &larb2
> + &larb4 &larb5 &larb7
> + &larb9 &larb11 &larb13
> + &larb14 &larb16 &larb17
> + &larb18 &larb19 &larb20>;
I just sent a patch [1] fixing the formatting of the mediatek,larbs properties
on other Mediatek Devicetrees. So please do the same here so we can avoid
introducing a new warning in dtbs_check.
Thanks,
Nícolas
[1] https://lore.kernel.org/all/20220225225315.80220-1-nfraprado@collabora.com/
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes
@ 2022-02-25 23:06 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-25 23:06 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, AngeloGioacchino Del Regno
Hi Allen,
actually there's one other thing, please see below.
On Fri, Feb 18, 2022 at 05:16:25PM +0800, Allen-KH Cheng wrote:
> + iommu0: m4u@1401d000 {
> + compatible = "mediatek,mt8192-m4u";
> + reg = <0 0x1401d000 0 0x1000>;
> + mediatek,larbs = <&larb0 &larb1 &larb2
> + &larb4 &larb5 &larb7
> + &larb9 &larb11 &larb13
> + &larb14 &larb16 &larb17
> + &larb18 &larb19 &larb20>;
I just sent a patch [1] fixing the formatting of the mediatek,larbs properties
on other Mediatek Devicetrees. So please do the same here so we can avoid
introducing a new warning in dtbs_check.
Thanks,
Nícolas
[1] https://lore.kernel.org/all/20220225225315.80220-1-nfraprado@collabora.com/
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Adds H264 venc node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 40887120fdb3..936aa788664f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1342,6 +1342,29 @@
power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
};
+ vcodec_enc: vcodec@0x17020000 {
+ compatible = "mediatek,mt8192-vcodec-enc";
+ reg = <0 0x17020000 0 0x2000>;
+ iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+ <&iommu0 M4U_PORT_L7_VENC_REC>,
+ <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,scp = <&scp>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc-set1";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Adds H264 venc node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 40887120fdb3..936aa788664f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1342,6 +1342,29 @@
power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
};
+ vcodec_enc: vcodec@0x17020000 {
+ compatible = "mediatek,mt8192-vcodec-enc";
+ reg = <0 0x17020000 0 0x2000>;
+ iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+ <&iommu0 M4U_PORT_L7_VENC_REC>,
+ <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,scp = <&scp>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc-set1";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
--
2.18.0
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^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Adds H264 venc node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 40887120fdb3..936aa788664f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1342,6 +1342,29 @@
power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
};
+ vcodec_enc: vcodec@0x17020000 {
+ compatible = "mediatek,mt8192-vcodec-enc";
+ reg = <0 0x17020000 0 0x2000>;
+ iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+ <&iommu0 M4U_PORT_L7_VENC_REC>,
+ <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,scp = <&scp>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc-set1";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Adds H264 venc node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Adds H264 venc node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Adds H264 venc node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 22:13 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 22:13 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:26PM +0800, Allen-KH Cheng wrote:
> Adds H264 venc node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 40887120fdb3..936aa788664f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1342,6 +1342,29 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> };
>
> + vcodec_enc: vcodec@0x17020000 {
The node address shouldn't have the '0x' prefix. Please drop it.
> + compatible = "mediatek,mt8192-vcodec-enc";
> + reg = <0 0x17020000 0 0x2000>;
> + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> + <&iommu0 M4U_PORT_L7_VENC_REC>,
> + <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
Please fix indentation:
iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
<&iommu0 M4U_PORT_L7_VENC_REC>,
<&iommu0 M4U_PORT_L7_VENC_BSDMA>,
<&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
<&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
<&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,scp = <&scp>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> + clocks = <&vencsys CLK_VENC_SET1_VENC>;
> + clock-names = "venc-set1";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> + };
> +
> camsys: clock-controller@1a000000 {
> compatible = "mediatek,mt8192-camsys";
> reg = <0 0x1a000000 0 0x1000>;
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
@ 2022-02-22 22:13 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 22:13 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:26PM +0800, Allen-KH Cheng wrote:
> Adds H264 venc node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 40887120fdb3..936aa788664f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1342,6 +1342,29 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> };
>
> + vcodec_enc: vcodec@0x17020000 {
The node address shouldn't have the '0x' prefix. Please drop it.
> + compatible = "mediatek,mt8192-vcodec-enc";
> + reg = <0 0x17020000 0 0x2000>;
> + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> + <&iommu0 M4U_PORT_L7_VENC_REC>,
> + <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
Please fix indentation:
iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
<&iommu0 M4U_PORT_L7_VENC_REC>,
<&iommu0 M4U_PORT_L7_VENC_BSDMA>,
<&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
<&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
<&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,scp = <&scp>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> + clocks = <&vencsys CLK_VENC_SET1_VENC>;
> + clock-names = "venc-set1";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> + };
> +
> camsys: clock-controller@1a000000 {
> compatible = "mediatek,mt8192-camsys";
> reg = <0 0x1a000000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
@ 2022-02-22 22:13 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 22:13 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:26PM +0800, Allen-KH Cheng wrote:
> Adds H264 venc node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 40887120fdb3..936aa788664f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1342,6 +1342,29 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> };
>
> + vcodec_enc: vcodec@0x17020000 {
The node address shouldn't have the '0x' prefix. Please drop it.
> + compatible = "mediatek,mt8192-vcodec-enc";
> + reg = <0 0x17020000 0 0x2000>;
> + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> + <&iommu0 M4U_PORT_L7_VENC_REC>,
> + <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
Please fix indentation:
iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
<&iommu0 M4U_PORT_L7_VENC_REC>,
<&iommu0 M4U_PORT_L7_VENC_BSDMA>,
<&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
<&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
<&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,scp = <&scp>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> + clocks = <&vencsys CLK_VENC_SET1_VENC>;
> + clock-names = "venc-set1";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> + };
> +
> camsys: clock-controller@1a000000 {
> compatible = "mediatek,mt8192-camsys";
> reg = <0 0x1a000000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
2022-02-22 22:13 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:36 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:36 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Hi
On Tue, 2022-02-22 at 17:13 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:26PM +0800, Allen-KH Cheng wrote:
> > Adds H264 venc node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23
> > +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 40887120fdb3..936aa788664f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1342,6 +1342,29 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_VENC>;
> > };
> >
> > + vcodec_enc: vcodec@0x17020000 {
>
> The node address shouldn't have the '0x' prefix. Please drop it.
>
OK
> > + compatible = "mediatek,mt8192-vcodec-enc";
> > + reg = <0 0x17020000 0 0x2000>;
> > + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> > + <&iommu0 M4U_PORT_L7_VENC_REC>,
> > + <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> > + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> > + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
>
> Please fix indentation:
> iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> <&iommu0 M4U_PORT_L7_VENC_REC>,
> <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
>
I will fix this.
Thanks,
Allen
> > + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + mediatek,scp = <&scp>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VENC>;
> > + clocks = <&vencsys CLK_VENC_SET1_VENC>;
> > + clock-names = "venc-set1";
> > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D4>;
> > + };
> > +
> > camsys: clock-controller@1a000000 {
> > compatible = "mediatek,mt8192-camsys";
> > reg = <0 0x1a000000 0 0x1000>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node
@ 2022-02-23 13:36 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:36 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Hi
On Tue, 2022-02-22 at 17:13 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:26PM +0800, Allen-KH Cheng wrote:
> > Adds H264 venc node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23
> > +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 40887120fdb3..936aa788664f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1342,6 +1342,29 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_VENC>;
> > };
> >
> > + vcodec_enc: vcodec@0x17020000 {
>
> The node address shouldn't have the '0x' prefix. Please drop it.
>
OK
> > + compatible = "mediatek,mt8192-vcodec-enc";
> > + reg = <0 0x17020000 0 0x2000>;
> > + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> > + <&iommu0 M4U_PORT_L7_VENC_REC>,
> > + <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> > + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> > + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> > + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
>
> Please fix indentation:
> iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> <&iommu0 M4U_PORT_L7_VENC_REC>,
> <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
>
I will fix this.
Thanks,
Allen
> > + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + mediatek,scp = <&scp>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VENC>;
> > + clocks = <&vencsys CLK_VENC_SET1_VENC>;
> > + clock-names = "venc-set1";
> > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D4>;
> > + };
> > +
> > camsys: clock-controller@1a000000 {
> > compatible = "mediatek,mt8192-camsys";
> > reg = <0 0x1a000000 0 0x1000>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add vcodec lat and core nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 936aa788664f..543a80252ce5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1291,6 +1291,64 @@
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
};
+ vcodec_dec: vcodec_dec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ };
+
+ vcodec_lat: vcodec_lat@0x16010000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
+ "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec_core: vcodec_core@0x16025000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
+ "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
larb5: larb@1600d000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1600d000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add vcodec lat and core nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 936aa788664f..543a80252ce5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1291,6 +1291,64 @@
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
};
+ vcodec_dec: vcodec_dec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ };
+
+ vcodec_lat: vcodec_lat@0x16010000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
+ "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec_core: vcodec_core@0x16025000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
+ "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
larb5: larb@1600d000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1600d000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add vcodec lat and core nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 936aa788664f..543a80252ce5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1291,6 +1291,64 @@
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
};
+ vcodec_dec: vcodec_dec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ };
+
+ vcodec_lat: vcodec_lat@0x16010000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
+ "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec_core: vcodec_core@0x16025000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
+ "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
larb5: larb@1600d000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1600d000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 936aa788664f..543a80252ce5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1291,6 +1291,64 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec_dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + };
> +
> + vcodec_lat: vcodec_lat@0x16010000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
Please fix indentation!
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
... etc.
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec_core@0x16025000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
ditto.
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 936aa788664f..543a80252ce5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1291,6 +1291,64 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec_dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + };
> +
> + vcodec_lat: vcodec_lat@0x16010000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
Please fix indentation!
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
... etc.
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec_core@0x16025000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
ditto.
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 936aa788664f..543a80252ce5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1291,6 +1291,64 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec_dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + };
> +
> + vcodec_lat: vcodec_lat@0x16010000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
Please fix indentation!
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
... etc.
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec_core@0x16025000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
ditto.
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-02-18 12:56 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:10 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:10 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add vcodec lat and core nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58
> > ++++++++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 936aa788664f..543a80252ce5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1291,6 +1291,64 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> > };
> >
> > + vcodec_dec: vcodec_dec@16000000 {
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + reg = <0 0x16000000 0 0x1000>; /*
> > VDEC_SYS */
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + };
> > +
> > + vcodec_lat: vcodec_lat@0x16010000 {
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0 0x16010000 0 0x800>; /*
> > VDEC_MISC */
> > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>
> Please fix indentation!
>
> iommus = <&iommu0
> M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
>
> <&iommu0
> M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
>
> <&iommu0
> M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>
> ... etc.
>
Hi Angelo,
My neglect for indentation.
I will fix this in next versionn.
Many thanks,
Allen
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "vdec-sel", "vdec-soc-vdec",
> > "vdec-soc-lat", "vdec-vdec",
> > + "vdec-top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec_core: vcodec_core@0x16025000 {
> > + compatible = "mediatek,mtk-vcodec-core";
> > + reg = <0 0x16025000 0 0x1000>; /*
> > VDEC_CORE_MISC */
> > + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
>
> ditto.
>
> > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys CLK_VDEC_VDEC>,
> > + <&vdecsys CLK_VDEC_LAT>,
> > + <&vdecsys CLK_VDEC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "vdec-sel", "vdec-soc-vdec",
> > "vdec-soc-lat", "vdec-vdec",
> > + "vdec-top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > + };
> > +
> > larb5: larb@1600d000 {
> > compatible = "mediatek,mt8192-smi-larb";
> > reg = <0 0x1600d000 0 0x1000>;
>
>
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-21 13:10 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:10 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add vcodec lat and core nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58
> > ++++++++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 936aa788664f..543a80252ce5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1291,6 +1291,64 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> > };
> >
> > + vcodec_dec: vcodec_dec@16000000 {
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + reg = <0 0x16000000 0 0x1000>; /*
> > VDEC_SYS */
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + };
> > +
> > + vcodec_lat: vcodec_lat@0x16010000 {
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0 0x16010000 0 0x800>; /*
> > VDEC_MISC */
> > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>
> Please fix indentation!
>
> iommus = <&iommu0
> M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
>
> <&iommu0
> M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
>
> <&iommu0
> M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>
> ... etc.
>
Hi Angelo,
My neglect for indentation.
I will fix this in next versionn.
Many thanks,
Allen
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "vdec-sel", "vdec-soc-vdec",
> > "vdec-soc-lat", "vdec-vdec",
> > + "vdec-top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec_core: vcodec_core@0x16025000 {
> > + compatible = "mediatek,mtk-vcodec-core";
> > + reg = <0 0x16025000 0 0x1000>; /*
> > VDEC_CORE_MISC */
> > + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
>
> ditto.
>
> > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys CLK_VDEC_VDEC>,
> > + <&vdecsys CLK_VDEC_LAT>,
> > + <&vdecsys CLK_VDEC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "vdec-sel", "vdec-soc-vdec",
> > "vdec-soc-lat", "vdec-vdec",
> > + "vdec-top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > + };
> > +
> > larb5: larb@1600d000 {
> > compatible = "mediatek,mt8192-smi-larb";
> > reg = <0 0x1600d000 0 0x1000>;
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 22:33 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 22:33 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:27PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 936aa788664f..543a80252ce5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1291,6 +1291,64 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec_dec@16000000 {
It's usually preferred to use '-' instead of '_' in the node name, like:
vcodec_dec: vcodec-dec@16000000 {
Same thing for the other vcodec nodes below.
But more importantly, the Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
dt-binding shows the mtk-vcodec-lat and mtk-vcodec-core as subnodes of
vcodec-dec. So I would follow that same structure here. Unless it does make more
sense to have the nodes separate like this, but in that case the dt-binding
should be updated.
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + };
> +
> + vcodec_lat: vcodec_lat@0x16010000 {
Again, please drop the '0x' prefix.
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec_core@0x16025000 {
Ditto.
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-22 22:33 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 22:33 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:27PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 936aa788664f..543a80252ce5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1291,6 +1291,64 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec_dec@16000000 {
It's usually preferred to use '-' instead of '_' in the node name, like:
vcodec_dec: vcodec-dec@16000000 {
Same thing for the other vcodec nodes below.
But more importantly, the Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
dt-binding shows the mtk-vcodec-lat and mtk-vcodec-core as subnodes of
vcodec-dec. So I would follow that same structure here. Unless it does make more
sense to have the nodes separate like this, but in that case the dt-binding
should be updated.
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + };
> +
> + vcodec_lat: vcodec_lat@0x16010000 {
Again, please drop the '0x' prefix.
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec_core@0x16025000 {
Ditto.
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-22 22:33 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 22:33 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:27PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 936aa788664f..543a80252ce5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1291,6 +1291,64 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec_dec@16000000 {
It's usually preferred to use '-' instead of '_' in the node name, like:
vcodec_dec: vcodec-dec@16000000 {
Same thing for the other vcodec nodes below.
But more importantly, the Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
dt-binding shows the mtk-vcodec-lat and mtk-vcodec-core as subnodes of
vcodec-dec. So I would follow that same structure here. Unless it does make more
sense to have the nodes separate like this, but in that case the dt-binding
should be updated.
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + };
> +
> + vcodec_lat: vcodec_lat@0x16010000 {
Again, please drop the '0x' prefix.
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec_core@0x16025000 {
Ditto.
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-02-22 22:33 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:39 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:39 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 17:33 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:27PM +0800, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58
> > ++++++++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 936aa788664f..543a80252ce5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1291,6 +1291,64 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> > };
> >
> > + vcodec_dec: vcodec_dec@16000000 {
>
> It's usually preferred to use '-' instead of '_' in the node name,
> like:
>
> vcodec_dec: vcodec-dec@16000000 {
>
> Same thing for the other vcodec nodes below.
>
> But more importantly, the
> Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> decoder.yaml
> dt-binding shows the mtk-vcodec-lat and mtk-vcodec-core as subnodes
> of
> vcodec-dec. So I would follow that same structure here. Unless it
> does make more
> sense to have the nodes separate like this, but in that case the dt-
> binding
> should be updated.
>
Hi Nícolas
I think it's ok set mtk-vcodec-lat and mtk-vcodec-core as subnodes of
vcodec-dec.
I will retest in mt8192 product and make sure this works.
Many thanks,
Allen
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + reg = <0 0x16000000 0 0x1000>; /*
> > VDEC_SYS */
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + };
> > +
> > + vcodec_lat: vcodec_lat@0x16010000 {
>
> Again, please drop the '0x' prefix.
>
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0 0x16010000 0 0x800>; /*
> > VDEC_MISC */
> > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "vdec-sel", "vdec-soc-vdec",
> > "vdec-soc-lat", "vdec-vdec",
> > + "vdec-top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec_core: vcodec_core@0x16025000 {
>
> Ditto.
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-02-23 13:39 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:39 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 17:33 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:27PM +0800, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58
> > ++++++++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 936aa788664f..543a80252ce5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1291,6 +1291,64 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> > };
> >
> > + vcodec_dec: vcodec_dec@16000000 {
>
> It's usually preferred to use '-' instead of '_' in the node name,
> like:
>
> vcodec_dec: vcodec-dec@16000000 {
>
> Same thing for the other vcodec nodes below.
>
> But more importantly, the
> Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> decoder.yaml
> dt-binding shows the mtk-vcodec-lat and mtk-vcodec-core as subnodes
> of
> vcodec-dec. So I would follow that same structure here. Unless it
> does make more
> sense to have the nodes separate like this, but in that case the dt-
> binding
> should be updated.
>
Hi Nícolas
I think it's ok set mtk-vcodec-lat and mtk-vcodec-core as subnodes of
vcodec-dec.
I will retest in mt8192 product and make sure this works.
Many thanks,
Allen
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + reg = <0 0x16000000 0 0x1000>; /*
> > VDEC_SYS */
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + };
> > +
> > + vcodec_lat: vcodec_lat@0x16010000 {
>
> Again, please drop the '0x' prefix.
>
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0 0x16010000 0 0x800>; /*
> > VDEC_MISC */
> > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "vdec-sel", "vdec-soc-vdec",
> > "vdec-soc-lat", "vdec-vdec",
> > + "vdec-top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec_core: vcodec_core@0x16025000 {
>
> Ditto.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add dpi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 543a80252ce5..55bcbf72a366 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1242,6 +1242,16 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
+ dpi0: dpi@14016000 {
+ compatible = "mediatek,mt8192-dpi";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DPI_DPI0>,
+ <&mmsys CLK_MM_DISP_DPI0>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ };
+
iommu0: m4u@1401d000 {
compatible = "mediatek,mt8192-m4u";
reg = <0 0x1401d000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add dpi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 543a80252ce5..55bcbf72a366 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1242,6 +1242,16 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
+ dpi0: dpi@14016000 {
+ compatible = "mediatek,mt8192-dpi";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DPI_DPI0>,
+ <&mmsys CLK_MM_DISP_DPI0>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ };
+
iommu0: m4u@1401d000 {
compatible = "mediatek,mt8192-m4u";
reg = <0 0x1401d000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add dpi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 543a80252ce5..55bcbf72a366 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1242,6 +1242,16 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
+ dpi0: dpi@14016000 {
+ compatible = "mediatek,mt8192-dpi";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DPI_DPI0>,
+ <&mmsys CLK_MM_DISP_DPI0>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ };
+
iommu0: m4u@1401d000 {
compatible = "mediatek,mt8192-m4u";
reg = <0 0x1401d000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add dpi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 543a80252ce5..55bcbf72a366 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1242,6 +1242,16 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> };
>
> + dpi0: dpi@14016000 {
> + compatible = "mediatek,mt8192-dpi";
> + reg = <0 0x14016000 0 0x1000>;
> + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DPI_DPI0>,
> + <&mmsys CLK_MM_DISP_DPI0>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
Please, for the same reason explained for mipi_tx0:
status = "disabled";
> + };
> +
> iommu0: m4u@1401d000 {
> compatible = "mediatek,mt8192-m4u";
> reg = <0 0x1401d000 0 0x1000>;
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add dpi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 543a80252ce5..55bcbf72a366 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1242,6 +1242,16 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> };
>
> + dpi0: dpi@14016000 {
> + compatible = "mediatek,mt8192-dpi";
> + reg = <0 0x14016000 0 0x1000>;
> + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DPI_DPI0>,
> + <&mmsys CLK_MM_DISP_DPI0>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
Please, for the same reason explained for mipi_tx0:
status = "disabled";
> + };
> +
> iommu0: m4u@1401d000 {
> compatible = "mediatek,mt8192-m4u";
> reg = <0 0x1401d000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add dpi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 543a80252ce5..55bcbf72a366 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1242,6 +1242,16 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> };
>
> + dpi0: dpi@14016000 {
> + compatible = "mediatek,mt8192-dpi";
> + reg = <0 0x14016000 0 0x1000>;
> + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DPI_DPI0>,
> + <&mmsys CLK_MM_DISP_DPI0>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
Please, for the same reason explained for mipi_tx0:
status = "disabled";
> + };
> +
> iommu0: m4u@1401d000 {
> compatible = "mediatek,mt8192-m4u";
> reg = <0 0x1401d000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
2022-02-18 12:56 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:13 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:13 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add dpi node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 543a80252ce5..55bcbf72a366 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1242,6 +1242,16 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > };
> >
> > + dpi0: dpi@14016000 {
> > + compatible = "mediatek,mt8192-dpi";
> > + reg = <0 0x14016000 0 0x1000>;
> > + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&mmsys CLK_MM_DPI_DPI0>,
> > + <&mmsys CLK_MM_DISP_DPI0>,
> > + <&apmixedsys CLK_APMIXED_TVDPLL>;
> > + clock-names = "pixel", "engine", "pll";
>
> Please, for the same reason explained for mipi_tx0:
>
> status = "disabled";
>
Hi Angelo,
Thsi is the same problem with mipi_tx0.
I will update in next version.
Many thanks,
Allen
> > + };
> > +
> > iommu0: m4u@1401d000 {
> > compatible = "mediatek,mt8192-m4u";
> > reg = <0 0x1401d000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node
@ 2022-02-21 13:13 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:13 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add dpi node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 543a80252ce5..55bcbf72a366 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1242,6 +1242,16 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > };
> >
> > + dpi0: dpi@14016000 {
> > + compatible = "mediatek,mt8192-dpi";
> > + reg = <0 0x14016000 0 0x1000>;
> > + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&mmsys CLK_MM_DPI_DPI0>,
> > + <&mmsys CLK_MM_DISP_DPI0>,
> > + <&apmixedsys CLK_APMIXED_TVDPLL>;
> > + clock-names = "pixel", "engine", "pll";
>
> Please, for the same reason explained for mipi_tx0:
>
> status = "disabled";
>
Hi Angelo,
Thsi is the same problem with mipi_tx0.
I will update in next version.
Many thanks,
Allen
> > + };
> > +
> > iommu0: m4u@1401d000 {
> > compatible = "mediatek,mt8192-m4u";
> > reg = <0 0x1401d000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add i2c aliases for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 55bcbf72a366..e3314cdc7c1a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -21,6 +21,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add i2c aliases for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 55bcbf72a366..e3314cdc7c1a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -21,6 +21,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add i2c aliases for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 55bcbf72a366..e3314cdc7c1a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -21,6 +21,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add i2c aliases for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 55bcbf72a366..e3314cdc7c1a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -21,6 +21,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add i2c aliases for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 55bcbf72a366..e3314cdc7c1a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -21,6 +21,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add i2c aliases for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 55bcbf72a366..e3314cdc7c1a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -21,6 +21,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-21 4:50 ` Chen-Yu Tsai
-1 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-21 4:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
Hi,
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add i2c aliases for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 55bcbf72a366..e3314cdc7c1a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -21,6 +21,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
AFAIK, maintainers have suggested against [1] having aliases in the .dtsi.
If the numbering isn't an issue, I suggest just dropping it altogether.
If it is, then the aliases should be added at the board level, and only
for the interfaces that are actually enabled.
ChenYu
[1] https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
@ 2022-02-21 4:50 ` Chen-Yu Tsai
0 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-21 4:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
Hi,
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add i2c aliases for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 55bcbf72a366..e3314cdc7c1a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -21,6 +21,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
AFAIK, maintainers have suggested against [1] having aliases in the .dtsi.
If the numbering isn't an issue, I suggest just dropping it altogether.
If it is, then the aliases should be added at the board level, and only
for the interfaces that are actually enabled.
ChenYu
[1] https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
@ 2022-02-21 4:50 ` Chen-Yu Tsai
0 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-21 4:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
Hi,
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add i2c aliases for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 55bcbf72a366..e3314cdc7c1a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -21,6 +21,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
AFAIK, maintainers have suggested against [1] having aliases in the .dtsi.
If the numbering isn't an issue, I suggest just dropping it altogether.
If it is, then the aliases should be added at the board level, and only
for the interfaces that are actually enabled.
ChenYu
[1] https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
2022-02-21 4:50 ` Chen-Yu Tsai
@ 2022-02-21 13:22 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:22 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
On Mon, 2022-02-21 at 12:50 +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > Add i2c aliases for mt8192 SoC
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 55bcbf72a366..e3314cdc7c1a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -21,6 +21,19 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + aliases {
> > + i2c0 = &i2c0;
> > + i2c1 = &i2c1;
> > + i2c2 = &i2c2;
> > + i2c3 = &i2c3;
> > + i2c4 = &i2c4;
> > + i2c5 = &i2c5;
> > + i2c6 = &i2c6;
> > + i2c7 = &i2c7;
> > + i2c8 = &i2c8;
> > + i2c9 = &i2c9;
>
> AFAIK, maintainers have suggested against [1] having aliases in the
> .dtsi.
>
> If the numbering isn't an issue, I suggest just dropping it
> altogether.
> If it is, then the aliases should be added at the board level, and
> only
> for the interfaces that are actually enabled.
>
> ChenYu
>
> [1]
> https://urldefense.com/v3/__https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!xXnhgMJXr_7T7q0dG965vVaZ-J2bDtpVWRouWVk5SjGO2f53HHesM8fhh1srbsWobbPCJrG-mqx6_dVs1Cfs2Njl4w$
>
Hi ChenYu,
Thanks for suggestion.
I will move this part to board level.
Best regards,
Allen
>
> > + };
> > +
> > clk26m: oscillator0 {
> > compatible = "fixed-clock";
> > #clock-cells = <0>;
> > --
> > 2.18.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases
@ 2022-02-21 13:22 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:22 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
On Mon, 2022-02-21 at 12:50 +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > Add i2c aliases for mt8192 SoC
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 55bcbf72a366..e3314cdc7c1a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -21,6 +21,19 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + aliases {
> > + i2c0 = &i2c0;
> > + i2c1 = &i2c1;
> > + i2c2 = &i2c2;
> > + i2c3 = &i2c3;
> > + i2c4 = &i2c4;
> > + i2c5 = &i2c5;
> > + i2c6 = &i2c6;
> > + i2c7 = &i2c7;
> > + i2c8 = &i2c8;
> > + i2c9 = &i2c9;
>
> AFAIK, maintainers have suggested against [1] having aliases in the
> .dtsi.
>
> If the numbering isn't an issue, I suggest just dropping it
> altogether.
> If it is, then the aliases should be added at the board level, and
> only
> for the interfaces that are actually enabled.
>
> ChenYu
>
> [1]
> https://urldefense.com/v3/__https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!xXnhgMJXr_7T7q0dG965vVaZ-J2bDtpVWRouWVk5SjGO2f53HHesM8fhh1srbsWobbPCJrG-mqx6_dVs1Cfs2Njl4w$
>
Hi ChenYu,
Thanks for suggestion.
I will move this part to board level.
Best regards,
Allen
>
> > + };
> > +
> > clk26m: oscillator0 {
> > compatible = "fixed-clock";
> > #clock-cells = <0>;
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add display nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e3314cdc7c1a..026f2d8141b0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -32,6 +32,11 @@
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
+ ovl0 = &ovl0;
+ ovl-2l0 = &ovl_2l0;
+ ovl-2l2 = &ovl_2l2;
+ rdma0 = &rdma0;
+ rdma4 = &rdma4;
};
clk26m: oscillator0 {
@@ -1224,6 +1229,13 @@
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ };
+
smi_common: smi@14002000 {
compatible = "mediatek,mt8192-smi-common";
reg = <0 0x14002000 0 0x1000>;
@@ -1255,6 +1267,109 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+ <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma-fifo-size = <5120>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8192-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ };
+
+ dither0: dither@1400e000 {
+ compatible = "mediatek,mt8192-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ };
+
+ ovl_2l2: ovl@14014000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ };
+
+ rdma4: rdma@14015000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+ iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+ mediatek,rdma-fifo-size = <2048>;
+ };
+
dpi0: dpi@14016000 {
compatible = "mediatek,mt8192-dpi";
reg = <0 0x14016000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add display nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e3314cdc7c1a..026f2d8141b0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -32,6 +32,11 @@
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
+ ovl0 = &ovl0;
+ ovl-2l0 = &ovl_2l0;
+ ovl-2l2 = &ovl_2l2;
+ rdma0 = &rdma0;
+ rdma4 = &rdma4;
};
clk26m: oscillator0 {
@@ -1224,6 +1229,13 @@
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ };
+
smi_common: smi@14002000 {
compatible = "mediatek,mt8192-smi-common";
reg = <0 0x14002000 0 0x1000>;
@@ -1255,6 +1267,109 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+ <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma-fifo-size = <5120>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8192-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ };
+
+ dither0: dither@1400e000 {
+ compatible = "mediatek,mt8192-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ };
+
+ ovl_2l2: ovl@14014000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ };
+
+ rdma4: rdma@14015000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+ iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+ mediatek,rdma-fifo-size = <2048>;
+ };
+
dpi0: dpi@14016000 {
compatible = "mediatek,mt8192-dpi";
reg = <0 0x14016000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add display nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e3314cdc7c1a..026f2d8141b0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -32,6 +32,11 @@
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
+ ovl0 = &ovl0;
+ ovl-2l0 = &ovl_2l0;
+ ovl-2l2 = &ovl_2l2;
+ rdma0 = &rdma0;
+ rdma4 = &rdma4;
};
clk26m: oscillator0 {
@@ -1224,6 +1229,13 @@
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ };
+
smi_common: smi@14002000 {
compatible = "mediatek,mt8192-smi-common";
reg = <0 0x14002000 0 0x1000>;
@@ -1255,6 +1267,109 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+ <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma-fifo-size = <5120>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8192-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ };
+
+ dither0: dither@1400e000 {
+ compatible = "mediatek,mt8192-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ };
+
+ ovl_2l2: ovl@14014000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ };
+
+ rdma4: rdma@14015000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+ iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+ mediatek,rdma-fifo-size = <2048>;
+ };
+
dpi0: dpi@14016000 {
compatible = "mediatek,mt8192-dpi";
reg = <0 0x14016000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add display nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add display nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add display nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 10:24 ` Chen-Yu Tsai
-1 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-22 10:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
Hi,
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add display nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e3314cdc7c1a..026f2d8141b0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -32,6 +32,11 @@
> i2c7 = &i2c7;
> i2c8 = &i2c8;
> i2c9 = &i2c9;
> + ovl0 = &ovl0;
> + ovl-2l0 = &ovl_2l0;
> + ovl-2l2 = &ovl_2l2;
> + rdma0 = &rdma0;
> + rdma4 = &rdma4;
> };
>
> clk26m: oscillator0 {
> @@ -1224,6 +1229,13 @@
> #clock-cells = <1>;
> };
>
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + };
> +
> smi_common: smi@14002000 {
> compatible = "mediatek,mt8192-smi-common";
> reg = <0 0x14002000 0 0x1000>;
> @@ -1255,6 +1267,109 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> };
>
> + ovl0: ovl@14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + ovl_2l0: ovl@14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + };
> +
> + rdma0: rdma@14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + mediatek,rdma-fifo-size = <5120>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + color0: color@14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + };
> +
> + ccorr0: ccorr@1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + };
> +
> + aal0: aal@1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd
suggests that there should be a fallback compatible? Otherwise this
doesn't probe.
ChenYu
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-22 10:24 ` Chen-Yu Tsai
0 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-22 10:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
Hi,
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add display nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e3314cdc7c1a..026f2d8141b0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -32,6 +32,11 @@
> i2c7 = &i2c7;
> i2c8 = &i2c8;
> i2c9 = &i2c9;
> + ovl0 = &ovl0;
> + ovl-2l0 = &ovl_2l0;
> + ovl-2l2 = &ovl_2l2;
> + rdma0 = &rdma0;
> + rdma4 = &rdma4;
> };
>
> clk26m: oscillator0 {
> @@ -1224,6 +1229,13 @@
> #clock-cells = <1>;
> };
>
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + };
> +
> smi_common: smi@14002000 {
> compatible = "mediatek,mt8192-smi-common";
> reg = <0 0x14002000 0 0x1000>;
> @@ -1255,6 +1267,109 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> };
>
> + ovl0: ovl@14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + ovl_2l0: ovl@14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + };
> +
> + rdma0: rdma@14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + mediatek,rdma-fifo-size = <5120>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + color0: color@14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + };
> +
> + ccorr0: ccorr@1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + };
> +
> + aal0: aal@1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd
suggests that there should be a fallback compatible? Otherwise this
doesn't probe.
ChenYu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-22 10:24 ` Chen-Yu Tsai
0 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-22 10:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
Hi,
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add display nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e3314cdc7c1a..026f2d8141b0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -32,6 +32,11 @@
> i2c7 = &i2c7;
> i2c8 = &i2c8;
> i2c9 = &i2c9;
> + ovl0 = &ovl0;
> + ovl-2l0 = &ovl_2l0;
> + ovl-2l2 = &ovl_2l2;
> + rdma0 = &rdma0;
> + rdma4 = &rdma4;
> };
>
> clk26m: oscillator0 {
> @@ -1224,6 +1229,13 @@
> #clock-cells = <1>;
> };
>
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + };
> +
> smi_common: smi@14002000 {
> compatible = "mediatek,mt8192-smi-common";
> reg = <0 0x14002000 0 0x1000>;
> @@ -1255,6 +1267,109 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> };
>
> + ovl0: ovl@14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + ovl_2l0: ovl@14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + };
> +
> + rdma0: rdma@14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + mediatek,rdma-fifo-size = <5120>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + color0: color@14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + };
> +
> + ccorr0: ccorr@1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + };
> +
> + aal0: aal@1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd
suggests that there should be a fallback compatible? Otherwise this
doesn't probe.
ChenYu
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
2022-02-22 10:24 ` Chen-Yu Tsai
(?)
@ 2022-02-23 15:35 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:35 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Allen-KH Cheng, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski, Project_Global_Chrome_Upstream_Group,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
Ryder Lee
On Tue, Feb 22, 2022 at 06:24:29PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > Add display nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
> > 1 file changed, 115 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index e3314cdc7c1a..026f2d8141b0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -32,6 +32,11 @@
> > i2c7 = &i2c7;
> > i2c8 = &i2c8;
> > i2c9 = &i2c9;
> > + ovl0 = &ovl0;
> > + ovl-2l0 = &ovl_2l0;
> > + ovl-2l2 = &ovl_2l2;
> > + rdma0 = &rdma0;
> > + rdma4 = &rdma4;
> > };
> >
> > clk26m: oscillator0 {
> > @@ -1224,6 +1229,13 @@
> > #clock-cells = <1>;
> > };
> >
> > + mutex: mutex@14001000 {
> > + compatible = "mediatek,mt8192-disp-mutex";
> > + reg = <0 0x14001000 0 0x1000>;
> > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > + };
> > +
> > smi_common: smi@14002000 {
> > compatible = "mediatek,mt8192-smi-common";
> > reg = <0 0x14002000 0 0x1000>;
> > @@ -1255,6 +1267,109 @@
> > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > };
> >
> > + ovl0: ovl@14005000 {
> > + compatible = "mediatek,mt8192-disp-ovl";
> > + reg = <0 0x14005000 0 0x1000>;
> > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + ovl_2l0: ovl@14006000 {
> > + compatible = "mediatek,mt8192-disp-ovl-2l";
> > + reg = <0 0x14006000 0 0x1000>;
> > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > + };
> > +
> > + rdma0: rdma@14007000 {
> > + compatible = "mediatek,mt8192-disp-rdma";
> > + reg = <0 0x14007000 0 0x1000>;
> > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > + mediatek,larb = <&larb0>;
> > + mediatek,rdma-fifo-size = <5120>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + color0: color@14009000 {
> > + compatible = "mediatek,mt8192-disp-color",
> > + "mediatek,mt8173-disp-color";
> > + reg = <0 0x14009000 0 0x1000>;
> > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + };
> > +
> > + ccorr0: ccorr@1400a000 {
> > + compatible = "mediatek,mt8192-disp-ccorr";
> > + reg = <0 0x1400a000 0 0x1000>;
> > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + };
> > +
> > + aal0: aal@1400b000 {
> > + compatible = "mediatek,mt8192-disp-aal";
>
> git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd
>
> suggests that there should be a fallback compatible? Otherwise this
> doesn't probe.
Indeed, the "mediatek,mt8173-disp-aal" compatible should be appended here for
the node to probe.
Thanks,
Nícolas
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-23 15:35 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:35 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Allen-KH Cheng, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski, Project_Global_Chrome_Upstream_Group,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
Ryder Lee
On Tue, Feb 22, 2022 at 06:24:29PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > Add display nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
> > 1 file changed, 115 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index e3314cdc7c1a..026f2d8141b0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -32,6 +32,11 @@
> > i2c7 = &i2c7;
> > i2c8 = &i2c8;
> > i2c9 = &i2c9;
> > + ovl0 = &ovl0;
> > + ovl-2l0 = &ovl_2l0;
> > + ovl-2l2 = &ovl_2l2;
> > + rdma0 = &rdma0;
> > + rdma4 = &rdma4;
> > };
> >
> > clk26m: oscillator0 {
> > @@ -1224,6 +1229,13 @@
> > #clock-cells = <1>;
> > };
> >
> > + mutex: mutex@14001000 {
> > + compatible = "mediatek,mt8192-disp-mutex";
> > + reg = <0 0x14001000 0 0x1000>;
> > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > + };
> > +
> > smi_common: smi@14002000 {
> > compatible = "mediatek,mt8192-smi-common";
> > reg = <0 0x14002000 0 0x1000>;
> > @@ -1255,6 +1267,109 @@
> > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > };
> >
> > + ovl0: ovl@14005000 {
> > + compatible = "mediatek,mt8192-disp-ovl";
> > + reg = <0 0x14005000 0 0x1000>;
> > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + ovl_2l0: ovl@14006000 {
> > + compatible = "mediatek,mt8192-disp-ovl-2l";
> > + reg = <0 0x14006000 0 0x1000>;
> > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > + };
> > +
> > + rdma0: rdma@14007000 {
> > + compatible = "mediatek,mt8192-disp-rdma";
> > + reg = <0 0x14007000 0 0x1000>;
> > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > + mediatek,larb = <&larb0>;
> > + mediatek,rdma-fifo-size = <5120>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + color0: color@14009000 {
> > + compatible = "mediatek,mt8192-disp-color",
> > + "mediatek,mt8173-disp-color";
> > + reg = <0 0x14009000 0 0x1000>;
> > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + };
> > +
> > + ccorr0: ccorr@1400a000 {
> > + compatible = "mediatek,mt8192-disp-ccorr";
> > + reg = <0 0x1400a000 0 0x1000>;
> > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + };
> > +
> > + aal0: aal@1400b000 {
> > + compatible = "mediatek,mt8192-disp-aal";
>
> git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd
>
> suggests that there should be a fallback compatible? Otherwise this
> doesn't probe.
Indeed, the "mediatek,mt8173-disp-aal" compatible should be appended here for
the node to probe.
Thanks,
Nícolas
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes
@ 2022-02-23 15:35 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:35 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Allen-KH Cheng, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski, Project_Global_Chrome_Upstream_Group,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
Ryder Lee
On Tue, Feb 22, 2022 at 06:24:29PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > Add display nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
> > 1 file changed, 115 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index e3314cdc7c1a..026f2d8141b0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -32,6 +32,11 @@
> > i2c7 = &i2c7;
> > i2c8 = &i2c8;
> > i2c9 = &i2c9;
> > + ovl0 = &ovl0;
> > + ovl-2l0 = &ovl_2l0;
> > + ovl-2l2 = &ovl_2l2;
> > + rdma0 = &rdma0;
> > + rdma4 = &rdma4;
> > };
> >
> > clk26m: oscillator0 {
> > @@ -1224,6 +1229,13 @@
> > #clock-cells = <1>;
> > };
> >
> > + mutex: mutex@14001000 {
> > + compatible = "mediatek,mt8192-disp-mutex";
> > + reg = <0 0x14001000 0 0x1000>;
> > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > + };
> > +
> > smi_common: smi@14002000 {
> > compatible = "mediatek,mt8192-smi-common";
> > reg = <0 0x14002000 0 0x1000>;
> > @@ -1255,6 +1267,109 @@
> > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > };
> >
> > + ovl0: ovl@14005000 {
> > + compatible = "mediatek,mt8192-disp-ovl";
> > + reg = <0 0x14005000 0 0x1000>;
> > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + ovl_2l0: ovl@14006000 {
> > + compatible = "mediatek,mt8192-disp-ovl-2l";
> > + reg = <0 0x14006000 0 0x1000>;
> > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > + };
> > +
> > + rdma0: rdma@14007000 {
> > + compatible = "mediatek,mt8192-disp-rdma";
> > + reg = <0 0x14007000 0 0x1000>;
> > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > + mediatek,larb = <&larb0>;
> > + mediatek,rdma-fifo-size = <5120>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + color0: color@14009000 {
> > + compatible = "mediatek,mt8192-disp-color",
> > + "mediatek,mt8173-disp-color";
> > + reg = <0 0x14009000 0 0x1000>;
> > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + };
> > +
> > + ccorr0: ccorr@1400a000 {
> > + compatible = "mediatek,mt8192-disp-ccorr";
> > + reg = <0 0x1400a000 0 0x1000>;
> > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + };
> > +
> > + aal0: aal@1400b000 {
> > + compatible = "mediatek,mt8192-disp-aal";
>
> git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd
>
> suggests that there should be a fallback compatible? Otherwise this
> doesn't probe.
Indeed, the "mediatek,mt8173-disp-aal" compatible should be appended here for
the node to probe.
Thanks,
Nícolas
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add dsi ndoe for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 026f2d8141b0..1f1555fd18f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1350,6 +1350,19 @@
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
};
+ dsi0: dsi@14010000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-dsi = <&mmsys 0x140>;
+ clocks = <&mmsys CLK_MM_DSI0>,
+ <&mmsys CLK_MM_DSI_DSI0>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ };
+
ovl_2l2: ovl@14014000 {
compatible = "mediatek,mt8192-disp-ovl-2l";
reg = <0 0x14014000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add dsi ndoe for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 026f2d8141b0..1f1555fd18f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1350,6 +1350,19 @@
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
};
+ dsi0: dsi@14010000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-dsi = <&mmsys 0x140>;
+ clocks = <&mmsys CLK_MM_DSI0>,
+ <&mmsys CLK_MM_DSI_DSI0>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ };
+
ovl_2l2: ovl@14014000 {
compatible = "mediatek,mt8192-disp-ovl-2l";
reg = <0 0x14014000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add dsi ndoe for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 026f2d8141b0..1f1555fd18f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1350,6 +1350,19 @@
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
};
+ dsi0: dsi@14010000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-dsi = <&mmsys 0x140>;
+ clocks = <&mmsys CLK_MM_DSI0>,
+ <&mmsys CLK_MM_DSI_DSI0>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ };
+
ovl_2l2: ovl@14014000 {
compatible = "mediatek,mt8192-disp-ovl-2l";
reg = <0 0x14014000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 026f2d8141b0..1f1555fd18f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1350,6 +1350,19 @@
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> };
>
> + dsi0: dsi@14010000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-dsi = <&mmsys 0x140>;
> + clocks = <&mmsys CLK_MM_DSI0>,
> + <&mmsys CLK_MM_DSI_DSI0>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
...please:
status = "disabled";
> + };
> +
> ovl_2l2: ovl@14014000 {
> compatible = "mediatek,mt8192-disp-ovl-2l";
> reg = <0 0x14014000 0 0x1000>;
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 026f2d8141b0..1f1555fd18f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1350,6 +1350,19 @@
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> };
>
> + dsi0: dsi@14010000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-dsi = <&mmsys 0x140>;
> + clocks = <&mmsys CLK_MM_DSI0>,
> + <&mmsys CLK_MM_DSI_DSI0>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
...please:
status = "disabled";
> + };
> +
> ovl_2l2: ovl@14014000 {
> compatible = "mediatek,mt8192-disp-ovl-2l";
> reg = <0 0x14014000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 026f2d8141b0..1f1555fd18f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1350,6 +1350,19 @@
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> };
>
> + dsi0: dsi@14010000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-dsi = <&mmsys 0x140>;
> + clocks = <&mmsys CLK_MM_DSI0>,
> + <&mmsys CLK_MM_DSI_DSI0>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
...please:
status = "disabled";
> + };
> +
> ovl_2l2: ovl@14014000 {
> compatible = "mediatek,mt8192-disp-ovl-2l";
> reg = <0 0x14014000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
2022-02-18 12:56 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:14 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:14 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add dsi ndoe for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 026f2d8141b0..1f1555fd18f5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1350,6 +1350,19 @@
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > };
> >
> > + dsi0: dsi@14010000 {
> > + compatible = "mediatek,mt8183-dsi";
> > + reg = <0 0x14010000 0 0x1000>;
> > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + mediatek,syscon-dsi = <&mmsys 0x140>;
> > + clocks = <&mmsys CLK_MM_DSI0>,
> > + <&mmsys CLK_MM_DSI_DSI0>,
> > + <&mipi_tx0>;
> > + clock-names = "engine", "digital", "hs";
> > + phys = <&mipi_tx0>;
> > + phy-names = "dphy";
>
> ...please:
> status = "disabled";
>
Hi Angelo,
It's the same problem with mipi_tx0.
I will update in next version.
Many thanks,
Allen
> > + };
> > +
> > ovl_2l2: ovl@14014000 {
> > compatible = "mediatek,mt8192-disp-ovl-2l";
> > reg = <0 0x14014000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-21 13:14 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:14 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add dsi ndoe for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 026f2d8141b0..1f1555fd18f5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1350,6 +1350,19 @@
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > };
> >
> > + dsi0: dsi@14010000 {
> > + compatible = "mediatek,mt8183-dsi";
> > + reg = <0 0x14010000 0 0x1000>;
> > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + mediatek,syscon-dsi = <&mmsys 0x140>;
> > + clocks = <&mmsys CLK_MM_DSI0>,
> > + <&mmsys CLK_MM_DSI_DSI0>,
> > + <&mipi_tx0>;
> > + clock-names = "engine", "digital", "hs";
> > + phys = <&mipi_tx0>;
> > + phy-names = "dphy";
>
> ...please:
> status = "disabled";
>
Hi Angelo,
It's the same problem with mipi_tx0.
I will update in next version.
Many thanks,
Allen
> > + };
> > +
> > ovl_2l2: ovl@14014000 {
> > compatible = "mediatek,mt8192-disp-ovl-2l";
> > reg = <0 0x14014000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 23:16 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 23:16 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:31PM +0800, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 026f2d8141b0..1f1555fd18f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1350,6 +1350,19 @@
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> };
>
> + dsi0: dsi@14010000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-dsi = <&mmsys 0x140>;
> + clocks = <&mmsys CLK_MM_DSI0>,
> + <&mmsys CLK_MM_DSI_DSI0>,
> + <&mipi_tx0>;
Please fix the indentation.
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + };
> +
> ovl_2l2: ovl@14014000 {
> compatible = "mediatek,mt8192-disp-ovl-2l";
> reg = <0 0x14014000 0 0x1000>;
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-22 23:16 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 23:16 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:31PM +0800, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 026f2d8141b0..1f1555fd18f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1350,6 +1350,19 @@
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> };
>
> + dsi0: dsi@14010000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-dsi = <&mmsys 0x140>;
> + clocks = <&mmsys CLK_MM_DSI0>,
> + <&mmsys CLK_MM_DSI_DSI0>,
> + <&mipi_tx0>;
Please fix the indentation.
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + };
> +
> ovl_2l2: ovl@14014000 {
> compatible = "mediatek,mt8192-disp-ovl-2l";
> reg = <0 0x14014000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-22 23:16 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 23:16 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:31PM +0800, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 026f2d8141b0..1f1555fd18f5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1350,6 +1350,19 @@
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> };
>
> + dsi0: dsi@14010000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-dsi = <&mmsys 0x140>;
> + clocks = <&mmsys CLK_MM_DSI0>,
> + <&mmsys CLK_MM_DSI_DSI0>,
> + <&mipi_tx0>;
Please fix the indentation.
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + };
> +
> ovl_2l2: ovl@14014000 {
> compatible = "mediatek,mt8192-disp-ovl-2l";
> reg = <0 0x14014000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
2022-02-22 23:16 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:14 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:14 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 18:16 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:31PM +0800, Allen-KH Cheng wrote:
> > Add dsi ndoe for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 026f2d8141b0..1f1555fd18f5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1350,6 +1350,19 @@
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > };
> >
> > + dsi0: dsi@14010000 {
> > + compatible = "mediatek,mt8183-dsi";
> > + reg = <0 0x14010000 0 0x1000>;
> > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + mediatek,syscon-dsi = <&mmsys 0x140>;
> > + clocks = <&mmsys CLK_MM_DSI0>,
> > + <&mmsys CLK_MM_DSI_DSI0>,
> > + <&mipi_tx0>;
>
> Please fix the indentation.
HI Nícolas,
I will fix this in next version, Thanks.
>
> > + clock-names = "engine", "digital", "hs";
> > + phys = <&mipi_tx0>;
> > + phy-names = "dphy";
> > + };
> > +
> > ovl_2l2: ovl@14014000 {
> > compatible = "mediatek,mt8192-disp-ovl-2l";
> > reg = <0 0x14014000 0 0x1000>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node
@ 2022-02-23 13:14 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:14 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 18:16 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:31PM +0800, Allen-KH Cheng wrote:
> > Add dsi ndoe for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 026f2d8141b0..1f1555fd18f5 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1350,6 +1350,19 @@
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > };
> >
> > + dsi0: dsi@14010000 {
> > + compatible = "mediatek,mt8183-dsi";
> > + reg = <0 0x14010000 0 0x1000>;
> > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + mediatek,syscon-dsi = <&mmsys 0x140>;
> > + clocks = <&mmsys CLK_MM_DSI0>,
> > + <&mmsys CLK_MM_DSI_DSI0>,
> > + <&mipi_tx0>;
>
> Please fix the indentation.
HI Nícolas,
I will fix this in next version, Thanks.
>
> > + clock-names = "engine", "digital", "hs";
> > + phys = <&mipi_tx0>;
> > + phy-names = "dphy";
> > + };
> > +
> > ovl_2l2: ovl@14014000 {
> > compatible = "mediatek,mt8192-disp-ovl-2l";
> > reg = <0 0x14014000 0 0x1000>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add gce info for display nodes.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 1f1555fd18f5..df884c48669e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1226,6 +1226,9 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
@@ -1234,6 +1237,8 @@
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
};
smi_common: smi@14002000 {
@@ -1275,6 +1280,7 @@
iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
};
ovl_2l0: ovl@14006000 {
@@ -1285,6 +1291,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
};
rdma0: rdma@14007000 {
@@ -1296,6 +1303,7 @@
mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <5120>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
};
color0: color@14009000 {
@@ -1305,6 +1313,7 @@
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ccorr0: ccorr@1400a000 {
@@ -1313,6 +1322,7 @@
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
aal0: aal@1400b000 {
@@ -1321,6 +1331,7 @@
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
gamma0: gamma@1400c000 {
@@ -1330,6 +1341,7 @@
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
postmask0: postmask@1400d000 {
@@ -1339,6 +1351,7 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
dither0: dither@1400e000 {
@@ -1348,6 +1361,7 @@
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
dsi0: dsi@14010000 {
@@ -1371,6 +1385,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
};
rdma4: rdma@14015000 {
@@ -1381,6 +1396,7 @@
clocks = <&mmsys CLK_MM_DISP_RDMA4>;
iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
mediatek,rdma-fifo-size = <2048>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
};
dpi0: dpi@14016000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add gce info for display nodes.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 1f1555fd18f5..df884c48669e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1226,6 +1226,9 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
@@ -1234,6 +1237,8 @@
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
};
smi_common: smi@14002000 {
@@ -1275,6 +1280,7 @@
iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
};
ovl_2l0: ovl@14006000 {
@@ -1285,6 +1291,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
};
rdma0: rdma@14007000 {
@@ -1296,6 +1303,7 @@
mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <5120>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
};
color0: color@14009000 {
@@ -1305,6 +1313,7 @@
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ccorr0: ccorr@1400a000 {
@@ -1313,6 +1322,7 @@
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
aal0: aal@1400b000 {
@@ -1321,6 +1331,7 @@
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
gamma0: gamma@1400c000 {
@@ -1330,6 +1341,7 @@
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
postmask0: postmask@1400d000 {
@@ -1339,6 +1351,7 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
dither0: dither@1400e000 {
@@ -1348,6 +1361,7 @@
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
dsi0: dsi@14010000 {
@@ -1371,6 +1385,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
};
rdma4: rdma@14015000 {
@@ -1381,6 +1396,7 @@
clocks = <&mmsys CLK_MM_DISP_RDMA4>;
iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
mediatek,rdma-fifo-size = <2048>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
};
dpi0: dpi@14016000 {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add gce info for display nodes.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 1f1555fd18f5..df884c48669e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1226,6 +1226,9 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
@@ -1234,6 +1237,8 @@
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
};
smi_common: smi@14002000 {
@@ -1275,6 +1280,7 @@
iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
};
ovl_2l0: ovl@14006000 {
@@ -1285,6 +1291,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
};
rdma0: rdma@14007000 {
@@ -1296,6 +1303,7 @@
mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <5120>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
};
color0: color@14009000 {
@@ -1305,6 +1313,7 @@
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ccorr0: ccorr@1400a000 {
@@ -1313,6 +1322,7 @@
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
aal0: aal@1400b000 {
@@ -1321,6 +1331,7 @@
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
gamma0: gamma@1400c000 {
@@ -1330,6 +1341,7 @@
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
postmask0: postmask@1400d000 {
@@ -1339,6 +1351,7 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
dither0: dither@1400e000 {
@@ -1348,6 +1361,7 @@
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
dsi0: dsi@14010000 {
@@ -1371,6 +1385,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
};
rdma4: rdma@14015000 {
@@ -1381,6 +1396,7 @@
clocks = <&mmsys CLK_MM_DISP_RDMA4>;
iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
mediatek,rdma-fifo-size = <2048>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
};
dpi0: dpi@14016000 {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add gce info for display nodes.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Please mention that this is required to get drivers' CMDQ support in this
commit message, as this is critical information.
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 1f1555fd18f5..df884c48669e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1226,6 +1226,9 @@
> mmsys: syscon@14000000 {
> compatible = "mediatek,mt8192-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> #clock-cells = <1>;
> };
>
> @@ -1234,6 +1237,8 @@
> reg = <0 0x14001000 0 0x1000>;
> interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> };
>
> smi_common: smi@14002000 {
> @@ -1275,6 +1280,7 @@
> iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> };
>
> ovl_2l0: ovl@14006000 {
> @@ -1285,6 +1291,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> };
>
> rdma0: rdma@14007000 {
> @@ -1296,6 +1303,7 @@
> mediatek,larb = <&larb0>;
> mediatek,rdma-fifo-size = <5120>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> };
>
> color0: color@14009000 {
> @@ -1305,6 +1313,7 @@
> interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ccorr0: ccorr@1400a000 {
> @@ -1313,6 +1322,7 @@
> interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> aal0: aal@1400b000 {
> @@ -1321,6 +1331,7 @@
> interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> gamma0: gamma@1400c000 {
> @@ -1330,6 +1341,7 @@
> interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> postmask0: postmask@1400d000 {
> @@ -1339,6 +1351,7 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> dither0: dither@1400e000 {
> @@ -1348,6 +1361,7 @@
> interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> dsi0: dsi@14010000 {
> @@ -1371,6 +1385,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> rdma4: rdma@14015000 {
> @@ -1381,6 +1396,7 @@
> clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> mediatek,rdma-fifo-size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> dpi0: dpi@14016000 {
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add gce info for display nodes.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Please mention that this is required to get drivers' CMDQ support in this
commit message, as this is critical information.
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 1f1555fd18f5..df884c48669e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1226,6 +1226,9 @@
> mmsys: syscon@14000000 {
> compatible = "mediatek,mt8192-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> #clock-cells = <1>;
> };
>
> @@ -1234,6 +1237,8 @@
> reg = <0 0x14001000 0 0x1000>;
> interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> };
>
> smi_common: smi@14002000 {
> @@ -1275,6 +1280,7 @@
> iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> };
>
> ovl_2l0: ovl@14006000 {
> @@ -1285,6 +1291,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> };
>
> rdma0: rdma@14007000 {
> @@ -1296,6 +1303,7 @@
> mediatek,larb = <&larb0>;
> mediatek,rdma-fifo-size = <5120>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> };
>
> color0: color@14009000 {
> @@ -1305,6 +1313,7 @@
> interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ccorr0: ccorr@1400a000 {
> @@ -1313,6 +1322,7 @@
> interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> aal0: aal@1400b000 {
> @@ -1321,6 +1331,7 @@
> interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> gamma0: gamma@1400c000 {
> @@ -1330,6 +1341,7 @@
> interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> postmask0: postmask@1400d000 {
> @@ -1339,6 +1351,7 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> dither0: dither@1400e000 {
> @@ -1348,6 +1361,7 @@
> interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> dsi0: dsi@14010000 {
> @@ -1371,6 +1385,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> rdma4: rdma@14015000 {
> @@ -1381,6 +1396,7 @@
> clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> mediatek,rdma-fifo-size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> dpi0: dpi@14016000 {
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add gce info for display nodes.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Please mention that this is required to get drivers' CMDQ support in this
commit message, as this is critical information.
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 1f1555fd18f5..df884c48669e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1226,6 +1226,9 @@
> mmsys: syscon@14000000 {
> compatible = "mediatek,mt8192-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> #clock-cells = <1>;
> };
>
> @@ -1234,6 +1237,8 @@
> reg = <0 0x14001000 0 0x1000>;
> interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> };
>
> smi_common: smi@14002000 {
> @@ -1275,6 +1280,7 @@
> iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> };
>
> ovl_2l0: ovl@14006000 {
> @@ -1285,6 +1291,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> };
>
> rdma0: rdma@14007000 {
> @@ -1296,6 +1303,7 @@
> mediatek,larb = <&larb0>;
> mediatek,rdma-fifo-size = <5120>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> };
>
> color0: color@14009000 {
> @@ -1305,6 +1313,7 @@
> interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ccorr0: ccorr@1400a000 {
> @@ -1313,6 +1322,7 @@
> interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> aal0: aal@1400b000 {
> @@ -1321,6 +1331,7 @@
> interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> gamma0: gamma@1400c000 {
> @@ -1330,6 +1341,7 @@
> interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> postmask0: postmask@1400d000 {
> @@ -1339,6 +1351,7 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> dither0: dither@1400e000 {
> @@ -1348,6 +1361,7 @@
> interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> dsi0: dsi@14010000 {
> @@ -1371,6 +1385,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> rdma4: rdma@14015000 {
> @@ -1381,6 +1396,7 @@
> clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> mediatek,rdma-fifo-size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> dpi0: dpi@14016000 {
_______________________________________________
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^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
2022-02-18 12:56 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:16 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:16 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add gce info for display nodes.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> Please mention that this is required to get drivers' CMDQ support in
> this
> commit message, as this is critical information.
>
Hi Angelo,
Thanks for your reminding, I will add those in commit message.
Best regards,
Allen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 1f1555fd18f5..df884c48669e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1226,6 +1226,9 @@
> > mmsys: syscon@14000000 {
> > compatible = "mediatek,mt8192-mmsys", "syscon";
> > reg = <0 0x14000000 0 0x1000>;
> > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
> > #clock-cells = <1>;
> > };
> >
> > @@ -1234,6 +1237,8 @@
> > reg = <0 0x14001000 0 0x1000>;
> > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > + <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> > };
> >
> > smi_common: smi@14002000 {
> > @@ -1275,6 +1280,7 @@
> > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>;
> > };
> >
> > ovl_2l0: ovl@14006000 {
> > @@ -1285,6 +1291,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>;
> > };
> >
> > rdma0: rdma@14007000 {
> > @@ -1296,6 +1303,7 @@
> > mediatek,larb = <&larb0>;
> > mediatek,rdma-fifo-size = <5120>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x7000 0x1000>;
> > };
> >
> > color0: color@14009000 {
> > @@ -1305,6 +1313,7 @@
> > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x9000 0x1000>;
> > };
> >
> > ccorr0: ccorr@1400a000 {
> > @@ -1313,6 +1322,7 @@
> > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xa000 0x1000>;
> > };
> >
> > aal0: aal@1400b000 {
> > @@ -1321,6 +1331,7 @@
> > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xb000 0x1000>;
> > };
> >
> > gamma0: gamma@1400c000 {
> > @@ -1330,6 +1341,7 @@
> > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xc000 0x1000>;
> > };
> >
> > postmask0: postmask@1400d000 {
> > @@ -1339,6 +1351,7 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xd000 0x1000>;
> > };
> >
> > dither0: dither@1400e000 {
> > @@ -1348,6 +1361,7 @@
> > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xe000 0x1000>;
> > };
> >
> > dsi0: dsi@14010000 {
> > @@ -1371,6 +1385,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x4000 0x1000>;
> > };
> >
> > rdma4: rdma@14015000 {
> > @@ -1381,6 +1396,7 @@
> > clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> > mediatek,rdma-fifo-size = <2048>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x5000 0x1000>;
> > };
> >
> > dpi0: dpi@14016000 {
>
>
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-21 13:16 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:16 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Nícolas F. R. A. Prado
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add gce info for display nodes.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> Please mention that this is required to get drivers' CMDQ support in
> this
> commit message, as this is critical information.
>
Hi Angelo,
Thanks for your reminding, I will add those in commit message.
Best regards,
Allen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 1f1555fd18f5..df884c48669e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1226,6 +1226,9 @@
> > mmsys: syscon@14000000 {
> > compatible = "mediatek,mt8192-mmsys", "syscon";
> > reg = <0 0x14000000 0 0x1000>;
> > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
> > #clock-cells = <1>;
> > };
> >
> > @@ -1234,6 +1237,8 @@
> > reg = <0 0x14001000 0 0x1000>;
> > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > + <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> > };
> >
> > smi_common: smi@14002000 {
> > @@ -1275,6 +1280,7 @@
> > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>;
> > };
> >
> > ovl_2l0: ovl@14006000 {
> > @@ -1285,6 +1291,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>;
> > };
> >
> > rdma0: rdma@14007000 {
> > @@ -1296,6 +1303,7 @@
> > mediatek,larb = <&larb0>;
> > mediatek,rdma-fifo-size = <5120>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x7000 0x1000>;
> > };
> >
> > color0: color@14009000 {
> > @@ -1305,6 +1313,7 @@
> > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x9000 0x1000>;
> > };
> >
> > ccorr0: ccorr@1400a000 {
> > @@ -1313,6 +1322,7 @@
> > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xa000 0x1000>;
> > };
> >
> > aal0: aal@1400b000 {
> > @@ -1321,6 +1331,7 @@
> > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xb000 0x1000>;
> > };
> >
> > gamma0: gamma@1400c000 {
> > @@ -1330,6 +1341,7 @@
> > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xc000 0x1000>;
> > };
> >
> > postmask0: postmask@1400d000 {
> > @@ -1339,6 +1351,7 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xd000 0x1000>;
> > };
> >
> > dither0: dither@1400e000 {
> > @@ -1348,6 +1361,7 @@
> > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xe000 0x1000>;
> > };
> >
> > dsi0: dsi@14010000 {
> > @@ -1371,6 +1385,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x4000 0x1000>;
> > };
> >
> > rdma4: rdma@14015000 {
> > @@ -1381,6 +1396,7 @@
> > clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> > mediatek,rdma-fifo-size = <2048>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x5000 0x1000>;
> > };
> >
> > dpi0: dpi@14016000 {
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 23:24 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 23:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> Add gce info for display nodes.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 1f1555fd18f5..df884c48669e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1226,6 +1226,9 @@
> mmsys: syscon@14000000 {
> compatible = "mediatek,mt8192-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
As a side note, the current mmsys dt-binding,
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml, doesn't
define mboxes or mediatek,gce-client-reg, but looks like there's already a patch
in the ML adding those:
https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/
> #clock-cells = <1>;
> };
>
> @@ -1234,6 +1237,8 @@
> reg = <0 0x14001000 0 0x1000>;
> interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> };
>
> smi_common: smi@14002000 {
> @@ -1275,6 +1280,7 @@
> iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> };
>
> ovl_2l0: ovl@14006000 {
> @@ -1285,6 +1291,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> };
>
> rdma0: rdma@14007000 {
> @@ -1296,6 +1303,7 @@
> mediatek,larb = <&larb0>;
> mediatek,rdma-fifo-size = <5120>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> };
>
> color0: color@14009000 {
> @@ -1305,6 +1313,7 @@
> interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ccorr0: ccorr@1400a000 {
> @@ -1313,6 +1322,7 @@
> interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> aal0: aal@1400b000 {
> @@ -1321,6 +1331,7 @@
> interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> gamma0: gamma@1400c000 {
> @@ -1330,6 +1341,7 @@
> interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> postmask0: postmask@1400d000 {
> @@ -1339,6 +1351,7 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> dither0: dither@1400e000 {
> @@ -1348,6 +1361,7 @@
> interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> dsi0: dsi@14010000 {
> @@ -1371,6 +1385,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> rdma4: rdma@14015000 {
> @@ -1381,6 +1396,7 @@
> clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> mediatek,rdma-fifo-size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> dpi0: dpi@14016000 {
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-22 23:24 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 23:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> Add gce info for display nodes.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 1f1555fd18f5..df884c48669e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1226,6 +1226,9 @@
> mmsys: syscon@14000000 {
> compatible = "mediatek,mt8192-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
As a side note, the current mmsys dt-binding,
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml, doesn't
define mboxes or mediatek,gce-client-reg, but looks like there's already a patch
in the ML adding those:
https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/
> #clock-cells = <1>;
> };
>
> @@ -1234,6 +1237,8 @@
> reg = <0 0x14001000 0 0x1000>;
> interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> };
>
> smi_common: smi@14002000 {
> @@ -1275,6 +1280,7 @@
> iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> };
>
> ovl_2l0: ovl@14006000 {
> @@ -1285,6 +1291,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> };
>
> rdma0: rdma@14007000 {
> @@ -1296,6 +1303,7 @@
> mediatek,larb = <&larb0>;
> mediatek,rdma-fifo-size = <5120>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> };
>
> color0: color@14009000 {
> @@ -1305,6 +1313,7 @@
> interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ccorr0: ccorr@1400a000 {
> @@ -1313,6 +1322,7 @@
> interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> aal0: aal@1400b000 {
> @@ -1321,6 +1331,7 @@
> interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> gamma0: gamma@1400c000 {
> @@ -1330,6 +1341,7 @@
> interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> postmask0: postmask@1400d000 {
> @@ -1339,6 +1351,7 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> dither0: dither@1400e000 {
> @@ -1348,6 +1361,7 @@
> interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> dsi0: dsi@14010000 {
> @@ -1371,6 +1385,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> rdma4: rdma@14015000 {
> @@ -1381,6 +1396,7 @@
> clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> mediatek,rdma-fifo-size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> dpi0: dpi@14016000 {
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-22 23:24 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-22 23:24 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> Add gce info for display nodes.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 1f1555fd18f5..df884c48669e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1226,6 +1226,9 @@
> mmsys: syscon@14000000 {
> compatible = "mediatek,mt8192-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
As a side note, the current mmsys dt-binding,
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml, doesn't
define mboxes or mediatek,gce-client-reg, but looks like there's already a patch
in the ML adding those:
https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/
> #clock-cells = <1>;
> };
>
> @@ -1234,6 +1237,8 @@
> reg = <0 0x14001000 0 0x1000>;
> interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> };
>
> smi_common: smi@14002000 {
> @@ -1275,6 +1280,7 @@
> iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> };
>
> ovl_2l0: ovl@14006000 {
> @@ -1285,6 +1291,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> };
>
> rdma0: rdma@14007000 {
> @@ -1296,6 +1303,7 @@
> mediatek,larb = <&larb0>;
> mediatek,rdma-fifo-size = <5120>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> };
>
> color0: color@14009000 {
> @@ -1305,6 +1313,7 @@
> interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ccorr0: ccorr@1400a000 {
> @@ -1313,6 +1322,7 @@
> interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> aal0: aal@1400b000 {
> @@ -1321,6 +1331,7 @@
> interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> gamma0: gamma@1400c000 {
> @@ -1330,6 +1341,7 @@
> interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> postmask0: postmask@1400d000 {
> @@ -1339,6 +1351,7 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> dither0: dither@1400e000 {
> @@ -1348,6 +1361,7 @@
> interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> dsi0: dsi@14010000 {
> @@ -1371,6 +1385,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> rdma4: rdma@14015000 {
> @@ -1381,6 +1396,7 @@
> clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> mediatek,rdma-fifo-size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> dpi0: dpi@14016000 {
> --
> 2.18.0
>
>
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
2022-02-22 23:24 ` Nícolas F. R. A. Prado
@ 2022-02-23 13:12 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:12 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 18:24 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> > Add gce info for display nodes.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 1f1555fd18f5..df884c48669e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1226,6 +1226,9 @@
> > mmsys: syscon@14000000 {
> > compatible = "mediatek,mt8192-mmsys", "syscon";
> > reg = <0 0x14000000 0 0x1000>;
> > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
>
> As a side note, the current mmsys dt-binding,
> Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml,
> doesn't
> define mboxes or mediatek,gce-client-reg, but looks like there's
> already a patch
> in the ML adding those:
>
>
https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$
>
Hi Nícolas,
Thanks for your reminding, Should I need to remove this patch from
series?
or I can add this ML to base and mention it in cover letter.
Best regards,
Allen
>
>
> > #clock-cells = <1>;
> > };
> >
> > @@ -1234,6 +1237,8 @@
> > reg = <0 0x14001000 0 0x1000>;
> > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > + <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> > };
> >
> > smi_common: smi@14002000 {
> > @@ -1275,6 +1280,7 @@
> > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>;
> > };
> >
> > ovl_2l0: ovl@14006000 {
> > @@ -1285,6 +1291,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>;
> > };
> >
> > rdma0: rdma@14007000 {
> > @@ -1296,6 +1303,7 @@
> > mediatek,larb = <&larb0>;
> > mediatek,rdma-fifo-size = <5120>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x7000 0x1000>;
> > };
> >
> > color0: color@14009000 {
> > @@ -1305,6 +1313,7 @@
> > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x9000 0x1000>;
> > };
> >
> > ccorr0: ccorr@1400a000 {
> > @@ -1313,6 +1322,7 @@
> > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xa000 0x1000>;
> > };
> >
> > aal0: aal@1400b000 {
> > @@ -1321,6 +1331,7 @@
> > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xb000 0x1000>;
> > };
> >
> > gamma0: gamma@1400c000 {
> > @@ -1330,6 +1341,7 @@
> > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xc000 0x1000>;
> > };
> >
> > postmask0: postmask@1400d000 {
> > @@ -1339,6 +1351,7 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xd000 0x1000>;
> > };
> >
> > dither0: dither@1400e000 {
> > @@ -1348,6 +1361,7 @@
> > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xe000 0x1000>;
> > };
> >
> > dsi0: dsi@14010000 {
> > @@ -1371,6 +1385,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x4000 0x1000>;
> > };
> >
> > rdma4: rdma@14015000 {
> > @@ -1381,6 +1396,7 @@
> > clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> > mediatek,rdma-fifo-size = <2048>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x5000 0x1000>;
> > };
> >
> > dpi0: dpi@14016000 {
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-23 13:12 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:12 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Tue, 2022-02-22 at 18:24 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> > Add gce info for display nodes.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 1f1555fd18f5..df884c48669e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1226,6 +1226,9 @@
> > mmsys: syscon@14000000 {
> > compatible = "mediatek,mt8192-mmsys", "syscon";
> > reg = <0 0x14000000 0 0x1000>;
> > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
>
> As a side note, the current mmsys dt-binding,
> Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml,
> doesn't
> define mboxes or mediatek,gce-client-reg, but looks like there's
> already a patch
> in the ML adding those:
>
>
https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$
>
Hi Nícolas,
Thanks for your reminding, Should I need to remove this patch from
series?
or I can add this ML to base and mention it in cover letter.
Best regards,
Allen
>
>
> > #clock-cells = <1>;
> > };
> >
> > @@ -1234,6 +1237,8 @@
> > reg = <0 0x14001000 0 0x1000>;
> > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > + <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> > };
> >
> > smi_common: smi@14002000 {
> > @@ -1275,6 +1280,7 @@
> > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>;
> > };
> >
> > ovl_2l0: ovl@14006000 {
> > @@ -1285,6 +1291,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>;
> > };
> >
> > rdma0: rdma@14007000 {
> > @@ -1296,6 +1303,7 @@
> > mediatek,larb = <&larb0>;
> > mediatek,rdma-fifo-size = <5120>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x7000 0x1000>;
> > };
> >
> > color0: color@14009000 {
> > @@ -1305,6 +1313,7 @@
> > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x9000 0x1000>;
> > };
> >
> > ccorr0: ccorr@1400a000 {
> > @@ -1313,6 +1322,7 @@
> > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xa000 0x1000>;
> > };
> >
> > aal0: aal@1400b000 {
> > @@ -1321,6 +1331,7 @@
> > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xb000 0x1000>;
> > };
> >
> > gamma0: gamma@1400c000 {
> > @@ -1330,6 +1341,7 @@
> > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xc000 0x1000>;
> > };
> >
> > postmask0: postmask@1400d000 {
> > @@ -1339,6 +1351,7 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xd000 0x1000>;
> > };
> >
> > dither0: dither@1400e000 {
> > @@ -1348,6 +1361,7 @@
> > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xe000 0x1000>;
> > };
> >
> > dsi0: dsi@14010000 {
> > @@ -1371,6 +1385,7 @@
> > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> > <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x4000 0x1000>;
> > };
> >
> > rdma4: rdma@14015000 {
> > @@ -1381,6 +1396,7 @@
> > clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> > mediatek,rdma-fifo-size = <2048>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x5000 0x1000>;
> > };
> >
> > dpi0: dpi@14016000 {
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
2022-02-23 13:12 ` allen-kh.cheng
(?)
@ 2022-02-23 15:20 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:20 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, AngeloGioacchino Del Regno
On Wed, Feb 23, 2022 at 09:12:37PM +0800, allen-kh.cheng wrote:
> On Tue, 2022-02-22 at 18:24 -0500, Nícolas F. R. A. Prado wrote:
> > On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> > > Add gce info for display nodes.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> > > 1 file changed, 16 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 1f1555fd18f5..df884c48669e 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1226,6 +1226,9 @@
> > > mmsys: syscon@14000000 {
> > > compatible = "mediatek,mt8192-mmsys", "syscon";
> > > reg = <0 0x14000000 0 0x1000>;
> > > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > > 0 0x1000>;
> >
> > As a side note, the current mmsys dt-binding,
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml,
> > doesn't
> > define mboxes or mediatek,gce-client-reg, but looks like there's
> > already a patch
> > in the ML adding those:
> >
> >
> https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$
> >
>
> Hi Nícolas,
>
> Thanks for your reminding, Should I need to remove this patch from
> series?
>
> or I can add this ML to base and mention it in cover letter.
I think it should be OK to just mention it in the cover letter.
Thanks,
Nícolas
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-23 15:20 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:20 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, AngeloGioacchino Del Regno
On Wed, Feb 23, 2022 at 09:12:37PM +0800, allen-kh.cheng wrote:
> On Tue, 2022-02-22 at 18:24 -0500, Nícolas F. R. A. Prado wrote:
> > On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> > > Add gce info for display nodes.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> > > 1 file changed, 16 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 1f1555fd18f5..df884c48669e 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1226,6 +1226,9 @@
> > > mmsys: syscon@14000000 {
> > > compatible = "mediatek,mt8192-mmsys", "syscon";
> > > reg = <0 0x14000000 0 0x1000>;
> > > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > > 0 0x1000>;
> >
> > As a side note, the current mmsys dt-binding,
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml,
> > doesn't
> > define mboxes or mediatek,gce-client-reg, but looks like there's
> > already a patch
> > in the ML adding those:
> >
> >
> https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$
> >
>
> Hi Nícolas,
>
> Thanks for your reminding, Should I need to remove this patch from
> series?
>
> or I can add this ML to base and mention it in cover letter.
I think it should be OK to just mention it in the cover letter.
Thanks,
Nícolas
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes
@ 2022-02-23 15:20 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 252+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-02-23 15:20 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, AngeloGioacchino Del Regno
On Wed, Feb 23, 2022 at 09:12:37PM +0800, allen-kh.cheng wrote:
> On Tue, 2022-02-22 at 18:24 -0500, Nícolas F. R. A. Prado wrote:
> > On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote:
> > > Add gce info for display nodes.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> > > 1 file changed, 16 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 1f1555fd18f5..df884c48669e 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1226,6 +1226,9 @@
> > > mmsys: syscon@14000000 {
> > > compatible = "mediatek,mt8192-mmsys", "syscon";
> > > reg = <0 0x14000000 0 0x1000>;
> > > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > > 0 0x1000>;
> >
> > As a side note, the current mmsys dt-binding,
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml,
> > doesn't
> > define mboxes or mediatek,gce-client-reg, but looks like there's
> > already a patch
> > in the ML adding those:
> >
> >
> https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$
> >
>
> Hi Nícolas,
>
> Thanks for your reminding, Should I need to remove this patch from
> series?
>
> or I can add this ML to base and mention it in cover letter.
I think it should be OK to just mention it in the cover letter.
Thanks,
Nícolas
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 9:16 ` Allen-KH Cheng
-1 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add pwm node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index df884c48669e..c0fc723fdf0a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -642,6 +642,16 @@
status = "disabled";
};
+ pwm0: pwm@1100e000 {
+ compatible = "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+ <&infracfg CLK_INFRA_DISP_PWM>;
+ clock-names = "main", "mm";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
--
2.18.0
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add pwm node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index df884c48669e..c0fc723fdf0a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -642,6 +642,16 @@
status = "disabled";
};
+ pwm0: pwm@1100e000 {
+ compatible = "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+ <&infracfg CLK_INFRA_DISP_PWM>;
+ clock-names = "main", "mm";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 252+ messages in thread* [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
@ 2022-02-18 9:16 ` Allen-KH Cheng
0 siblings, 0 replies; 252+ messages in thread
From: Allen-KH Cheng @ 2022-02-18 9:16 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add pwm node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index df884c48669e..c0fc723fdf0a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -642,6 +642,16 @@
status = "disabled";
};
+ pwm0: pwm@1100e000 {
+ compatible = "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+ <&infracfg CLK_INFRA_DISP_PWM>;
+ clock-names = "main", "mm";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 252+ messages in thread* Re: [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add pwm node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index df884c48669e..c0fc723fdf0a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -642,6 +642,16 @@
> status = "disabled";
> };
>
> + pwm0: pwm@1100e000 {
> + compatible = "mediatek,mt8183-disp-pwm";
> + reg = <0 0x1100e000 0 0x1000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
> + #pwm-cells = <2>;
> + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> + <&infracfg CLK_INFRA_DISP_PWM>;
> + clock-names = "main", "mm";
Depending on the machine, some displays may not be using this PWM node, so:
status = "disabled";
> + };
> +
> spi1: spi@11010000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
>
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add pwm node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index df884c48669e..c0fc723fdf0a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -642,6 +642,16 @@
> status = "disabled";
> };
>
> + pwm0: pwm@1100e000 {
> + compatible = "mediatek,mt8183-disp-pwm";
> + reg = <0 0x1100e000 0 0x1000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
> + #pwm-cells = <2>;
> + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> + <&infracfg CLK_INFRA_DISP_PWM>;
> + clock-names = "main", "mm";
Depending on the machine, some displays may not be using this PWM node, so:
status = "disabled";
> + };
> +
> spi1: spi@11010000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
@ 2022-02-18 12:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 252+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-18 12:56 UTC (permalink / raw)
To: Allen-KH Cheng, Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add pwm node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index df884c48669e..c0fc723fdf0a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -642,6 +642,16 @@
> status = "disabled";
> };
>
> + pwm0: pwm@1100e000 {
> + compatible = "mediatek,mt8183-disp-pwm";
> + reg = <0 0x1100e000 0 0x1000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
> + #pwm-cells = <2>;
> + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> + <&infracfg CLK_INFRA_DISP_PWM>;
> + clock-names = "main", "mm";
Depending on the machine, some displays may not be using this PWM node, so:
status = "disabled";
> + };
> +
> spi1: spi@11010000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
2022-02-18 12:56 ` AngeloGioacchino Del Regno
@ 2022-02-21 13:17 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:17 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add pwm node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index df884c48669e..c0fc723fdf0a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -642,6 +642,16 @@
> > status = "disabled";
> > };
> >
> > + pwm0: pwm@1100e000 {
> > + compatible = "mediatek,mt8183-disp-pwm";
> > + reg = <0 0x1100e000 0 0x1000>;
> > + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + #pwm-cells = <2>;
> > + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> > + <&infracfg CLK_INFRA_DISP_PWM>;
> > + clock-names = "main", "mm";
>
> Depending on the machine, some displays may not be using this PWM
> node, so:
>
> status = "disabled";
>
Hi Angelo,
Thsi is the same problem with mipi_tx0.
I will update in next version.
Many thanks,
Allen
> > + };
> > +
> > spi1: spi@11010000 {
> > compatible = "mediatek,mt8192-spi",
> > "mediatek,mt6765-spi";
> >
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread* Re: [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node
@ 2022-02-21 13:17 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-21 13:17 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Rob Herring,
--to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > Add pwm node for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index df884c48669e..c0fc723fdf0a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -642,6 +642,16 @@
> > status = "disabled";
> > };
> >
> > + pwm0: pwm@1100e000 {
> > + compatible = "mediatek,mt8183-disp-pwm";
> > + reg = <0 0x1100e000 0 0x1000>;
> > + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + #pwm-cells = <2>;
> > + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> > + <&infracfg CLK_INFRA_DISP_PWM>;
> > + clock-names = "main", "mm";
>
> Depending on the machine, some displays may not be using this PWM
> node, so:
>
> status = "disabled";
>
Hi Angelo,
Thsi is the same problem with mipi_tx0.
I will update in next version.
Many thanks,
Allen
> > + };
> > +
> > spi1: spi@11010000 {
> > compatible = "mediatek,mt8192-spi",
> > "mediatek,mt6765-spi";
> >
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 00/23] Add driver nodes for MT8192 SoC
2022-02-18 9:16 ` Allen-KH Cheng
(?)
@ 2022-02-22 3:21 ` Chen-Yu Tsai
-1 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-22 3:21 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> This series are based on tag: next-20220216, linux-next/master
> and apply the below patchs
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220207094024.22674-1-allen-kh.cheng@mediatek.com/
It would make things easier if you incorporated the above patch into this
series when you send v3.
ChenYu
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220217135620.10559-1-allen-kh.cheng@mediatek.com/
>
> There some patches are missed in PATCH v1.
> I resend series again and also add display related nodes in PATCH v2.
>
> changes since v1:
> - add usb-phy node for xhci node
> - move infracfg_rst patch in front of PCIe patch
> - add display nodes, i2c aliases and pwm node.
>
> Allen-KH Cheng (23):
> arm64: dts: mt8192: Add power domains controller
> arm64: dts: mt8192: Add pwrap node
> arm64: dts: mt8192: Add spmi node
> arm64: dts: mt8192: Add gce node
> arm64: dts: mt8192: Add SCP node
> arm64: dts: mt8192: Add usb-phy node
> arm64: dts: mt8192: Add xhci node
> arm64: dts: mt8192: Add audio-related nodes
> arm64: dts: mt8192: Add infracfg_rst node
> arm64: dts: mt8192: Add PCIe node
> arm64: dts: mt8192: Correct nor_flash status of mt8192
> arm64: dts: mt8192: Add efuse node
> arm64: dts: mt8192: Add mmc device nodes
> arm64: dts: mt8192: Add mipi_tx node
> arm64: dts: mt8192: Add m4u and smi nodes
> arm64: dts: mt8192: Add H264 venc device node
> arm64: dts: mt8192: Add vcodec lat and core nodes
> arm64: dts: mt8192: Add dpi node
> arm64: dts: mt8192: Add i2c aliases
> arm64: dts: mt8192: Add display nodes
> arm64: dts: mt8192: Add dsi node
> arm64: dts: mt8192: Add gce info for display nodes
> arm64: dts: mt8192: Add pwm node
>
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1000 +++++++++++++++++++++-
> 1 file changed, 989 insertions(+), 11 deletions(-)
>
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 00/23] Add driver nodes for MT8192 SoC
@ 2022-02-22 3:21 ` Chen-Yu Tsai
0 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-22 3:21 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> This series are based on tag: next-20220216, linux-next/master
> and apply the below patchs
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220207094024.22674-1-allen-kh.cheng@mediatek.com/
It would make things easier if you incorporated the above patch into this
series when you send v3.
ChenYu
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220217135620.10559-1-allen-kh.cheng@mediatek.com/
>
> There some patches are missed in PATCH v1.
> I resend series again and also add display related nodes in PATCH v2.
>
> changes since v1:
> - add usb-phy node for xhci node
> - move infracfg_rst patch in front of PCIe patch
> - add display nodes, i2c aliases and pwm node.
>
> Allen-KH Cheng (23):
> arm64: dts: mt8192: Add power domains controller
> arm64: dts: mt8192: Add pwrap node
> arm64: dts: mt8192: Add spmi node
> arm64: dts: mt8192: Add gce node
> arm64: dts: mt8192: Add SCP node
> arm64: dts: mt8192: Add usb-phy node
> arm64: dts: mt8192: Add xhci node
> arm64: dts: mt8192: Add audio-related nodes
> arm64: dts: mt8192: Add infracfg_rst node
> arm64: dts: mt8192: Add PCIe node
> arm64: dts: mt8192: Correct nor_flash status of mt8192
> arm64: dts: mt8192: Add efuse node
> arm64: dts: mt8192: Add mmc device nodes
> arm64: dts: mt8192: Add mipi_tx node
> arm64: dts: mt8192: Add m4u and smi nodes
> arm64: dts: mt8192: Add H264 venc device node
> arm64: dts: mt8192: Add vcodec lat and core nodes
> arm64: dts: mt8192: Add dpi node
> arm64: dts: mt8192: Add i2c aliases
> arm64: dts: mt8192: Add display nodes
> arm64: dts: mt8192: Add dsi node
> arm64: dts: mt8192: Add gce info for display nodes
> arm64: dts: mt8192: Add pwm node
>
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1000 +++++++++++++++++++++-
> 1 file changed, 989 insertions(+), 11 deletions(-)
>
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 00/23] Add driver nodes for MT8192 SoC
@ 2022-02-22 3:21 ` Chen-Yu Tsai
0 siblings, 0 replies; 252+ messages in thread
From: Chen-Yu Tsai @ 2022-02-22 3:21 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> This series are based on tag: next-20220216, linux-next/master
> and apply the below patchs
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220207094024.22674-1-allen-kh.cheng@mediatek.com/
It would make things easier if you incorporated the above patch into this
series when you send v3.
ChenYu
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220217135620.10559-1-allen-kh.cheng@mediatek.com/
>
> There some patches are missed in PATCH v1.
> I resend series again and also add display related nodes in PATCH v2.
>
> changes since v1:
> - add usb-phy node for xhci node
> - move infracfg_rst patch in front of PCIe patch
> - add display nodes, i2c aliases and pwm node.
>
> Allen-KH Cheng (23):
> arm64: dts: mt8192: Add power domains controller
> arm64: dts: mt8192: Add pwrap node
> arm64: dts: mt8192: Add spmi node
> arm64: dts: mt8192: Add gce node
> arm64: dts: mt8192: Add SCP node
> arm64: dts: mt8192: Add usb-phy node
> arm64: dts: mt8192: Add xhci node
> arm64: dts: mt8192: Add audio-related nodes
> arm64: dts: mt8192: Add infracfg_rst node
> arm64: dts: mt8192: Add PCIe node
> arm64: dts: mt8192: Correct nor_flash status of mt8192
> arm64: dts: mt8192: Add efuse node
> arm64: dts: mt8192: Add mmc device nodes
> arm64: dts: mt8192: Add mipi_tx node
> arm64: dts: mt8192: Add m4u and smi nodes
> arm64: dts: mt8192: Add H264 venc device node
> arm64: dts: mt8192: Add vcodec lat and core nodes
> arm64: dts: mt8192: Add dpi node
> arm64: dts: mt8192: Add i2c aliases
> arm64: dts: mt8192: Add display nodes
> arm64: dts: mt8192: Add dsi node
> arm64: dts: mt8192: Add gce info for display nodes
> arm64: dts: mt8192: Add pwm node
>
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1000 +++++++++++++++++++++-
> 1 file changed, 989 insertions(+), 11 deletions(-)
>
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 00/23] Add driver nodes for MT8192 SoC
2022-02-22 3:21 ` Chen-Yu Tsai
@ 2022-02-23 13:21 ` allen-kh.cheng
-1 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:21 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
On Tue, 2022-02-22 at 11:21 +0800, Chen-Yu Tsai wrote:
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > This series are based on tag: next-20220216, linux-next/master
> > and apply the below patchs
> >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220207094024.22674-1-allen-kh.cheng@mediatek.com/__;!!CTRNKA9wMg0ARbw!zMCLHB01ZObC6n6oHu5dE6SiAH_IkDBQhvydry6a_5p-mLTx841Cgy8VVZKPfXBIXpT76w$
> >
>
> It would make things easier if you incorporated the above patch into
> this
> series when you send v3.
>
> ChenYu
>
Hi ChenYu,
It's good to me. I will add this in v3. Thanks.
Allen
> >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220217135620.10559-1-allen-kh.cheng@mediatek.com/__;!!CTRNKA9wMg0ARbw!zMCLHB01ZObC6n6oHu5dE6SiAH_IkDBQhvydry6a_5p-mLTx841Cgy8VVZKPfXDBU4qenA$
> >
> >
> > There some patches are missed in PATCH v1.
> > I resend series again and also add display related nodes in PATCH
> > v2.
> >
> > changes since v1:
> > - add usb-phy node for xhci node
> > - move infracfg_rst patch in front of PCIe patch
> > - add display nodes, i2c aliases and pwm node.
> >
> > Allen-KH Cheng (23):
> > arm64: dts: mt8192: Add power domains controller
> > arm64: dts: mt8192: Add pwrap node
> > arm64: dts: mt8192: Add spmi node
> > arm64: dts: mt8192: Add gce node
> > arm64: dts: mt8192: Add SCP node
> > arm64: dts: mt8192: Add usb-phy node
> > arm64: dts: mt8192: Add xhci node
> > arm64: dts: mt8192: Add audio-related nodes
> > arm64: dts: mt8192: Add infracfg_rst node
> > arm64: dts: mt8192: Add PCIe node
> > arm64: dts: mt8192: Correct nor_flash status of mt8192
> > arm64: dts: mt8192: Add efuse node
> > arm64: dts: mt8192: Add mmc device nodes
> > arm64: dts: mt8192: Add mipi_tx node
> > arm64: dts: mt8192: Add m4u and smi nodes
> > arm64: dts: mt8192: Add H264 venc device node
> > arm64: dts: mt8192: Add vcodec lat and core nodes
> > arm64: dts: mt8192: Add dpi node
> > arm64: dts: mt8192: Add i2c aliases
> > arm64: dts: mt8192: Add display nodes
> > arm64: dts: mt8192: Add dsi node
> > arm64: dts: mt8192: Add gce info for display nodes
> > arm64: dts: mt8192: Add pwm node
> >
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1000
> > +++++++++++++++++++++-
> > 1 file changed, 989 insertions(+), 11 deletions(-)
> >
> > --
> > 2.18.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 252+ messages in thread
* Re: [PATCH v2 00/23] Add driver nodes for MT8192 SoC
@ 2022-02-23 13:21 ` allen-kh.cheng
0 siblings, 0 replies; 252+ messages in thread
From: allen-kh.cheng @ 2022-02-23 13:21 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Ryder Lee
On Tue, 2022-02-22 at 11:21 +0800, Chen-Yu Tsai wrote:
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > This series are based on tag: next-20220216, linux-next/master
> > and apply the below patchs
> >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220207094024.22674-1-allen-kh.cheng@mediatek.com/__;!!CTRNKA9wMg0ARbw!zMCLHB01ZObC6n6oHu5dE6SiAH_IkDBQhvydry6a_5p-mLTx841Cgy8VVZKPfXBIXpT76w$
> >
>
> It would make things easier if you incorporated the above patch into
> this
> series when you send v3.
>
> ChenYu
>
Hi ChenYu,
It's good to me. I will add this in v3. Thanks.
Allen
> >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220217135620.10559-1-allen-kh.cheng@mediatek.com/__;!!CTRNKA9wMg0ARbw!zMCLHB01ZObC6n6oHu5dE6SiAH_IkDBQhvydry6a_5p-mLTx841Cgy8VVZKPfXDBU4qenA$
> >
> >
> > There some patches are missed in PATCH v1.
> > I resend series again and also add display related nodes in PATCH
> > v2.
> >
> > changes since v1:
> > - add usb-phy node for xhci node
> > - move infracfg_rst patch in front of PCIe patch
> > - add display nodes, i2c aliases and pwm node.
> >
> > Allen-KH Cheng (23):
> > arm64: dts: mt8192: Add power domains controller
> > arm64: dts: mt8192: Add pwrap node
> > arm64: dts: mt8192: Add spmi node
> > arm64: dts: mt8192: Add gce node
> > arm64: dts: mt8192: Add SCP node
> > arm64: dts: mt8192: Add usb-phy node
> > arm64: dts: mt8192: Add xhci node
> > arm64: dts: mt8192: Add audio-related nodes
> > arm64: dts: mt8192: Add infracfg_rst node
> > arm64: dts: mt8192: Add PCIe node
> > arm64: dts: mt8192: Correct nor_flash status of mt8192
> > arm64: dts: mt8192: Add efuse node
> > arm64: dts: mt8192: Add mmc device nodes
> > arm64: dts: mt8192: Add mipi_tx node
> > arm64: dts: mt8192: Add m4u and smi nodes
> > arm64: dts: mt8192: Add H264 venc device node
> > arm64: dts: mt8192: Add vcodec lat and core nodes
> > arm64: dts: mt8192: Add dpi node
> > arm64: dts: mt8192: Add i2c aliases
> > arm64: dts: mt8192: Add display nodes
> > arm64: dts: mt8192: Add dsi node
> > arm64: dts: mt8192: Add gce info for display nodes
> > arm64: dts: mt8192: Add pwm node
> >
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1000
> > +++++++++++++++++++++-
> > 1 file changed, 989 insertions(+), 11 deletions(-)
> >
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 252+ messages in thread