From: Alexandre Torgue <alexandre.torgue@st.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Amelie Delaunay <amelie.delaunay@st.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] pinctrl: stm32: check node status before new gpio bank registering
Date: Mon, 30 Jul 2018 17:31:22 +0200 [thread overview]
Message-ID: <2f76dbc9-16f1-ddb6-be11-bf0c383b83c6@st.com> (raw)
In-Reply-To: <CACRpkdaDy5MGPMxh3GYFHL9VqTv44=t6J=xu_0sdXc4OHFo84g@mail.gmail.com>
Hi Linus
On 07/29/2018 10:11 PM, Linus Walleij wrote:
> On Mon, Jul 16, 2018 at 2:57 PM Alexandre Torgue
> <alexandre.torgue@st.com> wrote:
>
>> Register a new GPIO bank only if GPIO bank node is enabled. This patch also
>> adds checks on ranges which are defined only if a bank is registered.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
>
> Patch applied.
>
Thanks
> Alexandre can you check the discussion we've had about using
> GPIOLIB_IRQCHIP for multi-bank GPIOs with several IRQ
> lines as per drivers/gpio/gpio-tegra186.c?
>
> Is this approach applicable for STM32 so we can pull
> more stuff in under GPIOLIB_IRQCHIP?
>
Ok. I'm going to check what's possible to do. I let you know soon.
regards
Alex
> Yours,
> Linus Walleij
>
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Torgue <alexandre.torgue@st.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Amelie Delaunay <amelie.delaunay@st.com>
Subject: Re: [PATCH 2/2] pinctrl: stm32: check node status before new gpio bank registering
Date: Mon, 30 Jul 2018 17:31:22 +0200 [thread overview]
Message-ID: <2f76dbc9-16f1-ddb6-be11-bf0c383b83c6@st.com> (raw)
In-Reply-To: <CACRpkdaDy5MGPMxh3GYFHL9VqTv44=t6J=xu_0sdXc4OHFo84g@mail.gmail.com>
Hi Linus
On 07/29/2018 10:11 PM, Linus Walleij wrote:
> On Mon, Jul 16, 2018 at 2:57 PM Alexandre Torgue
> <alexandre.torgue@st.com> wrote:
>
>> Register a new GPIO bank only if GPIO bank node is enabled. This patch also
>> adds checks on ranges which are defined only if a bank is registered.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
>
> Patch applied.
>
Thanks
> Alexandre can you check the discussion we've had about using
> GPIOLIB_IRQCHIP for multi-bank GPIOs with several IRQ
> lines as per drivers/gpio/gpio-tegra186.c?
>
> Is this approach applicable for STM32 so we can pull
> more stuff in under GPIOLIB_IRQCHIP?
>
Ok. I'm going to check what's possible to do. I let you know soon.
regards
Alex
> Yours,
> Linus Walleij
>
WARNING: multiple messages have this Message-ID (diff)
From: alexandre.torgue@st.com (Alexandre Torgue)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] pinctrl: stm32: check node status before new gpio bank registering
Date: Mon, 30 Jul 2018 17:31:22 +0200 [thread overview]
Message-ID: <2f76dbc9-16f1-ddb6-be11-bf0c383b83c6@st.com> (raw)
In-Reply-To: <CACRpkdaDy5MGPMxh3GYFHL9VqTv44=t6J=xu_0sdXc4OHFo84g@mail.gmail.com>
Hi Linus
On 07/29/2018 10:11 PM, Linus Walleij wrote:
> On Mon, Jul 16, 2018 at 2:57 PM Alexandre Torgue
> <alexandre.torgue@st.com> wrote:
>
>> Register a new GPIO bank only if GPIO bank node is enabled. This patch also
>> adds checks on ranges which are defined only if a bank is registered.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
>
> Patch applied.
>
Thanks
> Alexandre can you check the discussion we've had about using
> GPIOLIB_IRQCHIP for multi-bank GPIOs with several IRQ
> lines as per drivers/gpio/gpio-tegra186.c?
>
> Is this approach applicable for STM32 so we can pull
> more stuff in under GPIOLIB_IRQCHIP?
>
Ok. I'm going to check what's possible to do. I let you know soon.
regards
Alex
> Yours,
> Linus Walleij
>
next prev parent reply other threads:[~2018-07-30 15:31 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-16 12:57 [PATCH 0/2] STM32 pinctrl updates Alexandre Torgue
2018-07-16 12:57 ` Alexandre Torgue
2018-07-16 12:57 ` Alexandre Torgue
2018-07-16 12:57 ` [PATCH 1/2] pinctrl: stm32: fix bank io port number Alexandre Torgue
2018-07-16 12:57 ` Alexandre Torgue
2018-07-16 12:57 ` Alexandre Torgue
2018-07-20 16:35 ` Rob Herring
2018-07-20 16:35 ` Rob Herring
2018-07-24 16:07 ` Alexandre Torgue
2018-07-24 16:07 ` Alexandre Torgue
2018-07-24 16:07 ` Alexandre Torgue
2018-07-25 14:00 ` Rob Herring
2018-07-25 14:00 ` Rob Herring
2018-07-25 14:00 ` Rob Herring
2018-07-29 20:02 ` Linus Walleij
2018-07-29 20:02 ` Linus Walleij
2018-07-29 20:02 ` Linus Walleij
2018-07-16 12:57 ` [PATCH 2/2] pinctrl: stm32: check node status before new gpio bank registering Alexandre Torgue
2018-07-16 12:57 ` Alexandre Torgue
2018-07-16 12:57 ` Alexandre Torgue
2018-07-29 20:11 ` Linus Walleij
2018-07-29 20:11 ` Linus Walleij
2018-07-29 20:11 ` Linus Walleij
2018-07-30 15:31 ` Alexandre Torgue [this message]
2018-07-30 15:31 ` Alexandre Torgue
2018-07-30 15:31 ` Alexandre Torgue
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