* [PATCH v2] target/arm: Implement SVE2 scatter store insns
@ 2020-04-22 14:15 Stephen Long
2020-04-24 20:06 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Stephen Long @ 2020-04-22 14:15 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal store
insns.
64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)
32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
Signed-off-by: Stephen Long <steplong@quicinc.com>
Cool, it seemed to typedef correctly.
---
target/arm/sve.decode | 10 ++++++++++
target/arm/translate-sve.c | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index dd987da648..ef5dd281a6 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1387,3 +1387,13 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
### SVE2 floating point matrix multiply accumulate
FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm
+
+### SVE2 Memory Store Group
+
+# SVE2 64-bit scatter non-temporal store (vector plus scalar)
+STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
+ @rprr_scatter_store xs=2 esz=3 scale=0
+
+# SVE2 32-bit scatter non-temporal store (vector plus scalar)
+STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
+ @rprr_scatter_store xs=0 esz=2 scale=0
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 29532424c1..4873e25182 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6038,6 +6038,14 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
return true;
}
+static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return trans_ST1_zprz(s, a);
+}
+
/*
* Prefetches
*/
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] target/arm: Implement SVE2 scatter store insns
2020-04-22 14:15 [PATCH v2] target/arm: Implement SVE2 scatter store insns Stephen Long
@ 2020-04-24 20:06 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2020-04-24 20:06 UTC (permalink / raw)
To: Stephen Long, qemu-devel; +Cc: qemu-arm, apazos
On 4/22/20 7:15 AM, Stephen Long wrote:
> Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal store
> insns.
>
> 64-bit
> * STNT1B (vector plus scalar)
> * STNT1H (vector plus scalar)
> * STNT1W (vector plus scalar)
> * STNT1D (vector plus scalar)
>
> 32-bit
> * STNT1B (vector plus scalar)
> * STNT1H (vector plus scalar)
> * STNT1W (vector plus scalar)
>
> Signed-off-by: Stephen Long <steplong@quicinc.com>
>
> Cool, it seemed to typedef correctly.
> ---
> target/arm/sve.decode | 10 ++++++++++
> target/arm/translate-sve.c | 8 ++++++++
> 2 files changed, 18 insertions(+)
Applied to my SVE2 branch. Thanks!
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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2020-04-24 20:06 ` Richard Henderson
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