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From: Greg Ungerer <gerg@kernel.org>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: NeilBrown <neil@brown.name>, driverdev-devel@linuxdriverproject.org
Subject: Re: staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function
Date: Mon, 3 Jun 2019 11:25:59 +1000	[thread overview]
Message-ID: <2fb10b81-d0d4-b2bc-bd85-b5a64bd5df8e@kernel.org> (raw)
In-Reply-To: <CAMhs-H-x_O21iq=Xm6LDFTTR4xVS4NrN9ePiCLsLpnxVQXieKA@mail.gmail.com>

Hi Sergio,

On 31/5/19 10:37 pm, Sergio Paracuellos wrote:
> On Thu, May 30, 2019 at 3:46 AM Greg Ungerer <gerg@kernel.org> wrote:
>> On 30/5/19 10:44 am, Greg Ungerer wrote:
>>> On 29/5/19 6:08 pm, Sergio Paracuellos wrote:
>>> [snip]
>>>> I have added gpio consumer stuff and reorder a bit the code to be more
>>>> similar to 4.20.
>>>>
>>>> I attach the patch. I have not try it to compile it, because my normal
>>>> environment is in another
>>>> computer and I am in the middle of moving from my current house and
>>>> don't have access to it, sorry.
>>>> So, please try this and let's see what happens.
>>>
>>> No problem, thanks for the patch.
>>>
>>> Unfortunately always locks up on kernel boot:
>>>
>>>     ...
>>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
>>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
>>>     mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
>>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
>>>     mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
>>>     mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
>>>     mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
>>>
>>> That was original linux-5.1 patched with your attached patch.
>>>
>>> I'll try and dig down into that further today and get some
>>> feedback on where it is failing.
>>
>> The first problem I see is that the GPIO MODE register bits for
>> PERST_MODE are set to 00, so in "PCIe Reset" mode. If I hack in
>> a register update for that with:
>>
>>       /* Force PERST PCIe reset into GPIO mode */
>>       *(unsigned int *)(0xbe000060) |=  BIT(10);
> 
> I have set GPIO mode for this in the new attached patch.
> 
>>
>> I do that at the start of mt7621_pcie_init_ports(). With that in
>> place I get further:
>>
>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
>>     mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
>>     mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
>>     mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
>>     mt7621-pci 1e140000.pcie: PCIE0 enabled
>>     mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
>>     mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
>>     pci_bus 0000:00: root bus resource [io  0xffffffff]
>>     pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
>>     pci_bus 0000:00: root bus resource [bus 00-ff]
>>     pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
>>
>> It hangs there...
> 
> I had review the boot order is working for you in version 4.20 and the
> order with the new patch applied. There were
> only one difference, the place where interrupt bits are set. I have
> changed that also in the new attached patch.
> 
> For me, the order now and how the different boot steps are being done
> in v4.20 are the same.
> 
> One other thing I don't really understand why is needed but is in the
> v4.20 code are this two lines:
> 
> pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
> pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
> 
> These are added also in the current patch.

Tried out this latest patch. Unfortunately no good news.

Boot gets through the PCI bus scan, but does not find any devices:

   mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
   mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
   mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
   mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
   mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
   mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
   mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
   mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
   mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
   mt7621-pci 1e140000.pcie: Nothing is connected in virtual bridges. Exiting...

And now in the completely weird and un-expected department the boot
continues on and appears to hang for me when it tries to attach a
UBI NAND flash partition. It hangs there for about a minute or so
and then dumps complaing about flash problems:

   ubi0: attaching mtd3
   ubi0: scanning is finished
   ubi0: empty MTD device detected
   ubi0 warning: do_sync_erase: error -5 while erasing PEB 0, retry
   ubi0 warning: do_sync_erase: error -5 while erasing PEB 0, retry
   ubi0 warning: do_sync_erase: error -5 while erasing PEB 0, retry
   ubi0 error: do_sync_erase: cannot erase PEB 0, error -5
   CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.1.0-ac0 #59
   Stack : 000000f0 00000000 00000000 808e0000 8ebf2000 80070584 808285b8 0000000b
         00000038 00000000 80827e00 8fc23b1c 80870000 00000001 8fc23ab0 aeddef9b
         00000000 00000000 80920000 00000000 00000000 808e7693 000000f1 00000000
         203a6d6d 00000000 00000000 00000000 80870000 00000000 00000000 8080a01c
         00000000 80870000 8ebf1014 8ebd2000 00000018 80361d24 00000004 808e0004
         ...
   Call Trace:
   [<8000cfc0>] show_stack+0x94/0x12c
   [<806e553c>] dump_stack+0x8c/0xd0
   [<803c73c8>] do_sync_erase+0xf4/0x208
   [<803c7694>] ubi_io_sync_erase+0x1b8/0x304
   [<803cbc90>] ubi_early_get_peb+0x148/0x1dc
   [<803ba930>] create_vtbl+0xb4/0x29c
   [<803bafc8>] ubi_read_volume_table+0x27c/0xae4
   [<803cc294>] ubi_attach+0x570/0x15dc
   [<803bf2a0>] ubi_attach_mtd_dev+0x5b0/0xbec
   [<808b0488>] ubi_init+0x1c0/0x274
   [<800015f4>] do_one_initcall+0x50/0x1ac
   [<80897e98>] kernel_init_freeable+0x184/0x26c
   [<807035b4>] kernel_init+0x14/0x110
   [<800071f8>] ret_from_kernel_thread+0x14/0x1c

I tried booting and running this several times, I always get the same
long hang and dump from USB/NAND. If I copy in the one linux-4.20
file, drivers/staging/mt7621-pci/pci-mt7621.c, then the system
boots, scans and finds PCI devices, and does not hang/dump on
UBI/NAND flash setup.

I'll try and dig into it some time today and get you some feedback.

Regards
Greg



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  parent reply	other threads:[~2019-06-03  1:26 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-21  6:44 staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function Greg Ungerer
2019-05-21  8:14 ` Sergio Paracuellos
2019-05-22  0:20   ` Greg Ungerer
2019-05-22  6:27     ` Sergio Paracuellos
2019-05-23  2:11       ` Greg Ungerer
2019-05-23  5:26         ` Sergio Paracuellos
2019-05-24  0:35           ` Greg Ungerer
2019-05-24  5:35             ` Sergio Paracuellos
2019-05-27  4:36               ` Greg Ungerer
2019-05-27  6:35                 ` Sergio Paracuellos
2019-05-27  7:29                   ` Greg Ungerer
2019-05-27  8:02                     ` Sergio Paracuellos
2019-05-29  7:11                       ` Greg Ungerer
2019-05-29  8:08                         ` Sergio Paracuellos
2019-05-30  0:44                           ` Greg Ungerer
2019-05-30  1:46                             ` Greg Ungerer
2019-05-31 12:37                               ` Sergio Paracuellos
2019-05-31 12:47                                 ` Greg Ungerer
2019-06-03  1:25                                 ` Greg Ungerer [this message]
2019-06-03  5:34                                   ` Sergio Paracuellos
2019-06-03 12:31                                     ` Greg Ungerer
2019-06-03 19:59                                       ` Sergio Paracuellos
2019-06-04  1:31                                         ` Greg Ungerer
2019-06-04  5:06                                           ` Sergio Paracuellos
2019-06-04  7:14                                             ` Greg Ungerer
2019-06-04  9:36                                               ` Sergio Paracuellos
2019-06-05  4:01                                                 ` Greg Ungerer
2019-06-05  5:47                                                   ` Sergio Paracuellos
2019-06-05 12:28                                                     ` Sergio Paracuellos
2019-06-06  3:06                                                       ` Greg Ungerer
2019-06-06  5:07                                                         ` Sergio Paracuellos
2019-06-06  6:47                                                           ` Greg Ungerer
     [not found]                                                           ` <CAGSetNsFiGZ_xCJFzYDhmZhPZPu90nTH7EDUHOQt1g-ZzxLw5A@mail.gmail.com>
2019-06-17  3:57                                                             ` Greg Ungerer
2019-06-19  5:28                                                               ` Sergio Paracuellos
     [not found]                           ` <CAGSetNvkNQpqo+F7BRbbh4tdr7FpAU28iyydV5eBCXztNPoFyQ@mail.gmail.com>
2019-05-30  0:47                             ` Greg Ungerer

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