* [PATCH] riscv: Do not save the scratch CSR during suspend
@ 2024-03-12 19:56 ` Samuel Holland
0 siblings, 0 replies; 12+ messages in thread
From: Samuel Holland @ 2024-03-12 19:56 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Samuel Holland, Albert Ou, Andrew Jones, Conor Dooley,
Ley Foon Tan, Paul Walmsley, Pavel Machek, Rafael J. Wysocki,
Sia Jee Heng, linux-kernel, linux-pm
While the processor is executing kernel code, the value of the scratch
CSR is always zero, so there is no need to save the value. Continue to
write the CSR during the resume flow, so we do not rely on firmware to
initialize it.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
arch/riscv/include/asm/suspend.h | 1 -
arch/riscv/kernel/suspend.c | 3 +--
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
index 491296a335d0..6569eefacf38 100644
--- a/arch/riscv/include/asm/suspend.h
+++ b/arch/riscv/include/asm/suspend.h
@@ -13,7 +13,6 @@ struct suspend_context {
/* Saved and restored by low-level functions */
struct pt_regs regs;
/* Saved and restored by high-level functions */
- unsigned long scratch;
unsigned long envcfg;
unsigned long tvec;
unsigned long ie;
diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
index 299795341e8a..3d306d8a253d 100644
--- a/arch/riscv/kernel/suspend.c
+++ b/arch/riscv/kernel/suspend.c
@@ -14,7 +14,6 @@
void suspend_save_csrs(struct suspend_context *context)
{
- context->scratch = csr_read(CSR_SCRATCH);
if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
context->envcfg = csr_read(CSR_ENVCFG);
context->tvec = csr_read(CSR_TVEC);
@@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
void suspend_restore_csrs(struct suspend_context *context)
{
- csr_write(CSR_SCRATCH, context->scratch);
+ csr_write(CSR_SCRATCH, 0);
if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
csr_write(CSR_ENVCFG, context->envcfg);
csr_write(CSR_TVEC, context->tvec);
--
2.43.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
2024-03-12 19:56 ` Samuel Holland
@ 2024-03-13 8:44 ` Andrew Jones
-1 siblings, 0 replies; 12+ messages in thread
From: Andrew Jones @ 2024-03-13 8:44 UTC (permalink / raw)
To: Samuel Holland
Cc: Palmer Dabbelt, linux-riscv, Albert Ou, Conor Dooley,
Ley Foon Tan, Paul Walmsley, Pavel Machek, Rafael J. Wysocki,
Sia Jee Heng, linux-kernel, linux-pm
On Tue, Mar 12, 2024 at 12:56:38PM -0700, Samuel Holland wrote:
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> arch/riscv/include/asm/suspend.h | 1 -
> arch/riscv/kernel/suspend.c | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
> index 491296a335d0..6569eefacf38 100644
> --- a/arch/riscv/include/asm/suspend.h
> +++ b/arch/riscv/include/asm/suspend.h
> @@ -13,7 +13,6 @@ struct suspend_context {
> /* Saved and restored by low-level functions */
> struct pt_regs regs;
> /* Saved and restored by high-level functions */
> - unsigned long scratch;
> unsigned long envcfg;
> unsigned long tvec;
> unsigned long ie;
> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
> index 299795341e8a..3d306d8a253d 100644
> --- a/arch/riscv/kernel/suspend.c
> +++ b/arch/riscv/kernel/suspend.c
> @@ -14,7 +14,6 @@
>
> void suspend_save_csrs(struct suspend_context *context)
> {
> - context->scratch = csr_read(CSR_SCRATCH);
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> context->envcfg = csr_read(CSR_ENVCFG);
> context->tvec = csr_read(CSR_TVEC);
> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>
> void suspend_restore_csrs(struct suspend_context *context)
> {
> - csr_write(CSR_SCRATCH, context->scratch);
> + csr_write(CSR_SCRATCH, 0);
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> csr_write(CSR_ENVCFG, context->envcfg);
> csr_write(CSR_TVEC, context->tvec);
> --
> 2.43.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
@ 2024-03-13 8:44 ` Andrew Jones
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Jones @ 2024-03-13 8:44 UTC (permalink / raw)
To: Samuel Holland
Cc: Palmer Dabbelt, linux-riscv, Albert Ou, Conor Dooley,
Ley Foon Tan, Paul Walmsley, Pavel Machek, Rafael J. Wysocki,
Sia Jee Heng, linux-kernel, linux-pm
On Tue, Mar 12, 2024 at 12:56:38PM -0700, Samuel Holland wrote:
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> arch/riscv/include/asm/suspend.h | 1 -
> arch/riscv/kernel/suspend.c | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
> index 491296a335d0..6569eefacf38 100644
> --- a/arch/riscv/include/asm/suspend.h
> +++ b/arch/riscv/include/asm/suspend.h
> @@ -13,7 +13,6 @@ struct suspend_context {
> /* Saved and restored by low-level functions */
> struct pt_regs regs;
> /* Saved and restored by high-level functions */
> - unsigned long scratch;
> unsigned long envcfg;
> unsigned long tvec;
> unsigned long ie;
> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
> index 299795341e8a..3d306d8a253d 100644
> --- a/arch/riscv/kernel/suspend.c
> +++ b/arch/riscv/kernel/suspend.c
> @@ -14,7 +14,6 @@
>
> void suspend_save_csrs(struct suspend_context *context)
> {
> - context->scratch = csr_read(CSR_SCRATCH);
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> context->envcfg = csr_read(CSR_ENVCFG);
> context->tvec = csr_read(CSR_TVEC);
> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>
> void suspend_restore_csrs(struct suspend_context *context)
> {
> - csr_write(CSR_SCRATCH, context->scratch);
> + csr_write(CSR_SCRATCH, 0);
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> csr_write(CSR_ENVCFG, context->envcfg);
> csr_write(CSR_TVEC, context->tvec);
> --
> 2.43.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH] riscv: Do not save the scratch CSR during suspend
2024-03-12 19:56 ` Samuel Holland
@ 2024-03-15 4:55 ` JeeHeng Sia
-1 siblings, 0 replies; 12+ messages in thread
From: JeeHeng Sia @ 2024-03-15 4:55 UTC (permalink / raw)
To: Samuel Holland, Palmer Dabbelt, linux-riscv
Cc: Albert Ou, Andrew Jones, Conor Dooley, Leyfoon Tan,
Paul Walmsley, Pavel Machek, Rafael J. Wysocki, linux-kernel,
linux-pm
> -----Original Message-----
> From: Samuel Holland <samuel.holland@sifive.com>
> Sent: Wednesday, March 13, 2024 3:57 AM
> To: Palmer Dabbelt <palmer@dabbelt.com>; linux-riscv@lists.infradead.org
> Cc: Samuel Holland <samuel.holland@sifive.com>; Albert Ou <aou@eecs.berkeley.edu>; Andrew Jones <ajones@ventanamicro.com>;
> Conor Dooley <conor.dooley@microchip.com>; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Paul Walmsley
> <paul.walmsley@sifive.com>; Pavel Machek <pavel@ucw.cz>; Rafael J. Wysocki <rafael@kernel.org>; JeeHeng Sia
> <jeeheng.sia@starfivetech.com>; linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org
> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
>
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> arch/riscv/include/asm/suspend.h | 1 -
> arch/riscv/kernel/suspend.c | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
> index 491296a335d0..6569eefacf38 100644
> --- a/arch/riscv/include/asm/suspend.h
> +++ b/arch/riscv/include/asm/suspend.h
> @@ -13,7 +13,6 @@ struct suspend_context {
> /* Saved and restored by low-level functions */
> struct pt_regs regs;
> /* Saved and restored by high-level functions */
> - unsigned long scratch;
> unsigned long envcfg;
> unsigned long tvec;
> unsigned long ie;
> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
> index 299795341e8a..3d306d8a253d 100644
> --- a/arch/riscv/kernel/suspend.c
> +++ b/arch/riscv/kernel/suspend.c
> @@ -14,7 +14,6 @@
>
> void suspend_save_csrs(struct suspend_context *context)
> {
> - context->scratch = csr_read(CSR_SCRATCH);
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> context->envcfg = csr_read(CSR_ENVCFG);
> context->tvec = csr_read(CSR_TVEC);
> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>
> void suspend_restore_csrs(struct suspend_context *context)
> {
> - csr_write(CSR_SCRATCH, context->scratch);
> + csr_write(CSR_SCRATCH, 0);
If the register is always zero, do we need to explicitly write zero to the register during resume?
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> csr_write(CSR_ENVCFG, context->envcfg);
> csr_write(CSR_TVEC, context->tvec);
> --
> 2.43.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH] riscv: Do not save the scratch CSR during suspend
@ 2024-03-15 4:55 ` JeeHeng Sia
0 siblings, 0 replies; 12+ messages in thread
From: JeeHeng Sia @ 2024-03-15 4:55 UTC (permalink / raw)
To: Samuel Holland, Palmer Dabbelt, linux-riscv
Cc: Albert Ou, Andrew Jones, Conor Dooley, Leyfoon Tan,
Paul Walmsley, Pavel Machek, Rafael J. Wysocki, linux-kernel,
linux-pm
> -----Original Message-----
> From: Samuel Holland <samuel.holland@sifive.com>
> Sent: Wednesday, March 13, 2024 3:57 AM
> To: Palmer Dabbelt <palmer@dabbelt.com>; linux-riscv@lists.infradead.org
> Cc: Samuel Holland <samuel.holland@sifive.com>; Albert Ou <aou@eecs.berkeley.edu>; Andrew Jones <ajones@ventanamicro.com>;
> Conor Dooley <conor.dooley@microchip.com>; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Paul Walmsley
> <paul.walmsley@sifive.com>; Pavel Machek <pavel@ucw.cz>; Rafael J. Wysocki <rafael@kernel.org>; JeeHeng Sia
> <jeeheng.sia@starfivetech.com>; linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org
> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
>
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> arch/riscv/include/asm/suspend.h | 1 -
> arch/riscv/kernel/suspend.c | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
> index 491296a335d0..6569eefacf38 100644
> --- a/arch/riscv/include/asm/suspend.h
> +++ b/arch/riscv/include/asm/suspend.h
> @@ -13,7 +13,6 @@ struct suspend_context {
> /* Saved and restored by low-level functions */
> struct pt_regs regs;
> /* Saved and restored by high-level functions */
> - unsigned long scratch;
> unsigned long envcfg;
> unsigned long tvec;
> unsigned long ie;
> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
> index 299795341e8a..3d306d8a253d 100644
> --- a/arch/riscv/kernel/suspend.c
> +++ b/arch/riscv/kernel/suspend.c
> @@ -14,7 +14,6 @@
>
> void suspend_save_csrs(struct suspend_context *context)
> {
> - context->scratch = csr_read(CSR_SCRATCH);
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> context->envcfg = csr_read(CSR_ENVCFG);
> context->tvec = csr_read(CSR_TVEC);
> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>
> void suspend_restore_csrs(struct suspend_context *context)
> {
> - csr_write(CSR_SCRATCH, context->scratch);
> + csr_write(CSR_SCRATCH, 0);
If the register is always zero, do we need to explicitly write zero to the register during resume?
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
> csr_write(CSR_ENVCFG, context->envcfg);
> csr_write(CSR_TVEC, context->tvec);
> --
> 2.43.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
2024-03-15 4:55 ` JeeHeng Sia
@ 2024-03-21 23:51 ` Samuel Holland
-1 siblings, 0 replies; 12+ messages in thread
From: Samuel Holland @ 2024-03-21 23:51 UTC (permalink / raw)
To: JeeHeng Sia, Palmer Dabbelt, linux-riscv
Cc: Albert Ou, Andrew Jones, Conor Dooley, Leyfoon Tan,
Paul Walmsley, Pavel Machek, Rafael J. Wysocki, linux-kernel,
linux-pm
On 2024-03-14 11:55 PM, JeeHeng Sia wrote:
>
>
>> -----Original Message-----
>> From: Samuel Holland <samuel.holland@sifive.com>
>> Sent: Wednesday, March 13, 2024 3:57 AM
>> To: Palmer Dabbelt <palmer@dabbelt.com>; linux-riscv@lists.infradead.org
>> Cc: Samuel Holland <samuel.holland@sifive.com>; Albert Ou <aou@eecs.berkeley.edu>; Andrew Jones <ajones@ventanamicro.com>;
>> Conor Dooley <conor.dooley@microchip.com>; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Paul Walmsley
>> <paul.walmsley@sifive.com>; Pavel Machek <pavel@ucw.cz>; Rafael J. Wysocki <rafael@kernel.org>; JeeHeng Sia
>> <jeeheng.sia@starfivetech.com>; linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org
>> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
>>
>> While the processor is executing kernel code, the value of the scratch
>> CSR is always zero, so there is no need to save the value. Continue to
>> write the CSR during the resume flow, so we do not rely on firmware to
>> initialize it.
>>
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>> arch/riscv/include/asm/suspend.h | 1 -
>> arch/riscv/kernel/suspend.c | 3 +--
>> 2 files changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
>> index 491296a335d0..6569eefacf38 100644
>> --- a/arch/riscv/include/asm/suspend.h
>> +++ b/arch/riscv/include/asm/suspend.h
>> @@ -13,7 +13,6 @@ struct suspend_context {
>> /* Saved and restored by low-level functions */
>> struct pt_regs regs;
>> /* Saved and restored by high-level functions */
>> - unsigned long scratch;
>> unsigned long envcfg;
>> unsigned long tvec;
>> unsigned long ie;
>> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
>> index 299795341e8a..3d306d8a253d 100644
>> --- a/arch/riscv/kernel/suspend.c
>> +++ b/arch/riscv/kernel/suspend.c
>> @@ -14,7 +14,6 @@
>>
>> void suspend_save_csrs(struct suspend_context *context)
>> {
>> - context->scratch = csr_read(CSR_SCRATCH);
>> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
>> context->envcfg = csr_read(CSR_ENVCFG);
>> context->tvec = csr_read(CSR_TVEC);
>> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>>
>> void suspend_restore_csrs(struct suspend_context *context)
>> {
>> - csr_write(CSR_SCRATCH, context->scratch);
>> + csr_write(CSR_SCRATCH, 0);
> If the register is always zero, do we need to explicitly write zero to the register during resume?
The register contains zero while executing in the kernel. While executing in
userspace, the value is nonzero. The value is checked at the beginning of
handle_exception(). We must ensure the value is zero before enabling interrupts,
or we might incorrectly think the interrupt was entered from userspace.
We don't know what the value will be when the hart comes out of non-retentive
suspend. Per the SBI HSM specification, Table 6: "All other registers remain in
an undefined state."
Regards,
Samuel
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
@ 2024-03-21 23:51 ` Samuel Holland
0 siblings, 0 replies; 12+ messages in thread
From: Samuel Holland @ 2024-03-21 23:51 UTC (permalink / raw)
To: JeeHeng Sia, Palmer Dabbelt, linux-riscv
Cc: Albert Ou, Andrew Jones, Conor Dooley, Leyfoon Tan,
Paul Walmsley, Pavel Machek, Rafael J. Wysocki, linux-kernel,
linux-pm
On 2024-03-14 11:55 PM, JeeHeng Sia wrote:
>
>
>> -----Original Message-----
>> From: Samuel Holland <samuel.holland@sifive.com>
>> Sent: Wednesday, March 13, 2024 3:57 AM
>> To: Palmer Dabbelt <palmer@dabbelt.com>; linux-riscv@lists.infradead.org
>> Cc: Samuel Holland <samuel.holland@sifive.com>; Albert Ou <aou@eecs.berkeley.edu>; Andrew Jones <ajones@ventanamicro.com>;
>> Conor Dooley <conor.dooley@microchip.com>; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Paul Walmsley
>> <paul.walmsley@sifive.com>; Pavel Machek <pavel@ucw.cz>; Rafael J. Wysocki <rafael@kernel.org>; JeeHeng Sia
>> <jeeheng.sia@starfivetech.com>; linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org
>> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
>>
>> While the processor is executing kernel code, the value of the scratch
>> CSR is always zero, so there is no need to save the value. Continue to
>> write the CSR during the resume flow, so we do not rely on firmware to
>> initialize it.
>>
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>> arch/riscv/include/asm/suspend.h | 1 -
>> arch/riscv/kernel/suspend.c | 3 +--
>> 2 files changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
>> index 491296a335d0..6569eefacf38 100644
>> --- a/arch/riscv/include/asm/suspend.h
>> +++ b/arch/riscv/include/asm/suspend.h
>> @@ -13,7 +13,6 @@ struct suspend_context {
>> /* Saved and restored by low-level functions */
>> struct pt_regs regs;
>> /* Saved and restored by high-level functions */
>> - unsigned long scratch;
>> unsigned long envcfg;
>> unsigned long tvec;
>> unsigned long ie;
>> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
>> index 299795341e8a..3d306d8a253d 100644
>> --- a/arch/riscv/kernel/suspend.c
>> +++ b/arch/riscv/kernel/suspend.c
>> @@ -14,7 +14,6 @@
>>
>> void suspend_save_csrs(struct suspend_context *context)
>> {
>> - context->scratch = csr_read(CSR_SCRATCH);
>> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
>> context->envcfg = csr_read(CSR_ENVCFG);
>> context->tvec = csr_read(CSR_TVEC);
>> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>>
>> void suspend_restore_csrs(struct suspend_context *context)
>> {
>> - csr_write(CSR_SCRATCH, context->scratch);
>> + csr_write(CSR_SCRATCH, 0);
> If the register is always zero, do we need to explicitly write zero to the register during resume?
The register contains zero while executing in the kernel. While executing in
userspace, the value is nonzero. The value is checked at the beginning of
handle_exception(). We must ensure the value is zero before enabling interrupts,
or we might incorrectly think the interrupt was entered from userspace.
We don't know what the value will be when the hart comes out of non-retentive
suspend. Per the SBI HSM specification, Table 6: "All other registers remain in
an undefined state."
Regards,
Samuel
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
2024-03-21 23:51 ` Samuel Holland
@ 2024-04-09 19:43 ` Palmer Dabbelt
-1 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2024-04-09 19:43 UTC (permalink / raw)
To: samuel.holland
Cc: jeeheng.sia, linux-riscv, aou, ajones, Conor Dooley, leyfoon.tan,
Paul Walmsley, pavel, rafael, linux-kernel, linux-pm
On Thu, 21 Mar 2024 16:51:31 PDT (-0700), samuel.holland@sifive.com wrote:
> On 2024-03-14 11:55 PM, JeeHeng Sia wrote:
>>
>>
>>> -----Original Message-----
>>> From: Samuel Holland <samuel.holland@sifive.com>
>>> Sent: Wednesday, March 13, 2024 3:57 AM
>>> To: Palmer Dabbelt <palmer@dabbelt.com>; linux-riscv@lists.infradead.org
>>> Cc: Samuel Holland <samuel.holland@sifive.com>; Albert Ou <aou@eecs.berkeley.edu>; Andrew Jones <ajones@ventanamicro.com>;
>>> Conor Dooley <conor.dooley@microchip.com>; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Paul Walmsley
>>> <paul.walmsley@sifive.com>; Pavel Machek <pavel@ucw.cz>; Rafael J. Wysocki <rafael@kernel.org>; JeeHeng Sia
>>> <jeeheng.sia@starfivetech.com>; linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org
>>> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
>>>
>>> While the processor is executing kernel code, the value of the scratch
>>> CSR is always zero, so there is no need to save the value. Continue to
>>> write the CSR during the resume flow, so we do not rely on firmware to
>>> initialize it.
>>>
>>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>>> ---
>>>
>>> arch/riscv/include/asm/suspend.h | 1 -
>>> arch/riscv/kernel/suspend.c | 3 +--
>>> 2 files changed, 1 insertion(+), 3 deletions(-)
>>>
>>> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
>>> index 491296a335d0..6569eefacf38 100644
>>> --- a/arch/riscv/include/asm/suspend.h
>>> +++ b/arch/riscv/include/asm/suspend.h
>>> @@ -13,7 +13,6 @@ struct suspend_context {
>>> /* Saved and restored by low-level functions */
>>> struct pt_regs regs;
>>> /* Saved and restored by high-level functions */
>>> - unsigned long scratch;
>>> unsigned long envcfg;
>>> unsigned long tvec;
>>> unsigned long ie;
>>> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
>>> index 299795341e8a..3d306d8a253d 100644
>>> --- a/arch/riscv/kernel/suspend.c
>>> +++ b/arch/riscv/kernel/suspend.c
>>> @@ -14,7 +14,6 @@
>>>
>>> void suspend_save_csrs(struct suspend_context *context)
>>> {
>>> - context->scratch = csr_read(CSR_SCRATCH);
>>> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
>>> context->envcfg = csr_read(CSR_ENVCFG);
>>> context->tvec = csr_read(CSR_TVEC);
>>> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>>>
>>> void suspend_restore_csrs(struct suspend_context *context)
>>> {
>>> - csr_write(CSR_SCRATCH, context->scratch);
>>> + csr_write(CSR_SCRATCH, 0);
>> If the register is always zero, do we need to explicitly write zero to the register during resume?
>
> The register contains zero while executing in the kernel. While executing in
> userspace, the value is nonzero. The value is checked at the beginning of
> handle_exception(). We must ensure the value is zero before enabling interrupts,
> or we might incorrectly think the interrupt was entered from userspace.
>
> We don't know what the value will be when the hart comes out of non-retentive
> suspend. Per the SBI HSM specification, Table 6: "All other registers remain in
> an undefined state."
We're also not setting it at all in `.macro suspend_restore_csrs`, which
I think is just a bug?
That said, I'm kind of seeing bugs everywhere I look in this now -- what
about all the other registers we can poke, like timers/counters or the
V/F state (or anything from M-mode, though maybe that's just someone
else's problem)?
I also think we'd break on medlow kernels, as a bunch of this relies on
medany-as-PIC for the SATP-off transition.
Maybe I'm going crazy here, though...
> Regards,
> Samuel
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
@ 2024-04-09 19:43 ` Palmer Dabbelt
0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2024-04-09 19:43 UTC (permalink / raw)
To: samuel.holland
Cc: jeeheng.sia, linux-riscv, aou, ajones, Conor Dooley, leyfoon.tan,
Paul Walmsley, pavel, rafael, linux-kernel, linux-pm
On Thu, 21 Mar 2024 16:51:31 PDT (-0700), samuel.holland@sifive.com wrote:
> On 2024-03-14 11:55 PM, JeeHeng Sia wrote:
>>
>>
>>> -----Original Message-----
>>> From: Samuel Holland <samuel.holland@sifive.com>
>>> Sent: Wednesday, March 13, 2024 3:57 AM
>>> To: Palmer Dabbelt <palmer@dabbelt.com>; linux-riscv@lists.infradead.org
>>> Cc: Samuel Holland <samuel.holland@sifive.com>; Albert Ou <aou@eecs.berkeley.edu>; Andrew Jones <ajones@ventanamicro.com>;
>>> Conor Dooley <conor.dooley@microchip.com>; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Paul Walmsley
>>> <paul.walmsley@sifive.com>; Pavel Machek <pavel@ucw.cz>; Rafael J. Wysocki <rafael@kernel.org>; JeeHeng Sia
>>> <jeeheng.sia@starfivetech.com>; linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org
>>> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
>>>
>>> While the processor is executing kernel code, the value of the scratch
>>> CSR is always zero, so there is no need to save the value. Continue to
>>> write the CSR during the resume flow, so we do not rely on firmware to
>>> initialize it.
>>>
>>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>>> ---
>>>
>>> arch/riscv/include/asm/suspend.h | 1 -
>>> arch/riscv/kernel/suspend.c | 3 +--
>>> 2 files changed, 1 insertion(+), 3 deletions(-)
>>>
>>> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
>>> index 491296a335d0..6569eefacf38 100644
>>> --- a/arch/riscv/include/asm/suspend.h
>>> +++ b/arch/riscv/include/asm/suspend.h
>>> @@ -13,7 +13,6 @@ struct suspend_context {
>>> /* Saved and restored by low-level functions */
>>> struct pt_regs regs;
>>> /* Saved and restored by high-level functions */
>>> - unsigned long scratch;
>>> unsigned long envcfg;
>>> unsigned long tvec;
>>> unsigned long ie;
>>> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
>>> index 299795341e8a..3d306d8a253d 100644
>>> --- a/arch/riscv/kernel/suspend.c
>>> +++ b/arch/riscv/kernel/suspend.c
>>> @@ -14,7 +14,6 @@
>>>
>>> void suspend_save_csrs(struct suspend_context *context)
>>> {
>>> - context->scratch = csr_read(CSR_SCRATCH);
>>> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
>>> context->envcfg = csr_read(CSR_ENVCFG);
>>> context->tvec = csr_read(CSR_TVEC);
>>> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>>>
>>> void suspend_restore_csrs(struct suspend_context *context)
>>> {
>>> - csr_write(CSR_SCRATCH, context->scratch);
>>> + csr_write(CSR_SCRATCH, 0);
>> If the register is always zero, do we need to explicitly write zero to the register during resume?
>
> The register contains zero while executing in the kernel. While executing in
> userspace, the value is nonzero. The value is checked at the beginning of
> handle_exception(). We must ensure the value is zero before enabling interrupts,
> or we might incorrectly think the interrupt was entered from userspace.
>
> We don't know what the value will be when the hart comes out of non-retentive
> suspend. Per the SBI HSM specification, Table 6: "All other registers remain in
> an undefined state."
We're also not setting it at all in `.macro suspend_restore_csrs`, which
I think is just a bug?
That said, I'm kind of seeing bugs everywhere I look in this now -- what
about all the other registers we can poke, like timers/counters or the
V/F state (or anything from M-mode, though maybe that's just someone
else's problem)?
I also think we'd break on medlow kernels, as a bunch of this relies on
medany-as-PIC for the SATP-off transition.
Maybe I'm going crazy here, though...
> Regards,
> Samuel
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
2024-03-12 19:56 ` Samuel Holland
@ 2024-04-10 14:20 ` patchwork-bot+linux-riscv
-1 siblings, 0 replies; 12+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-04-10 14:20 UTC (permalink / raw)
To: Samuel Holland
Cc: linux-riscv, palmer, aou, ajones, conor.dooley, leyfoon.tan,
paul.walmsley, pavel, rafael, jeeheng.sia, linux-kernel,
linux-pm
Hello:
This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Tue, 12 Mar 2024 12:56:38 -0700 you wrote:
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>
> [...]
Here is the summary with links:
- riscv: Do not save the scratch CSR during suspend
https://git.kernel.org/riscv/c/ba5ea59f768f
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] riscv: Do not save the scratch CSR during suspend
@ 2024-04-10 14:20 ` patchwork-bot+linux-riscv
0 siblings, 0 replies; 12+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-04-10 14:20 UTC (permalink / raw)
To: Samuel Holland
Cc: linux-riscv, palmer, aou, ajones, conor.dooley, leyfoon.tan,
paul.walmsley, pavel, rafael, jeeheng.sia, linux-kernel,
linux-pm
Hello:
This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Tue, 12 Mar 2024 12:56:38 -0700 you wrote:
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>
> [...]
Here is the summary with links:
- riscv: Do not save the scratch CSR during suspend
https://git.kernel.org/riscv/c/ba5ea59f768f
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread