[PATCH v5 0/6] drm/rockchip: px30 dsi support

[PATCH v5 0/6] drm/rockchip: px30 dsi support

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>

This series addes support for the px30 Rockchip soc to the dsi driver.
This includes support for external dsi-phys like used on the px30.

What happened between v1 and v5? The then separate dsi hs2lp timing
patch happened ;-) . As both it and this series touch similar areas
in the dsi driver ordering becomes an issue and so combining them to
make ordering explicit is helpful. v2-v4 where then iterations of the
timing patch.

So this v5 is mainly rebased on 5.5-rc1 and rechecked against drm-misc.

Heiko Stuebner (6):
  drm/bridge/synopsys: dsi: driver-specific configuration of phy timings
  drm/bridge/synopsys: dsi: move phy_ops callbacks around panel
    enablement
  dt-bindings: display: rockchip-dsi: document external phys
  drm/rockchip: add ability to handle external dphys in mipi-dsi
  dt-bindings: display: rockchip-dsi: add px30 compatible
  drm/rockchip: dsi: add px30 support

 .../display/rockchip/dw_mipi_dsi_rockchip.txt |  13 +-
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |  40 ++--
 drivers/gpu/drm/rockchip/Kconfig              |   1 +
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 173 +++++++++++++++++-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         |  13 ++
 include/drm/bridge/dw_mipi_dsi.h              |   9 +
 6 files changed, 227 insertions(+), 22 deletions(-)

-- 
2.24.0

[PATCH v5 0/6] drm/rockchip: px30 dsi support

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

This series addes support for the px30 Rockchip soc to the dsi driver.
This includes support for external dsi-phys like used on the px30.

What happened between v1 and v5? The then separate dsi hs2lp timing
patch happened ;-) . As both it and this series touch similar areas
in the dsi driver ordering becomes an issue and so combining them to
make ordering explicit is helpful. v2-v4 where then iterations of the
timing patch.

So this v5 is mainly rebased on 5.5-rc1 and rechecked against drm-misc.

Heiko Stuebner (6):
  drm/bridge/synopsys: dsi: driver-specific configuration of phy timings
  drm/bridge/synopsys: dsi: move phy_ops callbacks around panel
    enablement
  dt-bindings: display: rockchip-dsi: document external phys
  drm/rockchip: add ability to handle external dphys in mipi-dsi
  dt-bindings: display: rockchip-dsi: add px30 compatible
  drm/rockchip: dsi: add px30 support

 .../display/rockchip/dw_mipi_dsi_rockchip.txt |  13 +-
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |  40 ++--
 drivers/gpu/drm/rockchip/Kconfig              |   1 +
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 173 +++++++++++++++++-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         |  13 ++
 include/drm/bridge/dw_mipi_dsi.h              |   9 +
 6 files changed, 227 insertions(+), 22 deletions(-)

-- 
2.24.0

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[PATCH v5 1/6] drm/bridge/synopsys: dsi: driver-specific configuration of phy timings

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.

To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.

Right now this handles the hs2lp + lp2hs where Rockchip SoCs need handling
according to the phy speed, while STM seems to be ok with static values.

changes in v5:
- rebase on 5.5-rc1
- merge into px30 dsi series to prevent ordering conflicts

changes in v4:
- rebase to make it directly fit on top of drm-misc-next after all

changes in v3:
- check existence of phy_ops->get_timing in __dw_mipi_dsi_probe()
- emit actual error when get_timing() call fails
- add tags from Philippe and Yannick

changes in v2:
- add driver-specific handling, don't force all bridge users to use
  the same timings, as suggested by Philippe

Suggested-by: Philippe Cornu <philippe.cornu@st.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
Tested-by: Yannick Fertre <yannick.fertre@st.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 27 +++++--
 drivers/gpu/drm/rockchip/Kconfig              |  1 +
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 78 +++++++++++++++++++
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         | 13 ++++
 include/drm/bridge/dw_mipi_dsi.h              |  9 +++
 5 files changed, 121 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index b6e793bb653c..bfe0061e54a2 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -719,7 +719,15 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 
 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 {
+	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
+	struct dw_mipi_dsi_dphy_timing timing;
 	u32 hw_version;
+	int ret;
+
+	ret = phy_ops->get_timing(dsi->plat_data->priv_data,
+				  dsi->lane_mbps, &timing);
+	if (ret)
+		DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
 
 	/*
 	 * TODO dw drv improvements
@@ -732,16 +740,20 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 	hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
 
 	if (hw_version >= HWVER_131) {
-		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
-			  PHY_LP2HS_TIME_V131(0x40));
+		dsi_write(dsi, DSI_PHY_TMR_CFG,
+			  PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
+			  PHY_LP2HS_TIME_V131(timing.data_lp2hs));
 		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
 	} else {
-		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
-			  PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
+		dsi_write(dsi, DSI_PHY_TMR_CFG,
+			  PHY_HS2LP_TIME(timing.data_hs2lp) |
+			  PHY_LP2HS_TIME(timing.data_lp2hs) |
+			  MAX_RD_TIME(10000));
 	}
 
-	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
-		  | PHY_CLKLP2HS_TIME(0x40));
+	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
+		  PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
+		  PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
 }
 
 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -991,7 +1003,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
 	dsi->dev = dev;
 	dsi->plat_data = plat_data;
 
-	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
+	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||
+	    !plat_data->phy_ops->get_timing) {
 		DRM_ERROR("Phy not properly configured\n");
 		return ERR_PTR(-ENODEV);
 	}
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 6f4222f8beeb..4b7a276994ce 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -46,6 +46,7 @@ config ROCKCHIP_DW_HDMI
 
 config ROCKCHIP_DW_MIPI_DSI
 	bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+	select GENERIC_PHY_MIPI_DPHY
 	help
 	  This selects support for Rockchip SoC specific extensions
 	  for the Synopsys DesignWare HDMI driver. If you want to
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index bc073ec5c183..9406effe8077 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -559,9 +559,87 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 	return 0;
 }
 
+struct hstt {
+	unsigned int maxfreq;
+	struct dw_mipi_dsi_dphy_timing timing;
+};
+
+#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)	\
+{					\
+	.maxfreq = _maxfreq,		\
+	.timing = {			\
+		.clk_lp2hs = _c_lp2hs,	\
+		.clk_hs2lp = _c_hs2lp,	\
+		.data_lp2hs = _d_lp2hs,	\
+		.data_hs2lp = _d_hs2lp,	\
+	}				\
+}
+
+/* Table A-3 High-Speed Transition Times */
+struct hstt hstt_table[] = {
+	HSTT(  90,  32, 20,  26, 13),
+	HSTT( 100,  35, 23,  28, 14),
+	HSTT( 110,  32, 22,  26, 13),
+	HSTT( 130,  31, 20,  27, 13),
+	HSTT( 140,  33, 22,  26, 14),
+	HSTT( 150,  33, 21,  26, 14),
+	HSTT( 170,  32, 20,  27, 13),
+	HSTT( 180,  36, 23,  30, 15),
+	HSTT( 200,  40, 22,  33, 15),
+	HSTT( 220,  40, 22,  33, 15),
+	HSTT( 240,  44, 24,  36, 16),
+	HSTT( 250,  48, 24,  38, 17),
+	HSTT( 270,  48, 24,  38, 17),
+	HSTT( 300,  50, 27,  41, 18),
+	HSTT( 330,  56, 28,  45, 18),
+	HSTT( 360,  59, 28,  48, 19),
+	HSTT( 400,  61, 30,  50, 20),
+	HSTT( 450,  67, 31,  55, 21),
+	HSTT( 500,  73, 31,  59, 22),
+	HSTT( 550,  79, 36,  63, 24),
+	HSTT( 600,  83, 37,  68, 25),
+	HSTT( 650,  90, 38,  73, 27),
+	HSTT( 700,  95, 40,  77, 28),
+	HSTT( 750, 102, 40,  84, 28),
+	HSTT( 800, 106, 42,  87, 30),
+	HSTT( 850, 113, 44,  93, 31),
+	HSTT( 900, 118, 47,  98, 32),
+	HSTT( 950, 124, 47, 102, 34),
+	HSTT(1000, 130, 49, 107, 35),
+	HSTT(1050, 135, 51, 111, 37),
+	HSTT(1100, 139, 51, 114, 38),
+	HSTT(1150, 146, 54, 120, 40),
+	HSTT(1200, 153, 57, 125, 41),
+	HSTT(1250, 158, 58, 130, 42),
+	HSTT(1300, 163, 58, 135, 44),
+	HSTT(1350, 168, 60, 140, 45),
+	HSTT(1400, 172, 64, 144, 47),
+	HSTT(1450, 176, 65, 148, 48),
+	HSTT(1500, 181, 66, 153, 50)
+};
+
+static int
+dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
+			   struct dw_mipi_dsi_dphy_timing *timing)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
+		if (lane_mbps < hstt_table[i].maxfreq)
+			break;
+
+	if (i == ARRAY_SIZE(hstt_table))
+		i--;
+
+	*timing = hstt_table[i].timing;
+
+	return 0;
+}
+
 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
 	.init = dw_mipi_dsi_phy_init,
 	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
+	.get_timing = dw_mipi_dsi_phy_get_timing,
 };
 
 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 514efefb0016..4b165635b2d4 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -309,11 +309,24 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 	return 0;
 }
 
+static int
+dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
+			   struct dw_mipi_dsi_dphy_timing *timing)
+{
+	timing->clk_hs2lp = 0x40;
+	timing->clk_lp2hs = 0x40;
+	timing->data_hs2lp = 0x40;
+	timing->data_lp2hs = 0x40;
+
+	return 0;
+}
+
 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
 	.init = dw_mipi_dsi_phy_init,
 	.power_on = dw_mipi_dsi_phy_power_on,
 	.power_off = dw_mipi_dsi_phy_power_off,
 	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
+	.get_timing = dw_mipi_dsi_phy_get_timing,
 };
 
 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
index 94cc64a342e1..b0e390b3288e 100644
--- a/include/drm/bridge/dw_mipi_dsi.h
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -19,6 +19,13 @@ struct dw_mipi_dsi;
 struct mipi_dsi_device;
 struct platform_device;
 
+struct dw_mipi_dsi_dphy_timing {
+	u16 data_hs2lp;
+	u16 data_lp2hs;
+	u16 clk_hs2lp;
+	u16 clk_lp2hs;
+};
+
 struct dw_mipi_dsi_phy_ops {
 	int (*init)(void *priv_data);
 	void (*power_on)(void *priv_data);
@@ -27,6 +34,8 @@ struct dw_mipi_dsi_phy_ops {
 			     const struct drm_display_mode *mode,
 			     unsigned long mode_flags, u32 lanes, u32 format,
 			     unsigned int *lane_mbps);
+	int (*get_timing)(void *priv_data, unsigned int lane_mbps,
+			  struct dw_mipi_dsi_dphy_timing *timing);
 };
 
 struct dw_mipi_dsi_host_ops {
-- 
2.24.0

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[PATCH v5 2/6] drm/bridge/synopsys: dsi: move phy_ops callbacks around panel enablement

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

If implementation-specific phy_ops need to be defined they probably
should be enabled before trying to talk to the panel and disabled only
after the panel was disabled.

Right now they are enabled last and disabled first, so might make it
impossible to talk to some panels - example for this being the px30
with an external Innosilicon dphy that needs the phy to be enabled
to transfer commands to the panel.

So move the calls appropriately.

changed in v5:
- rebased on top of 5.5-rc1
- merged with dsi timing change to prevent ordering conflicts

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index bfe0061e54a2..b18351b6760a 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -810,9 +810,6 @@ static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
 	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 
-	if (phy_ops->power_off)
-		phy_ops->power_off(dsi->plat_data->priv_data);
-
 	/*
 	 * Switch to command mode before panel-bridge post_disable &
 	 * panel unprepare.
@@ -829,6 +826,9 @@ static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
 	 */
 	dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
 
+	if (phy_ops->power_off)
+		phy_ops->power_off(dsi->plat_data->priv_data);
+
 	if (dsi->slave) {
 		dw_mipi_dsi_disable(dsi->slave);
 		clk_disable_unprepare(dsi->slave->pclk);
@@ -895,6 +895,9 @@ static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
 
 	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
 	dw_mipi_dsi_set_mode(dsi, 0);
+
+	if (phy_ops->power_on)
+		phy_ops->power_on(dsi->plat_data->priv_data);
 }
 
 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
@@ -911,15 +914,11 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
 {
 	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
-	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 
 	/* Switch to video mode for panel-bridge enable & panel enable */
 	dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
 	if (dsi->slave)
 		dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
-
-	if (phy_ops->power_on)
-		phy_ops->power_on(dsi->plat_data->priv_data);
 }
 
 static enum drm_mode_status
-- 
2.24.0

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[PATCH v5 3/6] dt-bindings: display: rockchip-dsi: document external phys

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Some dw-mipi-dsi instances in Rockchip SoCs use external dphys.
In these cases the needs clock will also be generated externally
so these don't need the ref-clock as well.

changes in v5:
- rebased on top of 5.5-rc1
- merged with dsi timing change to prevent ordering conflicts

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt     | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index ce4c1fc9116c..1ba9237d0ac0 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -9,8 +9,9 @@ Required properties:
 - reg: Represent the physical address range of the controller.
 - interrupts: Represent the controller's interrupt to the CPU(s).
 - clocks, clock-names: Phandles to the controller's pll reference
-  clock(ref) and APB clock(pclk). For RK3399, a phy config clock
-  (phy_cfg) and a grf clock(grf) are required. As described in [1].
+  clock(ref) when using an internal dphy and APB clock(pclk).
+  For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
+  are required. As described in [1].
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
@@ -18,6 +19,8 @@ Required properties:
 - video port 1 for either a panel or subsequent encoder
 
 Optional properties:
+- phys: from general PHY binding: the phandle for the PHY device.
+- phy-names: Should be "dphy" if phys references an external phy.
 - power-domains: a phandle to mipi dsi power domain node.
 - resets: list of phandle + reset specifier pairs, as described in [3].
 - reset-names: string reset name, must be "apb".
-- 
2.24.0

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[PATCH v5 4/6] drm/rockchip: add ability to handle external dphys in mipi-dsi

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

While the common case is that the dsi controller uses an internal dphy,
accessed through the phy registers inside the dsi controller, there is
also the possibility to use a separate dphy from a different vendor.

One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
so add the support for handling such a constellation, including the pll
also getting generated inside that external phy.

changes in v5:
- rebased on top of 5.5-rc1
- merged with dsi timing change to prevent ordering conflicts

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 68 +++++++++++++++++--
 1 file changed, 64 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 9406effe8077..f16bd1e9b633 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -12,6 +12,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
+#include <linux/phy/phy.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 
@@ -223,6 +224,10 @@ struct dw_mipi_dsi_rockchip {
 	bool is_slave;
 	struct dw_mipi_dsi_rockchip *slave;
 
+	/* optional external dphy */
+	struct phy *phy;
+	union phy_configure_opts phy_opts;
+
 	unsigned int lane_mbps; /* per lane */
 	u16 input_div;
 	u16 feedback_div;
@@ -359,6 +364,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
 	struct dw_mipi_dsi_rockchip *dsi = priv_data;
 	int ret, i, vco;
 
+	if (dsi->phy)
+		return 0;
+
 	/*
 	 * Get vco from frequency(lane_mbps)
 	 * vco	frequency table
@@ -467,6 +475,28 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
 	return ret;
 }
 
+static void dw_mipi_dsi_phy_power_on(void *priv_data)
+{
+	struct dw_mipi_dsi_rockchip *dsi = priv_data;
+	int ret;
+
+	ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
+	if (ret) {
+		DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
+		return;
+	}
+
+	phy_configure(dsi->phy, &dsi->phy_opts);
+	phy_power_on(dsi->phy);
+}
+
+static void dw_mipi_dsi_phy_power_off(void *priv_data)
+{
+	struct dw_mipi_dsi_rockchip *dsi = priv_data;
+
+	phy_power_off(dsi->phy);
+}
+
 static int
 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 			  unsigned long mode_flags, u32 lanes, u32 format,
@@ -504,6 +534,17 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 				      "DPHY clock frequency is out of range\n");
 	}
 
+	/* for external phy only a the mipi_dphy_config is necessary */
+	if (dsi->phy) {
+		phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
+						 bpp, lanes,
+						 &dsi->phy_opts.mipi_dphy);
+		dsi->lane_mbps = target_mbps;
+		*lane_mbps = dsi->lane_mbps;
+
+		return 0;
+	}
+
 	fin = clk_get_rate(dsi->pllref_clk);
 	fout = target_mbps * USEC_PER_SEC;
 
@@ -638,6 +679,8 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
 
 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
 	.init = dw_mipi_dsi_phy_init,
+	.power_on = dw_mipi_dsi_phy_power_on,
+	.power_off = dw_mipi_dsi_phy_power_off,
 	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
 	.get_timing = dw_mipi_dsi_phy_get_timing,
 };
@@ -998,12 +1041,29 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	/* try to get a possible external dphy */
+	dsi->phy = devm_phy_optional_get(dev, "dphy");
+	if (IS_ERR(dsi->phy)) {
+		ret = PTR_ERR(dsi->phy);
+		DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
+		return ret;
+	}
+
 	dsi->pllref_clk = devm_clk_get(dev, "ref");
 	if (IS_ERR(dsi->pllref_clk)) {
-		ret = PTR_ERR(dsi->pllref_clk);
-		DRM_DEV_ERROR(dev,
-			      "Unable to get pll reference clock: %d\n", ret);
-		return ret;
+		if (dsi->phy) {
+			/*
+			 * if external phy is present, pll will be
+			 * generated there.
+			 */
+			dsi->pllref_clk = NULL;
+		} else {
+			ret = PTR_ERR(dsi->pllref_clk);
+			DRM_DEV_ERROR(dev,
+				      "Unable to get pll reference clock: %d\n",
+				      ret);
+			return ret;
+		}
 	}
 
 	if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
-- 
2.24.0

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[PATCH v5 5/6] dt-bindings: display: rockchip-dsi: add px30 compatible

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The px30 SoC also uses a dw-mipi-dsi controller, so add the
compatible value for it.

changes in v5:
- rebased on top of 5.5-rc1
- merged with dsi timing change to prevent ordering conflicts

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt      | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 1ba9237d0ac0..151be3bba06f 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -4,8 +4,10 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI
 Required properties:
 - #address-cells: Should be <1>.
 - #size-cells: Should be <0>.
-- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
-	      "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
+- compatible: one of
+	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
+	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
+	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
 - reg: Represent the physical address range of the controller.
 - interrupts: Represent the controller's interrupt to the CPU(s).
 - clocks, clock-names: Phandles to the controller's pll reference
-- 
2.24.0

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[PATCH v5 6/6] drm/rockchip: dsi: add px30 support

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>

Add the compatible and GRF definitions for the PX30 soc.

changes in v5:
- rebased on top of 5.5-rc1
- merged with dsi timing change to prevent ordering conflicts

Signed-off-by: Heiko Stuebner <heiko.stuebner-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>
---
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index f16bd1e9b633..f04b5064974d 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -140,6 +140,12 @@
 #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
 #define DW_MIPI_NEEDS_GRF_CLK		BIT(1)
 
+#define PX30_GRF_PD_VO_CON1		0x0438
+#define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)
+#define PX30_DSI_FORCERXMODE		BIT(6)
+#define PX30_DSI_TURNDISABLE		BIT(5)
+#define PX30_DSI_LCDC_SEL		BIT(0)
+
 #define RK3288_GRF_SOC_CON6		0x025c
 #define RK3288_DSI0_LCDC_SEL		BIT(6)
 #define RK3288_DSI1_LCDC_SEL		BIT(9)
@@ -1127,6 +1133,24 @@ static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
+	{
+		.reg = 0xff450000,
+		.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
+		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
+		.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
+					    PX30_DSI_LCDC_SEL),
+
+		.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
+		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
+					     PX30_DSI_FORCERXMODE |
+					     PX30_DSI_FORCETXSTOPMODE),
+
+		.max_data_lanes = 4,
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
 	{
 		.reg = 0xff960000,
@@ -1195,6 +1219,9 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
 
 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
 	{
+	 .compatible = "rockchip,px30-mipi-dsi",
+	 .data = &px30_chip_data,
+	}, {
 	 .compatible = "rockchip,rk3288-mipi-dsi",
 	 .data = &rk3288_chip_data,
 	}, {
-- 
2.24.0

[PATCH v5 6/6] drm/rockchip: dsi: add px30 support

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Add the compatible and GRF definitions for the PX30 soc.

changes in v5:
- rebased on top of 5.5-rc1
- merged with dsi timing change to prevent ordering conflicts

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index f16bd1e9b633..f04b5064974d 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -140,6 +140,12 @@
 #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
 #define DW_MIPI_NEEDS_GRF_CLK		BIT(1)
 
+#define PX30_GRF_PD_VO_CON1		0x0438
+#define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)
+#define PX30_DSI_FORCERXMODE		BIT(6)
+#define PX30_DSI_TURNDISABLE		BIT(5)
+#define PX30_DSI_LCDC_SEL		BIT(0)
+
 #define RK3288_GRF_SOC_CON6		0x025c
 #define RK3288_DSI0_LCDC_SEL		BIT(6)
 #define RK3288_DSI1_LCDC_SEL		BIT(9)
@@ -1127,6 +1133,24 @@ static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
+	{
+		.reg = 0xff450000,
+		.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
+		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
+		.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
+					    PX30_DSI_LCDC_SEL),
+
+		.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
+		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
+					     PX30_DSI_FORCERXMODE |
+					     PX30_DSI_FORCETXSTOPMODE),
+
+		.max_data_lanes = 4,
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
 	{
 		.reg = 0xff960000,
@@ -1195,6 +1219,9 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
 
 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
 	{
+	 .compatible = "rockchip,px30-mipi-dsi",
+	 .data = &px30_chip_data,
+	}, {
 	 .compatible = "rockchip,rk3288-mipi-dsi",
 	 .data = &rk3288_chip_data,
 	}, {
-- 
2.24.0

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Re: [PATCH v5 1/6] drm/bridge/synopsys: dsi: driver-specific configuration of phy timings

[Neil Armstrong]

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The timing values for dw-dsi are often dependent on the used display and
> according to Philippe Cornu will most likely also depend on the used phy
> technology in the soc-specific implementation.
> 
> To solve this and allow specific implementations to define them as needed
> add a new get_timing callback to phy_ops and call this from the dphy_timing
> function to retrieve the necessary values for the specific mode.
> 
> Right now this handles the hs2lp + lp2hs where Rockchip SoCs need handling
> according to the phy speed, while STM seems to be ok with static values.
> 
> changes in v5:
> - rebase on 5.5-rc1
> - merge into px30 dsi series to prevent ordering conflicts
> 
> changes in v4:
> - rebase to make it directly fit on top of drm-misc-next after all
> 
> changes in v3:
> - check existence of phy_ops->get_timing in __dw_mipi_dsi_probe()
> - emit actual error when get_timing() call fails
> - add tags from Philippe and Yannick
> 
> changes in v2:
> - add driver-specific handling, don't force all bridge users to use
>   the same timings, as suggested by Philippe
> 
> Suggested-by: Philippe Cornu <philippe.cornu@st.com>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
> Tested-by: Yannick Fertre <yannick.fertre@st.com>
> ---
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 27 +++++--
>  drivers/gpu/drm/rockchip/Kconfig              |  1 +
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 78 +++++++++++++++++++
>  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         | 13 ++++
>  include/drm/bridge/dw_mipi_dsi.h              |  9 +++
>  5 files changed, 121 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index b6e793bb653c..bfe0061e54a2 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -719,7 +719,15 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>  
>  static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>  {
> +	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
> +	struct dw_mipi_dsi_dphy_timing timing;
>  	u32 hw_version;
> +	int ret;
> +
> +	ret = phy_ops->get_timing(dsi->plat_data->priv_data,
> +				  dsi->lane_mbps, &timing);
> +	if (ret)
> +		DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
>  
>  	/*
>  	 * TODO dw drv improvements
> @@ -732,16 +740,20 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>  	hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
>  
>  	if (hw_version >= HWVER_131) {
> -		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
> -			  PHY_LP2HS_TIME_V131(0x40));
> +		dsi_write(dsi, DSI_PHY_TMR_CFG,
> +			  PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> +			  PHY_LP2HS_TIME_V131(timing.data_lp2hs));
>  		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
>  	} else {
> -		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
> -			  PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
> +		dsi_write(dsi, DSI_PHY_TMR_CFG,
> +			  PHY_HS2LP_TIME(timing.data_hs2lp) |
> +			  PHY_LP2HS_TIME(timing.data_lp2hs) |
> +			  MAX_RD_TIME(10000));
>  	}
>  
> -	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
> -		  | PHY_CLKLP2HS_TIME(0x40));
> +	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
> +		  PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> +		  PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
>  }
>  
>  static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> @@ -991,7 +1003,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>  	dsi->dev = dev;
>  	dsi->plat_data = plat_data;
>  
> -	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
> +	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||
> +	    !plat_data->phy_ops->get_timing) {
>  		DRM_ERROR("Phy not properly configured\n");
>  		return ERR_PTR(-ENODEV);
>  	}
> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
> index 6f4222f8beeb..4b7a276994ce 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -46,6 +46,7 @@ config ROCKCHIP_DW_HDMI
>  
>  config ROCKCHIP_DW_MIPI_DSI
>  	bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
> +	select GENERIC_PHY_MIPI_DPHY
>  	help
>  	  This selects support for Rockchip SoC specific extensions
>  	  for the Synopsys DesignWare HDMI driver. If you want to
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index bc073ec5c183..9406effe8077 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -559,9 +559,87 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  	return 0;
>  }
>  
> +struct hstt {
> +	unsigned int maxfreq;
> +	struct dw_mipi_dsi_dphy_timing timing;
> +};
> +
> +#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)	\
> +{					\
> +	.maxfreq = _maxfreq,		\
> +	.timing = {			\
> +		.clk_lp2hs = _c_lp2hs,	\
> +		.clk_hs2lp = _c_hs2lp,	\
> +		.data_lp2hs = _d_lp2hs,	\
> +		.data_hs2lp = _d_hs2lp,	\
> +	}				\
> +}
> +
> +/* Table A-3 High-Speed Transition Times */
> +struct hstt hstt_table[] = {
> +	HSTT(  90,  32, 20,  26, 13),
> +	HSTT( 100,  35, 23,  28, 14),
> +	HSTT( 110,  32, 22,  26, 13),
> +	HSTT( 130,  31, 20,  27, 13),
> +	HSTT( 140,  33, 22,  26, 14),
> +	HSTT( 150,  33, 21,  26, 14),
> +	HSTT( 170,  32, 20,  27, 13),
> +	HSTT( 180,  36, 23,  30, 15),
> +	HSTT( 200,  40, 22,  33, 15),
> +	HSTT( 220,  40, 22,  33, 15),
> +	HSTT( 240,  44, 24,  36, 16),
> +	HSTT( 250,  48, 24,  38, 17),
> +	HSTT( 270,  48, 24,  38, 17),
> +	HSTT( 300,  50, 27,  41, 18),
> +	HSTT( 330,  56, 28,  45, 18),
> +	HSTT( 360,  59, 28,  48, 19),
> +	HSTT( 400,  61, 30,  50, 20),
> +	HSTT( 450,  67, 31,  55, 21),
> +	HSTT( 500,  73, 31,  59, 22),
> +	HSTT( 550,  79, 36,  63, 24),
> +	HSTT( 600,  83, 37,  68, 25),
> +	HSTT( 650,  90, 38,  73, 27),
> +	HSTT( 700,  95, 40,  77, 28),
> +	HSTT( 750, 102, 40,  84, 28),
> +	HSTT( 800, 106, 42,  87, 30),
> +	HSTT( 850, 113, 44,  93, 31),
> +	HSTT( 900, 118, 47,  98, 32),
> +	HSTT( 950, 124, 47, 102, 34),
> +	HSTT(1000, 130, 49, 107, 35),
> +	HSTT(1050, 135, 51, 111, 37),
> +	HSTT(1100, 139, 51, 114, 38),
> +	HSTT(1150, 146, 54, 120, 40),
> +	HSTT(1200, 153, 57, 125, 41),
> +	HSTT(1250, 158, 58, 130, 42),
> +	HSTT(1300, 163, 58, 135, 44),
> +	HSTT(1350, 168, 60, 140, 45),
> +	HSTT(1400, 172, 64, 144, 47),
> +	HSTT(1450, 176, 65, 148, 48),
> +	HSTT(1500, 181, 66, 153, 50)
> +};
> +
> +static int
> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> +			   struct dw_mipi_dsi_dphy_timing *timing)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
> +		if (lane_mbps < hstt_table[i].maxfreq)
> +			break;
> +
> +	if (i == ARRAY_SIZE(hstt_table))
> +		i--;
> +
> +	*timing = hstt_table[i].timing;
> +
> +	return 0;
> +}
> +
>  static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
>  	.init = dw_mipi_dsi_phy_init,
>  	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> +	.get_timing = dw_mipi_dsi_phy_get_timing,
>  };
>  
>  static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,
> diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> index 514efefb0016..4b165635b2d4 100644
> --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> @@ -309,11 +309,24 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  	return 0;
>  }
>  
> +static int
> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> +			   struct dw_mipi_dsi_dphy_timing *timing)
> +{
> +	timing->clk_hs2lp = 0x40;
> +	timing->clk_lp2hs = 0x40;
> +	timing->data_hs2lp = 0x40;
> +	timing->data_lp2hs = 0x40;
> +
> +	return 0;
> +}
> +
>  static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
>  	.init = dw_mipi_dsi_phy_init,
>  	.power_on = dw_mipi_dsi_phy_power_on,
>  	.power_off = dw_mipi_dsi_phy_power_off,
>  	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> +	.get_timing = dw_mipi_dsi_phy_get_timing,
>  };
>  
>  static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
> diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
> index 94cc64a342e1..b0e390b3288e 100644
> --- a/include/drm/bridge/dw_mipi_dsi.h
> +++ b/include/drm/bridge/dw_mipi_dsi.h
> @@ -19,6 +19,13 @@ struct dw_mipi_dsi;
>  struct mipi_dsi_device;
>  struct platform_device;
>  
> +struct dw_mipi_dsi_dphy_timing {
> +	u16 data_hs2lp;
> +	u16 data_lp2hs;
> +	u16 clk_hs2lp;
> +	u16 clk_lp2hs;
> +};
> +
>  struct dw_mipi_dsi_phy_ops {
>  	int (*init)(void *priv_data);
>  	void (*power_on)(void *priv_data);
> @@ -27,6 +34,8 @@ struct dw_mipi_dsi_phy_ops {
>  			     const struct drm_display_mode *mode,
>  			     unsigned long mode_flags, u32 lanes, u32 format,
>  			     unsigned int *lane_mbps);
> +	int (*get_timing)(void *priv_data, unsigned int lane_mbps,
> +			  struct dw_mipi_dsi_dphy_timing *timing);
>  };
>  
>  struct dw_mipi_dsi_host_ops {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH v5 1/6] drm/bridge/synopsys: dsi: driver-specific configuration of phy timings

[Neil Armstrong]

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The timing values for dw-dsi are often dependent on the used display and
> according to Philippe Cornu will most likely also depend on the used phy
> technology in the soc-specific implementation.
> 
> To solve this and allow specific implementations to define them as needed
> add a new get_timing callback to phy_ops and call this from the dphy_timing
> function to retrieve the necessary values for the specific mode.
> 
> Right now this handles the hs2lp + lp2hs where Rockchip SoCs need handling
> according to the phy speed, while STM seems to be ok with static values.
> 
> changes in v5:
> - rebase on 5.5-rc1
> - merge into px30 dsi series to prevent ordering conflicts
> 
> changes in v4:
> - rebase to make it directly fit on top of drm-misc-next after all
> 
> changes in v3:
> - check existence of phy_ops->get_timing in __dw_mipi_dsi_probe()
> - emit actual error when get_timing() call fails
> - add tags from Philippe and Yannick
> 
> changes in v2:
> - add driver-specific handling, don't force all bridge users to use
>   the same timings, as suggested by Philippe
> 
> Suggested-by: Philippe Cornu <philippe.cornu@st.com>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
> Tested-by: Yannick Fertre <yannick.fertre@st.com>
> ---
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 27 +++++--
>  drivers/gpu/drm/rockchip/Kconfig              |  1 +
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 78 +++++++++++++++++++
>  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         | 13 ++++
>  include/drm/bridge/dw_mipi_dsi.h              |  9 +++
>  5 files changed, 121 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index b6e793bb653c..bfe0061e54a2 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -719,7 +719,15 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>  
>  static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>  {
> +	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
> +	struct dw_mipi_dsi_dphy_timing timing;
>  	u32 hw_version;
> +	int ret;
> +
> +	ret = phy_ops->get_timing(dsi->plat_data->priv_data,
> +				  dsi->lane_mbps, &timing);
> +	if (ret)
> +		DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
>  
>  	/*
>  	 * TODO dw drv improvements
> @@ -732,16 +740,20 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>  	hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
>  
>  	if (hw_version >= HWVER_131) {
> -		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
> -			  PHY_LP2HS_TIME_V131(0x40));
> +		dsi_write(dsi, DSI_PHY_TMR_CFG,
> +			  PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> +			  PHY_LP2HS_TIME_V131(timing.data_lp2hs));
>  		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
>  	} else {
> -		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
> -			  PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
> +		dsi_write(dsi, DSI_PHY_TMR_CFG,
> +			  PHY_HS2LP_TIME(timing.data_hs2lp) |
> +			  PHY_LP2HS_TIME(timing.data_lp2hs) |
> +			  MAX_RD_TIME(10000));
>  	}
>  
> -	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
> -		  | PHY_CLKLP2HS_TIME(0x40));
> +	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
> +		  PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> +		  PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
>  }
>  
>  static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> @@ -991,7 +1003,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>  	dsi->dev = dev;
>  	dsi->plat_data = plat_data;
>  
> -	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
> +	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||
> +	    !plat_data->phy_ops->get_timing) {
>  		DRM_ERROR("Phy not properly configured\n");
>  		return ERR_PTR(-ENODEV);
>  	}
> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
> index 6f4222f8beeb..4b7a276994ce 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -46,6 +46,7 @@ config ROCKCHIP_DW_HDMI
>  
>  config ROCKCHIP_DW_MIPI_DSI
>  	bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
> +	select GENERIC_PHY_MIPI_DPHY
>  	help
>  	  This selects support for Rockchip SoC specific extensions
>  	  for the Synopsys DesignWare HDMI driver. If you want to
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index bc073ec5c183..9406effe8077 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -559,9 +559,87 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  	return 0;
>  }
>  
> +struct hstt {
> +	unsigned int maxfreq;
> +	struct dw_mipi_dsi_dphy_timing timing;
> +};
> +
> +#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)	\
> +{					\
> +	.maxfreq = _maxfreq,		\
> +	.timing = {			\
> +		.clk_lp2hs = _c_lp2hs,	\
> +		.clk_hs2lp = _c_hs2lp,	\
> +		.data_lp2hs = _d_lp2hs,	\
> +		.data_hs2lp = _d_hs2lp,	\
> +	}				\
> +}
> +
> +/* Table A-3 High-Speed Transition Times */
> +struct hstt hstt_table[] = {
> +	HSTT(  90,  32, 20,  26, 13),
> +	HSTT( 100,  35, 23,  28, 14),
> +	HSTT( 110,  32, 22,  26, 13),
> +	HSTT( 130,  31, 20,  27, 13),
> +	HSTT( 140,  33, 22,  26, 14),
> +	HSTT( 150,  33, 21,  26, 14),
> +	HSTT( 170,  32, 20,  27, 13),
> +	HSTT( 180,  36, 23,  30, 15),
> +	HSTT( 200,  40, 22,  33, 15),
> +	HSTT( 220,  40, 22,  33, 15),
> +	HSTT( 240,  44, 24,  36, 16),
> +	HSTT( 250,  48, 24,  38, 17),
> +	HSTT( 270,  48, 24,  38, 17),
> +	HSTT( 300,  50, 27,  41, 18),
> +	HSTT( 330,  56, 28,  45, 18),
> +	HSTT( 360,  59, 28,  48, 19),
> +	HSTT( 400,  61, 30,  50, 20),
> +	HSTT( 450,  67, 31,  55, 21),
> +	HSTT( 500,  73, 31,  59, 22),
> +	HSTT( 550,  79, 36,  63, 24),
> +	HSTT( 600,  83, 37,  68, 25),
> +	HSTT( 650,  90, 38,  73, 27),
> +	HSTT( 700,  95, 40,  77, 28),
> +	HSTT( 750, 102, 40,  84, 28),
> +	HSTT( 800, 106, 42,  87, 30),
> +	HSTT( 850, 113, 44,  93, 31),
> +	HSTT( 900, 118, 47,  98, 32),
> +	HSTT( 950, 124, 47, 102, 34),
> +	HSTT(1000, 130, 49, 107, 35),
> +	HSTT(1050, 135, 51, 111, 37),
> +	HSTT(1100, 139, 51, 114, 38),
> +	HSTT(1150, 146, 54, 120, 40),
> +	HSTT(1200, 153, 57, 125, 41),
> +	HSTT(1250, 158, 58, 130, 42),
> +	HSTT(1300, 163, 58, 135, 44),
> +	HSTT(1350, 168, 60, 140, 45),
> +	HSTT(1400, 172, 64, 144, 47),
> +	HSTT(1450, 176, 65, 148, 48),
> +	HSTT(1500, 181, 66, 153, 50)
> +};
> +
> +static int
> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> +			   struct dw_mipi_dsi_dphy_timing *timing)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
> +		if (lane_mbps < hstt_table[i].maxfreq)
> +			break;
> +
> +	if (i == ARRAY_SIZE(hstt_table))
> +		i--;
> +
> +	*timing = hstt_table[i].timing;
> +
> +	return 0;
> +}
> +
>  static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
>  	.init = dw_mipi_dsi_phy_init,
>  	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> +	.get_timing = dw_mipi_dsi_phy_get_timing,
>  };
>  
>  static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,
> diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> index 514efefb0016..4b165635b2d4 100644
> --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> @@ -309,11 +309,24 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  	return 0;
>  }
>  
> +static int
> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> +			   struct dw_mipi_dsi_dphy_timing *timing)
> +{
> +	timing->clk_hs2lp = 0x40;
> +	timing->clk_lp2hs = 0x40;
> +	timing->data_hs2lp = 0x40;
> +	timing->data_lp2hs = 0x40;
> +
> +	return 0;
> +}
> +
>  static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
>  	.init = dw_mipi_dsi_phy_init,
>  	.power_on = dw_mipi_dsi_phy_power_on,
>  	.power_off = dw_mipi_dsi_phy_power_off,
>  	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> +	.get_timing = dw_mipi_dsi_phy_get_timing,
>  };
>  
>  static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
> diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
> index 94cc64a342e1..b0e390b3288e 100644
> --- a/include/drm/bridge/dw_mipi_dsi.h
> +++ b/include/drm/bridge/dw_mipi_dsi.h
> @@ -19,6 +19,13 @@ struct dw_mipi_dsi;
>  struct mipi_dsi_device;
>  struct platform_device;
>  
> +struct dw_mipi_dsi_dphy_timing {
> +	u16 data_hs2lp;
> +	u16 data_lp2hs;
> +	u16 clk_hs2lp;
> +	u16 clk_lp2hs;
> +};
> +
>  struct dw_mipi_dsi_phy_ops {
>  	int (*init)(void *priv_data);
>  	void (*power_on)(void *priv_data);
> @@ -27,6 +34,8 @@ struct dw_mipi_dsi_phy_ops {
>  			     const struct drm_display_mode *mode,
>  			     unsigned long mode_flags, u32 lanes, u32 format,
>  			     unsigned int *lane_mbps);
> +	int (*get_timing)(void *priv_data, unsigned int lane_mbps,
> +			  struct dw_mipi_dsi_dphy_timing *timing);
>  };
>  
>  struct dw_mipi_dsi_host_ops {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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Re: [PATCH v5 4/6] drm/rockchip: add ability to handle external dphys in mipi-dsi

[Neil Armstrong]

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> While the common case is that the dsi controller uses an internal dphy,
> accessed through the phy registers inside the dsi controller, there is
> also the possibility to use a separate dphy from a different vendor.
> 
> One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> so add the support for handling such a constellation, including the pll
> also getting generated inside that external phy.
> 
> changes in v5:
> - rebased on top of 5.5-rc1
> - merged with dsi timing change to prevent ordering conflicts
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 68 +++++++++++++++++--
>  1 file changed, 64 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index 9406effe8077..f16bd1e9b633 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -12,6 +12,7 @@
>  #include <linux/mfd/syscon.h>
>  #include <linux/module.h>
>  #include <linux/of_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/regmap.h>
>  
> @@ -223,6 +224,10 @@ struct dw_mipi_dsi_rockchip {
>  	bool is_slave;
>  	struct dw_mipi_dsi_rockchip *slave;
>  
> +	/* optional external dphy */
> +	struct phy *phy;
> +	union phy_configure_opts phy_opts;
> +
>  	unsigned int lane_mbps; /* per lane */
>  	u16 input_div;
>  	u16 feedback_div;
> @@ -359,6 +364,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
>  	struct dw_mipi_dsi_rockchip *dsi = priv_data;
>  	int ret, i, vco;
>  
> +	if (dsi->phy)
> +		return 0;
> +
>  	/*
>  	 * Get vco from frequency(lane_mbps)
>  	 * vco	frequency table
> @@ -467,6 +475,28 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
>  	return ret;
>  }
>  
> +static void dw_mipi_dsi_phy_power_on(void *priv_data)
> +{
> +	struct dw_mipi_dsi_rockchip *dsi = priv_data;
> +	int ret;
> +
> +	ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
> +	if (ret) {
> +		DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
> +		return;
> +	}
> +
> +	phy_configure(dsi->phy, &dsi->phy_opts);
> +	phy_power_on(dsi->phy);
> +}
> +
> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> +{
> +	struct dw_mipi_dsi_rockchip *dsi = priv_data;
> +
> +	phy_power_off(dsi->phy);
> +}
> +
>  static int
>  dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  			  unsigned long mode_flags, u32 lanes, u32 format,
> @@ -504,6 +534,17 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  				      "DPHY clock frequency is out of range\n");
>  	}
>  
> +	/* for external phy only a the mipi_dphy_config is necessary */
> +	if (dsi->phy) {
> +		phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
> +						 bpp, lanes,
> +						 &dsi->phy_opts.mipi_dphy);
> +		dsi->lane_mbps = target_mbps;
> +		*lane_mbps = dsi->lane_mbps;
> +
> +		return 0;
> +	}
> +
>  	fin = clk_get_rate(dsi->pllref_clk);
>  	fout = target_mbps * USEC_PER_SEC;
>  
> @@ -638,6 +679,8 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
>  
>  static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
>  	.init = dw_mipi_dsi_phy_init,
> +	.power_on = dw_mipi_dsi_phy_power_on,
> +	.power_off = dw_mipi_dsi_phy_power_off,
>  	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
>  	.get_timing = dw_mipi_dsi_phy_get_timing,
>  };
> @@ -998,12 +1041,29 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
>  		return -EINVAL;
>  	}
>  
> +	/* try to get a possible external dphy */
> +	dsi->phy = devm_phy_optional_get(dev, "dphy");
> +	if (IS_ERR(dsi->phy)) {
> +		ret = PTR_ERR(dsi->phy);
> +		DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
> +		return ret;
> +	}
> +
>  	dsi->pllref_clk = devm_clk_get(dev, "ref");
>  	if (IS_ERR(dsi->pllref_clk)) {
> -		ret = PTR_ERR(dsi->pllref_clk);
> -		DRM_DEV_ERROR(dev,
> -			      "Unable to get pll reference clock: %d\n", ret);
> -		return ret;
> +		if (dsi->phy) {
> +			/*
> +			 * if external phy is present, pll will be
> +			 * generated there.
> +			 */
> +			dsi->pllref_clk = NULL;
> +		} else {
> +			ret = PTR_ERR(dsi->pllref_clk);
> +			DRM_DEV_ERROR(dev,
> +				      "Unable to get pll reference clock: %d\n",
> +				      ret);
> +			return ret;
> +		}
>  	}
>  
>  	if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH v5 4/6] drm/rockchip: add ability to handle external dphys in mipi-dsi

[Neil Armstrong]

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> While the common case is that the dsi controller uses an internal dphy,
> accessed through the phy registers inside the dsi controller, there is
> also the possibility to use a separate dphy from a different vendor.
> 
> One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> so add the support for handling such a constellation, including the pll
> also getting generated inside that external phy.
> 
> changes in v5:
> - rebased on top of 5.5-rc1
> - merged with dsi timing change to prevent ordering conflicts
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 68 +++++++++++++++++--
>  1 file changed, 64 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index 9406effe8077..f16bd1e9b633 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -12,6 +12,7 @@
>  #include <linux/mfd/syscon.h>
>  #include <linux/module.h>
>  #include <linux/of_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/regmap.h>
>  
> @@ -223,6 +224,10 @@ struct dw_mipi_dsi_rockchip {
>  	bool is_slave;
>  	struct dw_mipi_dsi_rockchip *slave;
>  
> +	/* optional external dphy */
> +	struct phy *phy;
> +	union phy_configure_opts phy_opts;
> +
>  	unsigned int lane_mbps; /* per lane */
>  	u16 input_div;
>  	u16 feedback_div;
> @@ -359,6 +364,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
>  	struct dw_mipi_dsi_rockchip *dsi = priv_data;
>  	int ret, i, vco;
>  
> +	if (dsi->phy)
> +		return 0;
> +
>  	/*
>  	 * Get vco from frequency(lane_mbps)
>  	 * vco	frequency table
> @@ -467,6 +475,28 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
>  	return ret;
>  }
>  
> +static void dw_mipi_dsi_phy_power_on(void *priv_data)
> +{
> +	struct dw_mipi_dsi_rockchip *dsi = priv_data;
> +	int ret;
> +
> +	ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
> +	if (ret) {
> +		DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
> +		return;
> +	}
> +
> +	phy_configure(dsi->phy, &dsi->phy_opts);
> +	phy_power_on(dsi->phy);
> +}
> +
> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> +{
> +	struct dw_mipi_dsi_rockchip *dsi = priv_data;
> +
> +	phy_power_off(dsi->phy);
> +}
> +
>  static int
>  dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  			  unsigned long mode_flags, u32 lanes, u32 format,
> @@ -504,6 +534,17 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>  				      "DPHY clock frequency is out of range\n");
>  	}
>  
> +	/* for external phy only a the mipi_dphy_config is necessary */
> +	if (dsi->phy) {
> +		phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
> +						 bpp, lanes,
> +						 &dsi->phy_opts.mipi_dphy);
> +		dsi->lane_mbps = target_mbps;
> +		*lane_mbps = dsi->lane_mbps;
> +
> +		return 0;
> +	}
> +
>  	fin = clk_get_rate(dsi->pllref_clk);
>  	fout = target_mbps * USEC_PER_SEC;
>  
> @@ -638,6 +679,8 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
>  
>  static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
>  	.init = dw_mipi_dsi_phy_init,
> +	.power_on = dw_mipi_dsi_phy_power_on,
> +	.power_off = dw_mipi_dsi_phy_power_off,
>  	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
>  	.get_timing = dw_mipi_dsi_phy_get_timing,
>  };
> @@ -998,12 +1041,29 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
>  		return -EINVAL;
>  	}
>  
> +	/* try to get a possible external dphy */
> +	dsi->phy = devm_phy_optional_get(dev, "dphy");
> +	if (IS_ERR(dsi->phy)) {
> +		ret = PTR_ERR(dsi->phy);
> +		DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
> +		return ret;
> +	}
> +
>  	dsi->pllref_clk = devm_clk_get(dev, "ref");
>  	if (IS_ERR(dsi->pllref_clk)) {
> -		ret = PTR_ERR(dsi->pllref_clk);
> -		DRM_DEV_ERROR(dev,
> -			      "Unable to get pll reference clock: %d\n", ret);
> -		return ret;
> +		if (dsi->phy) {
> +			/*
> +			 * if external phy is present, pll will be
> +			 * generated there.
> +			 */
> +			dsi->pllref_clk = NULL;
> +		} else {
> +			ret = PTR_ERR(dsi->pllref_clk);
> +			DRM_DEV_ERROR(dev,
> +				      "Unable to get pll reference clock: %d\n",
> +				      ret);
> +			return ret;
> +		}
>  	}
>  
>  	if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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Re: [PATCH v5 6/6] drm/rockchip: dsi: add px30 support

[Neil Armstrong]

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> Add the compatible and GRF definitions for the PX30 soc.
> 
> changes in v5:
> - rebased on top of 5.5-rc1
> - merged with dsi timing change to prevent ordering conflicts
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index f16bd1e9b633..f04b5064974d 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -140,6 +140,12 @@
>  #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
>  #define DW_MIPI_NEEDS_GRF_CLK		BIT(1)
>  
> +#define PX30_GRF_PD_VO_CON1		0x0438
> +#define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)
> +#define PX30_DSI_FORCERXMODE		BIT(6)
> +#define PX30_DSI_TURNDISABLE		BIT(5)
> +#define PX30_DSI_LCDC_SEL		BIT(0)
> +
>  #define RK3288_GRF_SOC_CON6		0x025c
>  #define RK3288_DSI0_LCDC_SEL		BIT(6)
>  #define RK3288_DSI1_LCDC_SEL		BIT(9)
> @@ -1127,6 +1133,24 @@ static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
> +	{
> +		.reg = 0xff450000,
> +		.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
> +		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
> +		.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
> +					    PX30_DSI_LCDC_SEL),
> +
> +		.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
> +		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
> +					     PX30_DSI_FORCERXMODE |
> +					     PX30_DSI_FORCETXSTOPMODE),
> +
> +		.max_data_lanes = 4,
> +	},
> +	{ /* sentinel */ }
> +};
> +
>  static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
>  	{
>  		.reg = 0xff960000,
> @@ -1195,6 +1219,9 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
>  
>  static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
>  	{
> +	 .compatible = "rockchip,px30-mipi-dsi",
> +	 .data = &px30_chip_data,
> +	}, {
>  	 .compatible = "rockchip,rk3288-mipi-dsi",
>  	 .data = &rk3288_chip_data,
>  	}, {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH v5 6/6] drm/rockchip: dsi: add px30 support

[Neil Armstrong]

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> Add the compatible and GRF definitions for the PX30 soc.
> 
> changes in v5:
> - rebased on top of 5.5-rc1
> - merged with dsi timing change to prevent ordering conflicts
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index f16bd1e9b633..f04b5064974d 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -140,6 +140,12 @@
>  #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
>  #define DW_MIPI_NEEDS_GRF_CLK		BIT(1)
>  
> +#define PX30_GRF_PD_VO_CON1		0x0438
> +#define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)
> +#define PX30_DSI_FORCERXMODE		BIT(6)
> +#define PX30_DSI_TURNDISABLE		BIT(5)
> +#define PX30_DSI_LCDC_SEL		BIT(0)
> +
>  #define RK3288_GRF_SOC_CON6		0x025c
>  #define RK3288_DSI0_LCDC_SEL		BIT(6)
>  #define RK3288_DSI1_LCDC_SEL		BIT(9)
> @@ -1127,6 +1133,24 @@ static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
> +	{
> +		.reg = 0xff450000,
> +		.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
> +		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
> +		.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
> +					    PX30_DSI_LCDC_SEL),
> +
> +		.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
> +		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
> +					     PX30_DSI_FORCERXMODE |
> +					     PX30_DSI_FORCETXSTOPMODE),
> +
> +		.max_data_lanes = 4,
> +	},
> +	{ /* sentinel */ }
> +};
> +
>  static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
>  	{
>  		.reg = 0xff960000,
> @@ -1195,6 +1219,9 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
>  
>  static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
>  	{
> +	 .compatible = "rockchip,px30-mipi-dsi",
> +	 .data = &px30_chip_data,
> +	}, {
>  	 .compatible = "rockchip,rk3288-mipi-dsi",
>  	 .data = &rk3288_chip_data,
>  	}, {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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Re: [PATCH v5 0/6] drm/rockchip: px30 dsi support

[Neil Armstrong]

Hi,

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> This series addes support for the px30 Rockchip soc to the dsi driver.
> This includes support for external dsi-phys like used on the px30.
> 
> What happened between v1 and v5? The then separate dsi hs2lp timing
> patch happened ;-) . As both it and this series touch similar areas
> in the dsi driver ordering becomes an issue and so combining them to
> make ordering explicit is helpful. v2-v4 where then iterations of the
> timing patch.
> 
> So this v5 is mainly rebased on 5.5-rc1 and rechecked against drm-misc.
> 
> Heiko Stuebner (6):
>   drm/bridge/synopsys: dsi: driver-specific configuration of phy timings
>   drm/bridge/synopsys: dsi: move phy_ops callbacks around panel
>     enablement
>   dt-bindings: display: rockchip-dsi: document external phys
>   drm/rockchip: add ability to handle external dphys in mipi-dsi
>   dt-bindings: display: rockchip-dsi: add px30 compatible
>   drm/rockchip: dsi: add px30 support
> 
>  .../display/rockchip/dw_mipi_dsi_rockchip.txt |  13 +-
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |  40 ++--
>  drivers/gpu/drm/rockchip/Kconfig              |   1 +
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 173 +++++++++++++++++-
>  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         |  13 ++
>  include/drm/bridge/dw_mipi_dsi.h              |   9 +
>  6 files changed, 227 insertions(+), 22 deletions(-)
> 

You can go ahead and merge the whole serie with bridge stuff into drm-misc-next if you want,
or I can do it.

Neil

Re: [PATCH v5 0/6] drm/rockchip: px30 dsi support

[Neil Armstrong]

Hi,

On 09/12/2019 15:31, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> This series addes support for the px30 Rockchip soc to the dsi driver.
> This includes support for external dsi-phys like used on the px30.
> 
> What happened between v1 and v5? The then separate dsi hs2lp timing
> patch happened ;-) . As both it and this series touch similar areas
> in the dsi driver ordering becomes an issue and so combining them to
> make ordering explicit is helpful. v2-v4 where then iterations of the
> timing patch.
> 
> So this v5 is mainly rebased on 5.5-rc1 and rechecked against drm-misc.
> 
> Heiko Stuebner (6):
>   drm/bridge/synopsys: dsi: driver-specific configuration of phy timings
>   drm/bridge/synopsys: dsi: move phy_ops callbacks around panel
>     enablement
>   dt-bindings: display: rockchip-dsi: document external phys
>   drm/rockchip: add ability to handle external dphys in mipi-dsi
>   dt-bindings: display: rockchip-dsi: add px30 compatible
>   drm/rockchip: dsi: add px30 support
> 
>  .../display/rockchip/dw_mipi_dsi_rockchip.txt |  13 +-
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |  40 ++--
>  drivers/gpu/drm/rockchip/Kconfig              |   1 +
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 173 +++++++++++++++++-
>  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         |  13 ++
>  include/drm/bridge/dw_mipi_dsi.h              |   9 +
>  6 files changed, 227 insertions(+), 22 deletions(-)
> 

You can go ahead and merge the whole serie with bridge stuff into drm-misc-next if you want,
or I can do it.

Neil
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Re: [PATCH v5 0/6] drm/rockchip: px30 dsi support

[Heiko Stuebner]

Hi Neil,

Am Montag, 16. Dezember 2019, 11:40:00 CET schrieb Neil Armstrong:
> On 09/12/2019 15:31, Heiko Stuebner wrote:
> > From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> > 
> > This series addes support for the px30 Rockchip soc to the dsi driver.
> > This includes support for external dsi-phys like used on the px30.
> > 
> > What happened between v1 and v5? The then separate dsi hs2lp timing
> > patch happened ;-) . As both it and this series touch similar areas
> > in the dsi driver ordering becomes an issue and so combining them to
> > make ordering explicit is helpful. v2-v4 where then iterations of the
> > timing patch.
> > 
> > So this v5 is mainly rebased on 5.5-rc1 and rechecked against drm-misc.
> > 
> > Heiko Stuebner (6):
> >   drm/bridge/synopsys: dsi: driver-specific configuration of phy timings
> >   drm/bridge/synopsys: dsi: move phy_ops callbacks around panel
> >     enablement
> >   dt-bindings: display: rockchip-dsi: document external phys
> >   drm/rockchip: add ability to handle external dphys in mipi-dsi
> >   dt-bindings: display: rockchip-dsi: add px30 compatible
> >   drm/rockchip: dsi: add px30 support
> > 
> >  .../display/rockchip/dw_mipi_dsi_rockchip.txt |  13 +-
> >  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |  40 ++--
> >  drivers/gpu/drm/rockchip/Kconfig              |   1 +
> >  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 173 +++++++++++++++++-
> >  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         |  13 ++
> >  include/drm/bridge/dw_mipi_dsi.h              |   9 +
> >  6 files changed, 227 insertions(+), 22 deletions(-)
> > 
> 
> You can go ahead and merge the whole serie with bridge stuff into drm-misc-next if you want,
> or I can do it.

I've applied the patches to drm-misc-next now (after double checking again).

Thanks a lot for doing the reviews
Heiko

Re: [PATCH v5 0/6] drm/rockchip: px30 dsi support

[Heiko Stuebner]

Hi Neil,

Am Montag, 16. Dezember 2019, 11:40:00 CET schrieb Neil Armstrong:
> On 09/12/2019 15:31, Heiko Stuebner wrote:
> > From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> > 
> > This series addes support for the px30 Rockchip soc to the dsi driver.
> > This includes support for external dsi-phys like used on the px30.
> > 
> > What happened between v1 and v5? The then separate dsi hs2lp timing
> > patch happened ;-) . As both it and this series touch similar areas
> > in the dsi driver ordering becomes an issue and so combining them to
> > make ordering explicit is helpful. v2-v4 where then iterations of the
> > timing patch.
> > 
> > So this v5 is mainly rebased on 5.5-rc1 and rechecked against drm-misc.
> > 
> > Heiko Stuebner (6):
> >   drm/bridge/synopsys: dsi: driver-specific configuration of phy timings
> >   drm/bridge/synopsys: dsi: move phy_ops callbacks around panel
> >     enablement
> >   dt-bindings: display: rockchip-dsi: document external phys
> >   drm/rockchip: add ability to handle external dphys in mipi-dsi
> >   dt-bindings: display: rockchip-dsi: add px30 compatible
> >   drm/rockchip: dsi: add px30 support
> > 
> >  .../display/rockchip/dw_mipi_dsi_rockchip.txt |  13 +-
> >  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |  40 ++--
> >  drivers/gpu/drm/rockchip/Kconfig              |   1 +
> >  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 173 +++++++++++++++++-
> >  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         |  13 ++
> >  include/drm/bridge/dw_mipi_dsi.h              |   9 +
> >  6 files changed, 227 insertions(+), 22 deletions(-)
> > 
> 
> You can go ahead and merge the whole serie with bridge stuff into drm-misc-next if you want,
> or I can do it.

I've applied the patches to drm-misc-next now (after double checking again).

Thanks a lot for doing the reviews
Heiko


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