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From: Abhinav Kumar <quic_abhinavk@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
	Stephen Boyd <swboyd@chromium.org>,
	David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
	Bjorn Andersson <andersson@kernel.org>,
	<linux-arm-msm@vger.kernel.org>,
	<dri-devel@lists.freedesktop.org>,
	<freedreno@lists.freedesktop.org>
Subject: Re: [PATCH 6/8] drm/msm/dpu: use dpu_perf_cfg in DPU core_perf code
Date: Mon, 3 Jul 2023 17:46:27 -0700	[thread overview]
Message-ID: <30695ef4-1124-b526-a02f-cf351a08ddd9@quicinc.com> (raw)
In-Reply-To: <fc2e34f1-749f-22df-5af6-40da91f26c45@linaro.org>



On 6/20/2023 4:31 AM, Konrad Dybcio wrote:
> On 20.06.2023 13:18, Dmitry Baryshkov wrote:
>> On 20/06/2023 13:55, Konrad Dybcio wrote:
>>> On 20.06.2023 02:08, Dmitry Baryshkov wrote:
>>>> Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using
>>>> full-featured catalog data.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>
>>> Check below.
>>>
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 52 ++++++++-----------
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |  8 +--
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       |  2 +-
>>>>    3 files changed, 27 insertions(+), 35 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>>>> index 773e641eab28..78a7e3ea27a4 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>>>> @@ -19,11 +19,11 @@
>>>>
>>>>    /**
>>>>     * _dpu_core_perf_calc_bw() - to calculate BW per crtc
>>>> - * @kms:  pointer to the dpu_kms
>>>> + * @perf_cfg: performance configuration
>>>>     * @crtc: pointer to a crtc
>>>>     * Return: returns aggregated BW for all planes in crtc.
>>>>     */
>>>> -static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
>>>> +static u64 _dpu_core_perf_calc_bw(const struct dpu_perf_cfg *perf_cfg,
>>>>               struct drm_crtc *crtc)
>>>>    {
>>>>       struct drm_plane *plane;
>>>> @@ -39,7 +39,7 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
>>>>               crtc_plane_bw += pstate->plane_fetch_bw;
>>>>       }
>>>>
>>>> -    bw_factor = kms->catalog->perf->bw_inefficiency_factor;
>>>> +    bw_factor = perf_cfg->bw_inefficiency_factor;
>>> It's set to 120 for all SoCs.. and it sounds very much like some kind of a
>>> hack.
>>>
>>> The 105 on the other inefficiency factor is easy to spot:
>>>
>>> (1024/1000)^2 = 1.048576 =~= 1.05 = 105%
>>>
>>> It comes from a MiB-MB-MHz conversion that Qcom splattered all over
>>> downstream as due to ancient tragical design decisions in msmbus
>>> (which leak to the downstream interconnect a bit):
>>
>> This doesn't describe, why msm8226 and msm8974 had qcom,mdss-clk-factor
>> of 5/4. And 8084 got 1.05 as usual. I can only suppose that MDSS 1.0
>> (8974 v1) and 1.1 (8226) had some internal inefficiency / issues.
>>
>> Also, this 1.05 is a clock inefficiency, so it should not be related
>> to msm bus client code.
> Right. Maybe Abhinav could shed some light on this.
> 
> Konrad
>>

I will need to check with someone else about this as msm8974 and msm8226 
are quite old for me to remember.

That being said, I really dont think the explanation behind the number 
is going to be something which is going to be explained in detail here 
even if I did ask.

The name of the variable "clk_inefficiency_factor" says pretty much what 
has to be said for the purposes of this patch. I dont know if we will be 
able to go further into how that number came.

Coming to this patch itself, its not a major gain or major loss in my 
perspective.

Sure, we dont need to pass the full catalog today so we can just pass 
the perf_cfg. I cannot guarantee we wont need the full catalog later.


>>>
>>> The logic needs to get some input that corresponds to a clock rate
>>> of a bus clock (19.2, 200, 300 Mhz etc.) but the APIs expect a Kbps
>>> value. So at one point they invented a MHZ_TO_MBPS macro which did this
>>> conversion the other way around and probably had to account for it.
>>>
>>> I think they tried to make it make more sense, but it ended up being
>>> even more spaghetti :/
>>>
>>> Not yet sure how it's done on RPMh icc, but with SMD RPM, passing e.g.
>>>
>>> opp-peak-kBps = <(200 * 8 * 1000)>; # 200 MHz * 8-wide * KHz-to-MHz
>>>
>>> results in a "correct" end rate.
>>>
>>> Konrad
>>>>       if (bw_factor) {
>>>>               crtc_plane_bw *= bw_factor;
>>>>               do_div(crtc_plane_bw, 100);
>>
>>
>> --
>> With best wishes
>> Dmitry

WARNING: multiple messages have this Message-ID (diff)
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	Bjorn Andersson <andersson@kernel.org>,
	dri-devel@lists.freedesktop.org,
	Stephen Boyd <swboyd@chromium.org>,
	Marijn Suijten <marijn.suijten@somainline.org>
Subject: Re: [PATCH 6/8] drm/msm/dpu: use dpu_perf_cfg in DPU core_perf code
Date: Mon, 3 Jul 2023 17:46:27 -0700	[thread overview]
Message-ID: <30695ef4-1124-b526-a02f-cf351a08ddd9@quicinc.com> (raw)
In-Reply-To: <fc2e34f1-749f-22df-5af6-40da91f26c45@linaro.org>



On 6/20/2023 4:31 AM, Konrad Dybcio wrote:
> On 20.06.2023 13:18, Dmitry Baryshkov wrote:
>> On 20/06/2023 13:55, Konrad Dybcio wrote:
>>> On 20.06.2023 02:08, Dmitry Baryshkov wrote:
>>>> Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using
>>>> full-featured catalog data.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>
>>> Check below.
>>>
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 52 ++++++++-----------
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |  8 +--
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       |  2 +-
>>>>    3 files changed, 27 insertions(+), 35 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>>>> index 773e641eab28..78a7e3ea27a4 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>>>> @@ -19,11 +19,11 @@
>>>>
>>>>    /**
>>>>     * _dpu_core_perf_calc_bw() - to calculate BW per crtc
>>>> - * @kms:  pointer to the dpu_kms
>>>> + * @perf_cfg: performance configuration
>>>>     * @crtc: pointer to a crtc
>>>>     * Return: returns aggregated BW for all planes in crtc.
>>>>     */
>>>> -static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
>>>> +static u64 _dpu_core_perf_calc_bw(const struct dpu_perf_cfg *perf_cfg,
>>>>               struct drm_crtc *crtc)
>>>>    {
>>>>       struct drm_plane *plane;
>>>> @@ -39,7 +39,7 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
>>>>               crtc_plane_bw += pstate->plane_fetch_bw;
>>>>       }
>>>>
>>>> -    bw_factor = kms->catalog->perf->bw_inefficiency_factor;
>>>> +    bw_factor = perf_cfg->bw_inefficiency_factor;
>>> It's set to 120 for all SoCs.. and it sounds very much like some kind of a
>>> hack.
>>>
>>> The 105 on the other inefficiency factor is easy to spot:
>>>
>>> (1024/1000)^2 = 1.048576 =~= 1.05 = 105%
>>>
>>> It comes from a MiB-MB-MHz conversion that Qcom splattered all over
>>> downstream as due to ancient tragical design decisions in msmbus
>>> (which leak to the downstream interconnect a bit):
>>
>> This doesn't describe, why msm8226 and msm8974 had qcom,mdss-clk-factor
>> of 5/4. And 8084 got 1.05 as usual. I can only suppose that MDSS 1.0
>> (8974 v1) and 1.1 (8226) had some internal inefficiency / issues.
>>
>> Also, this 1.05 is a clock inefficiency, so it should not be related
>> to msm bus client code.
> Right. Maybe Abhinav could shed some light on this.
> 
> Konrad
>>

I will need to check with someone else about this as msm8974 and msm8226 
are quite old for me to remember.

That being said, I really dont think the explanation behind the number 
is going to be something which is going to be explained in detail here 
even if I did ask.

The name of the variable "clk_inefficiency_factor" says pretty much what 
has to be said for the purposes of this patch. I dont know if we will be 
able to go further into how that number came.

Coming to this patch itself, its not a major gain or major loss in my 
perspective.

Sure, we dont need to pass the full catalog today so we can just pass 
the perf_cfg. I cannot guarantee we wont need the full catalog later.


>>>
>>> The logic needs to get some input that corresponds to a clock rate
>>> of a bus clock (19.2, 200, 300 Mhz etc.) but the APIs expect a Kbps
>>> value. So at one point they invented a MHZ_TO_MBPS macro which did this
>>> conversion the other way around and probably had to account for it.
>>>
>>> I think they tried to make it make more sense, but it ended up being
>>> even more spaghetti :/
>>>
>>> Not yet sure how it's done on RPMh icc, but with SMD RPM, passing e.g.
>>>
>>> opp-peak-kBps = <(200 * 8 * 1000)>; # 200 MHz * 8-wide * KHz-to-MHz
>>>
>>> results in a "correct" end rate.
>>>
>>> Konrad
>>>>       if (bw_factor) {
>>>>               crtc_plane_bw *= bw_factor;
>>>>               do_div(crtc_plane_bw, 100);
>>
>>
>> --
>> With best wishes
>> Dmitry

  reply	other threads:[~2023-07-04  0:46 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-20  0:08 [PATCH 0/8] drm/msm/dpu: cleanup dpu_core_perf module Dmitry Baryshkov
2023-06-20  0:08 ` Dmitry Baryshkov
2023-06-20  0:08 ` [PATCH 1/8] drm/msm/dpu: drop enum dpu_core_perf_data_bus_id Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-06-20 10:35   ` Konrad Dybcio
2023-06-20 10:35     ` Konrad Dybcio
2023-07-03 21:30   ` Abhinav Kumar
2023-07-03 21:30     ` Abhinav Kumar
2023-06-20  0:08 ` [PATCH 2/8] drm/msm/dpu: drop performance tuning modes Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-06-20 10:45   ` Konrad Dybcio
2023-06-20 10:45     ` Konrad Dybcio
2023-07-03 21:40   ` Abhinav Kumar
2023-07-03 21:40     ` Abhinav Kumar
2023-07-03 22:20     ` Dmitry Baryshkov
2023-07-03 22:20       ` Dmitry Baryshkov
2023-07-03 22:26       ` Abhinav Kumar
2023-07-03 22:26         ` Abhinav Kumar
2023-07-03 22:36         ` Dmitry Baryshkov
2023-07-03 22:36           ` Dmitry Baryshkov
2023-06-20  0:08 ` [PATCH 3/8] drm/msm/dpu: drop dpu_core_perf_params::max_per_pipe_ib Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-06-20 10:46   ` Konrad Dybcio
2023-06-20 10:46     ` Konrad Dybcio
2023-06-20 10:53     ` Dmitry Baryshkov
2023-06-20 10:53       ` Dmitry Baryshkov
2023-07-03 21:53   ` Abhinav Kumar
2023-07-03 21:53     ` Abhinav Kumar
2023-06-20  0:08 ` [PATCH 4/8] drm/msm/dpu: rework indentation in dpu_core_perf Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-06-20 10:47   ` Konrad Dybcio
2023-06-20 10:47     ` Konrad Dybcio
2023-07-03 22:01   ` Abhinav Kumar
2023-07-03 22:01     ` Abhinav Kumar
2023-06-20  0:08 ` [PATCH 5/8] drm/msm/dpu: drop the dpu_core_perf_crtc_update()'s stop_req param Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-07-03 22:37   ` Abhinav Kumar
2023-07-03 22:37     ` Abhinav Kumar
2023-07-03 22:53     ` Dmitry Baryshkov
2023-07-03 22:53       ` Dmitry Baryshkov
2023-07-03 22:55       ` Abhinav Kumar
2023-07-03 22:55         ` Abhinav Kumar
2023-07-03 23:01         ` Dmitry Baryshkov
2023-07-03 23:01           ` Dmitry Baryshkov
2023-07-03 23:16           ` Abhinav Kumar
2023-07-03 23:16             ` Abhinav Kumar
2023-07-04  0:28             ` Dmitry Baryshkov
2023-07-04  0:28               ` Dmitry Baryshkov
2023-07-04  0:31               ` Abhinav Kumar
2023-07-04  0:31                 ` Abhinav Kumar
2023-06-20  0:08 ` [PATCH 6/8] drm/msm/dpu: use dpu_perf_cfg in DPU core_perf code Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-06-20 10:55   ` Konrad Dybcio
2023-06-20 10:55     ` Konrad Dybcio
2023-06-20 11:18     ` Dmitry Baryshkov
2023-06-20 11:18       ` Dmitry Baryshkov
2023-06-20 11:31       ` Konrad Dybcio
2023-06-20 11:31         ` Konrad Dybcio
2023-07-04  0:46         ` Abhinav Kumar [this message]
2023-07-04  0:46           ` Abhinav Kumar
2023-06-20  0:08 ` [PATCH 7/8] drm/msm/dpu: drop dpu_core_perf_destroy() Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-06-20 10:56   ` Konrad Dybcio
2023-06-20 10:56     ` Konrad Dybcio
2023-07-03 22:57   ` Abhinav Kumar
2023-07-03 22:57     ` Abhinav Kumar
2023-07-03 22:59     ` Dmitry Baryshkov
2023-07-03 22:59       ` Dmitry Baryshkov
2023-07-04  0:19       ` Abhinav Kumar
2023-07-04  0:19         ` Abhinav Kumar
2023-07-04 14:31         ` Dmitry Baryshkov
2023-07-04 14:31           ` Dmitry Baryshkov
2023-06-20  0:08 ` [PATCH 8/8] drm/msm/dpu: remove unused fields from struct dpu_core_perf Dmitry Baryshkov
2023-06-20  0:08   ` Dmitry Baryshkov
2023-06-20 10:56   ` Konrad Dybcio
2023-06-20 10:56     ` Konrad Dybcio
2023-07-04  0:25   ` Abhinav Kumar
2023-07-04  0:25     ` Abhinav Kumar

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