* [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration
@ 2021-09-03 6:50 Alistair Francis
2021-09-03 6:50 ` [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Alistair Francis @ 2021-09-03 6:50 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Using a macro for the PLIC configuration doesn't make the code any
easier to read. Instead it makes it harder to figure out what is going
on, so let's remove it.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5624adda58..d562ec6722 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -550,7 +550,7 @@ static char *plic_hart_config_string(int hart_count)
int i;
for (i = 0; i < hart_count; i++) {
- vals[i] = VIRT_PLIC_HART_CONFIG;
+ vals[i] = "MS";
}
vals[i] = NULL;
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function
2021-09-03 6:50 [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
@ 2021-09-03 6:50 ` Alistair Francis
2021-09-03 11:21 ` Bin Meng
2021-09-03 6:50 ` [PATCH v1 3/3] hw/riscv/microchip_pfsoc: " Alistair Francis
2021-09-03 10:41 ` Bin Meng
2 siblings, 1 reply; 7+ messages in thread
From: Alistair Francis @ 2021-09-03 6:50 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 1 -
hw/riscv/sifive_u.c | 36 +++++++++++++++++++++++-------------
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 349fee1f89..e95fd15298 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -71,7 +71,6 @@ enum {
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
};
-#define VIRT_PLIC_HART_CONFIG "MS"
#define VIRT_PLIC_NUM_SOURCES 127
#define VIRT_PLIC_NUM_PRIORITIES 7
#define VIRT_PLIC_PRIORITY_BASE 0x04
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6cc1a62b0f..9c51b4d052 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -738,6 +738,28 @@ static void sifive_u_machine_init_register_types(void)
type_init(sifive_u_machine_init_register_types)
+/*
+ * Return the per-socket PLIC hart topology configuration string
+ * (caller must free with g_free())
+ */
+static char *riscv_plic_hart_config_string(int hart_count)
+{
+ g_autofree const char **vals = g_new(const char *, hart_count + 1);
+ int i;
+
+ for (i = 0; i < hart_count; i++) {
+ if (i == 0) {
+ vals[i] = "M";
+ } else {
+ vals[i] = "MS";
+ }
+ }
+ vals[i] = NULL;
+
+ /* g_strjoinv() obliges us to cast away const here */
+ return g_strjoinv(",", (char **)vals);
+}
+
static void sifive_u_soc_instance_init(Object *obj)
{
SiFiveUSoCState *s = RISCV_U_SOC(obj);
@@ -776,7 +798,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
char *plic_hart_config;
- size_t plic_hart_config_len;
int i;
NICInfo *nd = &nd_table[0];
@@ -817,18 +838,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
l2lim_mem);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
- ms->smp.cpus;
- plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < ms->smp.cpus; i++) {
- if (i != 0) {
- strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
- plic_hart_config_len);
- } else {
- strncat(plic_hart_config, "M", plic_hart_config_len);
- }
- plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
- }
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v1 3/3] hw/riscv/microchip_pfsoc: Use the PLIC config helper function
2021-09-03 6:50 [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-09-03 6:50 ` [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function Alistair Francis
@ 2021-09-03 6:50 ` Alistair Francis
2021-09-03 10:41 ` Bin Meng
2 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2021-09-03 6:50 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 1 -
hw/riscv/microchip_pfsoc.c | 36 +++++++++++++++++++-----------
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index d30916f45d..a0673f5f59 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -138,7 +138,6 @@ enum {
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
-#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index eb8e79e0a1..ec237761e7 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -128,6 +128,28 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
};
+/*
+ * Return the per-socket PLIC hart topology configuration string
+ * (caller must free with g_free())
+ */
+static char *riscv_plic_hart_config_string(int hart_count)
+{
+ g_autofree const char **vals = g_new(const char *, hart_count + 1);
+ int i;
+
+ for (i = 0; i < hart_count; i++) {
+ if (i == 0) {
+ vals[i] = "M";
+ } else {
+ vals[i] = "MS";
+ }
+ }
+ vals[i] = NULL;
+
+ /* g_strjoinv() obliges us to cast away const here */
+ return g_strjoinv(",", (char **)vals);
+}
+
static void microchip_pfsoc_soc_instance_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -187,7 +209,6 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
char *plic_hart_config;
- size_t plic_hart_config_len;
NICInfo *nd;
int i;
@@ -259,18 +280,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
l2lim_mem);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
- ms->smp.cpus;
- plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < ms->smp.cpus; i++) {
- if (i != 0) {
- strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
- plic_hart_config_len);
- } else {
- strncat(plic_hart_config, "M", plic_hart_config_len);
- }
- plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
- }
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* PLIC */
s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration
2021-09-03 6:50 [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
@ 2021-09-03 10:41 ` Bin Meng
2021-09-03 6:50 ` [PATCH v1 3/3] hw/riscv/microchip_pfsoc: " Alistair Francis
2021-09-03 10:41 ` Bin Meng
2 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-09-03 10:41 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, Sep 3, 2021 at 2:50 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Using a macro for the PLIC configuration doesn't make the code any
> easier to read. Instead it makes it harder to figure out what is going
> on, so let's remove it.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5624adda58..d562ec6722 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -550,7 +550,7 @@ static char *plic_hart_config_string(int hart_count)
> int i;
>
> for (i = 0; i < hart_count; i++) {
> - vals[i] = VIRT_PLIC_HART_CONFIG;
This macro in virt.h should also be removed
> + vals[i] = "MS";
> }
> vals[i] = NULL;
>
> --
Other than that,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration
@ 2021-09-03 10:41 ` Bin Meng
0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-09-03 10:41 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Fri, Sep 3, 2021 at 2:50 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Using a macro for the PLIC configuration doesn't make the code any
> easier to read. Instead it makes it harder to figure out what is going
> on, so let's remove it.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5624adda58..d562ec6722 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -550,7 +550,7 @@ static char *plic_hart_config_string(int hart_count)
> int i;
>
> for (i = 0; i < hart_count; i++) {
> - vals[i] = VIRT_PLIC_HART_CONFIG;
This macro in virt.h should also be removed
> + vals[i] = "MS";
> }
> vals[i] = NULL;
>
> --
Other than that,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function
2021-09-03 6:50 ` [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function Alistair Francis
@ 2021-09-03 11:21 ` Bin Meng
0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-09-03 11:21 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, Sep 3, 2021 at 2:50 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/virt.h | 1 -
> hw/riscv/sifive_u.c | 36 +++++++++++++++++++++++-------------
> 2 files changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 349fee1f89..e95fd15298 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -71,7 +71,6 @@ enum {
> VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
> };
>
> -#define VIRT_PLIC_HART_CONFIG "MS"
This does not belong to this patch.
> #define VIRT_PLIC_NUM_SOURCES 127
> #define VIRT_PLIC_NUM_PRIORITIES 7
> #define VIRT_PLIC_PRIORITY_BASE 0x04
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 6cc1a62b0f..9c51b4d052 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -738,6 +738,28 @@ static void sifive_u_machine_init_register_types(void)
>
> type_init(sifive_u_machine_init_register_types)
>
> +/*
> + * Return the per-socket PLIC hart topology configuration string
> + * (caller must free with g_free())
> + */
> +static char *riscv_plic_hart_config_string(int hart_count)
I think we can create a common helper for all RISC-V machines to use.
The common helper generates the PLIC config string based on misa
feature bit RVS. If RVS is set then the corresponding hart string is
"MS", otherwise "M".
> +{
> + g_autofree const char **vals = g_new(const char *, hart_count + 1);
> + int i;
> +
> + for (i = 0; i < hart_count; i++) {
> + if (i == 0) {
> + vals[i] = "M";
> + } else {
> + vals[i] = "MS";
> + }
> + }
> + vals[i] = NULL;
> +
> + /* g_strjoinv() obliges us to cast away const here */
> + return g_strjoinv(",", (char **)vals);
> +}
> +
> static void sifive_u_soc_instance_init(Object *obj)
> {
> SiFiveUSoCState *s = RISCV_U_SOC(obj);
> @@ -776,7 +798,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> - size_t plic_hart_config_len;
> int i;
> NICInfo *nd = &nd_table[0];
>
> @@ -817,18 +838,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> l2lim_mem);
>
> /* create PLIC hart topology configuration string */
> - plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
> - ms->smp.cpus;
> - plic_hart_config = g_malloc0(plic_hart_config_len);
> - for (i = 0; i < ms->smp.cpus; i++) {
> - if (i != 0) {
> - strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
> - plic_hart_config_len);
> - } else {
> - strncat(plic_hart_config, "M", plic_hart_config_len);
> - }
> - plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
> - }
> + plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
>
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
Regards,
Bin
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function
@ 2021-09-03 11:21 ` Bin Meng
0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-09-03 11:21 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Fri, Sep 3, 2021 at 2:50 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/virt.h | 1 -
> hw/riscv/sifive_u.c | 36 +++++++++++++++++++++++-------------
> 2 files changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 349fee1f89..e95fd15298 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -71,7 +71,6 @@ enum {
> VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
> };
>
> -#define VIRT_PLIC_HART_CONFIG "MS"
This does not belong to this patch.
> #define VIRT_PLIC_NUM_SOURCES 127
> #define VIRT_PLIC_NUM_PRIORITIES 7
> #define VIRT_PLIC_PRIORITY_BASE 0x04
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 6cc1a62b0f..9c51b4d052 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -738,6 +738,28 @@ static void sifive_u_machine_init_register_types(void)
>
> type_init(sifive_u_machine_init_register_types)
>
> +/*
> + * Return the per-socket PLIC hart topology configuration string
> + * (caller must free with g_free())
> + */
> +static char *riscv_plic_hart_config_string(int hart_count)
I think we can create a common helper for all RISC-V machines to use.
The common helper generates the PLIC config string based on misa
feature bit RVS. If RVS is set then the corresponding hart string is
"MS", otherwise "M".
> +{
> + g_autofree const char **vals = g_new(const char *, hart_count + 1);
> + int i;
> +
> + for (i = 0; i < hart_count; i++) {
> + if (i == 0) {
> + vals[i] = "M";
> + } else {
> + vals[i] = "MS";
> + }
> + }
> + vals[i] = NULL;
> +
> + /* g_strjoinv() obliges us to cast away const here */
> + return g_strjoinv(",", (char **)vals);
> +}
> +
> static void sifive_u_soc_instance_init(Object *obj)
> {
> SiFiveUSoCState *s = RISCV_U_SOC(obj);
> @@ -776,7 +798,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> - size_t plic_hart_config_len;
> int i;
> NICInfo *nd = &nd_table[0];
>
> @@ -817,18 +838,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> l2lim_mem);
>
> /* create PLIC hart topology configuration string */
> - plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
> - ms->smp.cpus;
> - plic_hart_config = g_malloc0(plic_hart_config_len);
> - for (i = 0; i < ms->smp.cpus; i++) {
> - if (i != 0) {
> - strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
> - plic_hart_config_len);
> - } else {
> - strncat(plic_hart_config, "M", plic_hart_config_len);
> - }
> - plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
> - }
> + plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
>
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
Regards,
Bin
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-09-03 11:38 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-03 6:50 [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-09-03 6:50 ` [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function Alistair Francis
2021-09-03 11:21 ` Bin Meng
2021-09-03 11:21 ` Bin Meng
2021-09-03 6:50 ` [PATCH v1 3/3] hw/riscv/microchip_pfsoc: " Alistair Francis
2021-09-03 10:41 ` [PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration Bin Meng
2021-09-03 10:41 ` Bin Meng
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