From: "Heiko Stübner" <heiko@sntech.de> To: linux-kernel@vger.kernel.org, Atish Patra <atishp@rivosinc.com> Cc: Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: Re: [PATCH v4 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Wed, 16 Feb 2022 12:46:05 +0100 [thread overview] Message-ID: <3202369.D2aLoNIhS8@diego> (raw) In-Reply-To: <20220216002911.1219593-6-atishp@rivosinc.com> Am Mittwoch, 16. Februar 2022, 01:29:10 CET schrieb Atish Patra: > The isa string should begin with either rv64 or rv32. Otherwise, it is > an incorrect isa string. Currently, the string parsing continues even if > it doesnot begin with current XLEN. > > Fix this by checking if it found "rv64" or "rv32" in the beginning. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > arch/riscv/kernel/cpufeature.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 59c70c104256..cb9c9e0aab31 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) > for_each_of_cpu_node(node) { > unsigned long this_hwcap = 0; > DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); > + const char *temp; > > if (riscv_of_processor_hartid(node) < 0) > continue; > @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) > continue; > } > > + temp = isa; > #if IS_ENABLED(CONFIG_32BIT) > if (!strncmp(isa, "rv32", 4)) > isa += 4; > @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) > if (!strncmp(isa, "rv64", 4)) > isa += 4; > #endif > + /* The riscv,isa DT property must start with rv64 or rv32 */ > + if (temp == isa) > + continue; hmm, should (and can) this create some warning about the ignored malformed ISA string? Otherwise Tested-by: Heiko Stuebner <heiko@sntech.de> > bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); > for (; *isa; ++isa) { > const char *ext = isa++; >
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de> To: linux-kernel@vger.kernel.org, Atish Patra <atishp@rivosinc.com> Cc: Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: Re: [PATCH v4 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Wed, 16 Feb 2022 12:46:05 +0100 [thread overview] Message-ID: <3202369.D2aLoNIhS8@diego> (raw) In-Reply-To: <20220216002911.1219593-6-atishp@rivosinc.com> Am Mittwoch, 16. Februar 2022, 01:29:10 CET schrieb Atish Patra: > The isa string should begin with either rv64 or rv32. Otherwise, it is > an incorrect isa string. Currently, the string parsing continues even if > it doesnot begin with current XLEN. > > Fix this by checking if it found "rv64" or "rv32" in the beginning. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > arch/riscv/kernel/cpufeature.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 59c70c104256..cb9c9e0aab31 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) > for_each_of_cpu_node(node) { > unsigned long this_hwcap = 0; > DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); > + const char *temp; > > if (riscv_of_processor_hartid(node) < 0) > continue; > @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) > continue; > } > > + temp = isa; > #if IS_ENABLED(CONFIG_32BIT) > if (!strncmp(isa, "rv32", 4)) > isa += 4; > @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) > if (!strncmp(isa, "rv64", 4)) > isa += 4; > #endif > + /* The riscv,isa DT property must start with rv64 or rv32 */ > + if (temp == isa) > + continue; hmm, should (and can) this create some warning about the ignored malformed ISA string? Otherwise Tested-by: Heiko Stuebner <heiko@sntech.de> > bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); > for (; *isa; ++isa) { > const char *ext = isa++; > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-02-16 11:46 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-16 0:29 [PATCH v4 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra 2022-02-16 0:29 ` Atish Patra 2022-02-16 0:29 ` [PATCH v4 1/6] RISC-V: Correctly print supported extensions Atish Patra 2022-02-16 0:29 ` Atish Patra 2022-02-16 0:29 ` [PATCH v4 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra 2022-02-16 0:29 ` Atish Patra 2022-02-16 0:29 ` [PATCH v4 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra 2022-02-16 0:29 ` Atish Patra 2022-02-16 0:29 ` [PATCH v4 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra 2022-02-16 0:29 ` Atish Patra 2022-02-16 11:43 ` Heiko Stübner 2022-02-16 11:43 ` Heiko Stübner 2022-02-16 0:29 ` [PATCH v4 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra 2022-02-16 0:29 ` Atish Patra 2022-02-16 11:46 ` Heiko Stübner [this message] 2022-02-16 11:46 ` Heiko Stübner 2022-02-16 0:29 ` [PATCH v4 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra 2022-02-16 0:29 ` Atish Patra 2022-02-16 11:46 ` Heiko Stübner 2022-02-16 11:46 ` Heiko Stübner 2022-02-16 5:04 ` [PATCH 0/2] RISC-V: some improvements for Atish's framework (for v5) Tsukasa OI 2022-02-16 5:04 ` [PATCH 1/2] RISC-V: Better 'S' workaround Tsukasa OI 2022-02-16 5:04 ` [PATCH 2/2] RISC-V: Extract base ISA from device tree Tsukasa OI 2022-02-16 6:01 ` Atish Patra 2022-02-16 6:58 ` Tsukasa OI 2022-02-16 7:43 ` Atish Patra 2022-02-21 13:42 ` Tsukasa OI 2022-02-22 18:10 ` Atish Patra
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=3202369.D2aLoNIhS8@diego \ --to=heiko@sntech.de \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=atishp@atishpatra.org \ --cc=atishp@rivosinc.com \ --cc=damien.lemoal@wdc.com \ --cc=devicetree@vger.kernel.org \ --cc=jszhang@kernel.org \ --cc=krzysztof.kozlowski@canonical.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.