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* [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
@ 2022-05-30 12:34 ` Fabien Parent
  0 siblings, 0 replies; 13+ messages in thread
From: Fabien Parent @ 2022-05-30 12:34 UTC (permalink / raw)
  To: Sean Wang, Linus Walleij, Matthias Brugger
  Cc: Fabien Parent, linux-mediatek, linux-gpio, linux-arm-kernel,
	linux-kernel

On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly. Add a quirk for such SoCs, so that instead of using
the SET/CLR register use the main R/W register
to read/update/write the modes.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 46 ++++++++++++-------
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  3 ++
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index f25b3e09386b..156627d9c552 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -330,23 +330,37 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
 		return -EINVAL;
 	}
 
-	bit = BIT(pin & pctl->devdata->mode_mask);
-	if (enable)
-		reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullen_offset, pctl);
-	else
-		reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullen_offset, pctl);
-
-	if (isup)
-		reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullsel_offset, pctl);
-	else
-		reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullsel_offset, pctl);
+	if (pctl->devdata->quirks & MTK_PINCTRL_MODE_SET_CLR_BROKEN) {
+		bit = pin & pctl->devdata->mode_mask;
+		reg_pullen = mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset;
+		reg_pullsel = mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset;
+
+		regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullen,
+			BIT(bit), enable << bit);
+		regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullsel,
+			BIT(bit), isup << bit);
+	} else {
+		bit = BIT(pin & pctl->devdata->mode_mask);
+		if (enable)
+			reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset, pctl);
+		else
+			reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset, pctl);
+
+		if (isup)
+			reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset, pctl);
+		else
+			reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset, pctl);
+
+		regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
+		regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
+	}
 
-	regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
-	regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
 	return 0;
 }
 
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 6fe8564334c9..cc0dce8818c6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -22,6 +22,8 @@
 
 #define MTK_PINCTRL_NOT_SUPPORT	(0xffff)
 
+#define MTK_PINCTRL_MODE_SET_CLR_BROKEN   BIT(0)
+
 struct mtk_desc_function {
 	const char *name;
 	unsigned char muxval;
@@ -271,6 +273,7 @@ struct mtk_pinctrl_devdata {
 	unsigned int mode_mask;
 	unsigned int mode_per_reg;
 	unsigned int mode_shf;
+	unsigned long quirks;
 };
 
 struct mtk_pinctrl {
-- 
2.36.1


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
@ 2022-05-30 12:34 ` Fabien Parent
  0 siblings, 0 replies; 13+ messages in thread
From: Fabien Parent @ 2022-05-30 12:34 UTC (permalink / raw)
  To: Sean Wang, Linus Walleij, Matthias Brugger
  Cc: Fabien Parent, linux-mediatek, linux-gpio, linux-arm-kernel,
	linux-kernel

On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly. Add a quirk for such SoCs, so that instead of using
the SET/CLR register use the main R/W register
to read/update/write the modes.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 46 ++++++++++++-------
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  3 ++
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index f25b3e09386b..156627d9c552 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -330,23 +330,37 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
 		return -EINVAL;
 	}
 
-	bit = BIT(pin & pctl->devdata->mode_mask);
-	if (enable)
-		reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullen_offset, pctl);
-	else
-		reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullen_offset, pctl);
-
-	if (isup)
-		reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullsel_offset, pctl);
-	else
-		reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullsel_offset, pctl);
+	if (pctl->devdata->quirks & MTK_PINCTRL_MODE_SET_CLR_BROKEN) {
+		bit = pin & pctl->devdata->mode_mask;
+		reg_pullen = mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset;
+		reg_pullsel = mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset;
+
+		regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullen,
+			BIT(bit), enable << bit);
+		regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullsel,
+			BIT(bit), isup << bit);
+	} else {
+		bit = BIT(pin & pctl->devdata->mode_mask);
+		if (enable)
+			reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset, pctl);
+		else
+			reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset, pctl);
+
+		if (isup)
+			reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset, pctl);
+		else
+			reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset, pctl);
+
+		regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
+		regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
+	}
 
-	regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
-	regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
 	return 0;
 }
 
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 6fe8564334c9..cc0dce8818c6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -22,6 +22,8 @@
 
 #define MTK_PINCTRL_NOT_SUPPORT	(0xffff)
 
+#define MTK_PINCTRL_MODE_SET_CLR_BROKEN   BIT(0)
+
 struct mtk_desc_function {
 	const char *name;
 	unsigned char muxval;
@@ -271,6 +273,7 @@ struct mtk_pinctrl_devdata {
 	unsigned int mode_mask;
 	unsigned int mode_per_reg;
 	unsigned int mode_shf;
+	unsigned long quirks;
 };
 
 struct mtk_pinctrl {
-- 
2.36.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
@ 2022-05-30 12:34 ` Fabien Parent
  0 siblings, 0 replies; 13+ messages in thread
From: Fabien Parent @ 2022-05-30 12:34 UTC (permalink / raw)
  To: Sean Wang, Linus Walleij, Matthias Brugger
  Cc: Fabien Parent, linux-mediatek, linux-gpio, linux-arm-kernel,
	linux-kernel

On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly. Add a quirk for such SoCs, so that instead of using
the SET/CLR register use the main R/W register
to read/update/write the modes.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 46 ++++++++++++-------
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  3 ++
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index f25b3e09386b..156627d9c552 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -330,23 +330,37 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
 		return -EINVAL;
 	}
 
-	bit = BIT(pin & pctl->devdata->mode_mask);
-	if (enable)
-		reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullen_offset, pctl);
-	else
-		reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullen_offset, pctl);
-
-	if (isup)
-		reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullsel_offset, pctl);
-	else
-		reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
-			pctl->devdata->pullsel_offset, pctl);
+	if (pctl->devdata->quirks & MTK_PINCTRL_MODE_SET_CLR_BROKEN) {
+		bit = pin & pctl->devdata->mode_mask;
+		reg_pullen = mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset;
+		reg_pullsel = mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset;
+
+		regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullen,
+			BIT(bit), enable << bit);
+		regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullsel,
+			BIT(bit), isup << bit);
+	} else {
+		bit = BIT(pin & pctl->devdata->mode_mask);
+		if (enable)
+			reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset, pctl);
+		else
+			reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullen_offset, pctl);
+
+		if (isup)
+			reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset, pctl);
+		else
+			reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
+				pctl->devdata->pullsel_offset, pctl);
+
+		regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
+		regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
+	}
 
-	regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
-	regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
 	return 0;
 }
 
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 6fe8564334c9..cc0dce8818c6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -22,6 +22,8 @@
 
 #define MTK_PINCTRL_NOT_SUPPORT	(0xffff)
 
+#define MTK_PINCTRL_MODE_SET_CLR_BROKEN   BIT(0)
+
 struct mtk_desc_function {
 	const char *name;
 	unsigned char muxval;
@@ -271,6 +273,7 @@ struct mtk_pinctrl_devdata {
 	unsigned int mode_mask;
 	unsigned int mode_per_reg;
 	unsigned int mode_shf;
+	unsigned long quirks;
 };
 
 struct mtk_pinctrl {
-- 
2.36.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 2/2] pinctrl: mediatek: mt8365: use MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
  2022-05-30 12:34 ` Fabien Parent
  (?)
@ 2022-05-30 12:34   ` Fabien Parent
  -1 siblings, 0 replies; 13+ messages in thread
From: Fabien Parent @ 2022-05-30 12:34 UTC (permalink / raw)
  To: Sean Wang, Linus Walleij, Matthias Brugger
  Cc: Fabien Parent, linux-mediatek, linux-gpio, linux-arm-kernel,
	linux-kernel

On MT8365, the GPIO64 modes cannot be set using the SET/CLR register.
Use the MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk to workaround it.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
index 57f37a294063..a49fa685f5f5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
@@ -454,6 +454,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
 		.ap_num = 160,
 		.db_cnt = 160,
 	},
+	.quirks = MTK_PINCTRL_MODE_SET_CLR_BROKEN,
 };
 
 static const struct of_device_id mt8365_pctrl_match[] = {
-- 
2.36.1


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 2/2] pinctrl: mediatek: mt8365: use MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
@ 2022-05-30 12:34   ` Fabien Parent
  0 siblings, 0 replies; 13+ messages in thread
From: Fabien Parent @ 2022-05-30 12:34 UTC (permalink / raw)
  To: Sean Wang, Linus Walleij, Matthias Brugger
  Cc: Fabien Parent, linux-mediatek, linux-gpio, linux-arm-kernel,
	linux-kernel

On MT8365, the GPIO64 modes cannot be set using the SET/CLR register.
Use the MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk to workaround it.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
index 57f37a294063..a49fa685f5f5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
@@ -454,6 +454,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
 		.ap_num = 160,
 		.db_cnt = 160,
 	},
+	.quirks = MTK_PINCTRL_MODE_SET_CLR_BROKEN,
 };
 
 static const struct of_device_id mt8365_pctrl_match[] = {
-- 
2.36.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 2/2] pinctrl: mediatek: mt8365: use MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
@ 2022-05-30 12:34   ` Fabien Parent
  0 siblings, 0 replies; 13+ messages in thread
From: Fabien Parent @ 2022-05-30 12:34 UTC (permalink / raw)
  To: Sean Wang, Linus Walleij, Matthias Brugger
  Cc: Fabien Parent, linux-mediatek, linux-gpio, linux-arm-kernel,
	linux-kernel

On MT8365, the GPIO64 modes cannot be set using the SET/CLR register.
Use the MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk to workaround it.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
index 57f37a294063..a49fa685f5f5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
@@ -454,6 +454,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
 		.ap_num = 160,
 		.db_cnt = 160,
 	},
+	.quirks = MTK_PINCTRL_MODE_SET_CLR_BROKEN,
 };
 
 static const struct of_device_id mt8365_pctrl_match[] = {
-- 
2.36.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
  2022-05-30 12:34 ` Fabien Parent
  (?)
@ 2022-06-10 11:19   ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 13+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-06-10 11:19 UTC (permalink / raw)
  To: Fabien Parent, Sean Wang, Linus Walleij, Matthias Brugger
  Cc: linux-mediatek, linux-gpio, linux-arm-kernel, linux-kernel

Il 30/05/22 14:34, Fabien Parent ha scritto:
> On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> be set correctly. Add a quirk for such SoCs, so that instead of using
> the SET/CLR register use the main R/W register
> to read/update/write the modes.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>   drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 46 ++++++++++++-------
>   drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  3 ++
>   2 files changed, 33 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> index f25b3e09386b..156627d9c552 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> @@ -330,23 +330,37 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
>   		return -EINVAL;
>   	}
>   

That's not the right way of doing that, unless there are other SoCs that are
actually affected by this issue (and besides, any *new* pinctrl driver should
be using pinctrl-mtk-common-v2, which accounts for this quirk already).

Since MT8365 seems to be the only SoC that is affected by this issue, there's
a spec_pull_set() callback that you can use and you can indeed define your own
function in mt8365-pinctrl.c instead... but this, only if I got it right (and
I think I did, but please recheck!):

In this function, the call to spec_pull_set assigns 'arg' if 'enable == true',
else, MTK_PUPD_SET_R1R0_00...
...for "generic pull config", as stated in a comment in this function, 'arg' will
always be either 0 or 1, so you will get passed either:
     - 1, if pull-enable; or
     - MTK_PUPD_SET_R1R0_00 (100) if pull-disable.

Though, if I got the '1' part wrong, it's still doable because you care only about
one value in your case, so, if you get a MTK_PUPD_SET_R1R0_00, this means that you
have to do pull-disable.

The other args are passed as they are, so that's golden.

Regards,
Angelo

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
@ 2022-06-10 11:19   ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 13+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-06-10 11:19 UTC (permalink / raw)
  To: Fabien Parent, Sean Wang, Linus Walleij, Matthias Brugger
  Cc: linux-mediatek, linux-gpio, linux-arm-kernel, linux-kernel

Il 30/05/22 14:34, Fabien Parent ha scritto:
> On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> be set correctly. Add a quirk for such SoCs, so that instead of using
> the SET/CLR register use the main R/W register
> to read/update/write the modes.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>   drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 46 ++++++++++++-------
>   drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  3 ++
>   2 files changed, 33 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> index f25b3e09386b..156627d9c552 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> @@ -330,23 +330,37 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
>   		return -EINVAL;
>   	}
>   

That's not the right way of doing that, unless there are other SoCs that are
actually affected by this issue (and besides, any *new* pinctrl driver should
be using pinctrl-mtk-common-v2, which accounts for this quirk already).

Since MT8365 seems to be the only SoC that is affected by this issue, there's
a spec_pull_set() callback that you can use and you can indeed define your own
function in mt8365-pinctrl.c instead... but this, only if I got it right (and
I think I did, but please recheck!):

In this function, the call to spec_pull_set assigns 'arg' if 'enable == true',
else, MTK_PUPD_SET_R1R0_00...
...for "generic pull config", as stated in a comment in this function, 'arg' will
always be either 0 or 1, so you will get passed either:
     - 1, if pull-enable; or
     - MTK_PUPD_SET_R1R0_00 (100) if pull-disable.

Though, if I got the '1' part wrong, it's still doable because you care only about
one value in your case, so, if you get a MTK_PUPD_SET_R1R0_00, this means that you
have to do pull-disable.

The other args are passed as they are, so that's golden.

Regards,
Angelo

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
@ 2022-06-10 11:19   ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 13+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-06-10 11:19 UTC (permalink / raw)
  To: Fabien Parent, Sean Wang, Linus Walleij, Matthias Brugger
  Cc: linux-mediatek, linux-gpio, linux-arm-kernel, linux-kernel

Il 30/05/22 14:34, Fabien Parent ha scritto:
> On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> be set correctly. Add a quirk for such SoCs, so that instead of using
> the SET/CLR register use the main R/W register
> to read/update/write the modes.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>   drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 46 ++++++++++++-------
>   drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  3 ++
>   2 files changed, 33 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> index f25b3e09386b..156627d9c552 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> @@ -330,23 +330,37 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
>   		return -EINVAL;
>   	}
>   

That's not the right way of doing that, unless there are other SoCs that are
actually affected by this issue (and besides, any *new* pinctrl driver should
be using pinctrl-mtk-common-v2, which accounts for this quirk already).

Since MT8365 seems to be the only SoC that is affected by this issue, there's
a spec_pull_set() callback that you can use and you can indeed define your own
function in mt8365-pinctrl.c instead... but this, only if I got it right (and
I think I did, but please recheck!):

In this function, the call to spec_pull_set assigns 'arg' if 'enable == true',
else, MTK_PUPD_SET_R1R0_00...
...for "generic pull config", as stated in a comment in this function, 'arg' will
always be either 0 or 1, so you will get passed either:
     - 1, if pull-enable; or
     - MTK_PUPD_SET_R1R0_00 (100) if pull-disable.

Though, if I got the '1' part wrong, it's still doable because you care only about
one value in your case, so, if you get a MTK_PUPD_SET_R1R0_00, this means that you
have to do pull-disable.

The other args are passed as they are, so that's golden.

Regards,
Angelo

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
  2022-05-30 12:34 ` Fabien Parent
@ 2022-06-15 13:23   ` Linus Walleij
  -1 siblings, 0 replies; 13+ messages in thread
From: Linus Walleij @ 2022-06-15 13:23 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Sean Wang, Matthias Brugger, linux-mediatek, linux-gpio,
	linux-arm-kernel, linux-kernel

On Mon, May 30, 2022 at 2:35 PM Fabien Parent <fparent@baylibre.com> wrote:

> On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> be set correctly. Add a quirk for such SoCs, so that instead of using
> the SET/CLR register use the main R/W register
> to read/update/write the modes.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

What is the state of this patch set? I see changes are requested by
Angelo, are they being addressed?

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
@ 2022-06-15 13:23   ` Linus Walleij
  0 siblings, 0 replies; 13+ messages in thread
From: Linus Walleij @ 2022-06-15 13:23 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Sean Wang, Matthias Brugger, linux-mediatek, linux-gpio,
	linux-arm-kernel, linux-kernel

On Mon, May 30, 2022 at 2:35 PM Fabien Parent <fparent@baylibre.com> wrote:

> On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> be set correctly. Add a quirk for such SoCs, so that instead of using
> the SET/CLR register use the main R/W register
> to read/update/write the modes.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

What is the state of this patch set? I see changes are requested by
Angelo, are they being addressed?

Yours,
Linus Walleij

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
  2022-06-15 13:23   ` Linus Walleij
@ 2022-07-01  7:35     ` Markus Schneider-Pargmann
  -1 siblings, 0 replies; 13+ messages in thread
From: Markus Schneider-Pargmann @ 2022-07-01  7:35 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Fabien Parent, Sean Wang, Matthias Brugger, linux-mediatek,
	linux-gpio, linux-arm-kernel, linux-kernel

Hi Linus,

On Wed, Jun 15, 2022 at 03:23:57PM +0200, Linus Walleij wrote:
> On Mon, May 30, 2022 at 2:35 PM Fabien Parent <fparent@baylibre.com> wrote:
> 
> > On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> > be set correctly. Add a quirk for such SoCs, so that instead of using
> > the SET/CLR register use the main R/W register
> > to read/update/write the modes.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> 
> What is the state of this patch set? I see changes are requested by
> Angelo, are they being addressed?

I will probably pick up these patches and work on the comments, but I am
currently a bit busy on another project as well so it takes some time,
sorry.

Best,
Markus

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes
@ 2022-07-01  7:35     ` Markus Schneider-Pargmann
  0 siblings, 0 replies; 13+ messages in thread
From: Markus Schneider-Pargmann @ 2022-07-01  7:35 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Fabien Parent, Sean Wang, Matthias Brugger, linux-mediatek,
	linux-gpio, linux-arm-kernel, linux-kernel

Hi Linus,

On Wed, Jun 15, 2022 at 03:23:57PM +0200, Linus Walleij wrote:
> On Mon, May 30, 2022 at 2:35 PM Fabien Parent <fparent@baylibre.com> wrote:
> 
> > On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> > be set correctly. Add a quirk for such SoCs, so that instead of using
> > the SET/CLR register use the main R/W register
> > to read/update/write the modes.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> 
> What is the state of this patch set? I see changes are requested by
> Angelo, are they being addressed?

I will probably pick up these patches and work on the comments, but I am
currently a bit busy on another project as well so it takes some time,
sorry.

Best,
Markus

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-07-01  7:37 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-30 12:34 [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes Fabien Parent
2022-05-30 12:34 ` Fabien Parent
2022-05-30 12:34 ` Fabien Parent
2022-05-30 12:34 ` [PATCH 2/2] pinctrl: mediatek: mt8365: use MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk Fabien Parent
2022-05-30 12:34   ` Fabien Parent
2022-05-30 12:34   ` Fabien Parent
2022-06-10 11:19 ` [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes AngeloGioacchino Del Regno
2022-06-10 11:19   ` AngeloGioacchino Del Regno
2022-06-10 11:19   ` AngeloGioacchino Del Regno
2022-06-15 13:23 ` Linus Walleij
2022-06-15 13:23   ` Linus Walleij
2022-07-01  7:35   ` Markus Schneider-Pargmann
2022-07-01  7:35     ` Markus Schneider-Pargmann

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