[Intel-gfx] [PATCH 1/6] drm/i915/display/psr: Handle SU Y granularity

[Intel-gfx] [PATCH 1/6] drm/i915/display/psr: Handle SU Y granularity

[José Roberto de Souza]

We were only handling X and width granularity, what was causing issues
when sink had a granularity different than 4.

While at it, renaming su_x_granularity to su_w_granularity to better
match reality.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 110 ++++++++++++------
 2 files changed, 80 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 15e91a99c8b9a..f89152ca52a20 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1041,6 +1041,7 @@ struct intel_crtc_state {
 	bool has_psr2;
 	bool enable_psr2_sel_fetch;
 	u32 dc3co_exitline;
+	u16 su_y_granularity;
 
 	/*
 	 * Frequence the dpll for the port should run at. Differs from the
@@ -1498,7 +1499,8 @@ struct intel_psr {
 	ktime_t last_exit;
 	bool sink_not_reliable;
 	bool irq_aux_error;
-	u16 su_x_granularity;
+	u16 su_w_granularity;
+	u16 su_y_granularity;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 77865cf6641f8..fde30f937504e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -265,32 +265,44 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 	return val;
 }
 
-static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
+static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-	u16 val;
 	ssize_t r;
+	u16 w;
+	u8 y;
+
+	/* If sink don't have specific granularity requirements set legacy ones */
+	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+		/* As PSR2 HW sends full lines, we do not care about x granularity */
+		w = 4;
+		y = 4;
+		goto exit;
+	}
 
-	/*
-	 * Returning the default X granularity if granularity not required or
-	 * if DPCD read fails
-	 */
-	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
-		return 4;
-
-	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
 	if (r != 2)
 		drm_dbg_kms(&i915->drm,
 			    "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
-
 	/*
 	 * Spec says that if the value read is 0 the default granularity should
 	 * be used instead.
 	 */
-	if (r != 2 || val == 0)
-		val = 4;
+	if (r != 2 || w == 0)
+		w = 4;
 
-	return val;
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
+	if (r != 1) {
+		drm_dbg_kms(&i915->drm,
+			    "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
+		y = 4;
+	}
+	if (y == 0)
+		y = 1;
+
+exit:
+	intel_dp->psr.su_w_granularity = w;
+	intel_dp->psr.su_y_granularity = y;
 }
 
 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
@@ -346,8 +358,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 		if (intel_dp->psr.sink_psr2_support) {
 			intel_dp->psr.colorimetry_support =
 				intel_dp_get_colorimetry_status(intel_dp);
-			intel_dp->psr.su_x_granularity =
-				intel_dp_get_su_x_granulartiy(intel_dp);
+			intel_dp_get_su_granularity(intel_dp);
 		}
 	}
 }
@@ -742,6 +753,40 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 	return crtc_state->enable_psr2_sel_fetch = true;
 }
 
+static bool psr2_granularity_check(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state)
+{
+	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
+	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
+	u16 y_granularity = 0;
+
+	/* PSR2 HW only send full lines so we only need to validate the width */
+	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
+		return false;
+
+	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
+		return false;
+
+	/* HW tracking is only aligned to 4 lines */
+	if (!crtc_state->enable_psr2_sel_fetch)
+		return intel_dp->psr.su_y_granularity == 4;
+
+	/*
+	 * For SW tracking we can adjust the y to match sink requirement if
+	 * multiple of 4
+	 */
+	if (intel_dp->psr.su_y_granularity <= 2)
+		y_granularity = 4;
+	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
+		y_granularity = intel_dp->psr.su_y_granularity;
+
+	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
+		return false;
+
+	crtc_state->su_y_granularity = y_granularity;
+	return true;
+}
+
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -824,19 +869,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	/*
-	 * HW sends SU blocks of size four scan lines, which means the starting
-	 * X coordinate and Y granularity requirements will always be met. We
-	 * only need to validate the SU block width is a multiple of
-	 * x granularity.
-	 */
-	if (crtc_hdisplay % intel_dp->psr.su_x_granularity) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
-			    crtc_hdisplay, intel_dp->psr.su_x_granularity);
-		return false;
-	}
-
 	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 		if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 		    !HAS_PSR_HW_TRACKING(dev_priv)) {
@@ -853,6 +885,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (!psr2_granularity_check(intel_dp, crtc_state)) {
+		drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
+		return false;
+	}
+
 	if (!crtc_state->enable_psr2_sel_fetch &&
 	    (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
 		drm_dbg_kms(&dev_priv->drm,
@@ -1432,6 +1469,16 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
 		overlap_damage_area->y2 = damage_area->y2;
 }
 
+static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
+						struct drm_rect *pipe_clip)
+{
+	const u16 y_alignment = crtc_state->su_y_granularity;
+
+	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
+	if (pipe_clip->y2 % y_alignment)
+		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
+}
+
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc)
 {
@@ -1540,10 +1587,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	if (full_update)
 		goto skip_sel_fetch_set_loop;
 
-	/* It must be aligned to 4 lines */
-	pipe_clip.y1 -= pipe_clip.y1 % 4;
-	if (pipe_clip.y2 % 4)
-		pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4;
+	intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
 
 	/*
 	 * Now that we have the pipe damaged area check if it intersect with
-- 
2.32.0

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[Intel-gfx] [PATCH 2/6] drm/i915/display/adl_p: Implement Wa_22012278275

[José Roberto de Souza]

The PSR2_CTL io buffer wake and fast wake values do not match
expected in pre production hardware, so here adding a table that
matches with HW to program it with values that HW expect.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 29 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h          |  6 +++--
 2 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index fde30f937504e..c8d56387d9233 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -542,7 +542,34 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
 	val |= intel_psr2_get_tp_time(intel_dp);
 
-	if (DISPLAY_VER(dev_priv) >= 12) {
+	/* Wa_22012278275:adlp */
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
+		static const u8 map[] = {
+			2, /* 5 lines */
+			1, /* 6 lines */
+			0, /* 7 lines */
+			3, /* 8 lines */
+			6, /* 9 lines */
+			5, /* 10 lines */
+			4, /* 11 lines */
+			7, /* 12 lines */
+		};
+		/*
+		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
+		 * comments bellow for more information
+		 */
+		u32 tmp, lines = 7;
+
+		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
+
+		tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
+		tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
+		val |= tmp;
+
+		tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
+		tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
+		val |= tmp;
+	} else if (DISPLAY_VER(dev_priv) >= 12) {
 		/*
 		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
 		 * values from BSpec. In order to setting an optimal power
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 955027799d1de..4a98e49c58812 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4596,13 +4596,15 @@ enum {
 #define   EDP_PSR2_IO_BUFFER_WAKE(lines)	((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
 #define   EDP_PSR2_IO_BUFFER_WAKE_MASK		(3 << 13)
 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5
-#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT	13
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK	(7 << 13)
 #define   EDP_PSR2_FAST_WAKE_MAX_LINES		8
 #define   EDP_PSR2_FAST_WAKE(lines)		((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
 #define   EDP_PSR2_FAST_WAKE_MASK		(3 << 11)
 #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES	5
-#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
+#define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT	10
+#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
 #define   TGL_EDP_PSR2_FAST_WAKE_MASK		(7 << 10)
 #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
 #define   EDP_PSR2_TP2_TIME_100us		(1 << 8)
-- 
2.32.0

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Re: [Intel-gfx] [PATCH 2/6] drm/i915/display/adl_p: Implement Wa_22012278275

[Gwan-gyeong Mun]

On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> The PSR2_CTL io buffer wake and fast wake values do not match
> expected in pre production hardware, so here adding a table that
> matches with HW to program it with values that HW expect.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 29 +++++++++++++++++++++++-
>   drivers/gpu/drm/i915/i915_reg.h          |  6 +++--
>   2 files changed, 32 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index fde30f937504e..c8d56387d9233 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -542,7 +542,34 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>   	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
>   	val |= intel_psr2_get_tp_time(intel_dp);
>   
> -	if (DISPLAY_VER(dev_priv) >= 12) {
> +	/* Wa_22012278275:adlp */
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
> +		static const u8 map[] = {
> +			2, /* 5 lines */
> +			1, /* 6 lines */
> +			0, /* 7 lines */
> +			3, /* 8 lines */
> +			6, /* 9 lines */
> +			5, /* 10 lines */
> +			4, /* 11 lines */
> +			7, /* 12 lines */
> +		};
> +		/*
> +		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
> +		 * comments bellow for more information
typo on comments; bellow
except for the typo, looks good to me.

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> +		 */
> +		u32 tmp, lines = 7;
> +
> +		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
> +
> +		tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
> +		tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
> +		val |= tmp;
> +
> +		tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
> +		tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
> +		val |= tmp;
> +	} else if (DISPLAY_VER(dev_priv) >= 12) {
>   		/*
>   		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
>   		 * values from BSpec. In order to setting an optimal power
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 955027799d1de..4a98e49c58812 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4596,13 +4596,15 @@ enum {
>   #define   EDP_PSR2_IO_BUFFER_WAKE(lines)	((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
>   #define   EDP_PSR2_IO_BUFFER_WAKE_MASK		(3 << 13)
>   #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5
> -#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
> +#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT	13
> +#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
>   #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK	(7 << 13)
>   #define   EDP_PSR2_FAST_WAKE_MAX_LINES		8
>   #define   EDP_PSR2_FAST_WAKE(lines)		((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
>   #define   EDP_PSR2_FAST_WAKE_MASK		(3 << 11)
>   #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES	5
> -#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
> +#define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT	10
> +#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
>   #define   TGL_EDP_PSR2_FAST_WAKE_MASK		(7 << 10)
>   #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
>   #define   EDP_PSR2_TP2_TIME_100us		(1 << 8)
> 
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Re: [Intel-gfx] [PATCH 2/6] drm/i915/display/adl_p: Implement Wa_22012278275

[Jani Nikula]

This is well after this has been merged, but only spotted this now.

In the future, please add something sensible to the subject lines
instead of just the platform and workaround number. I'm looking at a
shortlog with:

      drm/i915/display/adl_p: Implement Wa_22012278275
      drm/i915/display/adl_p: Implement Wa_16011168373
      drm/i915/display/adl_p: Implement Wa_16011303918

and that's just completely unhelpful. :(

BR,
Jani.


On Wed, 16 Jun 2021, José Roberto de Souza <jose.souza@intel.com> wrote:
> The PSR2_CTL io buffer wake and fast wake values do not match
> expected in pre production hardware, so here adding a table that
> matches with HW to program it with values that HW expect.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 29 +++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h          |  6 +++--
>  2 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index fde30f937504e..c8d56387d9233 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -542,7 +542,34 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
>  	val |= intel_psr2_get_tp_time(intel_dp);
>  
> -	if (DISPLAY_VER(dev_priv) >= 12) {
> +	/* Wa_22012278275:adlp */
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
> +		static const u8 map[] = {
> +			2, /* 5 lines */
> +			1, /* 6 lines */
> +			0, /* 7 lines */
> +			3, /* 8 lines */
> +			6, /* 9 lines */
> +			5, /* 10 lines */
> +			4, /* 11 lines */
> +			7, /* 12 lines */
> +		};
> +		/*
> +		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
> +		 * comments bellow for more information
> +		 */
> +		u32 tmp, lines = 7;
> +
> +		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
> +
> +		tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
> +		tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
> +		val |= tmp;
> +
> +		tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
> +		tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
> +		val |= tmp;
> +	} else if (DISPLAY_VER(dev_priv) >= 12) {
>  		/*
>  		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
>  		 * values from BSpec. In order to setting an optimal power
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 955027799d1de..4a98e49c58812 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4596,13 +4596,15 @@ enum {
>  #define   EDP_PSR2_IO_BUFFER_WAKE(lines)	((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
>  #define   EDP_PSR2_IO_BUFFER_WAKE_MASK		(3 << 13)
>  #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5
> -#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
> +#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT	13
> +#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
>  #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK	(7 << 13)
>  #define   EDP_PSR2_FAST_WAKE_MAX_LINES		8
>  #define   EDP_PSR2_FAST_WAKE(lines)		((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
>  #define   EDP_PSR2_FAST_WAKE_MASK		(3 << 11)
>  #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES	5
> -#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
> +#define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT	10
> +#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
>  #define   TGL_EDP_PSR2_FAST_WAKE_MASK		(7 << 10)
>  #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
>  #define   EDP_PSR2_TP2_TIME_100us		(1 << 8)

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 2/6] drm/i915/display/adl_p: Implement Wa_22012278275

[Jani Nikula]

This is well after this has been merged, but only spotted this now.

In the future, please add something sensible to the subject lines
instead of just the platform and workaround number. I'm looking at a
shortlog with:

      drm/i915/display/adl_p: Implement Wa_22012278275
      drm/i915/display/adl_p: Implement Wa_16011168373
      drm/i915/display/adl_p: Implement Wa_16011303918

and that's just completely unhelpful. :(

BR,
Jani.


On Wed, 16 Jun 2021, José Roberto de Souza <jose.souza@intel.com> wrote:
> The PSR2_CTL io buffer wake and fast wake values do not match
> expected in pre production hardware, so here adding a table that
> matches with HW to program it with values that HW expect.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 29 +++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h          |  6 +++--
>  2 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index fde30f937504e..c8d56387d9233 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -542,7 +542,34 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
>  	val |= intel_psr2_get_tp_time(intel_dp);
>  
> -	if (DISPLAY_VER(dev_priv) >= 12) {
> +	/* Wa_22012278275:adlp */
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
> +		static const u8 map[] = {
> +			2, /* 5 lines */
> +			1, /* 6 lines */
> +			0, /* 7 lines */
> +			3, /* 8 lines */
> +			6, /* 9 lines */
> +			5, /* 10 lines */
> +			4, /* 11 lines */
> +			7, /* 12 lines */
> +		};
> +		/*
> +		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
> +		 * comments bellow for more information
> +		 */
> +		u32 tmp, lines = 7;
> +
> +		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
> +
> +		tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
> +		tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
> +		val |= tmp;
> +
> +		tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
> +		tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
> +		val |= tmp;
> +	} else if (DISPLAY_VER(dev_priv) >= 12) {
>  		/*
>  		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
>  		 * values from BSpec. In order to setting an optimal power
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 955027799d1de..4a98e49c58812 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4596,13 +4596,15 @@ enum {
>  #define   EDP_PSR2_IO_BUFFER_WAKE(lines)	((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
>  #define   EDP_PSR2_IO_BUFFER_WAKE_MASK		(3 << 13)
>  #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5
> -#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
> +#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT	13
> +#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
>  #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK	(7 << 13)
>  #define   EDP_PSR2_FAST_WAKE_MAX_LINES		8
>  #define   EDP_PSR2_FAST_WAKE(lines)		((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
>  #define   EDP_PSR2_FAST_WAKE_MASK		(3 << 11)
>  #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES	5
> -#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
> +#define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT	10
> +#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
>  #define   TGL_EDP_PSR2_FAST_WAKE_MASK		(7 << 10)
>  #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
>  #define   EDP_PSR2_TP2_TIME_100us		(1 << 8)

-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH 3/6] drm/i915/display/adl_p: Implement Wa_16011168373

[José Roberto de Souza]

Another WA that is required for PSR2.

BSpec: 54369
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h          |  8 ++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c8d56387d9233..e508816911fad 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1112,6 +1112,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
 			     intel_dp->psr.psr2_sel_fetch_enabled ?
 			     IGNORE_PSR2_HW_TRACKING : 0);
+
+	/* Wa_16011168373:adlp */
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
+	    intel_dp->psr.psr2_enabled)
+		intel_de_rmw(dev_priv,
+			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
+			     TRANS_SET_CONTEXT_LATENCY_MASK,
+			     TRANS_SET_CONTEXT_LATENCY_VALUE(1));
 }
 
 static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
@@ -1289,6 +1297,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
 
+	/* Wa_16011168373:adlp */
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
+	    intel_dp->psr.psr2_enabled)
+		intel_de_rmw(dev_priv,
+			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
+			     TRANS_SET_CONTEXT_LATENCY_MASK, 0);
+
 	/* Disable PSR on Sink */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a98e49c58812..568e5f108e2c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10368,6 +10368,14 @@ enum skl_power_gate {
 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
 /* See DP_MSA_MISC_* for the bit definitions */
 
+#define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
+#define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
+#define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
+#define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
+#define TRANS_SET_CONTEXT_LATENCY(tran)		_MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
+#define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
+#define  TRANS_SET_CONTEXT_LATENCY_VALUE(x)	REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
+
 /* LCPLL Control */
 #define LCPLL_CTL			_MMIO(0x130040)
 #define  LCPLL_PLL_DISABLE		(1 << 31)
-- 
2.32.0

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Re: [Intel-gfx] [PATCH 3/6] drm/i915/display/adl_p: Implement Wa_16011168373

[Gwan-gyeong Mun]

Looks good to me.

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> Another WA that is required for PSR2.
> 
> BSpec: 54369
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
>   drivers/gpu/drm/i915/i915_reg.h          |  8 ++++++++
>   2 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c8d56387d9233..e508816911fad 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1112,6 +1112,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>   		intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
>   			     intel_dp->psr.psr2_sel_fetch_enabled ?
>   			     IGNORE_PSR2_HW_TRACKING : 0);
> +
> +	/* Wa_16011168373:adlp */
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> +	    intel_dp->psr.psr2_enabled)
> +		intel_de_rmw(dev_priv,
> +			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> +			     TRANS_SET_CONTEXT_LATENCY_MASK,
> +			     TRANS_SET_CONTEXT_LATENCY_VALUE(1));
>   }
>   
>   static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> @@ -1289,6 +1297,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>   		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>   			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>   
> +	/* Wa_16011168373:adlp */
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> +	    intel_dp->psr.psr2_enabled)
> +		intel_de_rmw(dev_priv,
> +			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> +			     TRANS_SET_CONTEXT_LATENCY_MASK, 0);
> +
>   	/* Disable PSR on Sink */
>   	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
>   
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4a98e49c58812..568e5f108e2c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10368,6 +10368,14 @@ enum skl_power_gate {
>   #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
>   /* See DP_MSA_MISC_* for the bit definitions */
>   
> +#define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
> +#define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
> +#define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
> +#define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
> +#define TRANS_SET_CONTEXT_LATENCY(tran)		_MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
> +#define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
> +#define  TRANS_SET_CONTEXT_LATENCY_VALUE(x)	REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
> +
>   /* LCPLL Control */
>   #define LCPLL_CTL			_MMIO(0x130040)
>   #define  LCPLL_PLL_DISABLE		(1 << 31)
> 
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[Intel-gfx] [PATCH 4/6] drm/i915/xelpd: Handle PSR2 SDP indication in the prior scanline

[José Roberto de Souza]

In some modes there is not enough time during hblank to transmit PSR2
SDP plus the pixels CRC SDP, if such case happens PSR2 needs to be
disabled.
But eDP spec 1.4b allows to transmit PSR2 SDP in a prior scanline
alone and than later the CRC SDP, allowing PSR2 to be enabled in
those hblank constrained modes.

BSpec: 49274
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 37 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 3 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f89152ca52a20..56c4cb45c99df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1040,6 +1040,7 @@ struct intel_crtc_state {
 	bool has_psr;
 	bool has_psr2;
 	bool enable_psr2_sel_fetch;
+	bool req_psr2_sdp_prior_scanline;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
 
@@ -1494,6 +1495,7 @@ struct intel_psr {
 	bool colorimetry_support;
 	bool psr2_enabled;
 	bool psr2_sel_fetch_enabled;
+	bool req_psr2_sdp_prior_scanline;
 	u8 sink_sync_latency;
 	ktime_t last_entry_attempt;
 	ktime_t last_exit;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e508816911fad..3cb8758be4042 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -418,6 +418,9 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 			dpcd_val |= DP_PSR_CRC_VERIFICATION;
 	}
 
+	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
+		dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
+
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
@@ -585,6 +588,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 		val |= EDP_PSR2_FAST_WAKE(7);
 	}
 
+	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
+		val |= EDP_PSR2_SU_SDP_SCANLINE;
+
 	if (intel_dp->psr.psr2_sel_fetch_enabled) {
 		/* WA 1408330847 */
 		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
@@ -814,6 +820,29 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
 	return true;
 }
 
+static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
+							struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	u32 hblank_total, hblank_ns, req_ns;
+
+	hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
+	hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
+
+	/* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */
+	req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000);
+
+	if ((hblank_ns - req_ns) > 100)
+		return true;
+
+	if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
+		return false;
+
+	crtc_state->req_psr2_sdp_prior_scanline = true;
+	return true;
+}
+
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -926,6 +955,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");
+		return false;
+	}
+
 	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 	return true;
 }
@@ -1173,6 +1208,8 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	intel_dp->psr.dc3co_exit_delay = val;
 	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
 	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+	intel_dp->psr.req_psr2_sdp_prior_scanline =
+		crtc_state->req_psr2_sdp_prior_scanline;
 
 	if (!psr_interrupt_error_check(intel_dp))
 		return;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 568e5f108e2c4..e0bd60fe7a190 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4590,6 +4590,7 @@ enum {
 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
 #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
+#define   EDP_PSR2_SU_SDP_SCANLINE		REG_BIT(25) /* display 13+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)		((t) << 20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)
 #define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES	8
-- 
2.32.0

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Re: [Intel-gfx] [PATCH 4/6] drm/i915/xelpd: Handle PSR2 SDP indication in the prior scanline

[Gwan-gyeong Mun]

looks good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> In some modes there is not enough time during hblank to transmit PSR2
> SDP plus the pixels CRC SDP, if such case happens PSR2 needs to be
> disabled.
> But eDP spec 1.4b allows to transmit PSR2 SDP in a prior scanline
> alone and than later the CRC SDP, allowing PSR2 to be enabled in
> those hblank constrained modes.
> 
> BSpec: 49274
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>   .../drm/i915/display/intel_display_types.h    |  2 +
>   drivers/gpu/drm/i915/display/intel_psr.c      | 37 +++++++++++++++++++
>   drivers/gpu/drm/i915/i915_reg.h               |  1 +
>   3 files changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f89152ca52a20..56c4cb45c99df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1040,6 +1040,7 @@ struct intel_crtc_state {
>   	bool has_psr;
>   	bool has_psr2;
>   	bool enable_psr2_sel_fetch;
> +	bool req_psr2_sdp_prior_scanline;
>   	u32 dc3co_exitline;
>   	u16 su_y_granularity;
>   
> @@ -1494,6 +1495,7 @@ struct intel_psr {
>   	bool colorimetry_support;
>   	bool psr2_enabled;
>   	bool psr2_sel_fetch_enabled;
> +	bool req_psr2_sdp_prior_scanline;
>   	u8 sink_sync_latency;
>   	ktime_t last_entry_attempt;
>   	ktime_t last_exit;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index e508816911fad..3cb8758be4042 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -418,6 +418,9 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>   			dpcd_val |= DP_PSR_CRC_VERIFICATION;
>   	}
>   
> +	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
> +		dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
> +
>   	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>   
>   	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
> @@ -585,6 +588,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>   		val |= EDP_PSR2_FAST_WAKE(7);
>   	}
>   
> +	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
> +		val |= EDP_PSR2_SU_SDP_SCANLINE;
> +
>   	if (intel_dp->psr.psr2_sel_fetch_enabled) {
>   		/* WA 1408330847 */
>   		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> @@ -814,6 +820,29 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
>   	return true;
>   }
>   
> +static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
> +							struct intel_crtc_state *crtc_state)
> +{
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	u32 hblank_total, hblank_ns, req_ns;
> +
> +	hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
> +	hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
> +
> +	/* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */
> +	req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000);
> +
> +	if ((hblank_ns - req_ns) > 100)
> +		return true;
> +
> +	if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
> +		return false;
> +
> +	crtc_state->req_psr2_sdp_prior_scanline = true;
> +	return true;
> +}
> +
>   static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>   				    struct intel_crtc_state *crtc_state)
>   {
> @@ -926,6 +955,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>   		return false;
>   	}
>   
> +	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");
> +		return false;
> +	}
> +
>   	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
>   	return true;
>   }
> @@ -1173,6 +1208,8 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>   	intel_dp->psr.dc3co_exit_delay = val;
>   	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
>   	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> +	intel_dp->psr.req_psr2_sdp_prior_scanline =
> +		crtc_state->req_psr2_sdp_prior_scanline;
>   
>   	if (!psr_interrupt_error_check(intel_dp))
>   		return;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 568e5f108e2c4..e0bd60fe7a190 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4590,6 +4590,7 @@ enum {
>   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
>   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
>   #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
> +#define   EDP_PSR2_SU_SDP_SCANLINE		REG_BIT(25) /* display 13+ */
>   #define   EDP_MAX_SU_DISABLE_TIME(t)		((t) << 20)
>   #define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)
>   #define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES	8
> 
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[Intel-gfx] [PATCH 5/6] drm/i915/display/adl_p: Implement Wa_16011303918

[José Roberto de Souza]

PSR2 is not compatible with DC3CO or VRR in this stepping, so not
enabling PSR2 if VRR will be enabled or not enabling DC3CO if PSR2 is
possible.

BSpec: 54369
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3cb8758be4042..9643624fe160d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -733,6 +733,10 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
 		return;
 
+	/* Wa_16011303918:adlp */
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+		return;
+
 	/*
 	 * DC3CO Exit time 200us B.Spec 49196
 	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
@@ -961,6 +965,14 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	/* Wa_16011303918:adlp */
+	if (crtc_state->vrr.enable &&
+	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
+		return false;
+	}
+
 	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 	return true;
 }
-- 
2.32.0

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Re: [Intel-gfx] [PATCH 5/6] drm/i915/display/adl_p: Implement Wa_16011303918

[Gwan-gyeong Mun]

looks good to me

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> PSR2 is not compatible with DC3CO or VRR in this stepping, so not
> enabling PSR2 if VRR will be enabled or not enabling DC3CO if PSR2 is
> possible.
> 
> BSpec: 54369
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3cb8758be4042..9643624fe160d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -733,6 +733,10 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>   	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
>   		return;
>   
> +	/* Wa_16011303918:adlp */
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +		return;
> +
>   	/*
>   	 * DC3CO Exit time 200us B.Spec 49196
>   	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
> @@ -961,6 +965,14 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>   		return false;
>   	}
>   
> +	/* Wa_16011303918:adlp */
> +	if (crtc_state->vrr.enable &&
> +	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
> +		return false;
> +	}
> +
>   	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
>   	return true;
>   }
> 
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[Intel-gfx] [PATCH 6/6] drm/i915/display/adl_p: Implement PSR changes

[José Roberto de Souza]

Implements changes around PSR for alderlake-P:

- EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
- Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
  removed setting SU_REGION_START/END_ADDR will do this job
- SU_REGION_START/END_ADDR have now line granularity but will need to
  be aligned with DSC when the PSRS + DSC support lands

BSpec: 50422
BSpec: 50424
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
 drivers/gpu/drm/i915/i915_reg.h          | 26 ++++++++------
 2 files changed, 48 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9643624fe160d..46bb19c4b63a4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	u32 val;
+	u32 val = EDP_PSR2_ENABLE;
+
+	val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
 
-	val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
+	if (!IS_ALDERLAKE_P(dev_priv))
+		val |= EDP_SU_TRACK_ENABLE;
 
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
 		val |= EDP_Y_COORDINATE_ENABLE;
 
@@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 static bool psr2_granularity_check(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	u16 y_granularity = 0;
@@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
 		return intel_dp->psr.su_y_granularity == 4;
 
 	/*
-	 * For SW tracking we can adjust the y to match sink requirement if
-	 * multiple of 4
+	 * adl_p has 1 line granularity for other platforms with SW tracking we
+	 * can adjust the y coordinate to match sink requirement if multiple of
+	 * 4
 	 */
-	if (intel_dp->psr.su_y_granularity <= 2)
+	if (IS_ALDERLAKE_P(dev_priv))
+		y_granularity = intel_dp->psr.su_y_granularity;
+	else if (intel_dp->psr.su_y_granularity <= 2)
 		y_granularity = 4;
 	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
 		y_granularity = intel_dp->psr.su_y_granularity;
@@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
 				  struct drm_rect *clip, bool full_update)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val = PSR2_MAN_TRK_CTL_ENABLE;
 
 	if (full_update) {
-		val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+		if (IS_ALDERLAKE_P(dev_priv))
+			val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+		else
+			val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+
 		goto exit;
 	}
 
 	if (clip->y1 == -1)
 		goto exit;
 
-	drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
+	if (IS_ALDERLAKE_P(dev_priv)) {
+		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
+		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
+	} else {
+		drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
 
-	val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
-	val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
-	val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+		val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+		val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
+		val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+	}
 exit:
 	crtc_state->psr2_man_track_ctl = val;
 }
@@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
 						struct drm_rect *pipe_clip)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	const u16 y_alignment = crtc_state->su_y_granularity;
 
 	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
 	if (pipe_clip->y2 % y_alignment)
 		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
+
+	if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
+		drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
 }
 
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0bd60fe7a190..74dc5ebce60e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4586,7 +4586,7 @@ enum {
 #define _PSR2_CTL_EDP				0x6f900
 #define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(tran, _PSR2_CTL_A)
 #define   EDP_PSR2_ENABLE			(1 << 31)
-#define   EDP_SU_TRACK_ENABLE			(1 << 30)
+#define   EDP_SU_TRACK_ENABLE			(1 << 30) /* up to adl-p */
 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
 #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
@@ -4655,17 +4655,23 @@ enum {
 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
 #define PSR2_SU_STATUS_FRAMES		8
 
-#define _PSR2_MAN_TRK_CTL_A				0x60910
-#define _PSR2_MAN_TRK_CTL_EDP				0x6f910
-#define PSR2_MAN_TRK_CTL(tran)				_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
-#define  PSR2_MAN_TRK_CTL_ENABLE			REG_BIT(31)
-#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(30, 21)
-#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
+#define _PSR2_MAN_TRK_CTL_A					0x60910
+#define _PSR2_MAN_TRK_CTL_EDP					0x6f910
+#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
+#define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
+#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
+#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
 #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(20, 11)
 #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
-#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(3)
-#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
-#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
+#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
+#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
+#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
+#define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
+#define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
 
 /* Icelake DSC Rate Control Range Parameter Registers */
 #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
-- 
2.32.0

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Re: [Intel-gfx] [PATCH 6/6] drm/i915/display/adl_p: Implement PSR changes

[Gwan-gyeong Mun]

On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> Implements changes around PSR for alderlake-P:
> 
> - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> - Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
>    removed setting SU_REGION_START/END_ADDR will do this job
> - SU_REGION_START/END_ADDR have now line granularity but will need to
>    be aligned with DSC when the PSRS + DSC support lands
> 
> BSpec: 50422
> BSpec: 50424
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
>   drivers/gpu/drm/i915/i915_reg.h          | 26 ++++++++------
>   2 files changed, 48 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9643624fe160d..46bb19c4b63a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
>   static void hsw_activate_psr2(struct intel_dp *intel_dp)
>   {
>   	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	u32 val;
> +	u32 val = EDP_PSR2_ENABLE;
> +
> +	val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
>   
> -	val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> +	if (!IS_ALDERLAKE_P(dev_priv))
> +		val |= EDP_SU_TRACK_ENABLE;
>   
> -	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
>   	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
>   		val |= EDP_Y_COORDINATE_ENABLE;
>   
> @@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>   static bool psr2_granularity_check(struct intel_dp *intel_dp,
>   				   struct intel_crtc_state *crtc_state)
>   {
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>   	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>   	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>   	u16 y_granularity = 0;
> @@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
>   		return intel_dp->psr.su_y_granularity == 4;
>   
>   	/*
> -	 * For SW tracking we can adjust the y to match sink requirement if
> -	 * multiple of 4
> +	 * adl_p has 1 line granularity for other platforms with SW tracking we
> +	 * can adjust the y coordinate to match sink requirement if multiple of
> +	 * 4
>   	 */
> -	if (intel_dp->psr.su_y_granularity <= 2)
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		y_granularity = intel_dp->psr.su_y_granularity;
> +	else if (intel_dp->psr.su_y_granularity <= 2)
>   		y_granularity = 4;
>   	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
>   		y_granularity = intel_dp->psr.su_y_granularity;
> @@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
>   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>   				  struct drm_rect *clip, bool full_update)
>   {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	u32 val = PSR2_MAN_TRK_CTL_ENABLE;
The logic is not wrong, but the meaning of the register bit has changed.
The 31st bit in ADL-P means "SF partial frame enable".
It is recommended to add a macro such as 
ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE to the code to clarify the 
role of the changed register.
>   
>   	if (full_update) {
> -		val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> +		if (IS_ALDERLAKE_P(dev_priv))
> +			val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> +		else
> +			val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> +
>   		goto exit;
>   	}
>   
>   	if (clip->y1 == -1)
>   		goto exit;
>   
> -	drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> +	if (IS_ALDERLAKE_P(dev_priv)) {
> +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
> +	} else {
> +		drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
>   
> -	val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> -	val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> -	val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> +		val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> +		val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> +		val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> +	}
>   exit:
>   	crtc_state->psr2_man_track_ctl = val;
>   }
> @@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
>   static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
>   						struct drm_rect *pipe_clip)
>   {
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>   	const u16 y_alignment = crtc_state->su_y_granularity;
>   
>   	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
>   	if (pipe_clip->y2 % y_alignment)
>   		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
> +
> +	if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
> +		drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
>   }
>   
>   int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e0bd60fe7a190..74dc5ebce60e7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4586,7 +4586,7 @@ enum {
>   #define _PSR2_CTL_EDP				0x6f900
>   #define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(tran, _PSR2_CTL_A)
>   #define   EDP_PSR2_ENABLE			(1 << 31)
> -#define   EDP_SU_TRACK_ENABLE			(1 << 30)
> +#define   EDP_SU_TRACK_ENABLE			(1 << 30) /* up to adl-p */
>   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
>   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
>   #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
> @@ -4655,17 +4655,23 @@ enum {
>   #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
>   #define PSR2_SU_STATUS_FRAMES		8
>   
> -#define _PSR2_MAN_TRK_CTL_A				0x60910
> -#define _PSR2_MAN_TRK_CTL_EDP				0x6f910
> -#define PSR2_MAN_TRK_CTL(tran)				_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> -#define  PSR2_MAN_TRK_CTL_ENABLE			REG_BIT(31)
> -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(30, 21)
> -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> +#define _PSR2_MAN_TRK_CTL_A					0x60910
> +#define _PSR2_MAN_TRK_CTL_EDP					0x6f910
> +#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> +#define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
> +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
> +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
>   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(20, 11)
>   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> -#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(3)
> -#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
> -#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
> +#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
> +#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
> +#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
>   
>   /* Icelake DSC Rate Control Range Parameter Registers */
>   #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
> 
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Re: [Intel-gfx] [PATCH 6/6] drm/i915/display/adl_p: Implement PSR changes

[Souza, Jose]

On Wed, 2021-06-23 at 22:06 +0300, Gwan-gyeong Mun wrote:
> On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> > Implements changes around PSR for alderlake-P:
> > 
> > - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> > - Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
> >    removed setting SU_REGION_START/END_ADDR will do this job
> > - SU_REGION_START/END_ADDR have now line granularity but will need to
> >    be aligned with DSC when the PSRS + DSC support lands
> > 
> > BSpec: 50422
> > BSpec: 50424
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
> >   drivers/gpu/drm/i915/i915_reg.h          | 26 ++++++++------
> >   2 files changed, 48 insertions(+), 21 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 9643624fe160d..46bb19c4b63a4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
> >   static void hsw_activate_psr2(struct intel_dp *intel_dp)
> >   {
> >   	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -	u32 val;
> > +	u32 val = EDP_PSR2_ENABLE;
> > +
> > +	val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> >   
> > -	val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> > +	if (!IS_ALDERLAKE_P(dev_priv))
> > +		val |= EDP_SU_TRACK_ENABLE;
> >   
> > -	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> >   	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> >   		val |= EDP_Y_COORDINATE_ENABLE;
> >   
> > @@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> >   static bool psr2_granularity_check(struct intel_dp *intel_dp,
> >   				   struct intel_crtc_state *crtc_state)
> >   {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >   	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> >   	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> >   	u16 y_granularity = 0;
> > @@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
> >   		return intel_dp->psr.su_y_granularity == 4;
> >   
> >   	/*
> > -	 * For SW tracking we can adjust the y to match sink requirement if
> > -	 * multiple of 4
> > +	 * adl_p has 1 line granularity for other platforms with SW tracking we
> > +	 * can adjust the y coordinate to match sink requirement if multiple of
> > +	 * 4
> >   	 */
> > -	if (intel_dp->psr.su_y_granularity <= 2)
> > +	if (IS_ALDERLAKE_P(dev_priv))
> > +		y_granularity = intel_dp->psr.su_y_granularity;
> > +	else if (intel_dp->psr.su_y_granularity <= 2)
> >   		y_granularity = 4;
> >   	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> >   		y_granularity = intel_dp->psr.su_y_granularity;
> > @@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
> >   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> >   				  struct drm_rect *clip, bool full_update)
> >   {
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >   	u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> The logic is not wrong, but the meaning of the register bit has changed.
> The 31st bit in ADL-P means "SF partial frame enable".
> It is recommended to add a macro such as 
> ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE to the code to clarify the 
> role of the changed register.

In my opinion the meaning is the same, enable manual/software tracking.
It was just a register rename done as part of changes of the other bits. 

But if you really think is necessary I can do that, please let me know.

> >   
> >   	if (full_update) {
> > -		val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > +		if (IS_ALDERLAKE_P(dev_priv))
> > +			val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > +		else
> > +			val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > +
> >   		goto exit;
> >   	}
> >   
> >   	if (clip->y1 == -1)
> >   		goto exit;
> >   
> > -	drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> > +	if (IS_ALDERLAKE_P(dev_priv)) {
> > +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> > +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
> > +	} else {
> > +		drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> >   
> > -	val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > -	val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > -	val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > +		val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > +		val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > +		val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > +	}
> >   exit:
> >   	crtc_state->psr2_man_track_ctl = val;
> >   }
> > @@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
> >   static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
> >   						struct drm_rect *pipe_clip)
> >   {
> > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> >   	const u16 y_alignment = crtc_state->su_y_granularity;
> >   
> >   	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
> >   	if (pipe_clip->y2 % y_alignment)
> >   		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
> > +
> > +	if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
> > +		drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
> >   }
> >   
> >   int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e0bd60fe7a190..74dc5ebce60e7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4586,7 +4586,7 @@ enum {
> >   #define _PSR2_CTL_EDP				0x6f900
> >   #define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(tran, _PSR2_CTL_A)
> >   #define   EDP_PSR2_ENABLE			(1 << 31)
> > -#define   EDP_SU_TRACK_ENABLE			(1 << 30)
> > +#define   EDP_SU_TRACK_ENABLE			(1 << 30) /* up to adl-p */
> >   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
> >   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
> >   #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
> > @@ -4655,17 +4655,23 @@ enum {
> >   #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
> >   #define PSR2_SU_STATUS_FRAMES		8
> >   
> > -#define _PSR2_MAN_TRK_CTL_A				0x60910
> > -#define _PSR2_MAN_TRK_CTL_EDP				0x6f910
> > -#define PSR2_MAN_TRK_CTL(tran)				_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > -#define  PSR2_MAN_TRK_CTL_ENABLE			REG_BIT(31)
> > -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(30, 21)
> > -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > +#define _PSR2_MAN_TRK_CTL_A					0x60910
> > +#define _PSR2_MAN_TRK_CTL_EDP					0x6f910
> > +#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > +#define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
> > +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
> > +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> >   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(20, 11)
> >   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > -#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(3)
> > -#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
> > -#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
> > +#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
> > +#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
> > +#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
> > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
> > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
> > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > +#define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
> > +#define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
> >   
> >   /* Icelake DSC Rate Control Range Parameter Registers */
> >   #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
> > 

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Re: [Intel-gfx] [PATCH 6/6] drm/i915/display/adl_p: Implement PSR changes

[Souza, Jose]

On Thu, 2021-06-24 at 09:22 -0700, José Roberto de Souza wrote:
> On Wed, 2021-06-23 at 22:06 +0300, Gwan-gyeong Mun wrote:
> > On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> > > Implements changes around PSR for alderlake-P:
> > > 
> > > - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> > > - Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
> > >    removed setting SU_REGION_START/END_ADDR will do this job
> > > - SU_REGION_START/END_ADDR have now line granularity but will need to
> > >    be aligned with DSC when the PSRS + DSC support lands
> > > 
> > > BSpec: 50422
> > > BSpec: 50424
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
> > >   drivers/gpu/drm/i915/i915_reg.h          | 26 ++++++++------
> > >   2 files changed, 48 insertions(+), 21 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 9643624fe160d..46bb19c4b63a4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
> > >   static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > >   {
> > >   	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > -	u32 val;
> > > +	u32 val = EDP_PSR2_ENABLE;
> > > +
> > > +	val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> > >   
> > > -	val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > +	if (!IS_ALDERLAKE_P(dev_priv))
> > > +		val |= EDP_SU_TRACK_ENABLE;
> > >   
> > > -	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> > >   	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> > >   		val |= EDP_Y_COORDINATE_ENABLE;
> > >   
> > > @@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > >   static bool psr2_granularity_check(struct intel_dp *intel_dp,
> > >   				   struct intel_crtc_state *crtc_state)
> > >   {
> > > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >   	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> > >   	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > >   	u16 y_granularity = 0;
> > > @@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
> > >   		return intel_dp->psr.su_y_granularity == 4;
> > >   
> > >   	/*
> > > -	 * For SW tracking we can adjust the y to match sink requirement if
> > > -	 * multiple of 4
> > > +	 * adl_p has 1 line granularity for other platforms with SW tracking we
> > > +	 * can adjust the y coordinate to match sink requirement if multiple of
> > > +	 * 4
> > >   	 */
> > > -	if (intel_dp->psr.su_y_granularity <= 2)
> > > +	if (IS_ALDERLAKE_P(dev_priv))
> > > +		y_granularity = intel_dp->psr.su_y_granularity;
> > > +	else if (intel_dp->psr.su_y_granularity <= 2)
> > >   		y_granularity = 4;
> > >   	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> > >   		y_granularity = intel_dp->psr.su_y_granularity;
> > > @@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
> > >   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> > >   				  struct drm_rect *clip, bool full_update)
> > >   {
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >   	u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > The logic is not wrong, but the meaning of the register bit has changed.
> > The 31st bit in ADL-P means "SF partial frame enable".
> > It is recommended to add a macro such as 
> > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE to the code to clarify the 
> > role of the changed register.
> 
> In my opinion the meaning is the same, enable manual/software tracking.
> It was just a register rename done as part of changes of the other bits. 
> 
> But if you really think is necessary I can do that, please let me know.

And with or without that can I add your RVB?

> 
> > >   
> > >   	if (full_update) {
> > > -		val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > +		if (IS_ALDERLAKE_P(dev_priv))
> > > +			val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > +		else
> > > +			val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > +
> > >   		goto exit;
> > >   	}
> > >   
> > >   	if (clip->y1 == -1)
> > >   		goto exit;
> > >   
> > > -	drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> > > +	if (IS_ALDERLAKE_P(dev_priv)) {
> > > +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> > > +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
> > > +	} else {
> > > +		drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> > >   
> > > -	val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > -	val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > > -	val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > > +		val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > +		val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > > +		val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > > +	}
> > >   exit:
> > >   	crtc_state->psr2_man_track_ctl = val;
> > >   }
> > > @@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
> > >   static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
> > >   						struct drm_rect *pipe_clip)
> > >   {
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > >   	const u16 y_alignment = crtc_state->su_y_granularity;
> > >   
> > >   	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
> > >   	if (pipe_clip->y2 % y_alignment)
> > >   		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
> > > +
> > > +	if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
> > > +		drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
> > >   }
> > >   
> > >   int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index e0bd60fe7a190..74dc5ebce60e7 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4586,7 +4586,7 @@ enum {
> > >   #define _PSR2_CTL_EDP				0x6f900
> > >   #define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(tran, _PSR2_CTL_A)
> > >   #define   EDP_PSR2_ENABLE			(1 << 31)
> > > -#define   EDP_SU_TRACK_ENABLE			(1 << 30)
> > > +#define   EDP_SU_TRACK_ENABLE			(1 << 30) /* up to adl-p */
> > >   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
> > >   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
> > >   #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
> > > @@ -4655,17 +4655,23 @@ enum {
> > >   #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
> > >   #define PSR2_SU_STATUS_FRAMES		8
> > >   
> > > -#define _PSR2_MAN_TRK_CTL_A				0x60910
> > > -#define _PSR2_MAN_TRK_CTL_EDP				0x6f910
> > > -#define PSR2_MAN_TRK_CTL(tran)				_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > > -#define  PSR2_MAN_TRK_CTL_ENABLE			REG_BIT(31)
> > > -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(30, 21)
> > > -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > > +#define _PSR2_MAN_TRK_CTL_A					0x60910
> > > +#define _PSR2_MAN_TRK_CTL_EDP					0x6f910
> > > +#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > > +#define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
> > > +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
> > > +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > >   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(20, 11)
> > >   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > > -#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(3)
> > > -#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
> > > -#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
> > > +#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
> > > +#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
> > > +#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
> > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
> > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
> > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > > +#define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
> > > +#define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
> > >   
> > >   /* Icelake DSC Rate Control Range Parameter Registers */
> > >   #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
> > > 
> 

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Re: [Intel-gfx] [PATCH 6/6] drm/i915/display/adl_p: Implement PSR changes

[Souza, Jose]

On Thu, 2021-06-24 at 16:19 +0000, Souza, Jose wrote:
> On Thu, 2021-06-24 at 09:22 -0700, José Roberto de Souza wrote:
> > On Wed, 2021-06-23 at 22:06 +0300, Gwan-gyeong Mun wrote:
> > > On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> > > > Implements changes around PSR for alderlake-P:
> > > > 
> > > > - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> > > > - Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
> > > >    removed setting SU_REGION_START/END_ADDR will do this job
> > > > - SU_REGION_START/END_ADDR have now line granularity but will need to
> > > >    be aligned with DSC when the PSRS + DSC support lands
> > > > 
> > > > BSpec: 50422
> > > > BSpec: 50424
> > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > ---
> > > >   drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
> > > >   drivers/gpu/drm/i915/i915_reg.h          | 26 ++++++++------
> > > >   2 files changed, 48 insertions(+), 21 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 9643624fe160d..46bb19c4b63a4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
> > > >   static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > > >   {
> > > >   	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > -	u32 val;
> > > > +	u32 val = EDP_PSR2_ENABLE;
> > > > +
> > > > +	val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > >   
> > > > -	val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > > +	if (!IS_ALDERLAKE_P(dev_priv))
> > > > +		val |= EDP_SU_TRACK_ENABLE;
> > > >   
> > > > -	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> > > >   	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> > > >   		val |= EDP_Y_COORDINATE_ENABLE;
> > > >   
> > > > @@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > >   static bool psr2_granularity_check(struct intel_dp *intel_dp,
> > > >   				   struct intel_crtc_state *crtc_state)
> > > >   {
> > > > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > >   	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> > > >   	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > > >   	u16 y_granularity = 0;
> > > > @@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
> > > >   		return intel_dp->psr.su_y_granularity == 4;
> > > >   
> > > >   	/*
> > > > -	 * For SW tracking we can adjust the y to match sink requirement if
> > > > -	 * multiple of 4
> > > > +	 * adl_p has 1 line granularity for other platforms with SW tracking we
> > > > +	 * can adjust the y coordinate to match sink requirement if multiple of
> > > > +	 * 4
> > > >   	 */
> > > > -	if (intel_dp->psr.su_y_granularity <= 2)
> > > > +	if (IS_ALDERLAKE_P(dev_priv))
> > > > +		y_granularity = intel_dp->psr.su_y_granularity;
> > > > +	else if (intel_dp->psr.su_y_granularity <= 2)
> > > >   		y_granularity = 4;
> > > >   	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> > > >   		y_granularity = intel_dp->psr.su_y_granularity;
> > > > @@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
> > > >   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> > > >   				  struct drm_rect *clip, bool full_update)
> > > >   {
> > > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > >   	u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > > The logic is not wrong, but the meaning of the register bit has changed.
> > > The 31st bit in ADL-P means "SF partial frame enable".
> > > It is recommended to add a macro such as 
> > > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE to the code to clarify the 
> > > role of the changed register.
> > 
> > In my opinion the meaning is the same, enable manual/software tracking.
> > It was just a register rename done as part of changes of the other bits. 
> > 
> > But if you really think is necessary I can do that, please let me know.
> 
> And with or without that can I add your RVB?

I have pushed all the reviewed patches.

Another note about the requested change, we use PSR2_MAN_TRK_CTL_ENABLE in 3 different places.
Add a IS_ALDERLAKE_P() check in each place to use ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE instead of PSR2_MAN_TRK_CTL_ENABLE and both having the
same value looks terrible.

> 
> > 
> > > >   
> > > >   	if (full_update) {
> > > > -		val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > > +		if (IS_ALDERLAKE_P(dev_priv))
> > > > +			val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > > +		else
> > > > +			val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > > +
> > > >   		goto exit;
> > > >   	}
> > > >   
> > > >   	if (clip->y1 == -1)
> > > >   		goto exit;
> > > >   
> > > > -	drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> > > > +	if (IS_ALDERLAKE_P(dev_priv)) {
> > > > +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> > > > +		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
> > > > +	} else {
> > > > +		drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> > > >   
> > > > -	val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > > -	val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > > > -	val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > > > +		val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > > +		val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > > > +		val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > > > +	}
> > > >   exit:
> > > >   	crtc_state->psr2_man_track_ctl = val;
> > > >   }
> > > > @@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
> > > >   static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
> > > >   						struct drm_rect *pipe_clip)
> > > >   {
> > > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > >   	const u16 y_alignment = crtc_state->su_y_granularity;
> > > >   
> > > >   	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
> > > >   	if (pipe_clip->y2 % y_alignment)
> > > >   		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
> > > > +
> > > > +	if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
> > > > +		drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
> > > >   }
> > > >   
> > > >   int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index e0bd60fe7a190..74dc5ebce60e7 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -4586,7 +4586,7 @@ enum {
> > > >   #define _PSR2_CTL_EDP				0x6f900
> > > >   #define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(tran, _PSR2_CTL_A)
> > > >   #define   EDP_PSR2_ENABLE			(1 << 31)
> > > > -#define   EDP_SU_TRACK_ENABLE			(1 << 30)
> > > > +#define   EDP_SU_TRACK_ENABLE			(1 << 30) /* up to adl-p */
> > > >   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
> > > >   #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
> > > >   #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
> > > > @@ -4655,17 +4655,23 @@ enum {
> > > >   #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
> > > >   #define PSR2_SU_STATUS_FRAMES		8
> > > >   
> > > > -#define _PSR2_MAN_TRK_CTL_A				0x60910
> > > > -#define _PSR2_MAN_TRK_CTL_EDP				0x6f910
> > > > -#define PSR2_MAN_TRK_CTL(tran)				_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > > > -#define  PSR2_MAN_TRK_CTL_ENABLE			REG_BIT(31)
> > > > -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(30, 21)
> > > > -#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > > > +#define _PSR2_MAN_TRK_CTL_A					0x60910
> > > > +#define _PSR2_MAN_TRK_CTL_EDP					0x6f910
> > > > +#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > > > +#define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
> > > > +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
> > > > +#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > > >   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(20, 11)
> > > >   #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > > > -#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(3)
> > > > -#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
> > > > -#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
> > > > +#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
> > > > +#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
> > > > +#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
> > > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
> > > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
> > > > +#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > > > +#define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
> > > > +#define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
> > > >   
> > > >   /* Icelake DSC Rate Control Range Parameter Registers */
> > > >   #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
> > > > 
> > 
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity
URL   : https://patchwork.freedesktop.org/series/91594/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
47efae2a069f drm/i915/display/psr: Handle SU Y granularity
a03bc073ba13 drm/i915/display/adl_p: Implement Wa_22012278275
-:66: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/i915_reg.h:4600:
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)

-:74: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/i915_reg.h:4607:
+#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)

total: 0 errors, 2 warnings, 0 checks, 52 lines checked
b08ac7934e09 drm/i915/display/adl_p: Implement Wa_16011168373
b84f76144d24 drm/i915/xelpd: Handle PSR2 SDP indication in the prior scanline
07e0f4c3c72b drm/i915/display/adl_p: Implement Wa_16011303918
4f4308c4b4f7 drm/i915/display/adl_p: Implement PSR changes
-:149: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/i915_reg.h:4660:
+#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)

-:152: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#152: FILE: drivers/gpu/drm/i915/i915_reg.h:4663:
+#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)

-:162: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#162: FILE: drivers/gpu/drm/i915/i915_reg.h:4670:
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)

-:164: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#164: FILE: drivers/gpu/drm/i915/i915_reg.h:4672:
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)

total: 0 errors, 4 warnings, 0 checks, 131 lines checked


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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 3130 bytes --]

== Series Details ==

Series: series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity
URL   : https://patchwork.freedesktop.org/series/91594/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10233 -> Patchwork_20393
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/index.html

Known issues
------------

  Here are the changes found in Patchwork_20393 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [PASS][1] -> [INCOMPLETE][2] ([i915#151] / [i915#2405])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@runner@aborted:
    - fi-bdw-5557u:       NOTRUN -> [FAIL][3] ([i915#1602] / [i915#2029])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/fi-bdw-5557u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - {fi-tgl-dsi}:       [DMESG-WARN][4] ([i915#1982] / [i915#2411]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/fi-tgl-dsi/igt@i915_pm_rpm@module-reload.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/fi-tgl-dsi/igt@i915_pm_rpm@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411


Participating hosts (43 -> 38)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10233 -> Patchwork_20393

  CI-20190529: 20190529
  CI_DRM_10233: e00d16681acd7e91fd02f800adcc20cca89f6127 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6109: 61ba2ed489540e6a8a649be38abb075b3ab4d28a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20393: 4f4308c4b4f7762351a75b05ebed7c48aa00d4fc @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4f4308c4b4f7 drm/i915/display/adl_p: Implement PSR changes
07e0f4c3c72b drm/i915/display/adl_p: Implement Wa_16011303918
b84f76144d24 drm/i915/xelpd: Handle PSR2 SDP indication in the prior scanline
b08ac7934e09 drm/i915/display/adl_p: Implement Wa_16011168373
a03bc073ba13 drm/i915/display/adl_p: Implement Wa_22012278275
47efae2a069f drm/i915/display/psr: Handle SU Y granularity

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/index.html

[-- Attachment #1.2: Type: text/html, Size: 3817 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30295 bytes --]

== Series Details ==

Series: series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity
URL   : https://patchwork.freedesktop.org/series/91594/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10233_full -> Patchwork_20393_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20393_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20393_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20393_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-snb:          NOTRUN -> [TIMEOUT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-snb5/igt@gem_workarounds@suspend-resume-context.html

  
#### Warnings ####

  * igt@gem_exec_reloc@basic-wide-active@vecs0:
    - shard-tglb:         [FAIL][2] ([i915#2389]) -> [DMESG-FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-tglb6/igt@gem_exec_reloc@basic-wide-active@vecs0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-tglb5/igt@gem_exec_reloc@basic-wide-active@vecs0.html

  
Known issues
------------

  Here are the changes found in Patchwork_20393_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_mm@all@insert_range:
    - shard-skl:          NOTRUN -> [INCOMPLETE][4] ([i915#2485])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl7/igt@drm_mm@all@insert_range.html

  * igt@gem_create@create-massive:
    - shard-snb:          NOTRUN -> [DMESG-WARN][5] ([i915#3002])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-snb7/igt@gem_create@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@vcs1:
    - shard-kbl:          [PASS][6] -> [DMESG-WARN][7] ([i915#180])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs1.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs1.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-snb5/igt@gem_ctx_persistence@legacy-engines-mixed.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][9] -> [FAIL][10] ([i915#2410])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_eio@banned:
    - shard-tglb:         [PASS][11] -> [DMESG-WARN][12] ([i915#2868])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-tglb6/igt@gem_eio@banned.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-tglb5/igt@gem_eio@banned.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          NOTRUN -> [FAIL][13] ([i915#2846])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-glk:          [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][16] ([i915#2842])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          NOTRUN -> [FAIL][17] ([i915#2842])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl7/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-iclb:         [PASS][18] -> [FAIL][19] ([i915#2842])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb3/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_gttfill@engines@rcs0:
    - shard-glk:          [PASS][20] -> [DMESG-WARN][21] ([i915#118] / [i915#95]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-glk6/igt@gem_exec_gttfill@engines@rcs0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk9/igt@gem_exec_gttfill@engines@rcs0.html

  * igt@gem_exec_reloc@basic-wide-active@bcs0:
    - shard-apl:          NOTRUN -> [FAIL][22] ([i915#2389]) +3 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl3/igt@gem_exec_reloc@basic-wide-active@bcs0.html

  * igt@gem_mmap_offset@clear:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#3160])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl2/igt@gem_mmap_offset@clear.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl9/igt@gem_mmap_offset@clear.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-kbl:          NOTRUN -> [WARN][25] ([i915#2658]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl4/igt@gem_pwrite@basic-exhaustion.html
    - shard-apl:          NOTRUN -> [WARN][26] ([i915#2658])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl8/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3323])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl3/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-apl:          NOTRUN -> [DMESG-WARN][28] ([i915#3002])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl1/igt@gem_userptr_blits@input-checking.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          NOTRUN -> [INCOMPLETE][29] ([i915#2782])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-snb5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][30] -> [DMESG-WARN][31] ([i915#180]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180:
    - shard-skl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111304]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl6/igt@kms_ccs@pipe-c-crc-primary-rotation-180.html

  * igt@kms_chamelium@vga-hpd:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +17 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl3/igt@kms_chamelium@vga-hpd.html

  * igt@kms_color_chamelium@pipe-a-ctm-max:
    - shard-glk:          NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk9/igt@kms_color_chamelium@pipe-a-ctm-max.html

  * igt@kms_color_chamelium@pipe-a-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl3/igt@kms_color_chamelium@pipe-a-degamma.html

  * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
    - shard-snb:          NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-snb5/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-d-degamma:
    - shard-skl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl4/igt@kms_color_chamelium@pipe-d-degamma.html

  * igt@kms_content_protection@legacy:
    - shard-glk:          NOTRUN -> [SKIP][38] ([fdo#109271]) +18 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk9/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
    - shard-skl:          NOTRUN -> [SKIP][39] ([fdo#109271]) +109 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][40] -> [FAIL][41] ([i915#2346])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-kbl:          NOTRUN -> [SKIP][42] ([fdo#109271]) +67 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl3/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [PASS][43] -> [FAIL][44] ([i915#2122])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-glk:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#2642])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-snb:          NOTRUN -> [SKIP][46] ([fdo#109271]) +222 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - shard-skl:          [PASS][47] -> [FAIL][48] ([i915#49])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl3/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
    - shard-kbl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl4/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][52] ([i915#180])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
    - shard-skl:          NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +1 similar issue
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][57] ([i915#265]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#658]) +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
    - shard-skl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][61] -> [SKIP][62] ([fdo#109441]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-d-wait-forked-hang:
    - shard-apl:          NOTRUN -> [SKIP][63] ([fdo#109271]) +214 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl6/igt@kms_vblank@pipe-d-wait-forked-hang.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-skl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2437])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl1/igt@kms_writeback@writeback-invalid-parameters.html
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2437])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl6/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [PASS][66] -> [FAIL][67] ([i915#1722])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl6/igt@perf@polling-small-buf.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl3/igt@perf@polling-small-buf.html

  * igt@sysfs_clients@fair-0:
    - shard-skl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2994]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl4/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@fair-1:
    - shard-apl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2994]) +3 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl3/igt@sysfs_clients@fair-1.html

  * igt@sysfs_clients@fair-7:
    - shard-kbl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl7/igt@sysfs_clients@fair-7.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-skl:          [INCOMPLETE][71] ([i915#198]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl8/igt@gem_ctx_isolation@preservation-s3@vecs0.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl6/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][73] ([i915#2842]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-kbl:          [FAIL][75] ([i915#2842]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [FAIL][77] ([i915#2842]) -> [PASS][78] +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][79] ([i915#2849]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_parallel@engines@basic:
    - shard-glk:          [DMESG-WARN][81] ([i915#118] / [i915#95]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-glk2/igt@gem_exec_parallel@engines@basic.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk5/igt@gem_exec_parallel@engines@basic.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][83] ([i915#2190]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-tglb5/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@big-copy:
    - shard-skl:          [FAIL][85] ([i915#307]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl1/igt@gem_mmap_gtt@big-copy.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl4/igt@gem_mmap_gtt@big-copy.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
    - shard-iclb:         [FAIL][87] ([i915#307]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb2/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy-xy.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [FAIL][89] ([i915#644]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [DMESG-WARN][91] ([i915#1436] / [i915#716]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-glk3/igt@gen9_exec_parse@allowed-all.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk9/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][93] ([i915#454]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb3/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][95] ([i915#180]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [INCOMPLETE][97] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][99] ([i915#79]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
    - shard-kbl:          [FAIL][101] ([i915#79]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
    - shard-tglb:         [DMESG-WARN][103] ([i915#2868]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][105] ([i915#1188]) -> [PASS][106] +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-kbl:          [DMESG-WARN][107] ([i915#180]) -> [PASS][108] +5 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][109] ([fdo#108145] / [i915#265]) -> [PASS][110] +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][111] ([fdo#109441]) -> [PASS][112] +3 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][113] ([i915#180] / [i915#295]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][115] ([i915#1804] / [i915#2684]) -> [WARN][116] ([i915#2684])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][117] ([i915#2684]) -> [WARN][118] ([i915#1804] / [i915#2684])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][119] ([i915#658]) -> [SKIP][120] ([i915#2920]) +2 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-iclb:         [SKIP][121] ([i915#2920]) -> [SKIP][122] ([i915#658]) +2 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92]) -> ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl1/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl1/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl2/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl2/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl1/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl7/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl7/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl2/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl1/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl7/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-kbl4/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl7/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl7/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl6/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl1/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl2/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl2/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-kbl1/igt@runner@aborted.html
    - shard-apl:          ([FAIL][142], [FAIL][143]) ([i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][144], [FAIL][145], [FAIL][146]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-apl1/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10233/shard-apl3/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl6/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl1/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/shard-apl8/igt@runner@aborted.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.f

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20393/index.html

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Re: [Intel-gfx] [PATCH 1/6] drm/i915/display/psr: Handle SU Y granularity

[Gwan-gyeong Mun]

looks good to me.

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> We were only handling X and width granularity, what was causing issues
> when sink had a granularity different than 4.
> 
> While at it, renaming su_x_granularity to su_w_granularity to better
> match reality.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>   .../drm/i915/display/intel_display_types.h    |   4 +-
>   drivers/gpu/drm/i915/display/intel_psr.c      | 110 ++++++++++++------
>   2 files changed, 80 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 15e91a99c8b9a..f89152ca52a20 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1041,6 +1041,7 @@ struct intel_crtc_state {
>   	bool has_psr2;
>   	bool enable_psr2_sel_fetch;
>   	u32 dc3co_exitline;
> +	u16 su_y_granularity;
>   
>   	/*
>   	 * Frequence the dpll for the port should run at. Differs from the
> @@ -1498,7 +1499,8 @@ struct intel_psr {
>   	ktime_t last_exit;
>   	bool sink_not_reliable;
>   	bool irq_aux_error;
> -	u16 su_x_granularity;
> +	u16 su_w_granularity;
> +	u16 su_y_granularity;
>   	u32 dc3co_exitline;
>   	u32 dc3co_exit_delay;
>   	struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 77865cf6641f8..fde30f937504e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -265,32 +265,44 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
>   	return val;
>   }
>   
> -static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
> +static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
>   {
>   	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> -	u16 val;
>   	ssize_t r;
> +	u16 w;
> +	u8 y;
> +
> +	/* If sink don't have specific granularity requirements set legacy ones */
> +	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> +		/* As PSR2 HW sends full lines, we do not care about x granularity */
> +		w = 4;
> +		y = 4;
> +		goto exit;
> +	}
>   
> -	/*
> -	 * Returning the default X granularity if granularity not required or
> -	 * if DPCD read fails
> -	 */
> -	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
> -		return 4;
> -
> -	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
> +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
>   	if (r != 2)
>   		drm_dbg_kms(&i915->drm,
>   			    "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
> -
>   	/*
>   	 * Spec says that if the value read is 0 the default granularity should
>   	 * be used instead.
>   	 */
> -	if (r != 2 || val == 0)
> -		val = 4;
> +	if (r != 2 || w == 0)
> +		w = 4;
>   
> -	return val;
> +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
> +	if (r != 1) {
> +		drm_dbg_kms(&i915->drm,
> +			    "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
> +		y = 4;
> +	}
> +	if (y == 0)
> +		y = 1;
> +
> +exit:
> +	intel_dp->psr.su_w_granularity = w;
> +	intel_dp->psr.su_y_granularity = y;
>   }
>   
>   void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> @@ -346,8 +358,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>   		if (intel_dp->psr.sink_psr2_support) {
>   			intel_dp->psr.colorimetry_support =
>   				intel_dp_get_colorimetry_status(intel_dp);
> -			intel_dp->psr.su_x_granularity =
> -				intel_dp_get_su_x_granulartiy(intel_dp);
> +			intel_dp_get_su_granularity(intel_dp);
>   		}
>   	}
>   }
> @@ -742,6 +753,40 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>   	return crtc_state->enable_psr2_sel_fetch = true;
>   }
>   
> +static bool psr2_granularity_check(struct intel_dp *intel_dp,
> +				   struct intel_crtc_state *crtc_state)
> +{
> +	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> +	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> +	u16 y_granularity = 0;
> +
> +	/* PSR2 HW only send full lines so we only need to validate the width */
> +	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
> +		return false;
> +
> +	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
> +		return false;
> +
> +	/* HW tracking is only aligned to 4 lines */
> +	if (!crtc_state->enable_psr2_sel_fetch)
> +		return intel_dp->psr.su_y_granularity == 4;
> +
> +	/*
> +	 * For SW tracking we can adjust the y to match sink requirement if
> +	 * multiple of 4
> +	 */
> +	if (intel_dp->psr.su_y_granularity <= 2)
> +		y_granularity = 4;
> +	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> +		y_granularity = intel_dp->psr.su_y_granularity;
> +
> +	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
> +		return false;
> +
> +	crtc_state->su_y_granularity = y_granularity;
> +	return true;
> +}
> +
>   static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>   				    struct intel_crtc_state *crtc_state)
>   {
> @@ -824,19 +869,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>   		return false;
>   	}
>   
> -	/*
> -	 * HW sends SU blocks of size four scan lines, which means the starting
> -	 * X coordinate and Y granularity requirements will always be met. We
> -	 * only need to validate the SU block width is a multiple of
> -	 * x granularity.
> -	 */
> -	if (crtc_hdisplay % intel_dp->psr.su_x_granularity) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
> -			    crtc_hdisplay, intel_dp->psr.su_x_granularity);
> -		return false;
> -	}
> -
>   	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
>   		if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
>   		    !HAS_PSR_HW_TRACKING(dev_priv)) {
> @@ -853,6 +885,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>   		return false;
>   	}
>   
> +	if (!psr2_granularity_check(intel_dp, crtc_state)) {
> +		drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
> +		return false;
> +	}
> +
>   	if (!crtc_state->enable_psr2_sel_fetch &&
>   	    (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
>   		drm_dbg_kms(&dev_priv->drm,
> @@ -1432,6 +1469,16 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
>   		overlap_damage_area->y2 = damage_area->y2;
>   }
>   
> +static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
> +						struct drm_rect *pipe_clip)
> +{
> +	const u16 y_alignment = crtc_state->su_y_granularity;
> +
> +	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
> +	if (pipe_clip->y2 % y_alignment)
> +		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
> +}
> +
>   int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   				struct intel_crtc *crtc)
>   {
> @@ -1540,10 +1587,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   	if (full_update)
>   		goto skip_sel_fetch_set_loop;
>   
> -	/* It must be aligned to 4 lines */
> -	pipe_clip.y1 -= pipe_clip.y1 % 4;
> -	if (pipe_clip.y2 % 4)
> -		pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4;
> +	intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
>   
>   	/*
>   	 * Now that we have the pipe damaged area check if it intersect with
> 
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