Re: [PATCH v2 1/2] arm64: errata: Remove AES hwcap for COMPAT tasks

[James Morse <james.morse@arm.com>]

Hi Ard,

On 13/04/2022 18:33, Ard Biesheuvel wrote:
> On Wed, 13 Apr 2022 at 19:06, James Morse <james.morse@arm.com> wrote:
>>
>> Cortex-A57 and Cortex-A72 have an erratum where an interrupt that
>> occurs between a pair of AES instructions in aarch32 mode may corrupt
>> the ELR. The task will subsequently produce the wrong AES result.
>>
>> The AES instructions are part of the cryptographic extensions, which are
>> optional. User-space software will detect the support for these
>> instructions from the hwcaps. If the platform doesn't support these
>> instructions a software implementation should be used.
>>
>> Remove the hwcap bits on affected parts to indicate user-space should
>> not use the AES instructions.
>>
>> Signed-off-by: James Morse <james.morse@arm.com>
> 
> Acked-by: Ard Biesheuvel <ardb@kernel.org>

Thanks!

> One nit/question below,


>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
>> index 4c9b5b4b7a0b..8f85dac4cd79 100644
>> --- a/arch/arm64/kernel/cpu_errata.c
>> +++ b/arch/arm64/kernel/cpu_errata.c
>> @@ -393,6 +393,14 @@ static struct midr_range trbe_write_out_of_range_cpus[] = {
>>  };
>>  #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
>>
>> +#ifdef CONFIG_ARM64_ERRATUM_1742098
>> +static struct midr_range broken_aarch32_aes[] = {
>> +       MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

> Not sure it matters, but are you sure early A57 is affected as well?

That's what I remember reading last time too - but this is what the errata document on
developer.arm.com says. It's something I'm chasing up...


Thanks,

James

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