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From: Zhenyu Ye <yezhenyu2@huawei.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: <peterz@infradead.org>, <mark.rutland@arm.com>, <will@kernel.org>,
	<aneesh.kumar@linux.ibm.com>, <akpm@linux-foundation.org>,
	<npiggin@gmail.com>, <arnd@arndb.de>, <rostedt@goodmis.org>,
	<maz@kernel.org>, <suzuki.poulose@arm.com>, <tglx@linutronix.de>,
	<yuzhao@google.com>, <Dave.Martin@arm.com>,
	<steven.price@arm.com>, <broonie@kernel.org>,
	<guohanjun@huawei.com>, <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
	<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
	<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>,
	<kuhn.chenqun@huawei.com>
Subject: Re: [RESEND PATCH v5 3/6] arm64: Add tlbi_user_level TLB invalidation helper
Date: Fri, 10 Jul 2020 09:20:59 +0800	[thread overview]
Message-ID: <33a5dc75-8209-e198-bb41-8b4ab82c000e@huawei.com> (raw)
In-Reply-To: <20200709164845.GB6579@gaia>

Hi Catalin,

On 2020/7/10 0:48, Catalin Marinas wrote:
> On Thu, Jun 25, 2020 at 04:03:11PM +0800, Zhenyu Ye wrote:
>> @@ -189,8 +195,9 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
>>  	unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
>>  
>>  	dsb(ishst);
>> -	__tlbi(vale1is, addr);
>> -	__tlbi_user(vale1is, addr);
>> +	/* This function is only called on a small page */
>> +	__tlbi_level(vale1is, addr, 3);
>> +	__tlbi_user_level(vale1is, addr, 3);
>>  }
> 
> Actually, that's incorrect. It was ok in v2 of your patches when I
> suggested to drop level 0, just leave the function unchanged but I
> missed that you updated it to pass level 3.
> 
> pmdp_set_access_flags -> ptep_set_access_flags ->
> flush_tlb_fix_spurious_fault -> flush_tlb_page -> flush_tlb_page_nosync.

How do you want to fix this error? I notice that this series have been applied
to arm64 (for-next/tlbi).  Should I send a new series based on arm64 (for-next/tlbi)?

Thanks,
Zhenyu


WARNING: multiple messages have this Message-ID (diff)
From: Zhenyu Ye <yezhenyu2@huawei.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: peterz@infradead.org, mark.rutland@arm.com, will@kernel.org,
	aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org,
	npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org,
	maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de,
	yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com,
	broonie@kernel.org, guohanjun@huawei.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-mm@kvack.org, arm@kernel.org, xiexiangyou@huawei.com,
	prime.zeng@hisilicon.com, zhangshaokun@hisilicon.com,
	kuhn.chenqun@huawei.com
Subject: Re: [RESEND PATCH v5 3/6] arm64: Add tlbi_user_level TLB invalidation helper
Date: Fri, 10 Jul 2020 09:20:59 +0800	[thread overview]
Message-ID: <33a5dc75-8209-e198-bb41-8b4ab82c000e@huawei.com> (raw)
In-Reply-To: <20200709164845.GB6579@gaia>

Hi Catalin,

On 2020/7/10 0:48, Catalin Marinas wrote:
> On Thu, Jun 25, 2020 at 04:03:11PM +0800, Zhenyu Ye wrote:
>> @@ -189,8 +195,9 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
>>  	unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
>>  
>>  	dsb(ishst);
>> -	__tlbi(vale1is, addr);
>> -	__tlbi_user(vale1is, addr);
>> +	/* This function is only called on a small page */
>> +	__tlbi_level(vale1is, addr, 3);
>> +	__tlbi_user_level(vale1is, addr, 3);
>>  }
> 
> Actually, that's incorrect. It was ok in v2 of your patches when I
> suggested to drop level 0, just leave the function unchanged but I
> missed that you updated it to pass level 3.
> 
> pmdp_set_access_flags -> ptep_set_access_flags ->
> flush_tlb_fix_spurious_fault -> flush_tlb_page -> flush_tlb_page_nosync.

How do you want to fix this error? I notice that this series have been applied
to arm64 (for-next/tlbi).  Should I send a new series based on arm64 (for-next/tlbi)?

Thanks,
Zhenyu

WARNING: multiple messages have this Message-ID (diff)
From: Zhenyu Ye <yezhenyu2@huawei.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: mark.rutland@arm.com, peterz@infradead.org, linux-mm@kvack.org,
	guohanjun@huawei.com, will@kernel.org,
	linux-arch@vger.kernel.org, yuzhao@google.com,
	aneesh.kumar@linux.ibm.com, steven.price@arm.com, arm@kernel.org,
	Dave.Martin@arm.com, arnd@arndb.de, suzuki.poulose@arm.com,
	npiggin@gmail.com, zhangshaokun@hisilicon.com,
	broonie@kernel.org, rostedt@goodmis.org,
	prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com,
	tglx@linutronix.de, linux-arm-kernel@lists.infradead.org,
	xiexiangyou@huawei.com, linux-kernel@vger.kernel.org,
	maz@kernel.org, akpm@linux-foundation.org
Subject: Re: [RESEND PATCH v5 3/6] arm64: Add tlbi_user_level TLB invalidation helper
Date: Fri, 10 Jul 2020 09:20:59 +0800	[thread overview]
Message-ID: <33a5dc75-8209-e198-bb41-8b4ab82c000e@huawei.com> (raw)
In-Reply-To: <20200709164845.GB6579@gaia>

Hi Catalin,

On 2020/7/10 0:48, Catalin Marinas wrote:
> On Thu, Jun 25, 2020 at 04:03:11PM +0800, Zhenyu Ye wrote:
>> @@ -189,8 +195,9 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
>>  	unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
>>  
>>  	dsb(ishst);
>> -	__tlbi(vale1is, addr);
>> -	__tlbi_user(vale1is, addr);
>> +	/* This function is only called on a small page */
>> +	__tlbi_level(vale1is, addr, 3);
>> +	__tlbi_user_level(vale1is, addr, 3);
>>  }
> 
> Actually, that's incorrect. It was ok in v2 of your patches when I
> suggested to drop level 0, just leave the function unchanged but I
> missed that you updated it to pass level 3.
> 
> pmdp_set_access_flags -> ptep_set_access_flags ->
> flush_tlb_fix_spurious_fault -> flush_tlb_page -> flush_tlb_page_nosync.

How do you want to fix this error? I notice that this series have been applied
to arm64 (for-next/tlbi).  Should I send a new series based on arm64 (for-next/tlbi)?

Thanks,
Zhenyu


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-07-10  1:21 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-25  8:03 [RESEND PATCH v5 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-06-25  8:03 ` Zhenyu Ye
2020-06-25  8:03 ` Zhenyu Ye
2020-06-25  8:03 ` [RESEND PATCH v5 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03 ` [RESEND PATCH v5 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03 ` [RESEND PATCH v5 3/6] arm64: Add tlbi_user_level " Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-07-09 16:48   ` Catalin Marinas
2020-07-09 16:48     ` Catalin Marinas
2020-07-10  1:20     ` Zhenyu Ye [this message]
2020-07-10  1:20       ` Zhenyu Ye
2020-07-10  1:20       ` Zhenyu Ye
2020-07-10  8:53       ` Catalin Marinas
2020-07-10  8:53         ` Catalin Marinas
2020-06-25  8:03 ` [RESEND PATCH v5 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03 ` [RESEND PATCH v5 5/6] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03 ` [RESEND PATCH v5 6/6] arm64: tlb: Set the TTL field in flush_*_tlb_range Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-06-25  8:03   ` Zhenyu Ye
2020-07-07 13:49 ` [RESEND PATCH v5 0/6] arm64: tlb: add support for TTL feature Catalin Marinas

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