* [PATCH v5 0/8] soc: mediatek: MT8365 power support
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
Hi,
Thanks for the feedback of last round. As requested I replaced all hex
values with defines and redesigned the data format and regmap passing.
Thanks for any feedback!
Best,
Markus
Based on v6.4-rc1
Changes in v5:
- Create defines for all registers and bits in mt8365 power domain patch
- Redesign scpsys_bus_prot_data to use flags to store reg_update,
clr_ack as well as the difference between SMI and INFRACFG. The code
uses the appropriate regmap depending on the flags.
- The WAY_EN patch now uses two flags, one for inverted operations
'BUS_PROT_INVERTED' and one to use infracfg-nao for the status flags
'BUS_PROT_STA_COMPONENT_INFRA_NAO'.
Changes in v4:
- Redesigned WAY_EN patch and split it up in smaller patches.
- Added two documentation patches.
- Added mediatek,infracfg-nao field to the binding.
Changes in v3:
- Mainly redesigned WAY_EN patch to be easier to understand
- Rebased onto v6.0-rc1
- Several other stuff that is described in the individual patches
Changes in v2:
- Updated error handling path for scpsys_power_on()
- Minor updates described in each patch
Previous versions:
v1 - https://lore.kernel.org/linux-mediatek/20220530204214.913251-1-fparent@baylibre.com/
v2 - https://lore.kernel.org/linux-mediatek/20220725081853.1636444-1-msp@baylibre.com/
v3 - https://lore.kernel.org/linux-mediatek/20220822144303.3438467-1-msp@baylibre.com/
v4 - https://lore.kernel.org/linux-arm-kernel/20230105170735.1637416-1-msp@baylibre.com/
Alexandre Bailon (2):
soc: mediatek: Add support for WAY_EN operations
soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap
Fabien Parent (2):
dt-bindings: power: Add MT8365 power domains
soc: mediatek: pm-domains: Add support for MT8365
Markus Schneider-Pargmann (4):
soc: mediatek: pm-domains: Move bools to a flags field
soc: mediatek: pm-domains: Split bus_prot_mask
soc: mediatek: pm-domains: Create bus protection operation functions
soc: mediatek: pm-domains: Unify configuration for infracfg and smi
.../power/mediatek,power-controller.yaml | 6 +
drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8183-pm-domains.h | 198 +++----
drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++----
drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++---------
drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++-----
drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++--------
drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++
drivers/soc/mediatek/mtk-pm-domains.c | 157 ++++--
drivers/soc/mediatek/mtk-pm-domains.h | 60 +-
.../dt-bindings/power/mediatek,mt8365-power.h | 19 +
include/linux/soc/mediatek/infracfg.h | 41 ++
14 files changed, 1267 insertions(+), 919 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 0/8] soc: mediatek: MT8365 power support
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
Hi,
Thanks for the feedback of last round. As requested I replaced all hex
values with defines and redesigned the data format and regmap passing.
Thanks for any feedback!
Best,
Markus
Based on v6.4-rc1
Changes in v5:
- Create defines for all registers and bits in mt8365 power domain patch
- Redesign scpsys_bus_prot_data to use flags to store reg_update,
clr_ack as well as the difference between SMI and INFRACFG. The code
uses the appropriate regmap depending on the flags.
- The WAY_EN patch now uses two flags, one for inverted operations
'BUS_PROT_INVERTED' and one to use infracfg-nao for the status flags
'BUS_PROT_STA_COMPONENT_INFRA_NAO'.
Changes in v4:
- Redesigned WAY_EN patch and split it up in smaller patches.
- Added two documentation patches.
- Added mediatek,infracfg-nao field to the binding.
Changes in v3:
- Mainly redesigned WAY_EN patch to be easier to understand
- Rebased onto v6.0-rc1
- Several other stuff that is described in the individual patches
Changes in v2:
- Updated error handling path for scpsys_power_on()
- Minor updates described in each patch
Previous versions:
v1 - https://lore.kernel.org/linux-mediatek/20220530204214.913251-1-fparent@baylibre.com/
v2 - https://lore.kernel.org/linux-mediatek/20220725081853.1636444-1-msp@baylibre.com/
v3 - https://lore.kernel.org/linux-mediatek/20220822144303.3438467-1-msp@baylibre.com/
v4 - https://lore.kernel.org/linux-arm-kernel/20230105170735.1637416-1-msp@baylibre.com/
Alexandre Bailon (2):
soc: mediatek: Add support for WAY_EN operations
soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap
Fabien Parent (2):
dt-bindings: power: Add MT8365 power domains
soc: mediatek: pm-domains: Add support for MT8365
Markus Schneider-Pargmann (4):
soc: mediatek: pm-domains: Move bools to a flags field
soc: mediatek: pm-domains: Split bus_prot_mask
soc: mediatek: pm-domains: Create bus protection operation functions
soc: mediatek: pm-domains: Unify configuration for infracfg and smi
.../power/mediatek,power-controller.yaml | 6 +
drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8183-pm-domains.h | 198 +++----
drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++----
drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++---------
drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++-----
drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++--------
drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++
drivers/soc/mediatek/mtk-pm-domains.c | 157 ++++--
drivers/soc/mediatek/mtk-pm-domains.h | 60 +-
.../dt-bindings/power/mediatek,mt8365-power.h | 19 +
include/linux/soc/mediatek/infracfg.h | 41 ++
14 files changed, 1267 insertions(+), 919 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h
--
2.40.1
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 1/8] dt-bindings: power: Add MT8365 power domains
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Fabien Parent, Markus Schneider-Pargmann,
Krzysztof Kozlowski, Rob Herring
From: Fabien Parent <fparent@baylibre.com>
Add power domains dt-bindings for MT8365.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../power/mediatek,power-controller.yaml | 6 ++++++
.../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++
2 files changed, 25 insertions(+)
create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index c9acef80f452..8985e2df8a56 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt8188-power-controller
- mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
+ - mediatek,mt8365-power-controller
'#power-domain-cells':
const: 1
@@ -88,6 +89,7 @@ $defs:
"include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
+ "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
maxItems: 1
clocks:
@@ -115,6 +117,10 @@ $defs:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the INFRACFG register range.
+ mediatek,infracfg-nao:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the INFRACFG-NAO register range.
+
mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the SMI register range.
diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h
new file mode 100644
index 000000000000..e6cfd0ec7871
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8365-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
+#define _DT_BINDINGS_POWER_MT8365_POWER_H
+
+#define MT8365_POWER_DOMAIN_MM 0
+#define MT8365_POWER_DOMAIN_CONN 1
+#define MT8365_POWER_DOMAIN_MFG 2
+#define MT8365_POWER_DOMAIN_AUDIO 3
+#define MT8365_POWER_DOMAIN_CAM 4
+#define MT8365_POWER_DOMAIN_DSP 5
+#define MT8365_POWER_DOMAIN_VDEC 6
+#define MT8365_POWER_DOMAIN_VENC 7
+#define MT8365_POWER_DOMAIN_APU 8
+
+#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 1/8] dt-bindings: power: Add MT8365 power domains
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Fabien Parent, Markus Schneider-Pargmann,
Krzysztof Kozlowski, Rob Herring
From: Fabien Parent <fparent@baylibre.com>
Add power domains dt-bindings for MT8365.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../power/mediatek,power-controller.yaml | 6 ++++++
.../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++
2 files changed, 25 insertions(+)
create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index c9acef80f452..8985e2df8a56 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt8188-power-controller
- mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
+ - mediatek,mt8365-power-controller
'#power-domain-cells':
const: 1
@@ -88,6 +89,7 @@ $defs:
"include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
+ "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
maxItems: 1
clocks:
@@ -115,6 +117,10 @@ $defs:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the INFRACFG register range.
+ mediatek,infracfg-nao:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the INFRACFG-NAO register range.
+
mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the SMI register range.
diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h
new file mode 100644
index 000000000000..e6cfd0ec7871
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8365-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
+#define _DT_BINDINGS_POWER_MT8365_POWER_H
+
+#define MT8365_POWER_DOMAIN_MM 0
+#define MT8365_POWER_DOMAIN_CONN 1
+#define MT8365_POWER_DOMAIN_MFG 2
+#define MT8365_POWER_DOMAIN_AUDIO 3
+#define MT8365_POWER_DOMAIN_CAM 4
+#define MT8365_POWER_DOMAIN_DSP 5
+#define MT8365_POWER_DOMAIN_VDEC 6
+#define MT8365_POWER_DOMAIN_VENC 7
+#define MT8365_POWER_DOMAIN_APU 8
+
+#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
To simplify the macros, use a flags field for simple bools. This is in
preparation for more flags.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 6 +++---
drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++--------
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 354249cc1b12..aa9ab413479e 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
if (!mask)
break;
- if (bpd[i].bus_prot_reg_update)
+ if (bpd[i].flags & BUS_PROT_REG_UPDATE)
regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
else
regmap_write(regmap, bpd[i].bus_prot_set, mask);
@@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
if (!mask)
continue;
- if (bpd[i].bus_prot_reg_update)
+ if (bpd[i].flags & BUS_PROT_REG_UPDATE)
regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
else
regmap_write(regmap, bpd[i].bus_prot_clr, mask);
- if (bpd[i].ignore_clr_ack)
+ if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
continue;
ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 5ec53ee073c4..e26c8c317a6b 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -42,23 +42,27 @@
#define SPM_MAX_BUS_PROT_DATA 6
-#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
+enum scpsys_bus_prot_flags {
+ BUS_PROT_REG_UPDATE = BIT(1),
+ BUS_PROT_IGNORE_CLR_ACK = BIT(2),
+};
+
+#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
.bus_prot_mask = (_mask), \
.bus_prot_set = _set, \
.bus_prot_clr = _clr, \
.bus_prot_sta = _sta, \
- .bus_prot_reg_update = _update, \
- .ignore_clr_ack = _ignore, \
+ .flags = _flags \
}
#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, false, false)
+ _BUS_PROT(_mask, _set, _clr, _sta, 0)
#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, false, true)
+ _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, true, false)
+ _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
#define BUS_PROT_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(_mask, \
@@ -71,8 +75,7 @@ struct scpsys_bus_prot_data {
u32 bus_prot_set;
u32 bus_prot_clr;
u32 bus_prot_sta;
- bool bus_prot_reg_update;
- bool ignore_clr_ack;
+ u32 flags;
};
/**
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
To simplify the macros, use a flags field for simple bools. This is in
preparation for more flags.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 6 +++---
drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++--------
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 354249cc1b12..aa9ab413479e 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
if (!mask)
break;
- if (bpd[i].bus_prot_reg_update)
+ if (bpd[i].flags & BUS_PROT_REG_UPDATE)
regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
else
regmap_write(regmap, bpd[i].bus_prot_set, mask);
@@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
if (!mask)
continue;
- if (bpd[i].bus_prot_reg_update)
+ if (bpd[i].flags & BUS_PROT_REG_UPDATE)
regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
else
regmap_write(regmap, bpd[i].bus_prot_clr, mask);
- if (bpd[i].ignore_clr_ack)
+ if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
continue;
ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 5ec53ee073c4..e26c8c317a6b 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -42,23 +42,27 @@
#define SPM_MAX_BUS_PROT_DATA 6
-#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
+enum scpsys_bus_prot_flags {
+ BUS_PROT_REG_UPDATE = BIT(1),
+ BUS_PROT_IGNORE_CLR_ACK = BIT(2),
+};
+
+#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
.bus_prot_mask = (_mask), \
.bus_prot_set = _set, \
.bus_prot_clr = _clr, \
.bus_prot_sta = _sta, \
- .bus_prot_reg_update = _update, \
- .ignore_clr_ack = _ignore, \
+ .flags = _flags \
}
#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, false, false)
+ _BUS_PROT(_mask, _set, _clr, _sta, 0)
#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, false, true)
+ _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, true, false)
+ _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
#define BUS_PROT_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(_mask, \
@@ -71,8 +75,7 @@ struct scpsys_bus_prot_data {
u32 bus_prot_set;
u32 bus_prot_clr;
u32 bus_prot_sta;
- bool bus_prot_reg_update;
- bool ignore_clr_ack;
+ u32 flags;
};
/**
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 3/8] soc: mediatek: pm-domains: Split bus_prot_mask
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
bus_prot_mask is used for all operations, set clear and acknowledge. In
preparation of m8365 power domain support split this one mask into two,
one mask for set and clear, another one for acknowledge.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 24 ++++++++++++++----------
drivers/soc/mediatek/mtk-pm-domains.h | 14 ++++++++------
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index aa9ab413479e..c801fa763e89 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -123,18 +123,20 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
int i, ret;
for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
- u32 val, mask = bpd[i].bus_prot_mask;
+ u32 val;
+ u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
+ u32 sta_mask = bpd[i].bus_prot_sta_mask;
- if (!mask)
+ if (!set_clr_mask)
break;
if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
+ regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask);
else
- regmap_write(regmap, bpd[i].bus_prot_set, mask);
+ regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask);
ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, (val & mask) == mask,
+ val, (val & sta_mask) == sta_mask,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
if (ret)
return ret;
@@ -160,21 +162,23 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
int i, ret;
for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
- u32 val, mask = bpd[i].bus_prot_mask;
+ u32 val;
+ u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
+ u32 sta_mask = bpd[i].bus_prot_sta_mask;
- if (!mask)
+ if (!set_clr_mask)
continue;
if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
+ regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask);
else
- regmap_write(regmap, bpd[i].bus_prot_clr, mask);
+ regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask);
if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
continue;
ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, !(val & mask),
+ val, !(val & sta_mask),
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
if (ret)
return ret;
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index e26c8c317a6b..4b6ae56e7c95 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -47,22 +47,23 @@ enum scpsys_bus_prot_flags {
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
};
-#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
- .bus_prot_mask = (_mask), \
+#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
+ .bus_prot_set_clr_mask = (_set_clr_mask), \
.bus_prot_set = _set, \
.bus_prot_clr = _clr, \
+ .bus_prot_sta_mask = (_sta_mask), \
.bus_prot_sta = _sta, \
.flags = _flags \
}
#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, 0)
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
#define BUS_PROT_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(_mask, \
@@ -71,9 +72,10 @@ enum scpsys_bus_prot_flags {
INFRA_TOPAXI_PROTECTSTA1)
struct scpsys_bus_prot_data {
- u32 bus_prot_mask;
+ u32 bus_prot_set_clr_mask;
u32 bus_prot_set;
u32 bus_prot_clr;
+ u32 bus_prot_sta_mask;
u32 bus_prot_sta;
u32 flags;
};
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 3/8] soc: mediatek: pm-domains: Split bus_prot_mask
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
bus_prot_mask is used for all operations, set clear and acknowledge. In
preparation of m8365 power domain support split this one mask into two,
one mask for set and clear, another one for acknowledge.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 24 ++++++++++++++----------
drivers/soc/mediatek/mtk-pm-domains.h | 14 ++++++++------
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index aa9ab413479e..c801fa763e89 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -123,18 +123,20 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
int i, ret;
for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
- u32 val, mask = bpd[i].bus_prot_mask;
+ u32 val;
+ u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
+ u32 sta_mask = bpd[i].bus_prot_sta_mask;
- if (!mask)
+ if (!set_clr_mask)
break;
if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
+ regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask);
else
- regmap_write(regmap, bpd[i].bus_prot_set, mask);
+ regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask);
ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, (val & mask) == mask,
+ val, (val & sta_mask) == sta_mask,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
if (ret)
return ret;
@@ -160,21 +162,23 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
int i, ret;
for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
- u32 val, mask = bpd[i].bus_prot_mask;
+ u32 val;
+ u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
+ u32 sta_mask = bpd[i].bus_prot_sta_mask;
- if (!mask)
+ if (!set_clr_mask)
continue;
if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
+ regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask);
else
- regmap_write(regmap, bpd[i].bus_prot_clr, mask);
+ regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask);
if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
continue;
ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, !(val & mask),
+ val, !(val & sta_mask),
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
if (ret)
return ret;
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index e26c8c317a6b..4b6ae56e7c95 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -47,22 +47,23 @@ enum scpsys_bus_prot_flags {
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
};
-#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
- .bus_prot_mask = (_mask), \
+#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
+ .bus_prot_set_clr_mask = (_set_clr_mask), \
.bus_prot_set = _set, \
.bus_prot_clr = _clr, \
+ .bus_prot_sta_mask = (_sta_mask), \
.bus_prot_sta = _sta, \
.flags = _flags \
}
#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, 0)
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
#define BUS_PROT_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(_mask, \
@@ -71,9 +72,10 @@ enum scpsys_bus_prot_flags {
INFRA_TOPAXI_PROTECTSTA1)
struct scpsys_bus_prot_data {
- u32 bus_prot_mask;
+ u32 bus_prot_set_clr_mask;
u32 bus_prot_set;
u32 bus_prot_clr;
+ u32 bus_prot_sta_mask;
u32 bus_prot_sta;
u32 flags;
};
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 4/8] soc: mediatek: pm-domains: Create bus protection operation functions
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
Separate the register access used for bus protection enable/disable into
their own functions. These will be used later for WAY_EN support.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 68 +++++++++++++++------------
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index c801fa763e89..69dc24a73ce9 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -118,26 +118,50 @@ static int scpsys_sram_disable(struct scpsys_domain *pd)
MTK_POLL_TIMEOUT);
}
+static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd,
+ struct regmap *regmap)
+{
+ u32 val;
+ u32 sta_mask = bpd->bus_prot_sta_mask;
+
+ if (bpd->flags & BUS_PROT_REG_UPDATE)
+ regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
+ else
+ regmap_write(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
+
+ if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
+ return 0;
+
+ return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
+ val, !(val & sta_mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd,
+ struct regmap *regmap)
+{
+ u32 val;
+ u32 sta_mask = bpd->bus_prot_sta_mask;
+
+ if (bpd->flags & BUS_PROT_REG_UPDATE)
+ regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
+ else
+ regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
+
+ return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
+ val, (val & sta_mask) == sta_mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap)
{
int i, ret;
for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
- u32 val;
- u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
- u32 sta_mask = bpd[i].bus_prot_sta_mask;
-
- if (!set_clr_mask)
+ if (!bpd[i].bus_prot_set_clr_mask)
break;
- if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask);
- else
- regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask);
-
- ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, (val & sta_mask) == sta_mask,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ ret = scpsys_bus_protect_set(&bpd[i], regmap);
if (ret)
return ret;
}
@@ -162,24 +186,10 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
int i, ret;
for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
- u32 val;
- u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
- u32 sta_mask = bpd[i].bus_prot_sta_mask;
-
- if (!set_clr_mask)
- continue;
-
- if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask);
- else
- regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask);
-
- if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
+ if (!bpd[i].bus_prot_set_clr_mask)
continue;
- ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, !(val & sta_mask),
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ ret = scpsys_bus_protect_clear(&bpd[i], regmap);
if (ret)
return ret;
}
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 4/8] soc: mediatek: pm-domains: Create bus protection operation functions
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
Separate the register access used for bus protection enable/disable into
their own functions. These will be used later for WAY_EN support.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 68 +++++++++++++++------------
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index c801fa763e89..69dc24a73ce9 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -118,26 +118,50 @@ static int scpsys_sram_disable(struct scpsys_domain *pd)
MTK_POLL_TIMEOUT);
}
+static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd,
+ struct regmap *regmap)
+{
+ u32 val;
+ u32 sta_mask = bpd->bus_prot_sta_mask;
+
+ if (bpd->flags & BUS_PROT_REG_UPDATE)
+ regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
+ else
+ regmap_write(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
+
+ if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
+ return 0;
+
+ return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
+ val, !(val & sta_mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd,
+ struct regmap *regmap)
+{
+ u32 val;
+ u32 sta_mask = bpd->bus_prot_sta_mask;
+
+ if (bpd->flags & BUS_PROT_REG_UPDATE)
+ regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
+ else
+ regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
+
+ return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
+ val, (val & sta_mask) == sta_mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap)
{
int i, ret;
for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
- u32 val;
- u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
- u32 sta_mask = bpd[i].bus_prot_sta_mask;
-
- if (!set_clr_mask)
+ if (!bpd[i].bus_prot_set_clr_mask)
break;
- if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask);
- else
- regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask);
-
- ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, (val & sta_mask) == sta_mask,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ ret = scpsys_bus_protect_set(&bpd[i], regmap);
if (ret)
return ret;
}
@@ -162,24 +186,10 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
int i, ret;
for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
- u32 val;
- u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask;
- u32 sta_mask = bpd[i].bus_prot_sta_mask;
-
- if (!set_clr_mask)
- continue;
-
- if (bpd[i].flags & BUS_PROT_REG_UPDATE)
- regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask);
- else
- regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask);
-
- if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
+ if (!bpd[i].bus_prot_set_clr_mask)
continue;
- ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
- val, !(val & sta_mask),
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ ret = scpsys_bus_protect_clear(&bpd[i], regmap);
if (ret)
return ret;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
Use flags to distinguish between infracfg and smi subsystem for a bus
protection configuration. It simplifies enabling/disabling and prepares
the driver for the use of another regmap for mt8365.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8183-pm-domains.h | 198 ++++-----
drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++++-----
drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++++------------
drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++++------
drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++++----------
drivers/soc/mediatek/mtk-pm-domains.c | 64 ++-
drivers/soc/mediatek/mtk-pm-domains.h | 37 +-
10 files changed, 908 insertions(+), 899 deletions(-)
diff --git a/drivers/soc/mediatek/mt6795-pm-domains.h b/drivers/soc/mediatek/mt6795-pm-domains.h
index ef07c9dfdd9b..a3f7785b04bd 100644
--- a/drivers/soc/mediatek/mt6795-pm-domains.h
+++ b/drivers/soc/mediatek/mt6795-pm-domains.h
@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1),
},
},
[MT6795_POWER_DOMAIN_MJC] = {
@@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
},
},
};
diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediatek/mt8167-pm-domains.h
index 4d6c32759606..8a0e898b79ab 100644
--- a/drivers/soc/mediatek/mt8167-pm-domains.h
+++ b/drivers/soc/mediatek/mt8167-pm-domains.h
@@ -22,9 +22,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
- MT8167_TOP_AXI_PROT_EN_MCU_MM),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
+ MT8167_TOP_AXI_PROT_EN_MCU_MM),
},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -56,9 +56,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
- MT8167_TOP_AXI_PROT_EN_MFG_EMI),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
+ MT8167_TOP_AXI_PROT_EN_MFG_EMI),
},
},
[MT8167_POWER_DOMAIN_MFG_2D] = {
@@ -88,10 +88,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = 0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
- MT8167_TOP_AXI_PROT_EN_CONN_MCU |
- MT8167_TOP_AXI_PROT_EN_MCU_CONN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
+ MT8167_TOP_AXI_PROT_EN_CONN_MCU |
+ MT8167_TOP_AXI_PROT_EN_MCU_CONN),
},
},
};
diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h
index 1a5dc63b7357..7be0f47f5214 100644
--- a/drivers/soc/mediatek/mt8173-pm-domains.h
+++ b/drivers/soc/mediatek/mt8173-pm-domains.h
@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1),
},
},
[MT8173_POWER_DOMAIN_VENC_LT] = {
@@ -106,11 +106,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
},
},
};
diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediatek/mt8183-pm-domains.h
index 99de67fe5de8..5d5c0a620da4 100644
--- a/drivers/soc/mediatek/mt8183-pm-domains.h
+++ b/drivers/soc/mediatek/mt8183-pm-domains.h
@@ -28,9 +28,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_CONN,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
},
},
[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
@@ -79,11 +81,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,
- MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_1_MFG,
+ MT8183_TOP_AXI_PROT_EN_1_SET,
+ MT8183_TOP_AXI_PROT_EN_1_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1_1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MFG,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
},
},
[MT8183_POWER_DOMAIN_DISP] = {
@@ -94,17 +100,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,
- MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_1_DISP,
+ MT8183_TOP_AXI_PROT_EN_1_SET,
+ MT8183_TOP_AXI_PROT_EN_1_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1_1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_DISP,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_CAM] = {
@@ -115,21 +123,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_CAM,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_ISP] = {
@@ -140,21 +150,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VDEC] = {
@@ -165,11 +173,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VENC] = {
@@ -180,11 +188,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VPU_TOP] = {
@@ -195,25 +203,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
- MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR,
- MT8183_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VPU_CORE0] = {
@@ -224,15 +230,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
},
.caps = MTK_SCPD_SRAM_ISO,
},
@@ -244,15 +250,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
},
.caps = MTK_SCPD_SRAM_ISO,
},
diff --git a/drivers/soc/mediatek/mt8186-pm-domains.h b/drivers/soc/mediatek/mt8186-pm-domains.h
index fce86f79c505..25b5651f0ae2 100644
--- a/drivers/soc/mediatek/mt8186-pm-domains.h
+++ b/drivers/soc/mediatek/mt8186-pm-domains.h
@@ -33,23 +33,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -101,15 +101,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
},
},
[MT8186_POWER_DOMAIN_IMG] = {
@@ -120,15 +120,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -150,15 +150,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -170,15 +170,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -210,15 +210,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -230,15 +230,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -250,15 +250,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
- MT8186_TOP_AXI_PROT_EN_2_SET,
- MT8186_TOP_AXI_PROT_EN_2_CLR,
- MT8186_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
- MT8186_TOP_AXI_PROT_EN_2_SET,
- MT8186_TOP_AXI_PROT_EN_2_CLR,
- MT8186_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
+ MT8186_TOP_AXI_PROT_EN_2_SET,
+ MT8186_TOP_AXI_PROT_EN_2_CLR,
+ MT8186_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
+ MT8186_TOP_AXI_PROT_EN_2_SET,
+ MT8186_TOP_AXI_PROT_EN_2_CLR,
+ MT8186_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -268,23 +268,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.ctl_offs = 0x304,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -320,15 +320,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
- MT8186_TOP_AXI_PROT_EN_3_SET,
- MT8186_TOP_AXI_PROT_EN_3_CLR,
- MT8186_TOP_AXI_PROT_EN_3_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
- MT8186_TOP_AXI_PROT_EN_3_SET,
- MT8186_TOP_AXI_PROT_EN_3_CLR,
- MT8186_TOP_AXI_PROT_EN_3_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
+ MT8186_TOP_AXI_PROT_EN_3_SET,
+ MT8186_TOP_AXI_PROT_EN_3_CLR,
+ MT8186_TOP_AXI_PROT_EN_3_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
+ MT8186_TOP_AXI_PROT_EN_3_SET,
+ MT8186_TOP_AXI_PROT_EN_3_CLR,
+ MT8186_TOP_AXI_PROT_EN_3_STA),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h b/drivers/soc/mediatek/mt8188-pm-domains.h
index 0692cb444ed0..aa56ba31327d 100644
--- a/drivers/soc/mediatek/mt8188-pm-domains.h
+++ b/drivers/soc/mediatek/mt8188-pm-domains.h
@@ -33,31 +33,31 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
- MT8188_TOP_AXI_PROT_EN_1_SET,
- MT8188_TOP_AXI_PROT_EN_1_CLR,
- MT8188_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_1_SET,
+ MT8188_TOP_AXI_PROT_EN_1_CLR,
+ MT8188_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -99,15 +99,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -135,11 +135,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -151,11 +151,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -165,15 +165,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x35C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_ALWAYS_ON,
},
@@ -185,15 +185,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON,
},
@@ -205,15 +205,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -225,15 +225,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -245,15 +245,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -265,27 +265,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
},
[MT8188_POWER_DOMAIN_VDOSYS0] = {
@@ -296,19 +296,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
},
[MT8188_POWER_DOMAIN_VDOSYS1] = {
@@ -319,19 +319,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
},
[MT8188_POWER_DOMAIN_DP_TX] = {
@@ -342,11 +342,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -358,11 +358,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -374,19 +374,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
},
[MT8188_POWER_DOMAIN_WPE] = {
@@ -397,15 +397,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -417,15 +417,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -437,15 +437,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -457,19 +457,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -479,19 +479,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x3A4,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -503,15 +503,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -541,27 +541,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x3A0,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
- MT8188_TOP_AXI_PROT_EN_1_SET,
- MT8188_TOP_AXI_PROT_EN_1_CLR,
- MT8188_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
+ MT8188_TOP_AXI_PROT_EN_1_SET,
+ MT8188_TOP_AXI_PROT_EN_1_CLR,
+ MT8188_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -573,23 +573,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h
index b97b2051920f..17ee852cfc26 100644
--- a/drivers/soc/mediatek/mt8192-pm-domains.h
+++ b/drivers/soc/mediatek/mt8192-pm-domains.h
@@ -19,11 +19,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
},
},
[MT8192_POWER_DOMAIN_CONN] = {
@@ -34,19 +34,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
- MT8192_TOP_AXI_PROT_EN_1_SET,
- MT8192_TOP_AXI_PROT_EN_1_CLR,
- MT8192_TOP_AXI_PROT_EN_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_CONN,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -68,23 +68,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
- MT8192_TOP_AXI_PROT_EN_1_SET,
- MT8192_TOP_AXI_PROT_EN_1_CLR,
- MT8192_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
},
.caps = MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -141,27 +141,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_DISP,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8192_POWER_DOMAIN_IPE] = {
@@ -172,15 +172,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_ISP] = {
@@ -191,15 +191,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8192_POWER_DOMAIN_ISP2] = {
@@ -210,15 +210,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_MDP] = {
@@ -229,15 +229,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8192_POWER_DOMAIN_VENC] = {
@@ -248,15 +248,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_VDEC] = {
@@ -267,15 +267,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_VDEC2] = {
@@ -295,27 +295,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
- MT8192_TOP_AXI_PROT_EN_1_SET,
- MT8192_TOP_AXI_PROT_EN_1_CLR,
- MT8192_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
- MT8192_TOP_AXI_PROT_EN_VDNR_SET,
- MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
- MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
+ MT8192_TOP_AXI_PROT_EN_VDNR_SET,
+ MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
+ MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
},
},
[MT8192_POWER_DOMAIN_CAM_RAWA] = {
diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediatek/mt8195-pm-domains.h
index d7387ea1b9c9..8360d79bc1b4 100644
--- a/drivers/soc/mediatek/mt8195-pm-domains.h
+++ b/drivers/soc/mediatek/mt8195-pm-domains.h
@@ -23,15 +23,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
- MT8195_TOP_AXI_PROT_EN_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
+ MT8195_TOP_AXI_PROT_EN_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_MAC_P1] = {
@@ -42,15 +42,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
- MT8195_TOP_AXI_PROT_EN_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
+ MT8195_TOP_AXI_PROT_EN_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_PHY] = {
@@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -111,11 +111,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
},
},
[MT8195_POWER_DOMAIN_MFG0] = {
@@ -136,31 +136,31 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1,
- MT8195_TOP_AXI_PROT_EN_1_SET,
- MT8195_TOP_AXI_PROT_EN_1_CLR,
- MT8195_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MFG1,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1,
+ MT8195_TOP_AXI_PROT_EN_1_SET,
+ MT8195_TOP_AXI_PROT_EN_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -222,27 +222,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS0] = {
@@ -253,19 +253,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VPPSYS1] = {
@@ -276,19 +276,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS1] = {
@@ -299,19 +299,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_DP_TX] = {
@@ -322,11 +322,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -338,11 +338,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -364,19 +364,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDEC0] = {
@@ -387,23 +387,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -415,15 +415,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -435,15 +435,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -455,19 +455,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -479,15 +479,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -499,15 +499,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -529,15 +529,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -549,27 +549,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM,
- MT8195_TOP_AXI_PROT_EN_1_SET,
- MT8195_TOP_AXI_PROT_EN_1_CLR,
- MT8195_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_CAM,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_1_CAM,
+ MT8195_TOP_AXI_PROT_EN_1_SET,
+ MT8195_TOP_AXI_PROT_EN_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 69dc24a73ce9..3cdf62c0b6bd 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -118,9 +118,19 @@ static int scpsys_sram_disable(struct scpsys_domain *pd)
MTK_POLL_TIMEOUT);
}
-static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd,
- struct regmap *regmap)
+static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
{
+ if (bpd->flags & BUS_PROT_COMPONENT_SMI)
+ return pd->smi;
+ else
+ return pd->infracfg;
+}
+
+static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
+{
+ struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
@@ -137,9 +147,10 @@ static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
-static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd,
- struct regmap *regmap)
+static int scpsys_bus_protect_set(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
@@ -153,15 +164,16 @@ static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
-static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap)
+static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
{
- int i, ret;
+ for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
+ const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
+ int ret;
- for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
- if (!bpd[i].bus_prot_set_clr_mask)
+ if (!bpd->bus_prot_set_clr_mask)
break;
- ret = scpsys_bus_protect_set(&bpd[i], regmap);
+ ret = scpsys_bus_protect_set(pd, bpd);
if (ret)
return ret;
}
@@ -169,27 +181,16 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
return 0;
}
-static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
-{
- int ret;
-
- ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg);
- if (ret)
- return ret;
-
- return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi);
-}
-
-static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
- struct regmap *regmap)
+static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
{
- int i, ret;
+ for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
+ const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
+ int ret;
- for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
- if (!bpd[i].bus_prot_set_clr_mask)
+ if (!bpd->bus_prot_set_clr_mask)
continue;
- ret = scpsys_bus_protect_clear(&bpd[i], regmap);
+ ret = scpsys_bus_protect_clear(pd, bpd);
if (ret)
return ret;
}
@@ -197,17 +198,6 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
return 0;
}
-static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
-{
- int ret;
-
- ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi);
- if (ret)
- return ret;
-
- return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg);
-}
-
static int scpsys_regulator_enable(struct regulator *supply)
{
return supply ? regulator_enable(supply) : 0;
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 4b6ae56e7c95..356788263db2 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -45,6 +45,8 @@
enum scpsys_bus_prot_flags {
BUS_PROT_REG_UPDATE = BIT(1),
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
+ BUS_PROT_COMPONENT_INFRA = BIT(3),
+ BUS_PROT_COMPONENT_SMI = BIT(4),
};
#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
@@ -56,17 +58,30 @@ enum scpsys_bus_prot_flags {
.flags = _flags \
}
-#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
+#define BUS_PROT_INFRA_WR(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_INFRA)
-#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
+#define BUS_PROT_INFRA_WR_IGN(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_INFRA | BUS_PROT_IGNORE_CLR_ACK)
-#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
+#define BUS_PROT_INFRA_UPDATE(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_INFRA | BUS_PROT_REG_UPDATE)
-#define BUS_PROT_UPDATE_TOPAXI(_mask) \
- BUS_PROT_UPDATE(_mask, \
+#define BUS_PROT_SMI_WR(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_SMI)
+
+#define BUS_PROT_SMI_WR_IGN(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_SMI | BUS_PROT_IGNORE_CLR_ACK)
+
+#define BUS_PROT_SMI_UPDATE(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_SMI | BUS_PROT_REG_UPDATE)
+
+#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
+ BUS_PROT_INFRA_UPDATE(_mask, \
INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTSTA1)
@@ -90,8 +105,7 @@ struct scpsys_bus_prot_data {
* @ext_buck_iso_offs: The offset for external buck isolation
* @ext_buck_iso_mask: The mask for external buck isolation
* @caps: The flag for active wake-up action.
- * @bp_infracfg: bus protection for infracfg subsystem
- * @bp_smi: bus protection for smi subsystem
+ * @bp_cfg: bus protection configuration for any subsystem
*/
struct scpsys_domain_data {
const char *name;
@@ -102,8 +116,7 @@ struct scpsys_domain_data {
int ext_buck_iso_offs;
u32 ext_buck_iso_mask;
u8 caps;
- const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
- const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
+ const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
int pwr_sta_offs;
int pwr_sta2nd_offs;
};
--
2.40.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Markus Schneider-Pargmann
Use flags to distinguish between infracfg and smi subsystem for a bus
protection configuration. It simplifies enabling/disabling and prepares
the driver for the use of another regmap for mt8365.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8183-pm-domains.h | 198 ++++-----
drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++++-----
drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++++------------
drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++++------
drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++++----------
drivers/soc/mediatek/mtk-pm-domains.c | 64 ++-
drivers/soc/mediatek/mtk-pm-domains.h | 37 +-
10 files changed, 908 insertions(+), 899 deletions(-)
diff --git a/drivers/soc/mediatek/mt6795-pm-domains.h b/drivers/soc/mediatek/mt6795-pm-domains.h
index ef07c9dfdd9b..a3f7785b04bd 100644
--- a/drivers/soc/mediatek/mt6795-pm-domains.h
+++ b/drivers/soc/mediatek/mt6795-pm-domains.h
@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1),
},
},
[MT6795_POWER_DOMAIN_MJC] = {
@@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
},
},
};
diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediatek/mt8167-pm-domains.h
index 4d6c32759606..8a0e898b79ab 100644
--- a/drivers/soc/mediatek/mt8167-pm-domains.h
+++ b/drivers/soc/mediatek/mt8167-pm-domains.h
@@ -22,9 +22,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
- MT8167_TOP_AXI_PROT_EN_MCU_MM),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
+ MT8167_TOP_AXI_PROT_EN_MCU_MM),
},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -56,9 +56,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
- MT8167_TOP_AXI_PROT_EN_MFG_EMI),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
+ MT8167_TOP_AXI_PROT_EN_MFG_EMI),
},
},
[MT8167_POWER_DOMAIN_MFG_2D] = {
@@ -88,10 +88,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = 0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
- MT8167_TOP_AXI_PROT_EN_CONN_MCU |
- MT8167_TOP_AXI_PROT_EN_MCU_CONN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
+ MT8167_TOP_AXI_PROT_EN_CONN_MCU |
+ MT8167_TOP_AXI_PROT_EN_MCU_CONN),
},
},
};
diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h
index 1a5dc63b7357..7be0f47f5214 100644
--- a/drivers/soc/mediatek/mt8173-pm-domains.h
+++ b/drivers/soc/mediatek/mt8173-pm-domains.h
@@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1),
},
},
[MT8173_POWER_DOMAIN_VENC_LT] = {
@@ -106,11 +106,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .bp_infracfg = {
- BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
+ .bp_cfg = {
+ BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
},
},
};
diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediatek/mt8183-pm-domains.h
index 99de67fe5de8..5d5c0a620da4 100644
--- a/drivers/soc/mediatek/mt8183-pm-domains.h
+++ b/drivers/soc/mediatek/mt8183-pm-domains.h
@@ -28,9 +28,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_CONN,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
},
},
[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
@@ -79,11 +81,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,
- MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_1_MFG,
+ MT8183_TOP_AXI_PROT_EN_1_SET,
+ MT8183_TOP_AXI_PROT_EN_1_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1_1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MFG,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
},
},
[MT8183_POWER_DOMAIN_DISP] = {
@@ -94,17 +100,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,
- MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_1_DISP,
+ MT8183_TOP_AXI_PROT_EN_1_SET,
+ MT8183_TOP_AXI_PROT_EN_1_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1_1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_DISP,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_CAM] = {
@@ -115,21 +123,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_CAM,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_ISP] = {
@@ -140,21 +150,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VDEC] = {
@@ -165,11 +173,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VENC] = {
@@ -180,11 +188,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VPU_TOP] = {
@@ -195,25 +203,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
- MT8183_TOP_AXI_PROT_EN_SET,
- MT8183_TOP_AXI_PROT_EN_CLR,
- MT8183_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
- MT8183_TOP_AXI_PROT_EN_MM_SET,
- MT8183_TOP_AXI_PROT_EN_MM_CLR,
- MT8183_TOP_AXI_PROT_EN_MM_STA1),
- },
- .bp_smi = {
- BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
- MT8183_SMI_COMMON_CLAMP_EN_SET,
- MT8183_SMI_COMMON_CLAMP_EN_CLR,
- MT8183_SMI_COMMON_CLAMP_EN),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
+ MT8183_TOP_AXI_PROT_EN_SET,
+ MT8183_TOP_AXI_PROT_EN_CLR,
+ MT8183_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
+ MT8183_TOP_AXI_PROT_EN_MM_SET,
+ MT8183_TOP_AXI_PROT_EN_MM_CLR,
+ MT8183_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
+ MT8183_SMI_COMMON_CLAMP_EN_SET,
+ MT8183_SMI_COMMON_CLAMP_EN_CLR,
+ MT8183_SMI_COMMON_CLAMP_EN),
},
},
[MT8183_POWER_DOMAIN_VPU_CORE0] = {
@@ -224,15 +230,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
},
.caps = MTK_SCPD_SRAM_ISO,
},
@@ -244,15 +250,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
- BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
- MT8183_TOP_AXI_PROT_EN_MCU_SET,
- MT8183_TOP_AXI_PROT_EN_MCU_CLR,
- MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
+ BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
+ MT8183_TOP_AXI_PROT_EN_MCU_SET,
+ MT8183_TOP_AXI_PROT_EN_MCU_CLR,
+ MT8183_TOP_AXI_PROT_EN_MCU_STA1),
},
.caps = MTK_SCPD_SRAM_ISO,
},
diff --git a/drivers/soc/mediatek/mt8186-pm-domains.h b/drivers/soc/mediatek/mt8186-pm-domains.h
index fce86f79c505..25b5651f0ae2 100644
--- a/drivers/soc/mediatek/mt8186-pm-domains.h
+++ b/drivers/soc/mediatek/mt8186-pm-domains.h
@@ -33,23 +33,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -101,15 +101,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
},
},
[MT8186_POWER_DOMAIN_IMG] = {
@@ -120,15 +120,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -150,15 +150,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -170,15 +170,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -210,15 +210,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -230,15 +230,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -250,15 +250,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
- MT8186_TOP_AXI_PROT_EN_2_SET,
- MT8186_TOP_AXI_PROT_EN_2_CLR,
- MT8186_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
- MT8186_TOP_AXI_PROT_EN_2_SET,
- MT8186_TOP_AXI_PROT_EN_2_CLR,
- MT8186_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
+ MT8186_TOP_AXI_PROT_EN_2_SET,
+ MT8186_TOP_AXI_PROT_EN_2_CLR,
+ MT8186_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
+ MT8186_TOP_AXI_PROT_EN_2_SET,
+ MT8186_TOP_AXI_PROT_EN_2_CLR,
+ MT8186_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -268,23 +268,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.ctl_offs = 0x304,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
- MT8186_TOP_AXI_PROT_EN_1_SET,
- MT8186_TOP_AXI_PROT_EN_1_CLR,
- MT8186_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
- MT8186_TOP_AXI_PROT_EN_SET,
- MT8186_TOP_AXI_PROT_EN_CLR,
- MT8186_TOP_AXI_PROT_EN_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
+ MT8186_TOP_AXI_PROT_EN_1_SET,
+ MT8186_TOP_AXI_PROT_EN_1_CLR,
+ MT8186_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
+ MT8186_TOP_AXI_PROT_EN_SET,
+ MT8186_TOP_AXI_PROT_EN_CLR,
+ MT8186_TOP_AXI_PROT_EN_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -320,15 +320,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
- MT8186_TOP_AXI_PROT_EN_3_SET,
- MT8186_TOP_AXI_PROT_EN_3_CLR,
- MT8186_TOP_AXI_PROT_EN_3_STA),
- BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
- MT8186_TOP_AXI_PROT_EN_3_SET,
- MT8186_TOP_AXI_PROT_EN_3_CLR,
- MT8186_TOP_AXI_PROT_EN_3_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
+ MT8186_TOP_AXI_PROT_EN_3_SET,
+ MT8186_TOP_AXI_PROT_EN_3_CLR,
+ MT8186_TOP_AXI_PROT_EN_3_STA),
+ BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
+ MT8186_TOP_AXI_PROT_EN_3_SET,
+ MT8186_TOP_AXI_PROT_EN_3_CLR,
+ MT8186_TOP_AXI_PROT_EN_3_STA),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h b/drivers/soc/mediatek/mt8188-pm-domains.h
index 0692cb444ed0..aa56ba31327d 100644
--- a/drivers/soc/mediatek/mt8188-pm-domains.h
+++ b/drivers/soc/mediatek/mt8188-pm-domains.h
@@ -33,31 +33,31 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
- MT8188_TOP_AXI_PROT_EN_1_SET,
- MT8188_TOP_AXI_PROT_EN_1_CLR,
- MT8188_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_1_SET,
+ MT8188_TOP_AXI_PROT_EN_1_CLR,
+ MT8188_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -99,15 +99,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -135,11 +135,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -151,11 +151,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -165,15 +165,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x35C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_ALWAYS_ON,
},
@@ -185,15 +185,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON,
},
@@ -205,15 +205,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -225,15 +225,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -245,15 +245,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -265,27 +265,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
},
[MT8188_POWER_DOMAIN_VDOSYS0] = {
@@ -296,19 +296,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
- MT8188_TOP_AXI_PROT_EN_SET,
- MT8188_TOP_AXI_PROT_EN_CLR,
- MT8188_TOP_AXI_PROT_EN_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
},
[MT8188_POWER_DOMAIN_VDOSYS1] = {
@@ -319,19 +319,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
},
[MT8188_POWER_DOMAIN_DP_TX] = {
@@ -342,11 +342,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -358,11 +358,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
- MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -374,19 +374,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
},
[MT8188_POWER_DOMAIN_WPE] = {
@@ -397,15 +397,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -417,15 +417,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -437,15 +437,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -457,19 +457,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -479,19 +479,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x3A4,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -503,15 +503,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -541,27 +541,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x3A0,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
- MT8188_TOP_AXI_PROT_EN_1_SET,
- MT8188_TOP_AXI_PROT_EN_1_CLR,
- MT8188_TOP_AXI_PROT_EN_1_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
- MT8188_TOP_AXI_PROT_EN_MM_SET,
- MT8188_TOP_AXI_PROT_EN_MM_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
+ MT8188_TOP_AXI_PROT_EN_1_SET,
+ MT8188_TOP_AXI_PROT_EN_1_CLR,
+ MT8188_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -573,23 +573,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
- MT8188_TOP_AXI_PROT_EN_MM_2_SET,
- MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8188_TOP_AXI_PROT_EN_MM_2_STA),
- BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
- MT8188_TOP_AXI_PROT_EN_2_SET,
- MT8188_TOP_AXI_PROT_EN_2_CLR,
- MT8188_TOP_AXI_PROT_EN_2_STA),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h
index b97b2051920f..17ee852cfc26 100644
--- a/drivers/soc/mediatek/mt8192-pm-domains.h
+++ b/drivers/soc/mediatek/mt8192-pm-domains.h
@@ -19,11 +19,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
},
},
[MT8192_POWER_DOMAIN_CONN] = {
@@ -34,19 +34,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
- MT8192_TOP_AXI_PROT_EN_1_SET,
- MT8192_TOP_AXI_PROT_EN_1_CLR,
- MT8192_TOP_AXI_PROT_EN_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_CONN,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -68,23 +68,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
- MT8192_TOP_AXI_PROT_EN_1_SET,
- MT8192_TOP_AXI_PROT_EN_1_CLR,
- MT8192_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
},
.caps = MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -141,27 +141,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
- MT8192_TOP_AXI_PROT_EN_SET,
- MT8192_TOP_AXI_PROT_EN_CLR,
- MT8192_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_DISP,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8192_POWER_DOMAIN_IPE] = {
@@ -172,15 +172,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_ISP] = {
@@ -191,15 +191,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8192_POWER_DOMAIN_ISP2] = {
@@ -210,15 +210,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_MDP] = {
@@ -229,15 +229,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_2_SET,
- MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8192_POWER_DOMAIN_VENC] = {
@@ -248,15 +248,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_VDEC] = {
@@ -267,15 +267,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
},
},
[MT8192_POWER_DOMAIN_VDEC2] = {
@@ -295,27 +295,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
- MT8192_TOP_AXI_PROT_EN_2_SET,
- MT8192_TOP_AXI_PROT_EN_2_CLR,
- MT8192_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
- MT8192_TOP_AXI_PROT_EN_1_SET,
- MT8192_TOP_AXI_PROT_EN_1_CLR,
- MT8192_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
- MT8192_TOP_AXI_PROT_EN_MM_SET,
- MT8192_TOP_AXI_PROT_EN_MM_CLR,
- MT8192_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
- MT8192_TOP_AXI_PROT_EN_VDNR_SET,
- MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
- MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
+ MT8192_TOP_AXI_PROT_EN_VDNR_SET,
+ MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
+ MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
},
},
[MT8192_POWER_DOMAIN_CAM_RAWA] = {
diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediatek/mt8195-pm-domains.h
index d7387ea1b9c9..8360d79bc1b4 100644
--- a/drivers/soc/mediatek/mt8195-pm-domains.h
+++ b/drivers/soc/mediatek/mt8195-pm-domains.h
@@ -23,15 +23,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
- MT8195_TOP_AXI_PROT_EN_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
+ MT8195_TOP_AXI_PROT_EN_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_MAC_P1] = {
@@ -42,15 +42,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
- MT8195_TOP_AXI_PROT_EN_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
+ MT8195_TOP_AXI_PROT_EN_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_PHY] = {
@@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -111,11 +111,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
},
},
[MT8195_POWER_DOMAIN_MFG0] = {
@@ -136,31 +136,31 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1,
- MT8195_TOP_AXI_PROT_EN_1_SET,
- MT8195_TOP_AXI_PROT_EN_1_CLR,
- MT8195_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MFG1,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1,
+ MT8195_TOP_AXI_PROT_EN_1_SET,
+ MT8195_TOP_AXI_PROT_EN_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
@@ -222,27 +222,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS0] = {
@@ -253,19 +253,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0,
- MT8195_TOP_AXI_PROT_EN_SET,
- MT8195_TOP_AXI_PROT_EN_CLR,
- MT8195_TOP_AXI_PROT_EN_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
- MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0,
+ MT8195_TOP_AXI_PROT_EN_SET,
+ MT8195_TOP_AXI_PROT_EN_CLR,
+ MT8195_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VPPSYS1] = {
@@ -276,19 +276,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS1] = {
@@ -299,19 +299,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_DP_TX] = {
@@ -322,11 +322,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -338,11 +338,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
- MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -364,19 +364,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDEC0] = {
@@ -387,23 +387,23 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -415,15 +415,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -435,15 +435,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -455,19 +455,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -479,15 +479,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -499,15 +499,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -529,15 +529,15 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
@@ -549,27 +549,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .bp_infracfg = {
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM,
- MT8195_TOP_AXI_PROT_EN_2_SET,
- MT8195_TOP_AXI_PROT_EN_2_CLR,
- MT8195_TOP_AXI_PROT_EN_2_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM,
- MT8195_TOP_AXI_PROT_EN_1_SET,
- MT8195_TOP_AXI_PROT_EN_1_CLR,
- MT8195_TOP_AXI_PROT_EN_1_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
- MT8195_TOP_AXI_PROT_EN_MM_SET,
- MT8195_TOP_AXI_PROT_EN_MM_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_STA1),
- BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
- MT8195_TOP_AXI_PROT_EN_MM_2_SET,
- MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
- MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
+ .bp_cfg = {
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_CAM,
+ MT8195_TOP_AXI_PROT_EN_2_SET,
+ MT8195_TOP_AXI_PROT_EN_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_1_CAM,
+ MT8195_TOP_AXI_PROT_EN_1_SET,
+ MT8195_TOP_AXI_PROT_EN_1_CLR,
+ MT8195_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
+ MT8195_TOP_AXI_PROT_EN_MM_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
+ MT8195_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 69dc24a73ce9..3cdf62c0b6bd 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -118,9 +118,19 @@ static int scpsys_sram_disable(struct scpsys_domain *pd)
MTK_POLL_TIMEOUT);
}
-static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd,
- struct regmap *regmap)
+static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
{
+ if (bpd->flags & BUS_PROT_COMPONENT_SMI)
+ return pd->smi;
+ else
+ return pd->infracfg;
+}
+
+static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
+{
+ struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
@@ -137,9 +147,10 @@ static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
-static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd,
- struct regmap *regmap)
+static int scpsys_bus_protect_set(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
@@ -153,15 +164,16 @@ static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
-static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap)
+static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
{
- int i, ret;
+ for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
+ const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
+ int ret;
- for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
- if (!bpd[i].bus_prot_set_clr_mask)
+ if (!bpd->bus_prot_set_clr_mask)
break;
- ret = scpsys_bus_protect_set(&bpd[i], regmap);
+ ret = scpsys_bus_protect_set(pd, bpd);
if (ret)
return ret;
}
@@ -169,27 +181,16 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
return 0;
}
-static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
-{
- int ret;
-
- ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg);
- if (ret)
- return ret;
-
- return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi);
-}
-
-static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
- struct regmap *regmap)
+static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
{
- int i, ret;
+ for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
+ const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
+ int ret;
- for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
- if (!bpd[i].bus_prot_set_clr_mask)
+ if (!bpd->bus_prot_set_clr_mask)
continue;
- ret = scpsys_bus_protect_clear(&bpd[i], regmap);
+ ret = scpsys_bus_protect_clear(pd, bpd);
if (ret)
return ret;
}
@@ -197,17 +198,6 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
return 0;
}
-static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
-{
- int ret;
-
- ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi);
- if (ret)
- return ret;
-
- return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg);
-}
-
static int scpsys_regulator_enable(struct regulator *supply)
{
return supply ? regulator_enable(supply) : 0;
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 4b6ae56e7c95..356788263db2 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -45,6 +45,8 @@
enum scpsys_bus_prot_flags {
BUS_PROT_REG_UPDATE = BIT(1),
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
+ BUS_PROT_COMPONENT_INFRA = BIT(3),
+ BUS_PROT_COMPONENT_SMI = BIT(4),
};
#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
@@ -56,17 +58,30 @@ enum scpsys_bus_prot_flags {
.flags = _flags \
}
-#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
+#define BUS_PROT_INFRA_WR(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_INFRA)
-#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
+#define BUS_PROT_INFRA_WR_IGN(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_INFRA | BUS_PROT_IGNORE_CLR_ACK)
-#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
- _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
+#define BUS_PROT_INFRA_UPDATE(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_INFRA | BUS_PROT_REG_UPDATE)
-#define BUS_PROT_UPDATE_TOPAXI(_mask) \
- BUS_PROT_UPDATE(_mask, \
+#define BUS_PROT_SMI_WR(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_SMI)
+
+#define BUS_PROT_SMI_WR_IGN(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_SMI | BUS_PROT_IGNORE_CLR_ACK)
+
+#define BUS_PROT_SMI_UPDATE(_mask, _set, _clr, _sta) \
+ _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_COMPONENT_SMI | BUS_PROT_REG_UPDATE)
+
+#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
+ BUS_PROT_INFRA_UPDATE(_mask, \
INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTSTA1)
@@ -90,8 +105,7 @@ struct scpsys_bus_prot_data {
* @ext_buck_iso_offs: The offset for external buck isolation
* @ext_buck_iso_mask: The mask for external buck isolation
* @caps: The flag for active wake-up action.
- * @bp_infracfg: bus protection for infracfg subsystem
- * @bp_smi: bus protection for smi subsystem
+ * @bp_cfg: bus protection configuration for any subsystem
*/
struct scpsys_domain_data {
const char *name;
@@ -102,8 +116,7 @@ struct scpsys_domain_data {
int ext_buck_iso_offs;
u32 ext_buck_iso_mask;
u8 caps;
- const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
- const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
+ const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
int pwr_sta_offs;
int pwr_sta2nd_offs;
};
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Alexandre Bailon, Fabien Parent,
Markus Schneider-Pargmann
From: Alexandre Bailon <abailon@baylibre.com>
This updates the power domain to support WAY_EN operations. WAY_EN
operations on mt8365 are using a different component to check for the
acknowledgment, namely the infracfg-nao component. Also to enable a way
it the bit needs to be cleared while disabling a way needs a bit to be
set. To support these two operations two flags are added,
BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
another regmap is created if the INFRA_NAO capability is set.
This operation is required by the mt8365 for the MM power domain.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
2 files changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 3cdf62c0b6bd..4659f0a0aa08 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -44,6 +44,7 @@ struct scpsys_domain {
struct clk_bulk_data *clks;
int num_subsys_clks;
struct clk_bulk_data *subsys_clks;
+ struct regmap *infracfg_nao;
struct regmap *infracfg;
struct regmap *smi;
struct regulator *supply;
@@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
return pd->infracfg;
}
+static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
+{
+ if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
+ return pd->infracfg_nao;
+ else
+ return scpsys_bus_protect_get_regmap(pd, bpd);
+}
+
static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
+ u32 expected_ack;
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
+ expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
+
if (bpd->flags & BUS_PROT_REG_UPDATE)
regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
else
@@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
return 0;
- return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
- val, !(val & sta_mask),
+ return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
+ val, (val & sta_mask) == expected_ack,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
static int scpsys_bus_protect_set(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
@@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
else
regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
- return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
+ return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
val, (val & sta_mask) == sta_mask,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
@@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
if (!bpd->bus_prot_set_clr_mask)
break;
- ret = scpsys_bus_protect_set(pd, bpd);
+ if (bpd->flags & BUS_PROT_INVERTED)
+ ret = scpsys_bus_protect_clear(pd, bpd);
+ else
+ ret = scpsys_bus_protect_set(pd, bpd);
if (ret)
return ret;
}
@@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
if (!bpd->bus_prot_set_clr_mask)
continue;
- ret = scpsys_bus_protect_clear(pd, bpd);
+ if (bpd->flags & BUS_PROT_INVERTED)
+ ret = scpsys_bus_protect_set(pd, bpd);
+ else
+ ret = scpsys_bus_protect_clear(pd, bpd);
if (ret)
return ret;
}
@@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
return ERR_CAST(pd->smi);
}
+ pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
+ if (IS_ERR(pd->infracfg_nao)) {
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
+ return ERR_CAST(pd->infracfg_nao);
+
+ pd->infracfg_nao = NULL;
+ }
+
num_clks = of_clk_get_parent_count(node);
if (num_clks > 0) {
/* Calculate number of subsys_clks */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 356788263db2..562d4e92ce16 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -11,6 +11,7 @@
/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
#define MTK_SCPD_ALWAYS_ON BIT(5)
#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
+#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@@ -45,8 +46,10 @@
enum scpsys_bus_prot_flags {
BUS_PROT_REG_UPDATE = BIT(1),
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
- BUS_PROT_COMPONENT_INFRA = BIT(3),
- BUS_PROT_COMPONENT_SMI = BIT(4),
+ BUS_PROT_INVERTED = BIT(3),
+ BUS_PROT_COMPONENT_INFRA = BIT(4),
+ BUS_PROT_COMPONENT_SMI = BIT(5),
+ BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6),
};
#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Alexandre Bailon, Fabien Parent,
Markus Schneider-Pargmann
From: Alexandre Bailon <abailon@baylibre.com>
This updates the power domain to support WAY_EN operations. WAY_EN
operations on mt8365 are using a different component to check for the
acknowledgment, namely the infracfg-nao component. Also to enable a way
it the bit needs to be cleared while disabling a way needs a bit to be
set. To support these two operations two flags are added,
BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
another regmap is created if the INFRA_NAO capability is set.
This operation is required by the mt8365 for the MM power domain.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
2 files changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 3cdf62c0b6bd..4659f0a0aa08 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -44,6 +44,7 @@ struct scpsys_domain {
struct clk_bulk_data *clks;
int num_subsys_clks;
struct clk_bulk_data *subsys_clks;
+ struct regmap *infracfg_nao;
struct regmap *infracfg;
struct regmap *smi;
struct regulator *supply;
@@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
return pd->infracfg;
}
+static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
+{
+ if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
+ return pd->infracfg_nao;
+ else
+ return scpsys_bus_protect_get_regmap(pd, bpd);
+}
+
static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
+ u32 expected_ack;
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
+ expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
+
if (bpd->flags & BUS_PROT_REG_UPDATE)
regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
else
@@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
return 0;
- return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
- val, !(val & sta_mask),
+ return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
+ val, (val & sta_mask) == expected_ack,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
static int scpsys_bus_protect_set(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
@@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
else
regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
- return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
+ return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
val, (val & sta_mask) == sta_mask,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
@@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
if (!bpd->bus_prot_set_clr_mask)
break;
- ret = scpsys_bus_protect_set(pd, bpd);
+ if (bpd->flags & BUS_PROT_INVERTED)
+ ret = scpsys_bus_protect_clear(pd, bpd);
+ else
+ ret = scpsys_bus_protect_set(pd, bpd);
if (ret)
return ret;
}
@@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
if (!bpd->bus_prot_set_clr_mask)
continue;
- ret = scpsys_bus_protect_clear(pd, bpd);
+ if (bpd->flags & BUS_PROT_INVERTED)
+ ret = scpsys_bus_protect_set(pd, bpd);
+ else
+ ret = scpsys_bus_protect_clear(pd, bpd);
if (ret)
return ret;
}
@@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
return ERR_CAST(pd->smi);
}
+ pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
+ if (IS_ERR(pd->infracfg_nao)) {
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
+ return ERR_CAST(pd->infracfg_nao);
+
+ pd->infracfg_nao = NULL;
+ }
+
num_clks = of_clk_get_parent_count(node);
if (num_clks > 0) {
/* Calculate number of subsys_clks */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 356788263db2..562d4e92ce16 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -11,6 +11,7 @@
/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
#define MTK_SCPD_ALWAYS_ON BIT(5)
#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
+#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@@ -45,8 +46,10 @@
enum scpsys_bus_prot_flags {
BUS_PROT_REG_UPDATE = BIT(1),
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
- BUS_PROT_COMPONENT_INFRA = BIT(3),
- BUS_PROT_COMPONENT_SMI = BIT(4),
+ BUS_PROT_INVERTED = BIT(3),
+ BUS_PROT_COMPONENT_INFRA = BIT(4),
+ BUS_PROT_COMPONENT_SMI = BIT(5),
+ BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6),
};
#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 7/8] soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Alexandre Bailon, Fabien Parent,
Markus Schneider-Pargmann
From: Alexandre Bailon <abailon@baylibre.com>
This adds support for MTK_SCPD_STRICT_BUS_PROTECTION capability. It is a
strict bus protection policy that requires the bus protection to be
disabled before accessing the bus.
This is required by the mt8365, for the MM power domain.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 27 +++++++++++++++++++++++----
drivers/soc/mediatek/mtk-pm-domains.h | 1 +
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 4659f0a0aa08..5c458aa2ddbe 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -262,9 +262,17 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
- ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks);
- if (ret)
- goto err_pwr_ack;
+ /*
+ * In few Mediatek platforms(e.g. MT6779), the bus protect policy is
+ * stricter, which leads to bus protect release must be prior to bus
+ * access.
+ */
+ if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) {
+ ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
+ pd->subsys_clks);
+ if (ret)
+ goto err_pwr_ack;
+ }
ret = scpsys_sram_enable(pd);
if (ret < 0)
@@ -274,12 +282,23 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret < 0)
goto err_disable_sram;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) {
+ ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
+ pd->subsys_clks);
+ if (ret)
+ goto err_enable_bus_protect;
+ }
+
return 0;
+err_enable_bus_protect:
+ scpsys_bus_protect_enable(pd);
err_disable_sram:
scpsys_sram_disable(pd);
err_disable_subsys_clks:
- clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
+ if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION))
+ clk_bulk_disable_unprepare(pd->num_subsys_clks,
+ pd->subsys_clks);
err_pwr_ack:
clk_bulk_disable_unprepare(pd->num_clks, pd->clks);
err_reg:
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 562d4e92ce16..116c7875f74c 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -12,6 +12,7 @@
#define MTK_SCPD_ALWAYS_ON BIT(5)
#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
+#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 7/8] soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Alexandre Bailon, Fabien Parent,
Markus Schneider-Pargmann
From: Alexandre Bailon <abailon@baylibre.com>
This adds support for MTK_SCPD_STRICT_BUS_PROTECTION capability. It is a
strict bus protection policy that requires the bus protection to be
disabled before accessing the bus.
This is required by the mt8365, for the MM power domain.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 27 +++++++++++++++++++++++----
drivers/soc/mediatek/mtk-pm-domains.h | 1 +
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 4659f0a0aa08..5c458aa2ddbe 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -262,9 +262,17 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
- ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks);
- if (ret)
- goto err_pwr_ack;
+ /*
+ * In few Mediatek platforms(e.g. MT6779), the bus protect policy is
+ * stricter, which leads to bus protect release must be prior to bus
+ * access.
+ */
+ if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) {
+ ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
+ pd->subsys_clks);
+ if (ret)
+ goto err_pwr_ack;
+ }
ret = scpsys_sram_enable(pd);
if (ret < 0)
@@ -274,12 +282,23 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret < 0)
goto err_disable_sram;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) {
+ ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
+ pd->subsys_clks);
+ if (ret)
+ goto err_enable_bus_protect;
+ }
+
return 0;
+err_enable_bus_protect:
+ scpsys_bus_protect_enable(pd);
err_disable_sram:
scpsys_sram_disable(pd);
err_disable_subsys_clks:
- clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
+ if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION))
+ clk_bulk_disable_unprepare(pd->num_subsys_clks,
+ pd->subsys_clks);
err_pwr_ack:
clk_bulk_disable_unprepare(pd->num_clks, pd->clks);
err_reg:
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 562d4e92ce16..116c7875f74c 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -12,6 +12,7 @@
#define MTK_SCPD_ALWAYS_ON BIT(5)
#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
+#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Fabien Parent, Markus Schneider-Pargmann
From: Fabien Parent <fparent@baylibre.com>
Add the needed board data to support MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 5 +
include/linux/soc/mediatek/infracfg.h | 41 +++++
3 files changed, 243 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediatek/mt8365-pm-domains.h
new file mode 100644
index 000000000000..02f789e1c65a
--- /dev/null
+++ b/drivers/soc/mediatek/mt8365-pm-domains.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mediatek,mt8365-power.h>
+
+/*
+ * MT8365 power domain support
+ */
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
+ BUS_PROT_INFRA_WR(_mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
+ BUS_PROT_INFRA_WR(_mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
+
+#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
+ BUS_PROT_SMI_WR(BIT(port), \
+ MT8365_SMI_COMMON_CLAMP_EN_SET, \
+ MT8365_SMI_COMMON_CLAMP_EN_CLR, \
+ MT8365_SMI_COMMON_CLAMP_EN)
+
+#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
+ _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
+ BUS_PROT_COMPONENT_INFRA | \
+ BUS_PROT_STA_COMPONENT_INFRA_NAO | \
+ BUS_PROT_INVERTED | \
+ BUS_PROT_REG_UPDATE)
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
+ [MT8365_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x30c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
+ MT8365_BUS_PROT_WAY_EN(
+ MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
+ MT8365_INFRA_TOPAXI_SI0_CTL,
+ MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI0_STA),
+ MT8365_BUS_PROT_WAY_EN(
+ MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
+ MT8365_INFRA_TOPAXI_SI2_CTL,
+ MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI2_STA),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
+ },
+ .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
+ },
+ [MT8365_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
+ },
+ },
+ [MT8365_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(12, 8),
+ .sram_pdn_ack_bits = GENMASK(17, 13),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8365_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8365_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
+ },
+ },
+ [MT8365_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
+ },
+ },
+ [MT8365_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0370,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
+ },
+ },
+ [MT8365_POWER_DOMAIN_APU] = {
+ .name = "apu",
+ .sta_mask = BIT(16),
+ .ctl_offs = 0x0378,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(14, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 15),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
+ },
+ },
+ [MT8365_POWER_DOMAIN_DSP] = {
+ .name = "dsp",
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x037C,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+};
+
+static const struct scpsys_soc_data mt8365_scpsys_data = {
+ .domains_data = scpsys_domain_data_mt8365,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),
+};
+
+#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 5c458aa2ddbe..576d90c3f049 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -24,6 +24,7 @@
#include "mt8188-pm-domains.h"
#include "mt8192-pm-domains.h"
#include "mt8195-pm-domains.h"
+#include "mt8365-pm-domains.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt8195-power-controller",
.data = &mt8195_scpsys_data,
},
+ {
+ .compatible = "mediatek,mt8365-power-controller",
+ .data = &mt8365_scpsys_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index 07f67b3d8e97..f853397697b5 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -2,6 +2,47 @@
#ifndef __SOC_MEDIATEK_INFRACFG_H
#define __SOC_MEDIATEK_INFRACFG_H
+#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
+#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
+#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31)
+
+#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0
+# define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24)
+#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28
+# define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14)
+#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200
+# define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6)
+#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234
+# define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5)
+
+#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0
+#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4
+#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8
+
#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
--
2.40.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
@ 2023-06-19 8:53 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-19 8:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, AngeloGioacchino Del Regno, Tinghan Shen,
Fabien Parent, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Fabien Parent, Markus Schneider-Pargmann
From: Fabien Parent <fparent@baylibre.com>
Add the needed board data to support MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 5 +
include/linux/soc/mediatek/infracfg.h | 41 +++++
3 files changed, 243 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediatek/mt8365-pm-domains.h
new file mode 100644
index 000000000000..02f789e1c65a
--- /dev/null
+++ b/drivers/soc/mediatek/mt8365-pm-domains.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mediatek,mt8365-power.h>
+
+/*
+ * MT8365 power domain support
+ */
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
+ BUS_PROT_INFRA_WR(_mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
+ BUS_PROT_INFRA_WR(_mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
+
+#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
+ BUS_PROT_SMI_WR(BIT(port), \
+ MT8365_SMI_COMMON_CLAMP_EN_SET, \
+ MT8365_SMI_COMMON_CLAMP_EN_CLR, \
+ MT8365_SMI_COMMON_CLAMP_EN)
+
+#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
+ _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
+ BUS_PROT_COMPONENT_INFRA | \
+ BUS_PROT_STA_COMPONENT_INFRA_NAO | \
+ BUS_PROT_INVERTED | \
+ BUS_PROT_REG_UPDATE)
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
+ [MT8365_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x30c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
+ MT8365_BUS_PROT_WAY_EN(
+ MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
+ MT8365_INFRA_TOPAXI_SI0_CTL,
+ MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI0_STA),
+ MT8365_BUS_PROT_WAY_EN(
+ MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
+ MT8365_INFRA_TOPAXI_SI2_CTL,
+ MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI2_STA),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
+ },
+ .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
+ },
+ [MT8365_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
+ },
+ },
+ [MT8365_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(12, 8),
+ .sram_pdn_ack_bits = GENMASK(17, 13),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8365_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8365_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
+ },
+ },
+ [MT8365_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
+ },
+ },
+ [MT8365_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0370,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
+ },
+ },
+ [MT8365_POWER_DOMAIN_APU] = {
+ .name = "apu",
+ .sta_mask = BIT(16),
+ .ctl_offs = 0x0378,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(14, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 15),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
+ },
+ },
+ [MT8365_POWER_DOMAIN_DSP] = {
+ .name = "dsp",
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x037C,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+};
+
+static const struct scpsys_soc_data mt8365_scpsys_data = {
+ .domains_data = scpsys_domain_data_mt8365,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),
+};
+
+#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 5c458aa2ddbe..576d90c3f049 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -24,6 +24,7 @@
#include "mt8188-pm-domains.h"
#include "mt8192-pm-domains.h"
#include "mt8195-pm-domains.h"
+#include "mt8365-pm-domains.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt8195-power-controller",
.data = &mt8195_scpsys_data,
},
+ {
+ .compatible = "mediatek,mt8365-power-controller",
+ .data = &mt8365_scpsys_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index 07f67b3d8e97..f853397697b5 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -2,6 +2,47 @@
#ifndef __SOC_MEDIATEK_INFRACFG_H
#define __SOC_MEDIATEK_INFRACFG_H
+#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
+#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
+#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31)
+
+#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0
+# define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24)
+#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28
+# define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14)
+#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200
+# define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6)
+#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234
+# define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5)
+
+#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0
+#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4
+#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8
+
#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
--
2.40.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 9:22 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-19 9:22 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> Use flags to distinguish between infracfg and smi subsystem for a bus
> protection configuration. It simplifies enabling/disabling and prepares
> the driver for the use of another regmap for mt8365.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
> drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
> drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
> drivers/soc/mediatek/mt8183-pm-domains.h | 198 ++++-----
> drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++++-----
> drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++++------------
> drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++++------
> drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++++----------
> drivers/soc/mediatek/mtk-pm-domains.c | 64 ++-
> drivers/soc/mediatek/mtk-pm-domains.h | 37 +-
> 10 files changed, 908 insertions(+), 899 deletions(-)
>
..snip..
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 4b6ae56e7c95..356788263db2 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -45,6 +45,8 @@
> enum scpsys_bus_prot_flags {
> BUS_PROT_REG_UPDATE = BIT(1),
> BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> + BUS_PROT_COMPONENT_INFRA = BIT(3),
> + BUS_PROT_COMPONENT_SMI = BIT(4),
> };
>
> #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
> @@ -56,17 +58,30 @@ enum scpsys_bus_prot_flags {
> .flags = _flags \
> }
>
> -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
> +#define BUS_PROT_INFRA_WR(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_INFRA)
>
What about doing that like
#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta)
_BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip)
...so that instead of defining BUS_PROT_INFRA_WR, BUS_PROT_SMI_WR and
BUS_PROT_ANOTHERIP_WR, we keep just one macro?
That'd be then like:
.bp_cfg = {
BUS_PROT_WR(INFRA, MT8183_TOP_AXI_PROT_EN_1_DISP,
MT8183_TOP_AXI_PROT_EN_....
....),
BUS_PROT_WR(SMI, MT8183_SMI_COMMON_SMI_CLAMP_DISP,
.....),
}
IMO, that's cleaner, less lines of code and more flexible for eventual
future new variations of that.
Cheers,
Angelo
> -#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
> +#define BUS_PROT_INFRA_WR_IGN(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_INFRA | BUS_PROT_IGNORE_CLR_ACK)
>
> -#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
> +#define BUS_PROT_INFRA_UPDATE(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_INFRA | BUS_PROT_REG_UPDATE)
>
> -#define BUS_PROT_UPDATE_TOPAXI(_mask) \
> - BUS_PROT_UPDATE(_mask, \
> +#define BUS_PROT_SMI_WR(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_SMI)
> +
> +#define BUS_PROT_SMI_WR_IGN(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_SMI | BUS_PROT_IGNORE_CLR_ACK)
> +
> +#define BUS_PROT_SMI_UPDATE(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_SMI | BUS_PROT_REG_UPDATE)
> +
> +#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
> + BUS_PROT_INFRA_UPDATE(_mask, \
> INFRA_TOPAXI_PROTECTEN, \
> INFRA_TOPAXI_PROTECTEN, \
> INFRA_TOPAXI_PROTECTSTA1)
> @@ -90,8 +105,7 @@ struct scpsys_bus_prot_data {
> * @ext_buck_iso_offs: The offset for external buck isolation
> * @ext_buck_iso_mask: The mask for external buck isolation
> * @caps: The flag for active wake-up action.
> - * @bp_infracfg: bus protection for infracfg subsystem
> - * @bp_smi: bus protection for smi subsystem
> + * @bp_cfg: bus protection configuration for any subsystem
> */
> struct scpsys_domain_data {
> const char *name;
> @@ -102,8 +116,7 @@ struct scpsys_domain_data {
> int ext_buck_iso_offs;
> u32 ext_buck_iso_mask;
> u8 caps;
> - const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
> - const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
> + const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
> int pwr_sta_offs;
> int pwr_sta2nd_offs;
> };
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi
@ 2023-06-19 9:22 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-19 9:22 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> Use flags to distinguish between infracfg and smi subsystem for a bus
> protection configuration. It simplifies enabling/disabling and prepares
> the driver for the use of another regmap for mt8365.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
> drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
> drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
> drivers/soc/mediatek/mt8183-pm-domains.h | 198 ++++-----
> drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++++-----
> drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++++------------
> drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++++------
> drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++++----------
> drivers/soc/mediatek/mtk-pm-domains.c | 64 ++-
> drivers/soc/mediatek/mtk-pm-domains.h | 37 +-
> 10 files changed, 908 insertions(+), 899 deletions(-)
>
..snip..
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 4b6ae56e7c95..356788263db2 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -45,6 +45,8 @@
> enum scpsys_bus_prot_flags {
> BUS_PROT_REG_UPDATE = BIT(1),
> BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> + BUS_PROT_COMPONENT_INFRA = BIT(3),
> + BUS_PROT_COMPONENT_SMI = BIT(4),
> };
>
> #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
> @@ -56,17 +58,30 @@ enum scpsys_bus_prot_flags {
> .flags = _flags \
> }
>
> -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
> +#define BUS_PROT_INFRA_WR(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_INFRA)
>
What about doing that like
#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta)
_BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip)
...so that instead of defining BUS_PROT_INFRA_WR, BUS_PROT_SMI_WR and
BUS_PROT_ANOTHERIP_WR, we keep just one macro?
That'd be then like:
.bp_cfg = {
BUS_PROT_WR(INFRA, MT8183_TOP_AXI_PROT_EN_1_DISP,
MT8183_TOP_AXI_PROT_EN_....
....),
BUS_PROT_WR(SMI, MT8183_SMI_COMMON_SMI_CLAMP_DISP,
.....),
}
IMO, that's cleaner, less lines of code and more flexible for eventual
future new variations of that.
Cheers,
Angelo
> -#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
> +#define BUS_PROT_INFRA_WR_IGN(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_INFRA | BUS_PROT_IGNORE_CLR_ACK)
>
> -#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
> +#define BUS_PROT_INFRA_UPDATE(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_INFRA | BUS_PROT_REG_UPDATE)
>
> -#define BUS_PROT_UPDATE_TOPAXI(_mask) \
> - BUS_PROT_UPDATE(_mask, \
> +#define BUS_PROT_SMI_WR(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_SMI)
> +
> +#define BUS_PROT_SMI_WR_IGN(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_SMI | BUS_PROT_IGNORE_CLR_ACK)
> +
> +#define BUS_PROT_SMI_UPDATE(_mask, _set, _clr, _sta) \
> + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_COMPONENT_SMI | BUS_PROT_REG_UPDATE)
> +
> +#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
> + BUS_PROT_INFRA_UPDATE(_mask, \
> INFRA_TOPAXI_PROTECTEN, \
> INFRA_TOPAXI_PROTECTEN, \
> INFRA_TOPAXI_PROTECTSTA1)
> @@ -90,8 +105,7 @@ struct scpsys_bus_prot_data {
> * @ext_buck_iso_offs: The offset for external buck isolation
> * @ext_buck_iso_mask: The mask for external buck isolation
> * @caps: The flag for active wake-up action.
> - * @bp_infracfg: bus protection for infracfg subsystem
> - * @bp_smi: bus protection for smi subsystem
> + * @bp_cfg: bus protection configuration for any subsystem
> */
> struct scpsys_domain_data {
> const char *name;
> @@ -102,8 +116,7 @@ struct scpsys_domain_data {
> int ext_buck_iso_offs;
> u32 ext_buck_iso_mask;
> u8 caps;
> - const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
> - const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
> + const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
> int pwr_sta_offs;
> int pwr_sta2nd_offs;
> };
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 9:29 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-19 9:29 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Alexandre Bailon,
Fabien Parent
Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> From: Alexandre Bailon <abailon@baylibre.com>
>
> This updates the power domain to support WAY_EN operations. WAY_EN
> operations on mt8365 are using a different component to check for the
> acknowledgment, namely the infracfg-nao component. Also to enable a way
> it the bit needs to be cleared while disabling a way needs a bit to be
> set. To support these two operations two flags are added,
> BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
> another regmap is created if the INFRA_NAO capability is set.
>
> This operation is required by the mt8365 for the MM power domain.
>
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
> drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
> 2 files changed, 39 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index 3cdf62c0b6bd..4659f0a0aa08 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -44,6 +44,7 @@ struct scpsys_domain {
> struct clk_bulk_data *clks;
> int num_subsys_clks;
> struct clk_bulk_data *subsys_clks;
> + struct regmap *infracfg_nao;
> struct regmap *infracfg;
> struct regmap *smi;
> struct regulator *supply;
> @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
> return pd->infracfg;
> }
>
> +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
> + const struct scpsys_bus_prot_data *bpd)
> +{
> + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
> + return pd->infracfg_nao;
> + else
> + return scpsys_bus_protect_get_regmap(pd, bpd);
> +}
> +
> static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> const struct scpsys_bus_prot_data *bpd)
> {
> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> + u32 expected_ack;
> u32 val;
> u32 sta_mask = bpd->bus_prot_sta_mask;
>
> + expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
> +
> if (bpd->flags & BUS_PROT_REG_UPDATE)
> regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
> else
> @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
> return 0;
>
> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> - val, !(val & sta_mask),
> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> + val, (val & sta_mask) == expected_ack,
> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> }
>
> static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> const struct scpsys_bus_prot_data *bpd)
> {
> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> u32 val;
> u32 sta_mask = bpd->bus_prot_sta_mask;
> @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> else
> regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
>
> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> val, (val & sta_mask) == sta_mask,
> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> }
> @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> if (!bpd->bus_prot_set_clr_mask)
> break;
>
> - ret = scpsys_bus_protect_set(pd, bpd);
> + if (bpd->flags & BUS_PROT_INVERTED)
> + ret = scpsys_bus_protect_clear(pd, bpd);
> + else
> + ret = scpsys_bus_protect_set(pd, bpd);
> if (ret)
> return ret;
> }
> @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
> if (!bpd->bus_prot_set_clr_mask)
> continue;
>
> - ret = scpsys_bus_protect_clear(pd, bpd);
> + if (bpd->flags & BUS_PROT_INVERTED)
> + ret = scpsys_bus_protect_set(pd, bpd);
> + else
> + ret = scpsys_bus_protect_clear(pd, bpd);
> if (ret)
> return ret;
> }
> @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
> return ERR_CAST(pd->smi);
> }
>
> + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
If we don't expect infracfg-nao to be present, what's the point about trying to
get a regmap handle and then failing only if we do expect it to be there?
At this point you can just do...
if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
pd->infracfg_nao = syscon_regmap_lookup_by_phandle(...);
if (IS_ERR(....))
return ....
}
> + if (IS_ERR(pd->infracfg_nao)) {
> + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
> + return ERR_CAST(pd->infracfg_nao);
> +
> + pd->infracfg_nao = NULL;
> + }
> +
> num_clks = of_clk_get_parent_count(node);
> if (num_clks > 0) {
> /* Calculate number of subsys_clks */
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 356788263db2..562d4e92ce16 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -11,6 +11,7 @@
> /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
> #define MTK_SCPD_ALWAYS_ON BIT(5)
> #define MTK_SCPD_EXT_BUCK_ISO BIT(6)
> +#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
> #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
>
> #define SPM_VDE_PWR_CON 0x0210
> @@ -45,8 +46,10 @@
> enum scpsys_bus_prot_flags {
> BUS_PROT_REG_UPDATE = BIT(1),
> BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> - BUS_PROT_COMPONENT_INFRA = BIT(3),
> - BUS_PROT_COMPONENT_SMI = BIT(4),
> + BUS_PROT_INVERTED = BIT(3),
I get the reason why you're setting inverted as bit 3, but at that point you can
just set BUS_PROT_COMPONENT_INFRA to bit 4 from the very beginning, instead of
using bit 3 for that and then changing them all in a subsequent commit (this one).
Cheers,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
@ 2023-06-19 9:29 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-19 9:29 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Alexandre Bailon,
Fabien Parent
Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> From: Alexandre Bailon <abailon@baylibre.com>
>
> This updates the power domain to support WAY_EN operations. WAY_EN
> operations on mt8365 are using a different component to check for the
> acknowledgment, namely the infracfg-nao component. Also to enable a way
> it the bit needs to be cleared while disabling a way needs a bit to be
> set. To support these two operations two flags are added,
> BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
> another regmap is created if the INFRA_NAO capability is set.
>
> This operation is required by the mt8365 for the MM power domain.
>
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
> drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
> 2 files changed, 39 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index 3cdf62c0b6bd..4659f0a0aa08 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -44,6 +44,7 @@ struct scpsys_domain {
> struct clk_bulk_data *clks;
> int num_subsys_clks;
> struct clk_bulk_data *subsys_clks;
> + struct regmap *infracfg_nao;
> struct regmap *infracfg;
> struct regmap *smi;
> struct regulator *supply;
> @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
> return pd->infracfg;
> }
>
> +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
> + const struct scpsys_bus_prot_data *bpd)
> +{
> + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
> + return pd->infracfg_nao;
> + else
> + return scpsys_bus_protect_get_regmap(pd, bpd);
> +}
> +
> static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> const struct scpsys_bus_prot_data *bpd)
> {
> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> + u32 expected_ack;
> u32 val;
> u32 sta_mask = bpd->bus_prot_sta_mask;
>
> + expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
> +
> if (bpd->flags & BUS_PROT_REG_UPDATE)
> regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
> else
> @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
> return 0;
>
> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> - val, !(val & sta_mask),
> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> + val, (val & sta_mask) == expected_ack,
> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> }
>
> static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> const struct scpsys_bus_prot_data *bpd)
> {
> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> u32 val;
> u32 sta_mask = bpd->bus_prot_sta_mask;
> @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> else
> regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
>
> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> val, (val & sta_mask) == sta_mask,
> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> }
> @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> if (!bpd->bus_prot_set_clr_mask)
> break;
>
> - ret = scpsys_bus_protect_set(pd, bpd);
> + if (bpd->flags & BUS_PROT_INVERTED)
> + ret = scpsys_bus_protect_clear(pd, bpd);
> + else
> + ret = scpsys_bus_protect_set(pd, bpd);
> if (ret)
> return ret;
> }
> @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
> if (!bpd->bus_prot_set_clr_mask)
> continue;
>
> - ret = scpsys_bus_protect_clear(pd, bpd);
> + if (bpd->flags & BUS_PROT_INVERTED)
> + ret = scpsys_bus_protect_set(pd, bpd);
> + else
> + ret = scpsys_bus_protect_clear(pd, bpd);
> if (ret)
> return ret;
> }
> @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
> return ERR_CAST(pd->smi);
> }
>
> + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
If we don't expect infracfg-nao to be present, what's the point about trying to
get a regmap handle and then failing only if we do expect it to be there?
At this point you can just do...
if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
pd->infracfg_nao = syscon_regmap_lookup_by_phandle(...);
if (IS_ERR(....))
return ....
}
> + if (IS_ERR(pd->infracfg_nao)) {
> + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
> + return ERR_CAST(pd->infracfg_nao);
> +
> + pd->infracfg_nao = NULL;
> + }
> +
> num_clks = of_clk_get_parent_count(node);
> if (num_clks > 0) {
> /* Calculate number of subsys_clks */
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 356788263db2..562d4e92ce16 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -11,6 +11,7 @@
> /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
> #define MTK_SCPD_ALWAYS_ON BIT(5)
> #define MTK_SCPD_EXT_BUCK_ISO BIT(6)
> +#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
> #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
>
> #define SPM_VDE_PWR_CON 0x0210
> @@ -45,8 +46,10 @@
> enum scpsys_bus_prot_flags {
> BUS_PROT_REG_UPDATE = BIT(1),
> BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> - BUS_PROT_COMPONENT_INFRA = BIT(3),
> - BUS_PROT_COMPONENT_SMI = BIT(4),
> + BUS_PROT_INVERTED = BIT(3),
I get the reason why you're setting inverted as bit 3, but at that point you can
just set BUS_PROT_COMPONENT_INFRA to bit 4 from the very beginning, instead of
using bit 3 for that and then changing them all in a subsequent commit (this one).
Cheers,
Angelo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 9:32 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-19 9:32 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> To simplify the macros, use a flags field for simple bools. This is in
> preparation for more flags.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/soc/mediatek/mtk-pm-domains.c | 6 +++---
> drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++--------
> 2 files changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index 354249cc1b12..aa9ab413479e 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
> if (!mask)
> break;
>
> - if (bpd[i].bus_prot_reg_update)
> + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
> else
> regmap_write(regmap, bpd[i].bus_prot_set, mask);
> @@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
> if (!mask)
> continue;
>
> - if (bpd[i].bus_prot_reg_update)
> + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
> else
> regmap_write(regmap, bpd[i].bus_prot_clr, mask);
>
> - if (bpd[i].ignore_clr_ack)
> + if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
> continue;
>
> ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 5ec53ee073c4..e26c8c317a6b 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -42,23 +42,27 @@
>
> #define SPM_MAX_BUS_PROT_DATA 6
>
> -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
> +enum scpsys_bus_prot_flags {
> + BUS_PROT_REG_UPDATE = BIT(1),
> + BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> +};
> +
> +#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
> .bus_prot_mask = (_mask), \
> .bus_prot_set = _set, \
> .bus_prot_clr = _clr, \
> .bus_prot_sta = _sta, \
> - .bus_prot_reg_update = _update, \
> - .ignore_clr_ack = _ignore, \
> + .flags = _flags \
> }
>
> #define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _sta, false, false)
> + _BUS_PROT(_mask, _set, _clr, _sta, 0)
>
> #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _sta, false, true)
> + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
>
> #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _sta, true, false)
> + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
>
> #define BUS_PROT_UPDATE_TOPAXI(_mask) \
> BUS_PROT_UPDATE(_mask, \
> @@ -71,8 +75,7 @@ struct scpsys_bus_prot_data {
> u32 bus_prot_set;
> u32 bus_prot_clr;
> u32 bus_prot_sta;
> - bool bus_prot_reg_update;
> - bool ignore_clr_ack;
> + u32 flags;
As far as I understand, we don't expect more than six bits to be populated as bus
protection flags, so we can save some memory by changing that to u8...
...after which:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Regards,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field
@ 2023-06-19 9:32 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-19 9:32 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> To simplify the macros, use a flags field for simple bools. This is in
> preparation for more flags.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/soc/mediatek/mtk-pm-domains.c | 6 +++---
> drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++--------
> 2 files changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index 354249cc1b12..aa9ab413479e 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
> if (!mask)
> break;
>
> - if (bpd[i].bus_prot_reg_update)
> + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
> else
> regmap_write(regmap, bpd[i].bus_prot_set, mask);
> @@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
> if (!mask)
> continue;
>
> - if (bpd[i].bus_prot_reg_update)
> + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
> else
> regmap_write(regmap, bpd[i].bus_prot_clr, mask);
>
> - if (bpd[i].ignore_clr_ack)
> + if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
> continue;
>
> ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 5ec53ee073c4..e26c8c317a6b 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -42,23 +42,27 @@
>
> #define SPM_MAX_BUS_PROT_DATA 6
>
> -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
> +enum scpsys_bus_prot_flags {
> + BUS_PROT_REG_UPDATE = BIT(1),
> + BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> +};
> +
> +#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
> .bus_prot_mask = (_mask), \
> .bus_prot_set = _set, \
> .bus_prot_clr = _clr, \
> .bus_prot_sta = _sta, \
> - .bus_prot_reg_update = _update, \
> - .ignore_clr_ack = _ignore, \
> + .flags = _flags \
> }
>
> #define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _sta, false, false)
> + _BUS_PROT(_mask, _set, _clr, _sta, 0)
>
> #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _sta, false, true)
> + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
>
> #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> - _BUS_PROT(_mask, _set, _clr, _sta, true, false)
> + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
>
> #define BUS_PROT_UPDATE_TOPAXI(_mask) \
> BUS_PROT_UPDATE(_mask, \
> @@ -71,8 +75,7 @@ struct scpsys_bus_prot_data {
> u32 bus_prot_set;
> u32 bus_prot_clr;
> u32 bus_prot_sta;
> - bool bus_prot_reg_update;
> - bool ignore_clr_ack;
> + u32 flags;
As far as I understand, we don't expect more than six bits to be populated as bus
protection flags, so we can save some memory by changing that to u8...
...after which:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Regards,
Angelo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-19 20:47 ` kernel test robot
-1 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2023-06-19 20:47 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: oe-kbuild-all, Chun-Jie Chen, AngeloGioacchino Del Regno,
Tinghan Shen, Fabien Parent, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Markus Schneider-Pargmann
Hi Markus,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk-dt/for-next linus/master v6.4-rc7 next-20230619]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Markus-Schneider-Pargmann/dt-bindings-power-Add-MT8365-power-domains/20230619-165759
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20230619085344.2885311-9-msp%40baylibre.com
patch subject: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230620/202306200439.julbXDpI-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230620/202306200439.julbXDpI-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306200439.julbXDpI-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/bits.h:6,
from include/linux/bitops.h:6,
from include/linux/kernel.h:22,
from include/linux/clk.h:13,
from drivers/soc/mediatek/mtk-pm-domains.c:5:
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'unsigned char' changes value from '384' to '128' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^
drivers/soc/mediatek/mtk-pm-domains.h:15:41: note: in expansion of macro 'BIT'
15 | #define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8)
| ^~~
drivers/soc/mediatek/mt8365-pm-domains.h:69:25: note: in expansion of macro 'MTK_SCPD_STRICT_BUS_PROTECTION'
69 | .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +7 include/vdso/bits.h
3945ff37d2f48d Vincenzo Frascino 2020-03-20 6
3945ff37d2f48d Vincenzo Frascino 2020-03-20 @7 #define BIT(nr) (UL(1) << (nr))
cbdb1f163af2bb Andy Shevchenko 2022-11-28 8 #define BIT_ULL(nr) (ULL(1) << (nr))
3945ff37d2f48d Vincenzo Frascino 2020-03-20 9
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
@ 2023-06-19 20:47 ` kernel test robot
0 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2023-06-19 20:47 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: oe-kbuild-all, Chun-Jie Chen, AngeloGioacchino Del Regno,
Tinghan Shen, Fabien Parent, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Markus Schneider-Pargmann
Hi Markus,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk-dt/for-next linus/master v6.4-rc7 next-20230619]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Markus-Schneider-Pargmann/dt-bindings-power-Add-MT8365-power-domains/20230619-165759
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20230619085344.2885311-9-msp%40baylibre.com
patch subject: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230620/202306200439.julbXDpI-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230620/202306200439.julbXDpI-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306200439.julbXDpI-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/bits.h:6,
from include/linux/bitops.h:6,
from include/linux/kernel.h:22,
from include/linux/clk.h:13,
from drivers/soc/mediatek/mtk-pm-domains.c:5:
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'unsigned char' changes value from '384' to '128' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^
drivers/soc/mediatek/mtk-pm-domains.h:15:41: note: in expansion of macro 'BIT'
15 | #define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8)
| ^~~
drivers/soc/mediatek/mt8365-pm-domains.h:69:25: note: in expansion of macro 'MTK_SCPD_STRICT_BUS_PROTECTION'
69 | .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +7 include/vdso/bits.h
3945ff37d2f48d Vincenzo Frascino 2020-03-20 6
3945ff37d2f48d Vincenzo Frascino 2020-03-20 @7 #define BIT(nr) (UL(1) << (nr))
cbdb1f163af2bb Andy Shevchenko 2022-11-28 8 #define BIT_ULL(nr) (ULL(1) << (nr))
3945ff37d2f48d Vincenzo Frascino 2020-03-20 9
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-20 8:07 ` kernel test robot
-1 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2023-06-20 8:07 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: oe-kbuild-all, Chun-Jie Chen, AngeloGioacchino Del Regno,
Tinghan Shen, Fabien Parent, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Markus Schneider-Pargmann
Hi Markus,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk-dt/for-next linus/master v6.4-rc7 next-20230620]
[cannot apply to mbgg-mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Markus-Schneider-Pargmann/dt-bindings-power-Add-MT8365-power-domains/20230619-165759
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20230619085344.2885311-9-msp%40baylibre.com
patch subject: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
config: arm64-randconfig-s043-20230619 (https://download.01.org/0day-ci/archive/20230620/202306201523.rqsnbV9X-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230620/202306201523.rqsnbV9X-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306201523.rqsnbV9X-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
drivers/soc/mediatek/mtk-pm-domains.c: note: in included file:
>> drivers/soc/mediatek/mt8365-pm-domains.h:69:56: sparse: sparse: cast truncates bits from constant value (180 becomes 80)
vim +69 drivers/soc/mediatek/mt8365-pm-domains.h
8
9 /*
10 * MT8365 power domain support
11 */
12
13 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
14 BUS_PROT_INFRA_WR(_mask, \
15 MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
16 MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
17 MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
18
19 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
20 BUS_PROT_INFRA_WR(_mask, \
21 MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
22 MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
23 MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
24
25 #define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
26 BUS_PROT_SMI_WR(BIT(port), \
27 MT8365_SMI_COMMON_CLAMP_EN_SET, \
28 MT8365_SMI_COMMON_CLAMP_EN_CLR, \
29 MT8365_SMI_COMMON_CLAMP_EN)
30
31 #define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
32 _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
33 BUS_PROT_COMPONENT_INFRA | \
34 BUS_PROT_STA_COMPONENT_INFRA_NAO | \
35 BUS_PROT_INVERTED | \
36 BUS_PROT_REG_UPDATE)
37
38 static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
39 [MT8365_POWER_DOMAIN_MM] = {
40 .name = "mm",
41 .sta_mask = PWR_STATUS_DISP,
42 .ctl_offs = 0x30c,
43 .pwr_sta_offs = 0x0180,
44 .pwr_sta2nd_offs = 0x0184,
45 .sram_pdn_bits = GENMASK(8, 8),
46 .sram_pdn_ack_bits = GENMASK(12, 12),
47 .bp_cfg = {
48 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
49 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
50 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
51 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
52 MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
53 MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
54 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
55 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
56 MT8365_BUS_PROT_WAY_EN(
57 MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
58 MT8365_INFRA_TOPAXI_SI0_CTL,
59 MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
60 MT8365_INFRA_NAO_TOPAXI_SI0_STA),
61 MT8365_BUS_PROT_WAY_EN(
62 MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
63 MT8365_INFRA_TOPAXI_SI2_CTL,
64 MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
65 MT8365_INFRA_NAO_TOPAXI_SI2_STA),
66 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
67 MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
68 },
> 69 .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
70 },
71 [MT8365_POWER_DOMAIN_VENC] = {
72 .name = "venc",
73 .sta_mask = PWR_STATUS_VENC,
74 .ctl_offs = 0x0304,
75 .pwr_sta_offs = 0x0180,
76 .pwr_sta2nd_offs = 0x0184,
77 .sram_pdn_bits = GENMASK(8, 8),
78 .sram_pdn_ack_bits = GENMASK(12, 12),
79 .bp_cfg = {
80 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
81 },
82 },
83 [MT8365_POWER_DOMAIN_AUDIO] = {
84 .name = "audio",
85 .sta_mask = PWR_STATUS_AUDIO,
86 .ctl_offs = 0x0314,
87 .pwr_sta_offs = 0x0180,
88 .pwr_sta2nd_offs = 0x0184,
89 .sram_pdn_bits = GENMASK(12, 8),
90 .sram_pdn_ack_bits = GENMASK(17, 13),
91 .bp_cfg = {
92 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
93 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
94 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
95 },
96 .caps = MTK_SCPD_ACTIVE_WAKEUP,
97 },
98 [MT8365_POWER_DOMAIN_CONN] = {
99 .name = "conn",
100 .sta_mask = PWR_STATUS_CONN,
101 .ctl_offs = 0x032c,
102 .pwr_sta_offs = 0x0180,
103 .pwr_sta2nd_offs = 0x0184,
104 .sram_pdn_bits = 0,
105 .sram_pdn_ack_bits = 0,
106 .bp_cfg = {
107 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
108 MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
109 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
110 MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
111 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
112 MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
113 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
114 MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
115 },
116 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
117 },
118 [MT8365_POWER_DOMAIN_MFG] = {
119 .name = "mfg",
120 .sta_mask = PWR_STATUS_MFG,
121 .ctl_offs = 0x0338,
122 .pwr_sta_offs = 0x0180,
123 .pwr_sta2nd_offs = 0x0184,
124 .sram_pdn_bits = GENMASK(9, 8),
125 .sram_pdn_ack_bits = GENMASK(13, 12),
126 .bp_cfg = {
127 MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
128 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
129 MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
130 MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
131 },
132 },
133 [MT8365_POWER_DOMAIN_CAM] = {
134 .name = "cam",
135 .sta_mask = BIT(25),
136 .ctl_offs = 0x0344,
137 .pwr_sta_offs = 0x0180,
138 .pwr_sta2nd_offs = 0x0184,
139 .sram_pdn_bits = GENMASK(9, 8),
140 .sram_pdn_ack_bits = GENMASK(13, 12),
141 .bp_cfg = {
142 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
143 MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
144 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
145 },
146 },
147 [MT8365_POWER_DOMAIN_VDEC] = {
148 .name = "vdec",
149 .sta_mask = BIT(31),
150 .ctl_offs = 0x0370,
151 .pwr_sta_offs = 0x0180,
152 .pwr_sta2nd_offs = 0x0184,
153 .sram_pdn_bits = GENMASK(8, 8),
154 .sram_pdn_ack_bits = GENMASK(12, 12),
155 .bp_cfg = {
156 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
157 },
158 },
159 [MT8365_POWER_DOMAIN_APU] = {
160 .name = "apu",
161 .sta_mask = BIT(16),
162 .ctl_offs = 0x0378,
163 .pwr_sta_offs = 0x0180,
164 .pwr_sta2nd_offs = 0x0184,
165 .sram_pdn_bits = GENMASK(14, 8),
166 .sram_pdn_ack_bits = GENMASK(21, 15),
167 .bp_cfg = {
168 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
169 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
170 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
171 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
172 },
173 },
174 [MT8365_POWER_DOMAIN_DSP] = {
175 .name = "dsp",
176 .sta_mask = BIT(17),
177 .ctl_offs = 0x037C,
178 .pwr_sta_offs = 0x0180,
179 .pwr_sta2nd_offs = 0x0184,
180 .sram_pdn_bits = GENMASK(11, 8),
181 .sram_pdn_ack_bits = GENMASK(15, 12),
182 .bp_cfg = {
183 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
184 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
185 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
186 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
187 },
188 .caps = MTK_SCPD_ACTIVE_WAKEUP,
189 },
190 };
191
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
@ 2023-06-20 8:07 ` kernel test robot
0 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2023-06-20 8:07 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: oe-kbuild-all, Chun-Jie Chen, AngeloGioacchino Del Regno,
Tinghan Shen, Fabien Parent, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Markus Schneider-Pargmann
Hi Markus,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk-dt/for-next linus/master v6.4-rc7 next-20230620]
[cannot apply to mbgg-mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Markus-Schneider-Pargmann/dt-bindings-power-Add-MT8365-power-domains/20230619-165759
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20230619085344.2885311-9-msp%40baylibre.com
patch subject: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
config: arm64-randconfig-s043-20230619 (https://download.01.org/0day-ci/archive/20230620/202306201523.rqsnbV9X-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230620/202306201523.rqsnbV9X-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306201523.rqsnbV9X-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
drivers/soc/mediatek/mtk-pm-domains.c: note: in included file:
>> drivers/soc/mediatek/mt8365-pm-domains.h:69:56: sparse: sparse: cast truncates bits from constant value (180 becomes 80)
vim +69 drivers/soc/mediatek/mt8365-pm-domains.h
8
9 /*
10 * MT8365 power domain support
11 */
12
13 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
14 BUS_PROT_INFRA_WR(_mask, \
15 MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
16 MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
17 MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
18
19 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
20 BUS_PROT_INFRA_WR(_mask, \
21 MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
22 MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
23 MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
24
25 #define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
26 BUS_PROT_SMI_WR(BIT(port), \
27 MT8365_SMI_COMMON_CLAMP_EN_SET, \
28 MT8365_SMI_COMMON_CLAMP_EN_CLR, \
29 MT8365_SMI_COMMON_CLAMP_EN)
30
31 #define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
32 _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
33 BUS_PROT_COMPONENT_INFRA | \
34 BUS_PROT_STA_COMPONENT_INFRA_NAO | \
35 BUS_PROT_INVERTED | \
36 BUS_PROT_REG_UPDATE)
37
38 static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
39 [MT8365_POWER_DOMAIN_MM] = {
40 .name = "mm",
41 .sta_mask = PWR_STATUS_DISP,
42 .ctl_offs = 0x30c,
43 .pwr_sta_offs = 0x0180,
44 .pwr_sta2nd_offs = 0x0184,
45 .sram_pdn_bits = GENMASK(8, 8),
46 .sram_pdn_ack_bits = GENMASK(12, 12),
47 .bp_cfg = {
48 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
49 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
50 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
51 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
52 MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
53 MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
54 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
55 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
56 MT8365_BUS_PROT_WAY_EN(
57 MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
58 MT8365_INFRA_TOPAXI_SI0_CTL,
59 MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
60 MT8365_INFRA_NAO_TOPAXI_SI0_STA),
61 MT8365_BUS_PROT_WAY_EN(
62 MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
63 MT8365_INFRA_TOPAXI_SI2_CTL,
64 MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
65 MT8365_INFRA_NAO_TOPAXI_SI2_STA),
66 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
67 MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
68 },
> 69 .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
70 },
71 [MT8365_POWER_DOMAIN_VENC] = {
72 .name = "venc",
73 .sta_mask = PWR_STATUS_VENC,
74 .ctl_offs = 0x0304,
75 .pwr_sta_offs = 0x0180,
76 .pwr_sta2nd_offs = 0x0184,
77 .sram_pdn_bits = GENMASK(8, 8),
78 .sram_pdn_ack_bits = GENMASK(12, 12),
79 .bp_cfg = {
80 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
81 },
82 },
83 [MT8365_POWER_DOMAIN_AUDIO] = {
84 .name = "audio",
85 .sta_mask = PWR_STATUS_AUDIO,
86 .ctl_offs = 0x0314,
87 .pwr_sta_offs = 0x0180,
88 .pwr_sta2nd_offs = 0x0184,
89 .sram_pdn_bits = GENMASK(12, 8),
90 .sram_pdn_ack_bits = GENMASK(17, 13),
91 .bp_cfg = {
92 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
93 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
94 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
95 },
96 .caps = MTK_SCPD_ACTIVE_WAKEUP,
97 },
98 [MT8365_POWER_DOMAIN_CONN] = {
99 .name = "conn",
100 .sta_mask = PWR_STATUS_CONN,
101 .ctl_offs = 0x032c,
102 .pwr_sta_offs = 0x0180,
103 .pwr_sta2nd_offs = 0x0184,
104 .sram_pdn_bits = 0,
105 .sram_pdn_ack_bits = 0,
106 .bp_cfg = {
107 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
108 MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
109 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
110 MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
111 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
112 MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
113 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
114 MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
115 },
116 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
117 },
118 [MT8365_POWER_DOMAIN_MFG] = {
119 .name = "mfg",
120 .sta_mask = PWR_STATUS_MFG,
121 .ctl_offs = 0x0338,
122 .pwr_sta_offs = 0x0180,
123 .pwr_sta2nd_offs = 0x0184,
124 .sram_pdn_bits = GENMASK(9, 8),
125 .sram_pdn_ack_bits = GENMASK(13, 12),
126 .bp_cfg = {
127 MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
128 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
129 MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
130 MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
131 },
132 },
133 [MT8365_POWER_DOMAIN_CAM] = {
134 .name = "cam",
135 .sta_mask = BIT(25),
136 .ctl_offs = 0x0344,
137 .pwr_sta_offs = 0x0180,
138 .pwr_sta2nd_offs = 0x0184,
139 .sram_pdn_bits = GENMASK(9, 8),
140 .sram_pdn_ack_bits = GENMASK(13, 12),
141 .bp_cfg = {
142 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
143 MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
144 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
145 },
146 },
147 [MT8365_POWER_DOMAIN_VDEC] = {
148 .name = "vdec",
149 .sta_mask = BIT(31),
150 .ctl_offs = 0x0370,
151 .pwr_sta_offs = 0x0180,
152 .pwr_sta2nd_offs = 0x0184,
153 .sram_pdn_bits = GENMASK(8, 8),
154 .sram_pdn_ack_bits = GENMASK(12, 12),
155 .bp_cfg = {
156 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
157 },
158 },
159 [MT8365_POWER_DOMAIN_APU] = {
160 .name = "apu",
161 .sta_mask = BIT(16),
162 .ctl_offs = 0x0378,
163 .pwr_sta_offs = 0x0180,
164 .pwr_sta2nd_offs = 0x0184,
165 .sram_pdn_bits = GENMASK(14, 8),
166 .sram_pdn_ack_bits = GENMASK(21, 15),
167 .bp_cfg = {
168 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
169 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
170 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
171 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
172 },
173 },
174 [MT8365_POWER_DOMAIN_DSP] = {
175 .name = "dsp",
176 .sta_mask = BIT(17),
177 .ctl_offs = 0x037C,
178 .pwr_sta_offs = 0x0180,
179 .pwr_sta2nd_offs = 0x0184,
180 .sram_pdn_bits = GENMASK(11, 8),
181 .sram_pdn_ack_bits = GENMASK(15, 12),
182 .bp_cfg = {
183 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
184 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
185 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
186 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
187 },
188 .caps = MTK_SCPD_ACTIVE_WAKEUP,
189 },
190 };
191
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
2023-06-19 8:53 ` Markus Schneider-Pargmann
@ 2023-06-22 2:05 ` kernel test robot
-1 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2023-06-22 2:05 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: llvm, oe-kbuild-all, Chun-Jie Chen, AngeloGioacchino Del Regno,
Tinghan Shen, Fabien Parent, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Markus Schneider-Pargmann
Hi Markus,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk-dt/for-next linus/master v6.4-rc7 next-20230621]
[cannot apply to mbgg-mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Markus-Schneider-Pargmann/dt-bindings-power-Add-MT8365-power-domains/20230619-165759
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20230619085344.2885311-9-msp%40baylibre.com
patch subject: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
config: arm64-randconfig-r011-20230621 (https://download.01.org/0day-ci/archive/20230622/202306220952.WMdPoLzE-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce: (https://download.01.org/0day-ci/archive/20230622/202306220952.WMdPoLzE-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306220952.WMdPoLzE-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/soc/mediatek/mtk-pm-domains.c:27:
>> drivers/soc/mediatek/mt8365-pm-domains.h:69:42: warning: implicit conversion from 'unsigned long' to 'u8' (aka 'unsigned char') changes value from 384 to 128 [-Wconstant-conversion]
69 | .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +69 drivers/soc/mediatek/mt8365-pm-domains.h
8
9 /*
10 * MT8365 power domain support
11 */
12
13 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
14 BUS_PROT_INFRA_WR(_mask, \
15 MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
16 MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
17 MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
18
19 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
20 BUS_PROT_INFRA_WR(_mask, \
21 MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
22 MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
23 MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
24
25 #define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
26 BUS_PROT_SMI_WR(BIT(port), \
27 MT8365_SMI_COMMON_CLAMP_EN_SET, \
28 MT8365_SMI_COMMON_CLAMP_EN_CLR, \
29 MT8365_SMI_COMMON_CLAMP_EN)
30
31 #define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
32 _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
33 BUS_PROT_COMPONENT_INFRA | \
34 BUS_PROT_STA_COMPONENT_INFRA_NAO | \
35 BUS_PROT_INVERTED | \
36 BUS_PROT_REG_UPDATE)
37
38 static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
39 [MT8365_POWER_DOMAIN_MM] = {
40 .name = "mm",
41 .sta_mask = PWR_STATUS_DISP,
42 .ctl_offs = 0x30c,
43 .pwr_sta_offs = 0x0180,
44 .pwr_sta2nd_offs = 0x0184,
45 .sram_pdn_bits = GENMASK(8, 8),
46 .sram_pdn_ack_bits = GENMASK(12, 12),
47 .bp_cfg = {
48 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
49 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
50 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
51 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
52 MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
53 MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
54 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
55 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
56 MT8365_BUS_PROT_WAY_EN(
57 MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
58 MT8365_INFRA_TOPAXI_SI0_CTL,
59 MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
60 MT8365_INFRA_NAO_TOPAXI_SI0_STA),
61 MT8365_BUS_PROT_WAY_EN(
62 MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
63 MT8365_INFRA_TOPAXI_SI2_CTL,
64 MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
65 MT8365_INFRA_NAO_TOPAXI_SI2_STA),
66 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
67 MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
68 },
> 69 .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
70 },
71 [MT8365_POWER_DOMAIN_VENC] = {
72 .name = "venc",
73 .sta_mask = PWR_STATUS_VENC,
74 .ctl_offs = 0x0304,
75 .pwr_sta_offs = 0x0180,
76 .pwr_sta2nd_offs = 0x0184,
77 .sram_pdn_bits = GENMASK(8, 8),
78 .sram_pdn_ack_bits = GENMASK(12, 12),
79 .bp_cfg = {
80 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
81 },
82 },
83 [MT8365_POWER_DOMAIN_AUDIO] = {
84 .name = "audio",
85 .sta_mask = PWR_STATUS_AUDIO,
86 .ctl_offs = 0x0314,
87 .pwr_sta_offs = 0x0180,
88 .pwr_sta2nd_offs = 0x0184,
89 .sram_pdn_bits = GENMASK(12, 8),
90 .sram_pdn_ack_bits = GENMASK(17, 13),
91 .bp_cfg = {
92 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
93 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
94 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
95 },
96 .caps = MTK_SCPD_ACTIVE_WAKEUP,
97 },
98 [MT8365_POWER_DOMAIN_CONN] = {
99 .name = "conn",
100 .sta_mask = PWR_STATUS_CONN,
101 .ctl_offs = 0x032c,
102 .pwr_sta_offs = 0x0180,
103 .pwr_sta2nd_offs = 0x0184,
104 .sram_pdn_bits = 0,
105 .sram_pdn_ack_bits = 0,
106 .bp_cfg = {
107 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
108 MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
109 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
110 MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
111 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
112 MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
113 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
114 MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
115 },
116 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
117 },
118 [MT8365_POWER_DOMAIN_MFG] = {
119 .name = "mfg",
120 .sta_mask = PWR_STATUS_MFG,
121 .ctl_offs = 0x0338,
122 .pwr_sta_offs = 0x0180,
123 .pwr_sta2nd_offs = 0x0184,
124 .sram_pdn_bits = GENMASK(9, 8),
125 .sram_pdn_ack_bits = GENMASK(13, 12),
126 .bp_cfg = {
127 MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
128 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
129 MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
130 MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
131 },
132 },
133 [MT8365_POWER_DOMAIN_CAM] = {
134 .name = "cam",
135 .sta_mask = BIT(25),
136 .ctl_offs = 0x0344,
137 .pwr_sta_offs = 0x0180,
138 .pwr_sta2nd_offs = 0x0184,
139 .sram_pdn_bits = GENMASK(9, 8),
140 .sram_pdn_ack_bits = GENMASK(13, 12),
141 .bp_cfg = {
142 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
143 MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
144 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
145 },
146 },
147 [MT8365_POWER_DOMAIN_VDEC] = {
148 .name = "vdec",
149 .sta_mask = BIT(31),
150 .ctl_offs = 0x0370,
151 .pwr_sta_offs = 0x0180,
152 .pwr_sta2nd_offs = 0x0184,
153 .sram_pdn_bits = GENMASK(8, 8),
154 .sram_pdn_ack_bits = GENMASK(12, 12),
155 .bp_cfg = {
156 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
157 },
158 },
159 [MT8365_POWER_DOMAIN_APU] = {
160 .name = "apu",
161 .sta_mask = BIT(16),
162 .ctl_offs = 0x0378,
163 .pwr_sta_offs = 0x0180,
164 .pwr_sta2nd_offs = 0x0184,
165 .sram_pdn_bits = GENMASK(14, 8),
166 .sram_pdn_ack_bits = GENMASK(21, 15),
167 .bp_cfg = {
168 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
169 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
170 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
171 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
172 },
173 },
174 [MT8365_POWER_DOMAIN_DSP] = {
175 .name = "dsp",
176 .sta_mask = BIT(17),
177 .ctl_offs = 0x037C,
178 .pwr_sta_offs = 0x0180,
179 .pwr_sta2nd_offs = 0x0184,
180 .sram_pdn_bits = GENMASK(11, 8),
181 .sram_pdn_ack_bits = GENMASK(15, 12),
182 .bp_cfg = {
183 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
184 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
185 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
186 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
187 },
188 .caps = MTK_SCPD_ACTIVE_WAKEUP,
189 },
190 };
191
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
@ 2023-06-22 2:05 ` kernel test robot
0 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2023-06-22 2:05 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger
Cc: llvm, oe-kbuild-all, Chun-Jie Chen, AngeloGioacchino Del Regno,
Tinghan Shen, Fabien Parent, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Markus Schneider-Pargmann
Hi Markus,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk-dt/for-next linus/master v6.4-rc7 next-20230621]
[cannot apply to mbgg-mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Markus-Schneider-Pargmann/dt-bindings-power-Add-MT8365-power-domains/20230619-165759
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20230619085344.2885311-9-msp%40baylibre.com
patch subject: [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365
config: arm64-randconfig-r011-20230621 (https://download.01.org/0day-ci/archive/20230622/202306220952.WMdPoLzE-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce: (https://download.01.org/0day-ci/archive/20230622/202306220952.WMdPoLzE-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306220952.WMdPoLzE-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/soc/mediatek/mtk-pm-domains.c:27:
>> drivers/soc/mediatek/mt8365-pm-domains.h:69:42: warning: implicit conversion from 'unsigned long' to 'u8' (aka 'unsigned char') changes value from 384 to 128 [-Wconstant-conversion]
69 | .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +69 drivers/soc/mediatek/mt8365-pm-domains.h
8
9 /*
10 * MT8365 power domain support
11 */
12
13 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
14 BUS_PROT_INFRA_WR(_mask, \
15 MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
16 MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
17 MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
18
19 #define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
20 BUS_PROT_INFRA_WR(_mask, \
21 MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
22 MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
23 MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
24
25 #define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
26 BUS_PROT_SMI_WR(BIT(port), \
27 MT8365_SMI_COMMON_CLAMP_EN_SET, \
28 MT8365_SMI_COMMON_CLAMP_EN_CLR, \
29 MT8365_SMI_COMMON_CLAMP_EN)
30
31 #define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
32 _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
33 BUS_PROT_COMPONENT_INFRA | \
34 BUS_PROT_STA_COMPONENT_INFRA_NAO | \
35 BUS_PROT_INVERTED | \
36 BUS_PROT_REG_UPDATE)
37
38 static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
39 [MT8365_POWER_DOMAIN_MM] = {
40 .name = "mm",
41 .sta_mask = PWR_STATUS_DISP,
42 .ctl_offs = 0x30c,
43 .pwr_sta_offs = 0x0180,
44 .pwr_sta2nd_offs = 0x0184,
45 .sram_pdn_bits = GENMASK(8, 8),
46 .sram_pdn_ack_bits = GENMASK(12, 12),
47 .bp_cfg = {
48 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
49 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
50 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
51 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
52 MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
53 MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
54 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
55 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
56 MT8365_BUS_PROT_WAY_EN(
57 MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
58 MT8365_INFRA_TOPAXI_SI0_CTL,
59 MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
60 MT8365_INFRA_NAO_TOPAXI_SI0_STA),
61 MT8365_BUS_PROT_WAY_EN(
62 MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
63 MT8365_INFRA_TOPAXI_SI2_CTL,
64 MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
65 MT8365_INFRA_NAO_TOPAXI_SI2_STA),
66 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
67 MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
68 },
> 69 .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
70 },
71 [MT8365_POWER_DOMAIN_VENC] = {
72 .name = "venc",
73 .sta_mask = PWR_STATUS_VENC,
74 .ctl_offs = 0x0304,
75 .pwr_sta_offs = 0x0180,
76 .pwr_sta2nd_offs = 0x0184,
77 .sram_pdn_bits = GENMASK(8, 8),
78 .sram_pdn_ack_bits = GENMASK(12, 12),
79 .bp_cfg = {
80 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
81 },
82 },
83 [MT8365_POWER_DOMAIN_AUDIO] = {
84 .name = "audio",
85 .sta_mask = PWR_STATUS_AUDIO,
86 .ctl_offs = 0x0314,
87 .pwr_sta_offs = 0x0180,
88 .pwr_sta2nd_offs = 0x0184,
89 .sram_pdn_bits = GENMASK(12, 8),
90 .sram_pdn_ack_bits = GENMASK(17, 13),
91 .bp_cfg = {
92 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
93 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
94 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
95 },
96 .caps = MTK_SCPD_ACTIVE_WAKEUP,
97 },
98 [MT8365_POWER_DOMAIN_CONN] = {
99 .name = "conn",
100 .sta_mask = PWR_STATUS_CONN,
101 .ctl_offs = 0x032c,
102 .pwr_sta_offs = 0x0180,
103 .pwr_sta2nd_offs = 0x0184,
104 .sram_pdn_bits = 0,
105 .sram_pdn_ack_bits = 0,
106 .bp_cfg = {
107 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
108 MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
109 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
110 MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
111 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
112 MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
113 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
114 MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
115 },
116 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
117 },
118 [MT8365_POWER_DOMAIN_MFG] = {
119 .name = "mfg",
120 .sta_mask = PWR_STATUS_MFG,
121 .ctl_offs = 0x0338,
122 .pwr_sta_offs = 0x0180,
123 .pwr_sta2nd_offs = 0x0184,
124 .sram_pdn_bits = GENMASK(9, 8),
125 .sram_pdn_ack_bits = GENMASK(13, 12),
126 .bp_cfg = {
127 MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
128 MT8365_BUS_PROT_INFRA_WR_TOPAXI(
129 MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
130 MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
131 },
132 },
133 [MT8365_POWER_DOMAIN_CAM] = {
134 .name = "cam",
135 .sta_mask = BIT(25),
136 .ctl_offs = 0x0344,
137 .pwr_sta_offs = 0x0180,
138 .pwr_sta2nd_offs = 0x0184,
139 .sram_pdn_bits = GENMASK(9, 8),
140 .sram_pdn_ack_bits = GENMASK(13, 12),
141 .bp_cfg = {
142 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
143 MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
144 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
145 },
146 },
147 [MT8365_POWER_DOMAIN_VDEC] = {
148 .name = "vdec",
149 .sta_mask = BIT(31),
150 .ctl_offs = 0x0370,
151 .pwr_sta_offs = 0x0180,
152 .pwr_sta2nd_offs = 0x0184,
153 .sram_pdn_bits = GENMASK(8, 8),
154 .sram_pdn_ack_bits = GENMASK(12, 12),
155 .bp_cfg = {
156 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
157 },
158 },
159 [MT8365_POWER_DOMAIN_APU] = {
160 .name = "apu",
161 .sta_mask = BIT(16),
162 .ctl_offs = 0x0378,
163 .pwr_sta_offs = 0x0180,
164 .pwr_sta2nd_offs = 0x0184,
165 .sram_pdn_bits = GENMASK(14, 8),
166 .sram_pdn_ack_bits = GENMASK(21, 15),
167 .bp_cfg = {
168 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
169 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
170 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
171 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
172 },
173 },
174 [MT8365_POWER_DOMAIN_DSP] = {
175 .name = "dsp",
176 .sta_mask = BIT(17),
177 .ctl_offs = 0x037C,
178 .pwr_sta_offs = 0x0180,
179 .pwr_sta2nd_offs = 0x0184,
180 .sram_pdn_bits = GENMASK(11, 8),
181 .sram_pdn_ack_bits = GENMASK(15, 12),
182 .bp_cfg = {
183 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
184 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
185 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
186 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
187 },
188 .caps = MTK_SCPD_ACTIVE_WAKEUP,
189 },
190 };
191
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field
2023-06-19 9:32 ` AngeloGioacchino Del Regno
@ 2023-06-22 8:28 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-22 8:28 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Hi Angelo,
On Mon, Jun 19, 2023 at 11:32:18AM +0200, AngeloGioacchino Del Regno wrote:
> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> > To simplify the macros, use a flags field for simple bools. This is in
> > preparation for more flags.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/soc/mediatek/mtk-pm-domains.c | 6 +++---
> > drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++--------
> > 2 files changed, 14 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> > index 354249cc1b12..aa9ab413479e 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.c
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> > @@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
> > if (!mask)
> > break;
> > - if (bpd[i].bus_prot_reg_update)
> > + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> > regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
> > else
> > regmap_write(regmap, bpd[i].bus_prot_set, mask);
> > @@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
> > if (!mask)
> > continue;
> > - if (bpd[i].bus_prot_reg_update)
> > + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> > regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
> > else
> > regmap_write(regmap, bpd[i].bus_prot_clr, mask);
> > - if (bpd[i].ignore_clr_ack)
> > + if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
> > continue;
> > ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> > index 5ec53ee073c4..e26c8c317a6b 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.h
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> > @@ -42,23 +42,27 @@
> > #define SPM_MAX_BUS_PROT_DATA 6
> > -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
> > +enum scpsys_bus_prot_flags {
> > + BUS_PROT_REG_UPDATE = BIT(1),
> > + BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> > +};
> > +
> > +#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
> > .bus_prot_mask = (_mask), \
> > .bus_prot_set = _set, \
> > .bus_prot_clr = _clr, \
> > .bus_prot_sta = _sta, \
> > - .bus_prot_reg_update = _update, \
> > - .ignore_clr_ack = _ignore, \
> > + .flags = _flags \
> > }
> > #define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _sta, false, false)
> > + _BUS_PROT(_mask, _set, _clr, _sta, 0)
> > #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _sta, false, true)
> > + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
> > #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _sta, true, false)
> > + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
> > #define BUS_PROT_UPDATE_TOPAXI(_mask) \
> > BUS_PROT_UPDATE(_mask, \
> > @@ -71,8 +75,7 @@ struct scpsys_bus_prot_data {
> > u32 bus_prot_set;
> > u32 bus_prot_clr;
> > u32 bus_prot_sta;
> > - bool bus_prot_reg_update;
> > - bool ignore_clr_ack;
> > + u32 flags;
>
> As far as I understand, we don't expect more than six bits to be populated as bus
> protection flags, so we can save some memory by changing that to u8...
Thank you. Yes, also we can change it later if we need more flags at
some point. I will change it. But I guess it won't save any memory as
the compiler probably aligns the struct.
Best,
Markus
>
> ...after which:
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Regards,
> Angelo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field
@ 2023-06-22 8:28 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-22 8:28 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
Hi Angelo,
On Mon, Jun 19, 2023 at 11:32:18AM +0200, AngeloGioacchino Del Regno wrote:
> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> > To simplify the macros, use a flags field for simple bools. This is in
> > preparation for more flags.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/soc/mediatek/mtk-pm-domains.c | 6 +++---
> > drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++--------
> > 2 files changed, 14 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> > index 354249cc1b12..aa9ab413479e 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.c
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> > @@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st
> > if (!mask)
> > break;
> > - if (bpd[i].bus_prot_reg_update)
> > + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> > regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
> > else
> > regmap_write(regmap, bpd[i].bus_prot_set, mask);
> > @@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
> > if (!mask)
> > continue;
> > - if (bpd[i].bus_prot_reg_update)
> > + if (bpd[i].flags & BUS_PROT_REG_UPDATE)
> > regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
> > else
> > regmap_write(regmap, bpd[i].bus_prot_clr, mask);
> > - if (bpd[i].ignore_clr_ack)
> > + if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK)
> > continue;
> > ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> > index 5ec53ee073c4..e26c8c317a6b 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.h
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> > @@ -42,23 +42,27 @@
> > #define SPM_MAX_BUS_PROT_DATA 6
> > -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
> > +enum scpsys_bus_prot_flags {
> > + BUS_PROT_REG_UPDATE = BIT(1),
> > + BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> > +};
> > +
> > +#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \
> > .bus_prot_mask = (_mask), \
> > .bus_prot_set = _set, \
> > .bus_prot_clr = _clr, \
> > .bus_prot_sta = _sta, \
> > - .bus_prot_reg_update = _update, \
> > - .ignore_clr_ack = _ignore, \
> > + .flags = _flags \
> > }
> > #define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _sta, false, false)
> > + _BUS_PROT(_mask, _set, _clr, _sta, 0)
> > #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _sta, false, true)
> > + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK)
> > #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _sta, true, false)
> > + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE)
> > #define BUS_PROT_UPDATE_TOPAXI(_mask) \
> > BUS_PROT_UPDATE(_mask, \
> > @@ -71,8 +75,7 @@ struct scpsys_bus_prot_data {
> > u32 bus_prot_set;
> > u32 bus_prot_clr;
> > u32 bus_prot_sta;
> > - bool bus_prot_reg_update;
> > - bool ignore_clr_ack;
> > + u32 flags;
>
> As far as I understand, we don't expect more than six bits to be populated as bus
> protection flags, so we can save some memory by changing that to u8...
Thank you. Yes, also we can change it later if we need more flags at
some point. I will change it. But I guess it won't save any memory as
the compiler probably aligns the struct.
Best,
Markus
>
> ...after which:
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Regards,
> Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi
2023-06-19 9:22 ` AngeloGioacchino Del Regno
@ 2023-06-22 8:32 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-22 8:32 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On Mon, Jun 19, 2023 at 11:22:18AM +0200, AngeloGioacchino Del Regno wrote:
> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> > Use flags to distinguish between infracfg and smi subsystem for a bus
> > protection configuration. It simplifies enabling/disabling and prepares
> > the driver for the use of another regmap for mt8365.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
> > drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
> > drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
> > drivers/soc/mediatek/mt8183-pm-domains.h | 198 ++++-----
> > drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++++-----
> > drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++++------------
> > drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++++------
> > drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++++----------
> > drivers/soc/mediatek/mtk-pm-domains.c | 64 ++-
> > drivers/soc/mediatek/mtk-pm-domains.h | 37 +-
> > 10 files changed, 908 insertions(+), 899 deletions(-)
> >
>
> ..snip..
>
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> > index 4b6ae56e7c95..356788263db2 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.h
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> > @@ -45,6 +45,8 @@
> > enum scpsys_bus_prot_flags {
> > BUS_PROT_REG_UPDATE = BIT(1),
> > BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> > + BUS_PROT_COMPONENT_INFRA = BIT(3),
> > + BUS_PROT_COMPONENT_SMI = BIT(4),
> > };
> > #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
> > @@ -56,17 +58,30 @@ enum scpsys_bus_prot_flags {
> > .flags = _flags \
> > }
> > -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
> > +#define BUS_PROT_INFRA_WR(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_INFRA)
>
> What about doing that like
>
> #define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta)
> _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip)
>
> ...so that instead of defining BUS_PROT_INFRA_WR, BUS_PROT_SMI_WR and
> BUS_PROT_ANOTHERIP_WR, we keep just one macro?
>
> That'd be then like:
>
> .bp_cfg = {
> BUS_PROT_WR(INFRA, MT8183_TOP_AXI_PROT_EN_1_DISP,
> MT8183_TOP_AXI_PROT_EN_....
> ....),
> BUS_PROT_WR(SMI, MT8183_SMI_COMMON_SMI_CLAMP_DISP,
> .....),
> }
>
> IMO, that's cleaner, less lines of code and more flexible for eventual
> future new variations of that.
Yes it would be much cleaner, though it is a bit more intransparent how
these macros are resolved. Anyways I think it being cleaner outweighs
that. I will change it for the next version.
Thanks,
Markus
>
> Cheers,
> Angelo
>
> > -#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
> > +#define BUS_PROT_INFRA_WR_IGN(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_INFRA | BUS_PROT_IGNORE_CLR_ACK)
> > -#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
> > +#define BUS_PROT_INFRA_UPDATE(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_INFRA | BUS_PROT_REG_UPDATE)
> > -#define BUS_PROT_UPDATE_TOPAXI(_mask) \
> > - BUS_PROT_UPDATE(_mask, \
> > +#define BUS_PROT_SMI_WR(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_SMI)
> > +
> > +#define BUS_PROT_SMI_WR_IGN(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_SMI | BUS_PROT_IGNORE_CLR_ACK)
> > +
> > +#define BUS_PROT_SMI_UPDATE(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_SMI | BUS_PROT_REG_UPDATE)
> > +
> > +#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
> > + BUS_PROT_INFRA_UPDATE(_mask, \
> > INFRA_TOPAXI_PROTECTEN, \
> > INFRA_TOPAXI_PROTECTEN, \
> > INFRA_TOPAXI_PROTECTSTA1)
> > @@ -90,8 +105,7 @@ struct scpsys_bus_prot_data {
> > * @ext_buck_iso_offs: The offset for external buck isolation
> > * @ext_buck_iso_mask: The mask for external buck isolation
> > * @caps: The flag for active wake-up action.
> > - * @bp_infracfg: bus protection for infracfg subsystem
> > - * @bp_smi: bus protection for smi subsystem
> > + * @bp_cfg: bus protection configuration for any subsystem
> > */
> > struct scpsys_domain_data {
> > const char *name;
> > @@ -102,8 +116,7 @@ struct scpsys_domain_data {
> > int ext_buck_iso_offs;
> > u32 ext_buck_iso_mask;
> > u8 caps;
> > - const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
> > - const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
> > + const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
> > int pwr_sta_offs;
> > int pwr_sta2nd_offs;
> > };
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi
@ 2023-06-22 8:32 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-22 8:32 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On Mon, Jun 19, 2023 at 11:22:18AM +0200, AngeloGioacchino Del Regno wrote:
> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> > Use flags to distinguish between infracfg and smi subsystem for a bus
> > protection configuration. It simplifies enabling/disabling and prepares
> > the driver for the use of another regmap for mt8365.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
> > drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
> > drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
> > drivers/soc/mediatek/mt8183-pm-domains.h | 198 ++++-----
> > drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++++-----
> > drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++++------------
> > drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++++------
> > drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++++----------
> > drivers/soc/mediatek/mtk-pm-domains.c | 64 ++-
> > drivers/soc/mediatek/mtk-pm-domains.h | 37 +-
> > 10 files changed, 908 insertions(+), 899 deletions(-)
> >
>
> ..snip..
>
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> > index 4b6ae56e7c95..356788263db2 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.h
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> > @@ -45,6 +45,8 @@
> > enum scpsys_bus_prot_flags {
> > BUS_PROT_REG_UPDATE = BIT(1),
> > BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> > + BUS_PROT_COMPONENT_INFRA = BIT(3),
> > + BUS_PROT_COMPONENT_SMI = BIT(4),
> > };
> > #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
> > @@ -56,17 +58,30 @@ enum scpsys_bus_prot_flags {
> > .flags = _flags \
> > }
> > -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0)
> > +#define BUS_PROT_INFRA_WR(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_INFRA)
>
> What about doing that like
>
> #define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta)
> _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip)
>
> ...so that instead of defining BUS_PROT_INFRA_WR, BUS_PROT_SMI_WR and
> BUS_PROT_ANOTHERIP_WR, we keep just one macro?
>
> That'd be then like:
>
> .bp_cfg = {
> BUS_PROT_WR(INFRA, MT8183_TOP_AXI_PROT_EN_1_DISP,
> MT8183_TOP_AXI_PROT_EN_....
> ....),
> BUS_PROT_WR(SMI, MT8183_SMI_COMMON_SMI_CLAMP_DISP,
> .....),
> }
>
> IMO, that's cleaner, less lines of code and more flexible for eventual
> future new variations of that.
Yes it would be much cleaner, though it is a bit more intransparent how
these macros are resolved. Anyways I think it being cleaner outweighs
that. I will change it for the next version.
Thanks,
Markus
>
> Cheers,
> Angelo
>
> > -#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK)
> > +#define BUS_PROT_INFRA_WR_IGN(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_INFRA | BUS_PROT_IGNORE_CLR_ACK)
> > -#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
> > - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE)
> > +#define BUS_PROT_INFRA_UPDATE(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_INFRA | BUS_PROT_REG_UPDATE)
> > -#define BUS_PROT_UPDATE_TOPAXI(_mask) \
> > - BUS_PROT_UPDATE(_mask, \
> > +#define BUS_PROT_SMI_WR(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_SMI)
> > +
> > +#define BUS_PROT_SMI_WR_IGN(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_SMI | BUS_PROT_IGNORE_CLR_ACK)
> > +
> > +#define BUS_PROT_SMI_UPDATE(_mask, _set, _clr, _sta) \
> > + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \
> > + BUS_PROT_COMPONENT_SMI | BUS_PROT_REG_UPDATE)
> > +
> > +#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
> > + BUS_PROT_INFRA_UPDATE(_mask, \
> > INFRA_TOPAXI_PROTECTEN, \
> > INFRA_TOPAXI_PROTECTEN, \
> > INFRA_TOPAXI_PROTECTSTA1)
> > @@ -90,8 +105,7 @@ struct scpsys_bus_prot_data {
> > * @ext_buck_iso_offs: The offset for external buck isolation
> > * @ext_buck_iso_mask: The mask for external buck isolation
> > * @caps: The flag for active wake-up action.
> > - * @bp_infracfg: bus protection for infracfg subsystem
> > - * @bp_smi: bus protection for smi subsystem
> > + * @bp_cfg: bus protection configuration for any subsystem
> > */
> > struct scpsys_domain_data {
> > const char *name;
> > @@ -102,8 +116,7 @@ struct scpsys_domain_data {
> > int ext_buck_iso_offs;
> > u32 ext_buck_iso_mask;
> > u8 caps;
> > - const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
> > - const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
> > + const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
> > int pwr_sta_offs;
> > int pwr_sta2nd_offs;
> > };
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
2023-06-19 9:29 ` AngeloGioacchino Del Regno
@ 2023-06-22 8:39 ` Markus Schneider-Pargmann
-1 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-22 8:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Alexandre Bailon,
Fabien Parent
On Mon, Jun 19, 2023 at 11:29:18AM +0200, AngeloGioacchino Del Regno wrote:
> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> > From: Alexandre Bailon <abailon@baylibre.com>
> >
> > This updates the power domain to support WAY_EN operations. WAY_EN
> > operations on mt8365 are using a different component to check for the
> > acknowledgment, namely the infracfg-nao component. Also to enable a way
> > it the bit needs to be cleared while disabling a way needs a bit to be
> > set. To support these two operations two flags are added,
> > BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
> > another regmap is created if the INFRA_NAO capability is set.
> >
> > This operation is required by the mt8365 for the MM power domain.
> >
> > Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
> > drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
> > 2 files changed, 39 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> > index 3cdf62c0b6bd..4659f0a0aa08 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.c
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> > @@ -44,6 +44,7 @@ struct scpsys_domain {
> > struct clk_bulk_data *clks;
> > int num_subsys_clks;
> > struct clk_bulk_data *subsys_clks;
> > + struct regmap *infracfg_nao;
> > struct regmap *infracfg;
> > struct regmap *smi;
> > struct regulator *supply;
> > @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
> > return pd->infracfg;
> > }
> > +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
> > + const struct scpsys_bus_prot_data *bpd)
> > +{
> > + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
> > + return pd->infracfg_nao;
> > + else
> > + return scpsys_bus_protect_get_regmap(pd, bpd);
> > +}
> > +
> > static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> > const struct scpsys_bus_prot_data *bpd)
> > {
> > + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> > struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> > + u32 expected_ack;
> > u32 val;
> > u32 sta_mask = bpd->bus_prot_sta_mask;
> > + expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
> > +
> > if (bpd->flags & BUS_PROT_REG_UPDATE)
> > regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
> > else
> > @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> > if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
> > return 0;
> > - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> > - val, !(val & sta_mask),
> > + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> > + val, (val & sta_mask) == expected_ack,
> > MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > }
> > static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> > const struct scpsys_bus_prot_data *bpd)
> > {
> > + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> > struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> > u32 val;
> > u32 sta_mask = bpd->bus_prot_sta_mask;
> > @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> > else
> > regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
> > - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> > + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> > val, (val & sta_mask) == sta_mask,
> > MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > }
> > @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> > if (!bpd->bus_prot_set_clr_mask)
> > break;
> > - ret = scpsys_bus_protect_set(pd, bpd);
> > + if (bpd->flags & BUS_PROT_INVERTED)
> > + ret = scpsys_bus_protect_clear(pd, bpd);
> > + else
> > + ret = scpsys_bus_protect_set(pd, bpd);
> > if (ret)
> > return ret;
> > }
> > @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
> > if (!bpd->bus_prot_set_clr_mask)
> > continue;
> > - ret = scpsys_bus_protect_clear(pd, bpd);
> > + if (bpd->flags & BUS_PROT_INVERTED)
> > + ret = scpsys_bus_protect_set(pd, bpd);
> > + else
> > + ret = scpsys_bus_protect_clear(pd, bpd);
> > if (ret)
> > return ret;
> > }
> > @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
> > return ERR_CAST(pd->smi);
> > }
> > + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
>
> If we don't expect infracfg-nao to be present, what's the point about trying to
> get a regmap handle and then failing only if we do expect it to be there?
>
> At this point you can just do...
>
> if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
> pd->infracfg_nao = syscon_regmap_lookup_by_phandle(...);
> if (IS_ERR(....))
> return ....
> }
Yes! My code looks stupid. Thanks!
>
> > + if (IS_ERR(pd->infracfg_nao)) {
> > + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
> > + return ERR_CAST(pd->infracfg_nao);
> > +
> > + pd->infracfg_nao = NULL;
> > + }
> > +
> > num_clks = of_clk_get_parent_count(node);
> > if (num_clks > 0) {
> > /* Calculate number of subsys_clks */
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> > index 356788263db2..562d4e92ce16 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.h
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> > @@ -11,6 +11,7 @@
> > /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
> > #define MTK_SCPD_ALWAYS_ON BIT(5)
> > #define MTK_SCPD_EXT_BUCK_ISO BIT(6)
> > +#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
> > #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
> > #define SPM_VDE_PWR_CON 0x0210
> > @@ -45,8 +46,10 @@
> > enum scpsys_bus_prot_flags {
> > BUS_PROT_REG_UPDATE = BIT(1),
> > BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> > - BUS_PROT_COMPONENT_INFRA = BIT(3),
> > - BUS_PROT_COMPONENT_SMI = BIT(4),
> > + BUS_PROT_INVERTED = BIT(3),
>
> I get the reason why you're setting inverted as bit 3, but at that point you can
> just set BUS_PROT_COMPONENT_INFRA to bit 4 from the very beginning, instead of
> using bit 3 for that and then changing them all in a subsequent commit (this one).
Yes, I was torn between making the commits independent and avoiding this
move later on. I decided for the first. If you prefer I can set it to
the correct bits right from the beginning.
Best,
Markus
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
@ 2023-06-22 8:39 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 38+ messages in thread
From: Markus Schneider-Pargmann @ 2023-06-22 8:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Alexandre Bailon,
Fabien Parent
On Mon, Jun 19, 2023 at 11:29:18AM +0200, AngeloGioacchino Del Regno wrote:
> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
> > From: Alexandre Bailon <abailon@baylibre.com>
> >
> > This updates the power domain to support WAY_EN operations. WAY_EN
> > operations on mt8365 are using a different component to check for the
> > acknowledgment, namely the infracfg-nao component. Also to enable a way
> > it the bit needs to be cleared while disabling a way needs a bit to be
> > set. To support these two operations two flags are added,
> > BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
> > another regmap is created if the INFRA_NAO capability is set.
> >
> > This operation is required by the mt8365 for the MM power domain.
> >
> > Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
> > drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
> > 2 files changed, 39 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> > index 3cdf62c0b6bd..4659f0a0aa08 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.c
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> > @@ -44,6 +44,7 @@ struct scpsys_domain {
> > struct clk_bulk_data *clks;
> > int num_subsys_clks;
> > struct clk_bulk_data *subsys_clks;
> > + struct regmap *infracfg_nao;
> > struct regmap *infracfg;
> > struct regmap *smi;
> > struct regulator *supply;
> > @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
> > return pd->infracfg;
> > }
> > +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
> > + const struct scpsys_bus_prot_data *bpd)
> > +{
> > + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
> > + return pd->infracfg_nao;
> > + else
> > + return scpsys_bus_protect_get_regmap(pd, bpd);
> > +}
> > +
> > static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> > const struct scpsys_bus_prot_data *bpd)
> > {
> > + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> > struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> > + u32 expected_ack;
> > u32 val;
> > u32 sta_mask = bpd->bus_prot_sta_mask;
> > + expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
> > +
> > if (bpd->flags & BUS_PROT_REG_UPDATE)
> > regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
> > else
> > @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
> > if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
> > return 0;
> > - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> > - val, !(val & sta_mask),
> > + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> > + val, (val & sta_mask) == expected_ack,
> > MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > }
> > static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> > const struct scpsys_bus_prot_data *bpd)
> > {
> > + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
> > struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
> > u32 val;
> > u32 sta_mask = bpd->bus_prot_sta_mask;
> > @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> > else
> > regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
> > - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
> > + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
> > val, (val & sta_mask) == sta_mask,
> > MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > }
> > @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> > if (!bpd->bus_prot_set_clr_mask)
> > break;
> > - ret = scpsys_bus_protect_set(pd, bpd);
> > + if (bpd->flags & BUS_PROT_INVERTED)
> > + ret = scpsys_bus_protect_clear(pd, bpd);
> > + else
> > + ret = scpsys_bus_protect_set(pd, bpd);
> > if (ret)
> > return ret;
> > }
> > @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
> > if (!bpd->bus_prot_set_clr_mask)
> > continue;
> > - ret = scpsys_bus_protect_clear(pd, bpd);
> > + if (bpd->flags & BUS_PROT_INVERTED)
> > + ret = scpsys_bus_protect_set(pd, bpd);
> > + else
> > + ret = scpsys_bus_protect_clear(pd, bpd);
> > if (ret)
> > return ret;
> > }
> > @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
> > return ERR_CAST(pd->smi);
> > }
> > + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
>
> If we don't expect infracfg-nao to be present, what's the point about trying to
> get a regmap handle and then failing only if we do expect it to be there?
>
> At this point you can just do...
>
> if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
> pd->infracfg_nao = syscon_regmap_lookup_by_phandle(...);
> if (IS_ERR(....))
> return ....
> }
Yes! My code looks stupid. Thanks!
>
> > + if (IS_ERR(pd->infracfg_nao)) {
> > + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
> > + return ERR_CAST(pd->infracfg_nao);
> > +
> > + pd->infracfg_nao = NULL;
> > + }
> > +
> > num_clks = of_clk_get_parent_count(node);
> > if (num_clks > 0) {
> > /* Calculate number of subsys_clks */
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> > index 356788263db2..562d4e92ce16 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.h
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> > @@ -11,6 +11,7 @@
> > /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
> > #define MTK_SCPD_ALWAYS_ON BIT(5)
> > #define MTK_SCPD_EXT_BUCK_ISO BIT(6)
> > +#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
> > #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
> > #define SPM_VDE_PWR_CON 0x0210
> > @@ -45,8 +46,10 @@
> > enum scpsys_bus_prot_flags {
> > BUS_PROT_REG_UPDATE = BIT(1),
> > BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> > - BUS_PROT_COMPONENT_INFRA = BIT(3),
> > - BUS_PROT_COMPONENT_SMI = BIT(4),
> > + BUS_PROT_INVERTED = BIT(3),
>
> I get the reason why you're setting inverted as bit 3, but at that point you can
> just set BUS_PROT_COMPONENT_INFRA to bit 4 from the very beginning, instead of
> using bit 3 for that and then changing them all in a subsequent commit (this one).
Yes, I was torn between making the commits independent and avoiding this
move later on. I decided for the first. If you prefer I can set it to
the correct bits right from the beginning.
Best,
Markus
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
2023-06-22 8:39 ` Markus Schneider-Pargmann
@ 2023-06-22 9:17 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-22 9:17 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Alexandre Bailon,
Fabien Parent
Il 22/06/23 10:39, Markus Schneider-Pargmann ha scritto:
> On Mon, Jun 19, 2023 at 11:29:18AM +0200, AngeloGioacchino Del Regno wrote:
>> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
>>> From: Alexandre Bailon <abailon@baylibre.com>
>>>
>>> This updates the power domain to support WAY_EN operations. WAY_EN
>>> operations on mt8365 are using a different component to check for the
>>> acknowledgment, namely the infracfg-nao component. Also to enable a way
>>> it the bit needs to be cleared while disabling a way needs a bit to be
>>> set. To support these two operations two flags are added,
>>> BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
>>> another regmap is created if the INFRA_NAO capability is set.
>>>
>>> This operation is required by the mt8365 for the MM power domain.
>>>
>>> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>> ---
>>> drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
>>> drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
>>> 2 files changed, 39 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
>>> index 3cdf62c0b6bd..4659f0a0aa08 100644
>>> --- a/drivers/soc/mediatek/mtk-pm-domains.c
>>> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
>>> @@ -44,6 +44,7 @@ struct scpsys_domain {
>>> struct clk_bulk_data *clks;
>>> int num_subsys_clks;
>>> struct clk_bulk_data *subsys_clks;
>>> + struct regmap *infracfg_nao;
>>> struct regmap *infracfg;
>>> struct regmap *smi;
>>> struct regulator *supply;
>>> @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
>>> return pd->infracfg;
>>> }
>>> +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
>>> + const struct scpsys_bus_prot_data *bpd)
>>> +{
>>> + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
>>> + return pd->infracfg_nao;
>>> + else
>>> + return scpsys_bus_protect_get_regmap(pd, bpd);
>>> +}
>>> +
>>> static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
>>> const struct scpsys_bus_prot_data *bpd)
>>> {
>>> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
>>> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
>>> + u32 expected_ack;
>>> u32 val;
>>> u32 sta_mask = bpd->bus_prot_sta_mask;
>>> + expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
>>> +
>>> if (bpd->flags & BUS_PROT_REG_UPDATE)
>>> regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
>>> else
>>> @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
>>> if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
>>> return 0;
>>> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
>>> - val, !(val & sta_mask),
>>> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
>>> + val, (val & sta_mask) == expected_ack,
>>> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
>>> }
>>> static int scpsys_bus_protect_set(struct scpsys_domain *pd,
>>> const struct scpsys_bus_prot_data *bpd)
>>> {
>>> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
>>> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
>>> u32 val;
>>> u32 sta_mask = bpd->bus_prot_sta_mask;
>>> @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
>>> else
>>> regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
>>> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
>>> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
>>> val, (val & sta_mask) == sta_mask,
>>> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
>>> }
>>> @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
>>> if (!bpd->bus_prot_set_clr_mask)
>>> break;
>>> - ret = scpsys_bus_protect_set(pd, bpd);
>>> + if (bpd->flags & BUS_PROT_INVERTED)
>>> + ret = scpsys_bus_protect_clear(pd, bpd);
>>> + else
>>> + ret = scpsys_bus_protect_set(pd, bpd);
>>> if (ret)
>>> return ret;
>>> }
>>> @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
>>> if (!bpd->bus_prot_set_clr_mask)
>>> continue;
>>> - ret = scpsys_bus_protect_clear(pd, bpd);
>>> + if (bpd->flags & BUS_PROT_INVERTED)
>>> + ret = scpsys_bus_protect_set(pd, bpd);
>>> + else
>>> + ret = scpsys_bus_protect_clear(pd, bpd);
>>> if (ret)
>>> return ret;
>>> }
>>> @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
>>> return ERR_CAST(pd->smi);
>>> }
>>> + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
>>
>> If we don't expect infracfg-nao to be present, what's the point about trying to
>> get a regmap handle and then failing only if we do expect it to be there?
>>
>> At this point you can just do...
>>
>> if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
>> pd->infracfg_nao = syscon_regmap_lookup_by_phandle(...);
>> if (IS_ERR(....))
>> return ....
>> }
>
> Yes! My code looks stupid. Thanks!
>
Hahaha, no worries!
>>
>>> + if (IS_ERR(pd->infracfg_nao)) {
>>> + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
>>> + return ERR_CAST(pd->infracfg_nao);
>>> +
>>> + pd->infracfg_nao = NULL;
>>> + }
>>> +
>>> num_clks = of_clk_get_parent_count(node);
>>> if (num_clks > 0) {
>>> /* Calculate number of subsys_clks */
>>> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
>>> index 356788263db2..562d4e92ce16 100644
>>> --- a/drivers/soc/mediatek/mtk-pm-domains.h
>>> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
>>> @@ -11,6 +11,7 @@
>>> /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
>>> #define MTK_SCPD_ALWAYS_ON BIT(5)
>>> #define MTK_SCPD_EXT_BUCK_ISO BIT(6)
>>> +#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
>>> #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
>>> #define SPM_VDE_PWR_CON 0x0210
>>> @@ -45,8 +46,10 @@
>>> enum scpsys_bus_prot_flags {
>>> BUS_PROT_REG_UPDATE = BIT(1),
>>> BUS_PROT_IGNORE_CLR_ACK = BIT(2),
>>> - BUS_PROT_COMPONENT_INFRA = BIT(3),
>>> - BUS_PROT_COMPONENT_SMI = BIT(4),
>>> + BUS_PROT_INVERTED = BIT(3),
>>
>> I get the reason why you're setting inverted as bit 3, but at that point you can
>> just set BUS_PROT_COMPONENT_INFRA to bit 4 from the very beginning, instead of
>> using bit 3 for that and then changing them all in a subsequent commit (this one).
>
> Yes, I was torn between making the commits independent and avoiding this
> move later on. I decided for the first. If you prefer I can set it to
> the correct bits right from the beginning.
>
I don't see how setting BUS_PROT_COMPONENT_INFRA to bit(4) from the beginning
would add dependencies between commits. The first commit alone will still work,
with the added benefit of less noise in this commit.
You should, at that point, mention in the commit message that you're setting
INFRA to BIT(4) because BIT(3) "is going to be populated in a later commit".
That, unless anyone else has strong opinions against.
Cheers,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations
@ 2023-06-22 9:17 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-22 9:17 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Chun-Jie Chen, Tinghan Shen, Fabien Parent, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Alexandre Bailon,
Fabien Parent
Il 22/06/23 10:39, Markus Schneider-Pargmann ha scritto:
> On Mon, Jun 19, 2023 at 11:29:18AM +0200, AngeloGioacchino Del Regno wrote:
>> Il 19/06/23 10:53, Markus Schneider-Pargmann ha scritto:
>>> From: Alexandre Bailon <abailon@baylibre.com>
>>>
>>> This updates the power domain to support WAY_EN operations. WAY_EN
>>> operations on mt8365 are using a different component to check for the
>>> acknowledgment, namely the infracfg-nao component. Also to enable a way
>>> it the bit needs to be cleared while disabling a way needs a bit to be
>>> set. To support these two operations two flags are added,
>>> BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
>>> another regmap is created if the INFRA_NAO capability is set.
>>>
>>> This operation is required by the mt8365 for the MM power domain.
>>>
>>> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>> ---
>>> drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
>>> drivers/soc/mediatek/mtk-pm-domains.h | 7 +++--
>>> 2 files changed, 39 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
>>> index 3cdf62c0b6bd..4659f0a0aa08 100644
>>> --- a/drivers/soc/mediatek/mtk-pm-domains.c
>>> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
>>> @@ -44,6 +44,7 @@ struct scpsys_domain {
>>> struct clk_bulk_data *clks;
>>> int num_subsys_clks;
>>> struct clk_bulk_data *subsys_clks;
>>> + struct regmap *infracfg_nao;
>>> struct regmap *infracfg;
>>> struct regmap *smi;
>>> struct regulator *supply;
>>> @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
>>> return pd->infracfg;
>>> }
>>> +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
>>> + const struct scpsys_bus_prot_data *bpd)
>>> +{
>>> + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
>>> + return pd->infracfg_nao;
>>> + else
>>> + return scpsys_bus_protect_get_regmap(pd, bpd);
>>> +}
>>> +
>>> static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
>>> const struct scpsys_bus_prot_data *bpd)
>>> {
>>> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
>>> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
>>> + u32 expected_ack;
>>> u32 val;
>>> u32 sta_mask = bpd->bus_prot_sta_mask;
>>> + expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
>>> +
>>> if (bpd->flags & BUS_PROT_REG_UPDATE)
>>> regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
>>> else
>>> @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
>>> if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
>>> return 0;
>>> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
>>> - val, !(val & sta_mask),
>>> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
>>> + val, (val & sta_mask) == expected_ack,
>>> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
>>> }
>>> static int scpsys_bus_protect_set(struct scpsys_domain *pd,
>>> const struct scpsys_bus_prot_data *bpd)
>>> {
>>> + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
>>> struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
>>> u32 val;
>>> u32 sta_mask = bpd->bus_prot_sta_mask;
>>> @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
>>> else
>>> regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
>>> - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
>>> + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
>>> val, (val & sta_mask) == sta_mask,
>>> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
>>> }
>>> @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
>>> if (!bpd->bus_prot_set_clr_mask)
>>> break;
>>> - ret = scpsys_bus_protect_set(pd, bpd);
>>> + if (bpd->flags & BUS_PROT_INVERTED)
>>> + ret = scpsys_bus_protect_clear(pd, bpd);
>>> + else
>>> + ret = scpsys_bus_protect_set(pd, bpd);
>>> if (ret)
>>> return ret;
>>> }
>>> @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
>>> if (!bpd->bus_prot_set_clr_mask)
>>> continue;
>>> - ret = scpsys_bus_protect_clear(pd, bpd);
>>> + if (bpd->flags & BUS_PROT_INVERTED)
>>> + ret = scpsys_bus_protect_set(pd, bpd);
>>> + else
>>> + ret = scpsys_bus_protect_clear(pd, bpd);
>>> if (ret)
>>> return ret;
>>> }
>>> @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
>>> return ERR_CAST(pd->smi);
>>> }
>>> + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
>>
>> If we don't expect infracfg-nao to be present, what's the point about trying to
>> get a regmap handle and then failing only if we do expect it to be there?
>>
>> At this point you can just do...
>>
>> if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
>> pd->infracfg_nao = syscon_regmap_lookup_by_phandle(...);
>> if (IS_ERR(....))
>> return ....
>> }
>
> Yes! My code looks stupid. Thanks!
>
Hahaha, no worries!
>>
>>> + if (IS_ERR(pd->infracfg_nao)) {
>>> + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO))
>>> + return ERR_CAST(pd->infracfg_nao);
>>> +
>>> + pd->infracfg_nao = NULL;
>>> + }
>>> +
>>> num_clks = of_clk_get_parent_count(node);
>>> if (num_clks > 0) {
>>> /* Calculate number of subsys_clks */
>>> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
>>> index 356788263db2..562d4e92ce16 100644
>>> --- a/drivers/soc/mediatek/mtk-pm-domains.h
>>> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
>>> @@ -11,6 +11,7 @@
>>> /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
>>> #define MTK_SCPD_ALWAYS_ON BIT(5)
>>> #define MTK_SCPD_EXT_BUCK_ISO BIT(6)
>>> +#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
>>> #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
>>> #define SPM_VDE_PWR_CON 0x0210
>>> @@ -45,8 +46,10 @@
>>> enum scpsys_bus_prot_flags {
>>> BUS_PROT_REG_UPDATE = BIT(1),
>>> BUS_PROT_IGNORE_CLR_ACK = BIT(2),
>>> - BUS_PROT_COMPONENT_INFRA = BIT(3),
>>> - BUS_PROT_COMPONENT_SMI = BIT(4),
>>> + BUS_PROT_INVERTED = BIT(3),
>>
>> I get the reason why you're setting inverted as bit 3, but at that point you can
>> just set BUS_PROT_COMPONENT_INFRA to bit 4 from the very beginning, instead of
>> using bit 3 for that and then changing them all in a subsequent commit (this one).
>
> Yes, I was torn between making the commits independent and avoiding this
> move later on. I decided for the first. If you prefer I can set it to
> the correct bits right from the beginning.
>
I don't see how setting BUS_PROT_COMPONENT_INFRA to bit(4) from the beginning
would add dependencies between commits. The first commit alone will still work,
with the added benefit of less noise in this commit.
You should, at that point, mention in the commit message that you're setting
INFRA to BIT(4) because BIT(3) "is going to be populated in a later commit".
That, unless anyone else has strong opinions against.
Cheers,
Angelo
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2023-06-22 9:27 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-19 8:53 [PATCH v5 0/8] soc: mediatek: MT8365 power support Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 8:53 ` [PATCH v5 1/8] dt-bindings: power: Add MT8365 power domains Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 8:53 ` [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 9:32 ` AngeloGioacchino Del Regno
2023-06-19 9:32 ` AngeloGioacchino Del Regno
2023-06-22 8:28 ` Markus Schneider-Pargmann
2023-06-22 8:28 ` Markus Schneider-Pargmann
2023-06-19 8:53 ` [PATCH v5 3/8] soc: mediatek: pm-domains: Split bus_prot_mask Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 8:53 ` [PATCH v5 4/8] soc: mediatek: pm-domains: Create bus protection operation functions Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 8:53 ` [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 9:22 ` AngeloGioacchino Del Regno
2023-06-19 9:22 ` AngeloGioacchino Del Regno
2023-06-22 8:32 ` Markus Schneider-Pargmann
2023-06-22 8:32 ` Markus Schneider-Pargmann
2023-06-19 8:53 ` [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 9:29 ` AngeloGioacchino Del Regno
2023-06-19 9:29 ` AngeloGioacchino Del Regno
2023-06-22 8:39 ` Markus Schneider-Pargmann
2023-06-22 8:39 ` Markus Schneider-Pargmann
2023-06-22 9:17 ` AngeloGioacchino Del Regno
2023-06-22 9:17 ` AngeloGioacchino Del Regno
2023-06-19 8:53 ` [PATCH v5 7/8] soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 8:53 ` [PATCH v5 8/8] soc: mediatek: pm-domains: Add support for MT8365 Markus Schneider-Pargmann
2023-06-19 8:53 ` Markus Schneider-Pargmann
2023-06-19 20:47 ` kernel test robot
2023-06-19 20:47 ` kernel test robot
2023-06-20 8:07 ` kernel test robot
2023-06-20 8:07 ` kernel test robot
2023-06-22 2:05 ` kernel test robot
2023-06-22 2:05 ` kernel test robot
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