* [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times
@ 2018-10-28 1:08 Ferruh Yigit
2018-10-28 1:08 ` [PATCH 2/3] service: fix possible NULL access Ferruh Yigit
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ferruh Yigit @ 2018-10-28 1:08 UTC (permalink / raw)
To: Konstantin Ananyev, Jasvinder Singh, Olivier Matz
Cc: dev, Ferruh Yigit, stable
Fix cppcheck warning by marking variable as unsigned.
Fixes: dc276b5780c2 ("acl: new library")
Fixes: 986ff526fb84 ("net: add CRC computation API")
Cc: stable@dpdk.org
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
---
lib/librte_acl/acl_gen.c | 2 +-
lib/librte_net/rte_net_crc.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/librte_acl/acl_gen.c b/lib/librte_acl/acl_gen.c
index bed66be08..35a0140b4 100644
--- a/lib/librte_acl/acl_gen.c
+++ b/lib/librte_acl/acl_gen.c
@@ -163,7 +163,7 @@ acl_count_sequential_groups(struct rte_acl_bitset *bits, int zero_one)
for (n = QRANGE_MIN; n < UINT8_MAX + 1; n++) {
if (bits->bits[n / (sizeof(bits_t) * 8)] &
- (1 << (n % (sizeof(bits_t) * 8)))) {
+ (1U << (n % (sizeof(bits_t) * 8)))) {
if (zero_one == 1 && last_bit != 1)
ranges++;
last_bit = 1;
diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c
index 73ac3a959..dca0830e2 100644
--- a/lib/librte_net/rte_net_crc.c
+++ b/lib/librte_net/rte_net_crc.c
@@ -69,8 +69,8 @@ reflect_32bits(uint32_t val)
uint32_t i, res = 0;
for (i = 0; i < 32; i++)
- if ((val & (1 << i)) != 0)
- res |= (uint32_t)(1 << (31 - i));
+ if ((val & (1U << i)) != 0)
+ res |= (uint32_t)(1U << (31 - i));
return res;
}
--
2.17.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] service: fix possible NULL access
2018-10-28 1:08 [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times Ferruh Yigit
@ 2018-10-28 1:08 ` Ferruh Yigit
2018-10-29 16:12 ` Van Haaren, Harry
2018-10-28 1:08 ` [PATCH 3/3] vhost: fix possible out of bound access Ferruh Yigit
2018-11-06 0:26 ` [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times Thomas Monjalon
2 siblings, 1 reply; 6+ messages in thread
From: Ferruh Yigit @ 2018-10-28 1:08 UTC (permalink / raw)
To: Harry van Haaren; +Cc: dev, Ferruh Yigit, stable
Fixes: 21698354c832 ("service: introduce service cores concept")
Cc: stable@dpdk.org
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
---
lib/librte_eal/common/rte_service.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/librte_eal/common/rte_service.c b/lib/librte_eal/common/rte_service.c
index 8767c7225..0f3695c4b 100644
--- a/lib/librte_eal/common/rte_service.c
+++ b/lib/librte_eal/common/rte_service.c
@@ -795,6 +795,9 @@ rte_service_dump_one(FILE *f, struct rte_service_spec_impl *s,
return;
}
+ if (f == NULL)
+ return;
+
fprintf(f, " %s: stats %d\tcalls %"PRIu64"\tcycles %"
PRIu64"\tavg: %"PRIu64"\n",
s->spec.name, service_stats_enabled(s), s->calls,
--
2.17.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/3] service: fix possible NULL access
2018-10-28 1:08 ` [PATCH 2/3] service: fix possible NULL access Ferruh Yigit
@ 2018-10-29 16:12 ` Van Haaren, Harry
0 siblings, 0 replies; 6+ messages in thread
From: Van Haaren, Harry @ 2018-10-29 16:12 UTC (permalink / raw)
To: Yigit, Ferruh; +Cc: dev, stable
> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Saturday, October 27, 2018 6:09 PM
> To: Van Haaren, Harry <harry.van.haaren@intel.com>
> Cc: dev@dpdk.org; Yigit, Ferruh <ferruh.yigit@intel.com>; stable@dpdk.org
> Subject: [PATCH 2/3] service: fix possible NULL access
>
> Fixes: 21698354c832 ("service: introduce service cores concept")
> Cc: stable@dpdk.org
>
> Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
> ---
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] vhost: fix possible out of bound access
2018-10-28 1:08 [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times Ferruh Yigit
2018-10-28 1:08 ` [PATCH 2/3] service: fix possible NULL access Ferruh Yigit
@ 2018-10-28 1:08 ` Ferruh Yigit
2018-10-31 17:28 ` Maxime Coquelin
2018-11-06 0:26 ` [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times Thomas Monjalon
2 siblings, 1 reply; 6+ messages in thread
From: Ferruh Yigit @ 2018-10-28 1:08 UTC (permalink / raw)
To: Maxime Coquelin, Tiwei Bie, Zhihong Wang; +Cc: dev, Ferruh Yigit, stable
Fixes: d7280c9fffcb ("vhost: support selective datapath")
Cc: stable@dpdk.org
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
---
lib/librte_vhost/vdpa.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/librte_vhost/vdpa.c b/lib/librte_vhost/vdpa.c
index c2c5dff1d..e7d849ee0 100644
--- a/lib/librte_vhost/vdpa.c
+++ b/lib/librte_vhost/vdpa.c
@@ -63,6 +63,9 @@ rte_vdpa_register_device(struct rte_vdpa_dev_addr *addr,
break;
}
+ if (i == MAX_VHOST_DEVICE)
+ return -1;
+
sprintf(device_name, "vdpa-dev-%d", i);
dev = rte_zmalloc(device_name, sizeof(struct rte_vdpa_device),
RTE_CACHE_LINE_SIZE);
--
2.17.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 3/3] vhost: fix possible out of bound access
2018-10-28 1:08 ` [PATCH 3/3] vhost: fix possible out of bound access Ferruh Yigit
@ 2018-10-31 17:28 ` Maxime Coquelin
0 siblings, 0 replies; 6+ messages in thread
From: Maxime Coquelin @ 2018-10-31 17:28 UTC (permalink / raw)
To: Ferruh Yigit, Tiwei Bie, Zhihong Wang; +Cc: dev, stable
On 10/28/18 2:08 AM, Ferruh Yigit wrote:
> Fixes: d7280c9fffcb ("vhost: support selective datapath")
> Cc: stable@dpdk.org
>
> Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
> ---
> lib/librte_vhost/vdpa.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/lib/librte_vhost/vdpa.c b/lib/librte_vhost/vdpa.c
> index c2c5dff1d..e7d849ee0 100644
> --- a/lib/librte_vhost/vdpa.c
> +++ b/lib/librte_vhost/vdpa.c
> @@ -63,6 +63,9 @@ rte_vdpa_register_device(struct rte_vdpa_dev_addr *addr,
> break;
> }
>
> + if (i == MAX_VHOST_DEVICE)
> + return -1;
> +
> sprintf(device_name, "vdpa-dev-%d", i);
> dev = rte_zmalloc(device_name, sizeof(struct rte_vdpa_device),
> RTE_CACHE_LINE_SIZE);
>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Thanks,
Maxime
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times
2018-10-28 1:08 [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times Ferruh Yigit
2018-10-28 1:08 ` [PATCH 2/3] service: fix possible NULL access Ferruh Yigit
2018-10-28 1:08 ` [PATCH 3/3] vhost: fix possible out of bound access Ferruh Yigit
@ 2018-11-06 0:26 ` Thomas Monjalon
2 siblings, 0 replies; 6+ messages in thread
From: Thomas Monjalon @ 2018-11-06 0:26 UTC (permalink / raw)
To: Ferruh Yigit
Cc: dev, Konstantin Ananyev, Jasvinder Singh, Olivier Matz, stable
28/10/2018 02:08, Ferruh Yigit:
> Fix cppcheck warning by marking variable as unsigned.
>
> Fixes: dc276b5780c2 ("acl: new library")
> Fixes: 986ff526fb84 ("net: add CRC computation API")
> Cc: stable@dpdk.org
>
> Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Series applied, thanks
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-11-06 0:26 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-28 1:08 [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times Ferruh Yigit
2018-10-28 1:08 ` [PATCH 2/3] service: fix possible NULL access Ferruh Yigit
2018-10-29 16:12 ` Van Haaren, Harry
2018-10-28 1:08 ` [PATCH 3/3] vhost: fix possible out of bound access Ferruh Yigit
2018-10-31 17:28 ` Maxime Coquelin
2018-11-06 0:26 ` [PATCH 1/3] lib: fix shifting 32 bits signed variable 31 times Thomas Monjalon
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