[PATCH] mtd: spi-nor: Enable locking for n25q00/n25q00a

[PATCH] mtd: spi-nor: Enable locking for n25q00/n25q00a

[Jungseung Lee]

n25q00 and n25q00a use the 4 bit Block Protection scheme and support
Top/Bottom protection via the BP and TB bits of the Status Register.

This patch enables the locking for n25q00/n25q00a.

Tested on n25q00 with cirrus controller. The other is modified
according to the datasheet.

Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
 drivers/mtd/spi-nor/micron-st.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 6c034b9718e2..51d677844480 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -59,9 +59,13 @@ static const struct flash_info st_parts[] = {
 			      SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048,
 			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+			      SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+			      SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6 |
 			      NO_CHIP_ERASE) },
 	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048,
 			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+			      SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+			      SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6 |
 			      NO_CHIP_ERASE) },
 	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
 			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
-- 
2.17.1


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Re: [PATCH] mtd: spi-nor: Enable locking for n25q00/n25q00a

[Tudor.Ambarus]

Hi, Jungseung,

On Tuesday, April 21, 2020 9:33:13 AM EEST Jungseung Lee wrote:
> Tested on n25q00 with cirrus controller. The other is modified
> according to the datasheet.

What is the difference between n25q00 and n25q00a? I'm reluctant to add flags 
to flashes solely by datasheet info, without testing. I saw too many faults in 
the past.

Let me know if you're ok with applying just the changes for n25q00, they look 
fine.

Cheers,
ta



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Re: [PATCH] mtd: spi-nor: Enable locking for n25q00/n25q00a

[Jungseung Lee]

Hi, Tudor,

On Tue, 2020-04-28 at 07:34 +0000, Tudor.Ambarus@microchip.com wrote:
> Hi, Jungseung,
> 
> On Tuesday, April 21, 2020 9:33:13 AM EEST Jungseung Lee wrote:
> > Tested on n25q00 with cirrus controller. The other is modified
> > according to the datasheet.
> 
> What is the difference between n25q00 and n25q00a? I'm reluctant to
> add flags 
> to flashes solely by datasheet info, without testing. I saw too many
> faults in 
> the past.
> 

The device ID of n25q00 is 0x20ba21, and the the device ID of n25q00a
is 0x20bb21. BAh = 3V, BBh = 1.8V. 

The Vcc they are using is differ. That's only one I could find in their
datasheet and they are also sharing their datasheet.

> Let me know if you're ok with applying just the changes for n25q00,
> they look 
> fine.
> 

I understand. It's also good for me.

Thanks,

> Cheers,
> ta
> 
> 
> 


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Re: [PATCH] mtd: spi-nor: Enable locking for n25q00/n25q00a

[Tudor.Ambarus]

On Tuesday, April 28, 2020 11:35:13 AM EEST Jungseung Lee wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> Hi, Tudor,
> 
> On Tue, 2020-04-28 at 07:34 +0000, Tudor.Ambarus@microchip.com wrote:
> > Hi, Jungseung,
> > 
> > On Tuesday, April 21, 2020 9:33:13 AM EEST Jungseung Lee wrote:
> > > Tested on n25q00 with cirrus controller. The other is modified
> > > according to the datasheet.
> > 
> > What is the difference between n25q00 and n25q00a? I'm reluctant to
> > add flags
> > to flashes solely by datasheet info, without testing. I saw too many
> > faults in
> > the past.
> 
> The device ID of n25q00 is 0x20ba21, and the the device ID of n25q00a
> is 0x20bb21. BAh = 3V, BBh = 1.8V.
> 
> The Vcc they are using is differ. That's only one I could find in their
> datasheet and they are also sharing their datasheet.
> 
> > Let me know if you're ok with applying just the changes for n25q00,
> > they look
> > fine.
> 
> I understand. It's also good for me.
> 

I updated the patch to enable locking just for n25q00. Applied to spi-nor/
next.

Cheers,
ta




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