* [PATCH 1/3] target/mips: Fix MSA MADDV.B opcode
2021-10-22 17:45 [PATCH 0/3] target/mips: MSA opcode fixes Philippe Mathieu-Daudé
@ 2021-10-22 17:45 ` Philippe Mathieu-Daudé
2021-10-22 21:41 ` Richard Henderson
2021-10-22 17:45 ` [PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-22 17:45 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
The result of the 'Vector Multiply and Add' opcode is incorrect
with Byte vectors. Probably due to a copy/paste error, commit
7a7a162adde mistakenly used the $wt (target register) instead
of $wd (destination register) as first operand. Fix that.
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index e40c1b70575..d978909527f 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
- pwd->b[0] = msa_maddv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
- pwd->b[1] = msa_maddv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
- pwd->b[2] = msa_maddv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
- pwd->b[3] = msa_maddv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
- pwd->b[4] = msa_maddv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
- pwd->b[5] = msa_maddv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
- pwd->b[6] = msa_maddv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
- pwd->b[7] = msa_maddv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
- pwd->b[8] = msa_maddv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
- pwd->b[9] = msa_maddv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
- pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
- pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
- pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
- pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
- pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
- pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+ pwd->b[0] = msa_maddv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_maddv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_maddv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_maddv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_maddv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_maddv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_maddv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_maddv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_maddv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_maddv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
}
void helper_msa_maddv_h(CPUMIPSState *env,
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 1/3] target/mips: Fix MSA MADDV.B opcode
2021-10-22 17:45 ` [PATCH 1/3] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
@ 2021-10-22 21:41 ` Richard Henderson
0 siblings, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2021-10-22 21:41 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 10/22/21 10:45 AM, Philippe Mathieu-Daudé wrote:
> The result of the 'Vector Multiply and Add' opcode is incorrect
> with Byte vectors. Probably due to a copy/paste error, commit
> 7a7a162adde mistakenly used the $wt (target register) instead
> of $wd (destination register) as first operand. Fix that.
>
> Cc: Aleksandar Rikalo<aleksandar.rikalo@syrmia.com>
> Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode
2021-10-22 17:45 [PATCH 0/3] target/mips: MSA opcode fixes Philippe Mathieu-Daudé
2021-10-22 17:45 ` [PATCH 1/3] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
@ 2021-10-22 17:45 ` Philippe Mathieu-Daudé
2021-10-22 21:42 ` Richard Henderson
2021-10-22 17:45 ` [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register Philippe Mathieu-Daudé
2021-10-26 18:08 ` [PATCH 0/3] target/mips: MSA opcode fixes Philippe Mathieu-Daudé
3 siblings, 1 reply; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-22 17:45 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
The result of the 'Vector Multiply and Subtract' opcode is
incorrect with Byte vectors. Probably due to a copy/paste error,
commit 5f148a02327 mistakenly used the $wt (target register)
instead of $wd (destination register) as first operand. Fix that.
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index d978909527f..5667b1f0a15 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3303,22 +3303,22 @@ void helper_msa_msubv_b(CPUMIPSState *env,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
- pwd->b[0] = msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
- pwd->b[1] = msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
- pwd->b[2] = msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
- pwd->b[3] = msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
- pwd->b[4] = msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
- pwd->b[5] = msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
- pwd->b[6] = msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
- pwd->b[7] = msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
- pwd->b[8] = msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
- pwd->b[9] = msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
- pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
- pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
- pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
- pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
- pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
- pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+ pwd->b[0] = msa_msubv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_msubv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_msubv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_msubv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_msubv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_msubv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_msubv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_msubv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_msubv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_msubv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_msubv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_msubv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_msubv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_msubv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_msubv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_msubv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
}
void helper_msa_msubv_h(CPUMIPSState *env,
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode
2021-10-22 17:45 ` [PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
@ 2021-10-22 21:42 ` Richard Henderson
0 siblings, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2021-10-22 21:42 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 10/22/21 10:45 AM, Philippe Mathieu-Daudé wrote:
> The result of the 'Vector Multiply and Subtract' opcode is
> incorrect with Byte vectors. Probably due to a copy/paste error,
> commit 5f148a02327 mistakenly used the $wt (target register)
> instead of $wd (destination register) as first operand. Fix that.
>
> Cc: Aleksandar Rikalo<aleksandar.rikalo@syrmia.com>
> Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register
2021-10-22 17:45 [PATCH 0/3] target/mips: MSA opcode fixes Philippe Mathieu-Daudé
2021-10-22 17:45 ` [PATCH 1/3] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-22 17:45 ` [PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
@ 2021-10-22 17:45 ` Philippe Mathieu-Daudé
2021-10-23 7:38 ` Philippe Mathieu-Daudé
2021-10-23 12:31 ` Jiaxun Yang
2021-10-26 18:08 ` [PATCH 0/3] target/mips: MSA opcode fixes Philippe Mathieu-Daudé
3 siblings, 2 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-22 17:45 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
When using the Loongson-3A4000 CPU, the MSAIR is returned with a
zero value (because unimplemented). Checking on real hardware,
this value appears incorrect:
$ cat /proc/cpuinfo
system type : generic-loongson-machine
machine : loongson,generic
cpu model : Loongson-3 V0.4 FPU V0.1
model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2
...
Checking the CFCMSA opcode result with gdb we get 0x60140:
Breakpoint 1, 0x00000001200037c4 in main ()
1: x/i $pc
=> 0x1200037c4 <main+52>: cfcmsa v0,msa_ir
(gdb) si
0x00000001200037c8 in main ()
(gdb) i r v0
v0: 0x60140
So set MSAIR=0x60140 for the Loongson-3A4000 CPU model added in
commit af868995e1b ("target/mips: Add Loongson-3 CPU definition").
Cc: Huacai Chen <chenhuacai@kernel.org>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu-defs.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index cbc45fcb0e8..f43a8e7c9d9 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -886,6 +886,7 @@ const mips_def_t mips_defs[] =
(0x1 << FCR0_D) | (0x1 << FCR0_S),
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .MSAIR = (0x601 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
.SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register
2021-10-22 17:45 ` [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register Philippe Mathieu-Daudé
@ 2021-10-23 7:38 ` Philippe Mathieu-Daudé
2021-10-23 12:31 ` Jiaxun Yang
1 sibling, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 7:38 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
On 10/22/21 19:45, Philippe Mathieu-Daudé wrote:
> When using the Loongson-3A4000 CPU, the MSAIR is returned with a
> zero value (because unimplemented). Checking on real hardware,
> this value appears incorrect:
>
> $ cat /proc/cpuinfo
> system type : generic-loongson-machine
> machine : loongson,generic
> cpu model : Loongson-3 V0.4 FPU V0.1
> model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
> isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
> ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2
> ...
>
> Checking the CFCMSA opcode result with gdb we get 0x60140:
>
> Breakpoint 1, 0x00000001200037c4 in main ()
> 1: x/i $pc
> => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir
> (gdb) si
> 0x00000001200037c8 in main ()
> (gdb) i r v0
> v0: 0x60140
>
> So set MSAIR=0x60140 for the Loongson-3A4000 CPU model added in
> commit af868995e1b ("target/mips: Add Loongson-3 CPU definition").
>
> Cc: Huacai Chen <chenhuacai@kernel.org>
> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu-defs.c.inc | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index cbc45fcb0e8..f43a8e7c9d9 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -886,6 +886,7 @@ const mips_def_t mips_defs[] =
> (0x1 << FCR0_D) | (0x1 << FCR0_S),
> .CP1_fcr31 = 0,
> .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
> + .MSAIR = (0x601 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
Rev and ProcID are 8-bit, then only bit 16 is defined in the spec
(WRP: Vector Registers Partitioning). Bits 17 and 18 are "reserved"
per the spec revision 1.12.
Changing that by
.MSAIR = (1 << MSAIR_ProcID),
or
.MSAIR = (1 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
allows guests to see non-zero Implementation ProcessorID.
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register
2021-10-22 17:45 ` [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register Philippe Mathieu-Daudé
2021-10-23 7:38 ` Philippe Mathieu-Daudé
@ 2021-10-23 12:31 ` Jiaxun Yang
1 sibling, 0 replies; 9+ messages in thread
From: Jiaxun Yang @ 2021-10-23 12:31 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
在 2021/10/22 18:45, Philippe Mathieu-Daudé 写道:
> When using the Loongson-3A4000 CPU, the MSAIR is returned with a
> zero value (because unimplemented). Checking on real hardware,
> this value appears incorrect:
>
> $ cat /proc/cpuinfo
> system type : generic-loongson-machine
> machine : loongson,generic
> cpu model : Loongson-3 V0.4 FPU V0.1
> model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
> isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
> ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2
> ...
>
> Checking the CFCMSA opcode result with gdb we get 0x60140:
>
> Breakpoint 1, 0x00000001200037c4 in main ()
> 1: x/i $pc
> => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir
> (gdb) si
> 0x00000001200037c8 in main ()
> (gdb) i r v0
> v0: 0x60140
>
> So set MSAIR=0x60140 for the Loongson-3A4000 CPU model added in
> commit af868995e1b ("target/mips: Add Loongson-3 CPU definition").
>
> Cc: Huacai Chen <chenhuacai@kernel.org>
> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> target/mips/cpu-defs.c.inc | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index cbc45fcb0e8..f43a8e7c9d9 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -886,6 +886,7 @@ const mips_def_t mips_defs[] =
> (0x1 << FCR0_D) | (0x1 << FCR0_S),
> .CP1_fcr31 = 0,
> .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
> + .MSAIR = (0x601 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
> .SEGBITS = 48,
> .PABITS = 48,
> .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] target/mips: MSA opcode fixes
2021-10-22 17:45 [PATCH 0/3] target/mips: MSA opcode fixes Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-10-22 17:45 ` [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register Philippe Mathieu-Daudé
@ 2021-10-26 18:08 ` Philippe Mathieu-Daudé
3 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-26 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
On 10/22/21 19:45, Philippe Mathieu-Daudé wrote:
> Fix a pair of MSA opcodes, and update the MSA_IR config register
> in the Loongson-3A4000 model.
>
> Philippe Mathieu-Daudé (3):
> target/mips: Fix MSA MADDV.B opcode
> target/mips: Fix MSA MSUBV.B opcode
Patches 1 & 2 applied to mips-next.
^ permalink raw reply [flat|nested] 9+ messages in thread