* [PATCH 0/7] SUNIV USB support (and updating mailmap)
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
This patchset introduces support for F1C100s' USB.
As I switched to a new mail address, and this patchset contains patches
authored before this change, a mailmap update is added.
The DT binding and driver support for SUNIV USB PHY/MUSB are added, in
addition to DT changes to the DTSI and Lichee Nano DT.
Icenowy Zheng (7):
mailmap: update Icenowy Zheng's mail address
dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string
phy: sun4i-usb: add support for the USB PHY on F1C100s SoC
musb: sunxi: add support for the F1C100s MUSB controller
ARM: suniv: add USB-related device nodes
ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
.mailmap | 3 +
.../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
.../usb/allwinner,sun4i-a10-musb.yaml | 1 +
.../boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++
arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
drivers/usb/musb/sunxi.c | 8 +-
7 files changed, 146 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 0/7] SUNIV USB support (and updating mailmap)
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
This patchset introduces support for F1C100s' USB.
As I switched to a new mail address, and this patchset contains patches
authored before this change, a mailmap update is added.
The DT binding and driver support for SUNIV USB PHY/MUSB are added, in
addition to DT changes to the DTSI and Lichee Nano DT.
Icenowy Zheng (7):
mailmap: update Icenowy Zheng's mail address
dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string
phy: sun4i-usb: add support for the USB PHY on F1C100s SoC
musb: sunxi: add support for the F1C100s MUSB controller
ARM: suniv: add USB-related device nodes
ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
.mailmap | 3 +
.../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
.../usb/allwinner,sun4i-a10-musb.yaml | 1 +
.../boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++
arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
drivers/usb/musb/sunxi.c | 8 +-
7 files changed, 146 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
--
2.36.0
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 0/7] SUNIV USB support (and updating mailmap)
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
This patchset introduces support for F1C100s' USB.
As I switched to a new mail address, and this patchset contains patches
authored before this change, a mailmap update is added.
The DT binding and driver support for SUNIV USB PHY/MUSB are added, in
addition to DT changes to the DTSI and Lichee Nano DT.
Icenowy Zheng (7):
mailmap: update Icenowy Zheng's mail address
dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string
phy: sun4i-usb: add support for the USB PHY on F1C100s SoC
musb: sunxi: add support for the F1C100s MUSB controller
ARM: suniv: add USB-related device nodes
ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
.mailmap | 3 +
.../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
.../usb/allwinner,sun4i-a10-musb.yaml | 1 +
.../boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++
arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
drivers/usb/musb/sunxi.c | 8 +-
7 files changed, 146 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/7] mailmap: update Icenowy Zheng's mail address
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 7:04 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Due to the SMTP provider adopted by AOSC applied some more restricted
rate limit that is not suitable for sending kernel patches, I switched
to a mailbox hosted on my own domain name now. In addition, there's a
single commit that is pushed to the mainline kernel tree during my
internship at Sipeed the last year.
Map two AOSC mail addresses (both aosc.io and aosc.xyz domain names) and
a defunct Sipeed mail address to the new mail address.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.mailmap | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.mailmap b/.mailmap
index 825fae8e6b7b..b4065082029e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -150,6 +150,9 @@ Henrik Rydberg <rydberg@bitmath.org>
Herbert Xu <herbert@gondor.apana.org.au>
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.io>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.xyz>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@sipeed.com>
Jacob Shin <Jacob.Shin@amd.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 1/7] mailmap: update Icenowy Zheng's mail address
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Due to the SMTP provider adopted by AOSC applied some more restricted
rate limit that is not suitable for sending kernel patches, I switched
to a mailbox hosted on my own domain name now. In addition, there's a
single commit that is pushed to the mainline kernel tree during my
internship at Sipeed the last year.
Map two AOSC mail addresses (both aosc.io and aosc.xyz domain names) and
a defunct Sipeed mail address to the new mail address.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.mailmap | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.mailmap b/.mailmap
index 825fae8e6b7b..b4065082029e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -150,6 +150,9 @@ Henrik Rydberg <rydberg@bitmath.org>
Herbert Xu <herbert@gondor.apana.org.au>
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.io>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.xyz>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@sipeed.com>
Jacob Shin <Jacob.Shin@amd.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
--
2.36.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 1/7] mailmap: update Icenowy Zheng's mail address
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Due to the SMTP provider adopted by AOSC applied some more restricted
rate limit that is not suitable for sending kernel patches, I switched
to a mailbox hosted on my own domain name now. In addition, there's a
single commit that is pushed to the mainline kernel tree during my
internship at Sipeed the last year.
Map two AOSC mail addresses (both aosc.io and aosc.xyz domain names) and
a defunct Sipeed mail address to the new mail address.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.mailmap | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.mailmap b/.mailmap
index 825fae8e6b7b..b4065082029e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -150,6 +150,9 @@ Henrik Rydberg <rydberg@bitmath.org>
Herbert Xu <herbert@gondor.apana.org.au>
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.io>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@aosc.xyz>
+Icenowy Zheng <uwu@icenowy.me> <icenowy@sipeed.com>
Jacob Shin <Jacob.Shin@amd.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 7:04 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
because it has only one OTG USB controller, no host-only OHCI/EHCI
controllers.
Add a binding document for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
new file mode 100644
index 000000000000..180fa8840bf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner F1C100s USB PHY Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ "#phy-cells":
+ const: 1
+
+ compatible:
+ const: allwinner,suniv-f1c100s-usb-phy
+
+ reg:
+ maxItems: 1
+ description: PHY Control registers
+
+ reg-names:
+ const: phy_ctrl
+
+ clocks:
+ maxItems: 1
+ description: USB OTG PHY bus clock
+
+ clock-names:
+ const: usb0_phy
+
+ resets:
+ maxItems: 1
+ description: USB OTG reset
+
+ reset-names:
+ const: usb0_reset
+
+ usb0_id_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG ID pin
+
+ usb0_vbus_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG VBUS detect pin
+
+ usb0_vbus_power-supply:
+ description: Power supply to detect the USB OTG VBUS
+
+ usb0_vbus-supply:
+ description: Regulator controlling USB OTG VBUS
+
+required:
+ - "#phy-cells"
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
+ #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
+
+ phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
+ };
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
because it has only one OTG USB controller, no host-only OHCI/EHCI
controllers.
Add a binding document for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
new file mode 100644
index 000000000000..180fa8840bf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner F1C100s USB PHY Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ "#phy-cells":
+ const: 1
+
+ compatible:
+ const: allwinner,suniv-f1c100s-usb-phy
+
+ reg:
+ maxItems: 1
+ description: PHY Control registers
+
+ reg-names:
+ const: phy_ctrl
+
+ clocks:
+ maxItems: 1
+ description: USB OTG PHY bus clock
+
+ clock-names:
+ const: usb0_phy
+
+ resets:
+ maxItems: 1
+ description: USB OTG reset
+
+ reset-names:
+ const: usb0_reset
+
+ usb0_id_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG ID pin
+
+ usb0_vbus_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG VBUS detect pin
+
+ usb0_vbus_power-supply:
+ description: Power supply to detect the USB OTG VBUS
+
+ usb0_vbus-supply:
+ description: Regulator controlling USB OTG VBUS
+
+required:
+ - "#phy-cells"
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
+ #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
+
+ phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
+ };
--
2.36.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
because it has only one OTG USB controller, no host-only OHCI/EHCI
controllers.
Add a binding document for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
new file mode 100644
index 000000000000..180fa8840bf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner F1C100s USB PHY Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ "#phy-cells":
+ const: 1
+
+ compatible:
+ const: allwinner,suniv-f1c100s-usb-phy
+
+ reg:
+ maxItems: 1
+ description: PHY Control registers
+
+ reg-names:
+ const: phy_ctrl
+
+ clocks:
+ maxItems: 1
+ description: USB OTG PHY bus clock
+
+ clock-names:
+ const: usb0_phy
+
+ resets:
+ maxItems: 1
+ description: USB OTG reset
+
+ reset-names:
+ const: usb0_reset
+
+ usb0_id_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG ID pin
+
+ usb0_vbus_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG VBUS detect pin
+
+ usb0_vbus_power-supply:
+ description: Power supply to detect the USB OTG VBUS
+
+ usb0_vbus-supply:
+ description: Regulator controlling USB OTG VBUS
+
+required:
+ - "#phy-cells"
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
+ #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
+
+ phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
+ };
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/7] dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 7:04 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Allwinner F1C100s has a hybrid MUSB controller between the A10 one and
the A33 one.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
index 933fa356d2ce..144f562f2591 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
@@ -17,6 +17,7 @@ properties:
- const: allwinner,sun6i-a31-musb
- const: allwinner,sun8i-a33-musb
- const: allwinner,sun8i-h3-musb
+ - const: allwinner,suniv-f1c100s-musb
- items:
- enum:
- allwinner,sun8i-a83t-musb
--
2.36.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/7] dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Allwinner F1C100s has a hybrid MUSB controller between the A10 one and
the A33 one.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
index 933fa356d2ce..144f562f2591 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
@@ -17,6 +17,7 @@ properties:
- const: allwinner,sun6i-a31-musb
- const: allwinner,sun8i-a33-musb
- const: allwinner,sun8i-h3-musb
+ - const: allwinner,suniv-f1c100s-musb
- items:
- enum:
- allwinner,sun8i-a83t-musb
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/7] dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
Allwinner F1C100s has a hybrid MUSB controller between the A10 one and
the A33 one.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
index 933fa356d2ce..144f562f2591 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
@@ -17,6 +17,7 @@ properties:
- const: allwinner,sun6i-a31-musb
- const: allwinner,sun8i-a33-musb
- const: allwinner,sun8i-h3-musb
+ - const: allwinner,suniv-f1c100s-musb
- items:
- enum:
- allwinner,sun8i-a83t-musb
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/7] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 7:04 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The F1C100s SoC has one USB OTG port connected to a MUSB controller.
Add support for its USB PHY.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index d5f3b42eb8ce..f6592c8d611b 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
sun8i_v3s_phy,
sun50i_a64_phy,
sun50i_h6_phy,
+ suniv_f1c100s_phy,
};
struct sun4i_usb_phy_cfg {
@@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return 0;
}
+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
+ .num_phys = 1,
+ .type = suniv_f1c100s_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A10,
+ .dedicated_clocks = true,
+};
+
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.num_phys = 3,
.type = sun4i_a10_phy,
@@ -988,6 +997,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = &sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
+ { .compatible = "allwinner,suniv-f1c100s-usb-phy",
+ .data = &suniv_f1c100s_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.36.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/7] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The F1C100s SoC has one USB OTG port connected to a MUSB controller.
Add support for its USB PHY.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index d5f3b42eb8ce..f6592c8d611b 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
sun8i_v3s_phy,
sun50i_a64_phy,
sun50i_h6_phy,
+ suniv_f1c100s_phy,
};
struct sun4i_usb_phy_cfg {
@@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return 0;
}
+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
+ .num_phys = 1,
+ .type = suniv_f1c100s_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A10,
+ .dedicated_clocks = true,
+};
+
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.num_phys = 3,
.type = sun4i_a10_phy,
@@ -988,6 +997,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = &sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
+ { .compatible = "allwinner,suniv-f1c100s-usb-phy",
+ .data = &suniv_f1c100s_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/7] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The F1C100s SoC has one USB OTG port connected to a MUSB controller.
Add support for its USB PHY.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index d5f3b42eb8ce..f6592c8d611b 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -109,6 +109,7 @@ enum sun4i_usb_phy_type {
sun8i_v3s_phy,
sun50i_a64_phy,
sun50i_h6_phy,
+ suniv_f1c100s_phy,
};
struct sun4i_usb_phy_cfg {
@@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return 0;
}
+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
+ .num_phys = 1,
+ .type = suniv_f1c100s_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A10,
+ .dedicated_clocks = true,
+};
+
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.num_phys = 3,
.type = sun4i_a10_phy,
@@ -988,6 +997,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = &sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
+ { .compatible = "allwinner,suniv-f1c100s-usb-phy",
+ .data = &suniv_f1c100s_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/7] musb: sunxi: add support for the F1C100s MUSB controller
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 7:04 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The suniv SoC has a MUSB controller like the one in A33, but with a SRAM
region to be claimed.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/usb/musb/sunxi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 961c858fb349..2cb512e172f8 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -722,14 +722,17 @@ static int sunxi_musb_probe(struct platform_device *pdev)
INIT_WORK(&glue->work, sunxi_musb_work);
glue->host_nb.notifier_call = sunxi_musb_host_notifier;
- if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
+ }
if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
- of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
+ of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
}
@@ -826,6 +829,7 @@ static const struct of_device_id sunxi_musb_match[] = {
{ .compatible = "allwinner,sun6i-a31-musb", },
{ .compatible = "allwinner,sun8i-a33-musb", },
{ .compatible = "allwinner,sun8i-h3-musb", },
+ { .compatible = "allwinner,suniv-f1c100s-musb", },
{}
};
MODULE_DEVICE_TABLE(of, sunxi_musb_match);
--
2.36.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/7] musb: sunxi: add support for the F1C100s MUSB controller
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The suniv SoC has a MUSB controller like the one in A33, but with a SRAM
region to be claimed.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/usb/musb/sunxi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 961c858fb349..2cb512e172f8 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -722,14 +722,17 @@ static int sunxi_musb_probe(struct platform_device *pdev)
INIT_WORK(&glue->work, sunxi_musb_work);
glue->host_nb.notifier_call = sunxi_musb_host_notifier;
- if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
+ }
if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
- of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
+ of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
}
@@ -826,6 +829,7 @@ static const struct of_device_id sunxi_musb_match[] = {
{ .compatible = "allwinner,sun6i-a31-musb", },
{ .compatible = "allwinner,sun8i-a33-musb", },
{ .compatible = "allwinner,sun8i-h3-musb", },
+ { .compatible = "allwinner,suniv-f1c100s-musb", },
{}
};
MODULE_DEVICE_TABLE(of, sunxi_musb_match);
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/7] musb: sunxi: add support for the F1C100s MUSB controller
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The suniv SoC has a MUSB controller like the one in A33, but with a SRAM
region to be claimed.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/usb/musb/sunxi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 961c858fb349..2cb512e172f8 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -722,14 +722,17 @@ static int sunxi_musb_probe(struct platform_device *pdev)
INIT_WORK(&glue->work, sunxi_musb_work);
glue->host_nb.notifier_call = sunxi_musb_host_notifier;
- if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
+ }
if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
- of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
+ of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
}
@@ -826,6 +829,7 @@ static const struct of_device_id sunxi_musb_match[] = {
{ .compatible = "allwinner,sun6i-a31-musb", },
{ .compatible = "allwinner,sun8i-a33-musb", },
{ .compatible = "allwinner,sun8i-h3-musb", },
+ { .compatible = "allwinner,suniv-f1c100s-musb", },
{}
};
MODULE_DEVICE_TABLE(of, sunxi_musb_match);
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/7] ARM: suniv: add USB-related device nodes
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 7:04 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.
Add their device tree node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0edc1724407b..a01541ba42c5 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -133,6 +133,32 @@ mmc1: mmc@1c10000 {
#size-cells = <0>;
};
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>;
--
2.36.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/7] ARM: suniv: add USB-related device nodes
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.
Add their device tree node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0edc1724407b..a01541ba42c5 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -133,6 +133,32 @@ mmc1: mmc@1c10000 {
#size-cells = <0>;
};
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>;
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/7] ARM: suniv: add USB-related device nodes
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.
Add their device tree node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0edc1724407b..a01541ba42c5 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -133,6 +133,32 @@ mmc1: mmc@1c10000 {
#size-cells = <0>;
};
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>;
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 7/7] ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 7:04 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected
to the USB pins of the SoC and ID pin connected to PE2 GPIO.
Enable the USB functionality.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index 04e59b8381cb..1935d8c8855b 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "suniv-f1c100s.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -50,8 +52,22 @@ flash@0 {
};
};
+&otg_sram {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
--
2.36.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 7/7] ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected
to the USB pins of the SoC and ID pin connected to PE2 GPIO.
Enable the USB functionality.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index 04e59b8381cb..1935d8c8855b 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "suniv-f1c100s.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -50,8 +52,22 @@ flash@0 {
};
};
+&otg_sram {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
--
2.36.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 7/7] ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
@ 2022-06-08 7:04 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 7:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Greg Kroah-Hartman, Bin Liu
Cc: linux-kernel, linux-phy, devicetree, linux-arm-kernel,
linux-sunxi, linux-usb, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected
to the USB pins of the SoC and ID pin connected to PE2 GPIO.
Enable the USB functionality.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index 04e59b8381cb..1935d8c8855b 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "suniv-f1c100s.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -50,8 +52,22 @@ flash@0 {
};
};
+&otg_sram {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 13:45 ` Rob Herring
-1 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-08 13:45 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Samuel Holland, Greg Kroah-Hartman, Rob Herring, Jernej Skrabec,
Chen-Yu Tsai, linux-phy, Bin Liu, linux-usb, Vinod Koul,
linux-arm-kernel, linux-sunxi, linux-kernel,
Kishon Vijay Abraham I, devicetree
On Wed, 08 Jun 2022 15:04:47 +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dts:19:18: fatal error: dt-bindings/clock/suniv-f1c100s-ccu.h: No such file or directory
19 | #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:383: Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1404: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 13:45 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-08 13:45 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Samuel Holland, Greg Kroah-Hartman, Rob Herring, Jernej Skrabec,
Chen-Yu Tsai, linux-phy, Bin Liu, linux-usb, Vinod Koul,
linux-arm-kernel, linux-sunxi, linux-kernel,
Kishon Vijay Abraham I, devicetree
On Wed, 08 Jun 2022 15:04:47 +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dts:19:18: fatal error: dt-bindings/clock/suniv-f1c100s-ccu.h: No such file or directory
19 | #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:383: Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1404: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 13:45 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-08 13:45 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Samuel Holland, Greg Kroah-Hartman, Rob Herring, Jernej Skrabec,
Chen-Yu Tsai, linux-phy, Bin Liu, linux-usb, Vinod Koul,
linux-arm-kernel, linux-sunxi, linux-kernel,
Kishon Vijay Abraham I, devicetree
On Wed, 08 Jun 2022 15:04:47 +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dts:19:18: fatal error: dt-bindings/clock/suniv-f1c100s-ccu.h: No such file or directory
19 | #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:383: Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1404: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
2022-06-08 7:04 ` Icenowy Zheng
(?)
@ 2022-06-08 14:49 ` Rob Herring
-1 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-08 14:49 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> new file mode 100644
> index 000000000000..180fa8840bf7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license please.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner F1C100s USB PHY Device Tree Bindings
> +
> +maintainers:
> + - Chen-Yu Tsai <wens@csie.org>
> + - Maxime Ripard <mripard@kernel.org>
> +
> +properties:
> + "#phy-cells":
> + const: 1
> +
> + compatible:
> + const: allwinner,suniv-f1c100s-usb-phy
> +
> + reg:
> + maxItems: 1
> + description: PHY Control registers
> +
> + reg-names:
> + const: phy_ctrl
> +
> + clocks:
> + maxItems: 1
> + description: USB OTG PHY bus clock
> +
> + clock-names:
> + const: usb0_phy
*-names is not needed with only one entry. Plus, just using the module
name is not a great choice.
> +
> + resets:
> + maxItems: 1
> + description: USB OTG reset
> +
> + reset-names:
> + const: usb0_reset
Same here.
> + usb0_id_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG ID pin
> +
> + usb0_vbus_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG VBUS detect pin
> +
> + usb0_vbus_power-supply:
> + description: Power supply to detect the USB OTG VBUS
> +
> + usb0_vbus-supply:
> + description: Regulator controlling USB OTG VBUS
Why the 'usb0_' prefix?
Are these GPIOs and Vbus supply connected to the phy? If not, these all
belong in a connector node (as that is where they are connected to in
h/w).
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> + - reg-names
> + - resets
> + - reset-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> +
> + phy@1c13400 {
> + compatible = "allwinner,suniv-f1c100s-usb-phy";
> + reg = <0x01c13400 0x10>;
> + reg-names = "phy_ctrl";
> + clocks = <&ccu CLK_USB_PHY0>;
> + clock-names = "usb0_phy";
> + resets = <&ccu RST_USB_PHY0>;
> + reset-names = "usb0_reset";
> + #phy-cells = <1>;
> + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> + };
> --
> 2.36.0
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 14:49 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-08 14:49 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> new file mode 100644
> index 000000000000..180fa8840bf7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license please.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner F1C100s USB PHY Device Tree Bindings
> +
> +maintainers:
> + - Chen-Yu Tsai <wens@csie.org>
> + - Maxime Ripard <mripard@kernel.org>
> +
> +properties:
> + "#phy-cells":
> + const: 1
> +
> + compatible:
> + const: allwinner,suniv-f1c100s-usb-phy
> +
> + reg:
> + maxItems: 1
> + description: PHY Control registers
> +
> + reg-names:
> + const: phy_ctrl
> +
> + clocks:
> + maxItems: 1
> + description: USB OTG PHY bus clock
> +
> + clock-names:
> + const: usb0_phy
*-names is not needed with only one entry. Plus, just using the module
name is not a great choice.
> +
> + resets:
> + maxItems: 1
> + description: USB OTG reset
> +
> + reset-names:
> + const: usb0_reset
Same here.
> + usb0_id_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG ID pin
> +
> + usb0_vbus_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG VBUS detect pin
> +
> + usb0_vbus_power-supply:
> + description: Power supply to detect the USB OTG VBUS
> +
> + usb0_vbus-supply:
> + description: Regulator controlling USB OTG VBUS
Why the 'usb0_' prefix?
Are these GPIOs and Vbus supply connected to the phy? If not, these all
belong in a connector node (as that is where they are connected to in
h/w).
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> + - reg-names
> + - resets
> + - reset-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> +
> + phy@1c13400 {
> + compatible = "allwinner,suniv-f1c100s-usb-phy";
> + reg = <0x01c13400 0x10>;
> + reg-names = "phy_ctrl";
> + clocks = <&ccu CLK_USB_PHY0>;
> + clock-names = "usb0_phy";
> + resets = <&ccu RST_USB_PHY0>;
> + reset-names = "usb0_reset";
> + #phy-cells = <1>;
> + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> + };
> --
> 2.36.0
>
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 14:49 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-08 14:49 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> new file mode 100644
> index 000000000000..180fa8840bf7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license please.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner F1C100s USB PHY Device Tree Bindings
> +
> +maintainers:
> + - Chen-Yu Tsai <wens@csie.org>
> + - Maxime Ripard <mripard@kernel.org>
> +
> +properties:
> + "#phy-cells":
> + const: 1
> +
> + compatible:
> + const: allwinner,suniv-f1c100s-usb-phy
> +
> + reg:
> + maxItems: 1
> + description: PHY Control registers
> +
> + reg-names:
> + const: phy_ctrl
> +
> + clocks:
> + maxItems: 1
> + description: USB OTG PHY bus clock
> +
> + clock-names:
> + const: usb0_phy
*-names is not needed with only one entry. Plus, just using the module
name is not a great choice.
> +
> + resets:
> + maxItems: 1
> + description: USB OTG reset
> +
> + reset-names:
> + const: usb0_reset
Same here.
> + usb0_id_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG ID pin
> +
> + usb0_vbus_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG VBUS detect pin
> +
> + usb0_vbus_power-supply:
> + description: Power supply to detect the USB OTG VBUS
> +
> + usb0_vbus-supply:
> + description: Regulator controlling USB OTG VBUS
Why the 'usb0_' prefix?
Are these GPIOs and Vbus supply connected to the phy? If not, these all
belong in a connector node (as that is where they are connected to in
h/w).
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> + - reg-names
> + - resets
> + - reset-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> +
> + phy@1c13400 {
> + compatible = "allwinner,suniv-f1c100s-usb-phy";
> + reg = <0x01c13400 0x10>;
> + reg-names = "phy_ctrl";
> + clocks = <&ccu CLK_USB_PHY0>;
> + clock-names = "usb0_phy";
> + resets = <&ccu RST_USB_PHY0>;
> + reset-names = "usb0_reset";
> + #phy-cells = <1>;
> + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> + };
> --
> 2.36.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
2022-06-08 14:49 ` Rob Herring
(?)
@ 2022-06-08 14:52 ` Icenowy Zheng
-1 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 14:52 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
在 2022-06-08星期三的 08:49 -0600,Rob Herring写道:
> On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > SoCs,
> > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > controllers.
> >
> > Add a binding document for it.
> >
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > ---
> > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > +++++++++++++++++++
> > 1 file changed, 83 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > usb-phy.yaml
> > new file mode 100644
> > index 000000000000..180fa8840bf7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > @@ -0,0 +1,83 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license please.
I am based on another Allwinner USB PHY binding file in the same
directory, and that file is single licensed. I created a new file
because each variant of the PHY has a single file now.
>
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > +
> > +maintainers:
> > + - Chen-Yu Tsai <wens@csie.org>
> > + - Maxime Ripard <mripard@kernel.org>
> > +
> > +properties:
> > + "#phy-cells":
> > + const: 1
> > +
> > + compatible:
> > + const: allwinner,suniv-f1c100s-usb-phy
> > +
> > + reg:
> > + maxItems: 1
> > + description: PHY Control registers
> > +
> > + reg-names:
> > + const: phy_ctrl
> > +
> > + clocks:
> > + maxItems: 1
> > + description: USB OTG PHY bus clock
> > +
> > + clock-names:
> > + const: usb0_phy
>
> *-names is not needed with only one entry. Plus, just using the
> module
> name is not a great choice.
However the driver expects it...
Should I patch the driver to use no name on F1C100s?
>
> > +
> > + resets:
> > + maxItems: 1
> > + description: USB OTG reset
> > +
> > + reset-names:
> > + const: usb0_reset
>
> Same here.
>
> > + usb0_id_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG ID pin
> > +
> > + usb0_vbus_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG VBUS detect pin
> > +
> > + usb0_vbus_power-supply:
> > + description: Power supply to detect the USB OTG VBUS
> > +
> > + usb0_vbus-supply:
> > + description: Regulator controlling USB OTG VBUS
>
> Why the 'usb0_' prefix?
>
> Are these GPIOs and Vbus supply connected to the phy? If not, these
> all
> belong in a connector node (as that is where they are connected to in
> h/w).
Well these are historical things of phy-sun4i-usb driver too.
>
> > +
> > +required:
> > + - "#phy-cells"
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - reg
> > + - reg-names
> > + - resets
> > + - reset-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/gpio/gpio.h>
> > + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> > + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> > +
> > + phy@1c13400 {
> > + compatible = "allwinner,suniv-f1c100s-usb-phy";
> > + reg = <0x01c13400 0x10>;
> > + reg-names = "phy_ctrl";
> > + clocks = <&ccu CLK_USB_PHY0>;
> > + clock-names = "usb0_phy";
> > + resets = <&ccu RST_USB_PHY0>;
> > + reset-names = "usb0_reset";
> > + #phy-cells = <1>;
> > + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> > + };
> > --
> > 2.36.0
> >
> >
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 14:52 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 14:52 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
在 2022-06-08星期三的 08:49 -0600,Rob Herring写道:
> On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > SoCs,
> > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > controllers.
> >
> > Add a binding document for it.
> >
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > ---
> > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > +++++++++++++++++++
> > 1 file changed, 83 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > usb-phy.yaml
> > new file mode 100644
> > index 000000000000..180fa8840bf7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > @@ -0,0 +1,83 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license please.
I am based on another Allwinner USB PHY binding file in the same
directory, and that file is single licensed. I created a new file
because each variant of the PHY has a single file now.
>
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > +
> > +maintainers:
> > + - Chen-Yu Tsai <wens@csie.org>
> > + - Maxime Ripard <mripard@kernel.org>
> > +
> > +properties:
> > + "#phy-cells":
> > + const: 1
> > +
> > + compatible:
> > + const: allwinner,suniv-f1c100s-usb-phy
> > +
> > + reg:
> > + maxItems: 1
> > + description: PHY Control registers
> > +
> > + reg-names:
> > + const: phy_ctrl
> > +
> > + clocks:
> > + maxItems: 1
> > + description: USB OTG PHY bus clock
> > +
> > + clock-names:
> > + const: usb0_phy
>
> *-names is not needed with only one entry. Plus, just using the
> module
> name is not a great choice.
However the driver expects it...
Should I patch the driver to use no name on F1C100s?
>
> > +
> > + resets:
> > + maxItems: 1
> > + description: USB OTG reset
> > +
> > + reset-names:
> > + const: usb0_reset
>
> Same here.
>
> > + usb0_id_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG ID pin
> > +
> > + usb0_vbus_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG VBUS detect pin
> > +
> > + usb0_vbus_power-supply:
> > + description: Power supply to detect the USB OTG VBUS
> > +
> > + usb0_vbus-supply:
> > + description: Regulator controlling USB OTG VBUS
>
> Why the 'usb0_' prefix?
>
> Are these GPIOs and Vbus supply connected to the phy? If not, these
> all
> belong in a connector node (as that is where they are connected to in
> h/w).
Well these are historical things of phy-sun4i-usb driver too.
>
> > +
> > +required:
> > + - "#phy-cells"
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - reg
> > + - reg-names
> > + - resets
> > + - reset-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/gpio/gpio.h>
> > + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> > + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> > +
> > + phy@1c13400 {
> > + compatible = "allwinner,suniv-f1c100s-usb-phy";
> > + reg = <0x01c13400 0x10>;
> > + reg-names = "phy_ctrl";
> > + clocks = <&ccu CLK_USB_PHY0>;
> > + clock-names = "usb0_phy";
> > + resets = <&ccu RST_USB_PHY0>;
> > + reset-names = "usb0_reset";
> > + #phy-cells = <1>;
> > + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> > + };
> > --
> > 2.36.0
> >
> >
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-08 14:52 ` Icenowy Zheng
0 siblings, 0 replies; 36+ messages in thread
From: Icenowy Zheng @ 2022-06-08 14:52 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
在 2022-06-08星期三的 08:49 -0600,Rob Herring写道:
> On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > SoCs,
> > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > controllers.
> >
> > Add a binding document for it.
> >
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > ---
> > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > +++++++++++++++++++
> > 1 file changed, 83 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > usb-phy.yaml
> > new file mode 100644
> > index 000000000000..180fa8840bf7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > @@ -0,0 +1,83 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license please.
I am based on another Allwinner USB PHY binding file in the same
directory, and that file is single licensed. I created a new file
because each variant of the PHY has a single file now.
>
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > +
> > +maintainers:
> > + - Chen-Yu Tsai <wens@csie.org>
> > + - Maxime Ripard <mripard@kernel.org>
> > +
> > +properties:
> > + "#phy-cells":
> > + const: 1
> > +
> > + compatible:
> > + const: allwinner,suniv-f1c100s-usb-phy
> > +
> > + reg:
> > + maxItems: 1
> > + description: PHY Control registers
> > +
> > + reg-names:
> > + const: phy_ctrl
> > +
> > + clocks:
> > + maxItems: 1
> > + description: USB OTG PHY bus clock
> > +
> > + clock-names:
> > + const: usb0_phy
>
> *-names is not needed with only one entry. Plus, just using the
> module
> name is not a great choice.
However the driver expects it...
Should I patch the driver to use no name on F1C100s?
>
> > +
> > + resets:
> > + maxItems: 1
> > + description: USB OTG reset
> > +
> > + reset-names:
> > + const: usb0_reset
>
> Same here.
>
> > + usb0_id_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG ID pin
> > +
> > + usb0_vbus_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG VBUS detect pin
> > +
> > + usb0_vbus_power-supply:
> > + description: Power supply to detect the USB OTG VBUS
> > +
> > + usb0_vbus-supply:
> > + description: Regulator controlling USB OTG VBUS
>
> Why the 'usb0_' prefix?
>
> Are these GPIOs and Vbus supply connected to the phy? If not, these
> all
> belong in a connector node (as that is where they are connected to in
> h/w).
Well these are historical things of phy-sun4i-usb driver too.
>
> > +
> > +required:
> > + - "#phy-cells"
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - reg
> > + - reg-names
> > + - resets
> > + - reset-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/gpio/gpio.h>
> > + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> > + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> > +
> > + phy@1c13400 {
> > + compatible = "allwinner,suniv-f1c100s-usb-phy";
> > + reg = <0x01c13400 0x10>;
> > + reg-names = "phy_ctrl";
> > + clocks = <&ccu CLK_USB_PHY0>;
> > + clock-names = "usb0_phy";
> > + resets = <&ccu RST_USB_PHY0>;
> > + reset-names = "usb0_reset";
> > + #phy-cells = <1>;
> > + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> > + };
> > --
> > 2.36.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
2022-06-08 14:52 ` Icenowy Zheng
(?)
@ 2022-06-16 15:59 ` Rob Herring
-1 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-16 15:59 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
On Wed, Jun 08, 2022 at 10:52:52PM +0800, Icenowy Zheng wrote:
> 在 2022-06-08星期三的 08:49 -0600,Rob Herring写道:
> > On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > > SoCs,
> > > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > > controllers.
> > >
> > > Add a binding document for it.
> > >
> > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > > ---
> > > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > > +++++++++++++++++++
> > > 1 file changed, 83 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > > phy.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > > usb-phy.yaml
> > > new file mode 100644
> > > index 000000000000..180fa8840bf7
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > @@ -0,0 +1,83 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> >
> > Dual license please.
>
> I am based on another Allwinner USB PHY binding file in the same
> directory, and that file is single licensed. I created a new file
> because each variant of the PHY has a single file now.
Okay, describing the source and the differences in the commit message
would be helpful.
>
> >
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Chen-Yu Tsai <wens@csie.org>
> > > + - Maxime Ripard <mripard@kernel.org>
> > > +
> > > +properties:
> > > + "#phy-cells":
> > > + const: 1
> > > +
> > > + compatible:
> > > + const: allwinner,suniv-f1c100s-usb-phy
> > > +
> > > + reg:
> > > + maxItems: 1
> > > + description: PHY Control registers
> > > +
> > > + reg-names:
> > > + const: phy_ctrl
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > + description: USB OTG PHY bus clock
> > > +
> > > + clock-names:
> > > + const: usb0_phy
> >
> > *-names is not needed with only one entry. Plus, just using the
> > module
> > name is not a great choice.
>
> However the driver expects it...
>
> Should I patch the driver to use no name on F1C100s?
>
> >
> > > +
> > > + resets:
> > > + maxItems: 1
> > > + description: USB OTG reset
> > > +
> > > + reset-names:
> > > + const: usb0_reset
> >
> > Same here.
> >
> > > + usb0_id_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG ID pin
> > > +
> > > + usb0_vbus_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG VBUS detect pin
> > > +
> > > + usb0_vbus_power-supply:
> > > + description: Power supply to detect the USB OTG VBUS
> > > +
> > > + usb0_vbus-supply:
> > > + description: Regulator controlling USB OTG VBUS
> >
> > Why the 'usb0_' prefix?
> >
> > Are these GPIOs and Vbus supply connected to the phy? If not, these
> > all
> > belong in a connector node (as that is where they are connected to in
> > h/w).
>
> Well these are historical things of phy-sun4i-usb driver too.
Okay, there should perhaps be a common schema so this sharing is clear.
Though longer term there should be a move to the common way of handling
these for new platforms.
So I guess in summary:
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-16 15:59 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-16 15:59 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
On Wed, Jun 08, 2022 at 10:52:52PM +0800, Icenowy Zheng wrote:
> 在 2022-06-08星期三的 08:49 -0600,Rob Herring写道:
> > On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > > SoCs,
> > > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > > controllers.
> > >
> > > Add a binding document for it.
> > >
> > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > > ---
> > > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > > +++++++++++++++++++
> > > 1 file changed, 83 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > > phy.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > > usb-phy.yaml
> > > new file mode 100644
> > > index 000000000000..180fa8840bf7
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > @@ -0,0 +1,83 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> >
> > Dual license please.
>
> I am based on another Allwinner USB PHY binding file in the same
> directory, and that file is single licensed. I created a new file
> because each variant of the PHY has a single file now.
Okay, describing the source and the differences in the commit message
would be helpful.
>
> >
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Chen-Yu Tsai <wens@csie.org>
> > > + - Maxime Ripard <mripard@kernel.org>
> > > +
> > > +properties:
> > > + "#phy-cells":
> > > + const: 1
> > > +
> > > + compatible:
> > > + const: allwinner,suniv-f1c100s-usb-phy
> > > +
> > > + reg:
> > > + maxItems: 1
> > > + description: PHY Control registers
> > > +
> > > + reg-names:
> > > + const: phy_ctrl
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > + description: USB OTG PHY bus clock
> > > +
> > > + clock-names:
> > > + const: usb0_phy
> >
> > *-names is not needed with only one entry. Plus, just using the
> > module
> > name is not a great choice.
>
> However the driver expects it...
>
> Should I patch the driver to use no name on F1C100s?
>
> >
> > > +
> > > + resets:
> > > + maxItems: 1
> > > + description: USB OTG reset
> > > +
> > > + reset-names:
> > > + const: usb0_reset
> >
> > Same here.
> >
> > > + usb0_id_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG ID pin
> > > +
> > > + usb0_vbus_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG VBUS detect pin
> > > +
> > > + usb0_vbus_power-supply:
> > > + description: Power supply to detect the USB OTG VBUS
> > > +
> > > + usb0_vbus-supply:
> > > + description: Regulator controlling USB OTG VBUS
> >
> > Why the 'usb0_' prefix?
> >
> > Are these GPIOs and Vbus supply connected to the phy? If not, these
> > all
> > belong in a connector node (as that is where they are connected to in
> > h/w).
>
> Well these are historical things of phy-sun4i-usb driver too.
Okay, there should perhaps be a common schema so this sharing is clear.
Though longer term there should be a move to the common way of handling
these for new platforms.
So I guess in summary:
Reviewed-by: Rob Herring <robh@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
@ 2022-06-16 15:59 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2022-06-16 15:59 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Kishon Vijay Abraham I, Vinod Koul, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Bin Liu, linux-kernel,
linux-phy, devicetree, linux-arm-kernel, linux-sunxi, linux-usb
On Wed, Jun 08, 2022 at 10:52:52PM +0800, Icenowy Zheng wrote:
> 在 2022-06-08星期三的 08:49 -0600,Rob Herring写道:
> > On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > > SoCs,
> > > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > > controllers.
> > >
> > > Add a binding document for it.
> > >
> > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > > ---
> > > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > > +++++++++++++++++++
> > > 1 file changed, 83 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > > phy.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > > usb-phy.yaml
> > > new file mode 100644
> > > index 000000000000..180fa8840bf7
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > @@ -0,0 +1,83 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> >
> > Dual license please.
>
> I am based on another Allwinner USB PHY binding file in the same
> directory, and that file is single licensed. I created a new file
> because each variant of the PHY has a single file now.
Okay, describing the source and the differences in the commit message
would be helpful.
>
> >
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Chen-Yu Tsai <wens@csie.org>
> > > + - Maxime Ripard <mripard@kernel.org>
> > > +
> > > +properties:
> > > + "#phy-cells":
> > > + const: 1
> > > +
> > > + compatible:
> > > + const: allwinner,suniv-f1c100s-usb-phy
> > > +
> > > + reg:
> > > + maxItems: 1
> > > + description: PHY Control registers
> > > +
> > > + reg-names:
> > > + const: phy_ctrl
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > + description: USB OTG PHY bus clock
> > > +
> > > + clock-names:
> > > + const: usb0_phy
> >
> > *-names is not needed with only one entry. Plus, just using the
> > module
> > name is not a great choice.
>
> However the driver expects it...
>
> Should I patch the driver to use no name on F1C100s?
>
> >
> > > +
> > > + resets:
> > > + maxItems: 1
> > > + description: USB OTG reset
> > > +
> > > + reset-names:
> > > + const: usb0_reset
> >
> > Same here.
> >
> > > + usb0_id_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG ID pin
> > > +
> > > + usb0_vbus_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG VBUS detect pin
> > > +
> > > + usb0_vbus_power-supply:
> > > + description: Power supply to detect the USB OTG VBUS
> > > +
> > > + usb0_vbus-supply:
> > > + description: Regulator controlling USB OTG VBUS
> >
> > Why the 'usb0_' prefix?
> >
> > Are these GPIOs and Vbus supply connected to the phy? If not, these
> > all
> > belong in a connector node (as that is where they are connected to in
> > h/w).
>
> Well these are historical things of phy-sun4i-usb driver too.
Okay, there should perhaps be a common schema so this sharing is clear.
Though longer term there should be a move to the common way of handling
these for new platforms.
So I guess in summary:
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-06-16 16:01 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-08 7:04 [PATCH 0/7] SUNIV USB support (and updating mailmap) Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` [PATCH 1/7] mailmap: update Icenowy Zheng's mail address Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` [PATCH 2/7] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 13:45 ` Rob Herring
2022-06-08 13:45 ` Rob Herring
2022-06-08 13:45 ` Rob Herring
2022-06-08 14:49 ` Rob Herring
2022-06-08 14:49 ` Rob Herring
2022-06-08 14:49 ` Rob Herring
2022-06-08 14:52 ` Icenowy Zheng
2022-06-08 14:52 ` Icenowy Zheng
2022-06-08 14:52 ` Icenowy Zheng
2022-06-16 15:59 ` Rob Herring
2022-06-16 15:59 ` Rob Herring
2022-06-16 15:59 ` Rob Herring
2022-06-08 7:04 ` [PATCH 3/7] dt-bindings: usb: sunxi-musb: add F1C100s MUSB compatible string Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` [PATCH 4/7] phy: sun4i-usb: add support for the USB PHY on F1C100s SoC Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` [PATCH 5/7] musb: sunxi: add support for the F1C100s MUSB controller Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` [PATCH 6/7] ARM: suniv: add USB-related device nodes Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` [PATCH 7/7] ARM: suniv: f1c100s: enable USB on Lichee Pi Nano Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
2022-06-08 7:04 ` Icenowy Zheng
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