From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
tianfei.zhang@intel.com, corbet@lwn.net,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-serial <linux-serial@vger.kernel.org>,
Jiri Slaby <jirislaby@kernel.org>,
geert+renesas@glider.be,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
johan@kernel.org, Lukas Wunner <lukas@wunner.de>,
marpagan@redhat.com
Subject: Re: [PATCH v4 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550.
Date: Fri, 21 Oct 2022 12:24:35 +0300 (EEST) [thread overview]
Message-ID: <37342f3-cac7-e127-5bea-27b78dbc31c@linux.intel.com> (raw)
In-Reply-To: <20221020212610.697729-5-matthew.gerlach@linux.intel.com>
On Thu, 20 Oct 2022, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Add a Device Feature List (DFL) bus driver for the Altera
> 16550 implementation of UART.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
> + p = dfh_find_param(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT);
> + if (!p)
> + return dev_err_probe(dev, -EINVAL, "missing REG_LAYOUT param\n");
> +
> + v = *p;
> + uart->port.regshift = FIELD_GET(DFHv1_PARAM_ID_REG_SHIFT, v);
> + reg_width = FIELD_GET(DFHv1_PARAM_ID_REG_WIDTH, v);
Just use *p directly for the FIELD_GETs. I suppose you can drop v after
changing it.
Other than that and what Andy noted, this patch looks good.
--
i.
next prev parent reply other threads:[~2022-10-21 9:24 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 21:26 [PATCH v4 0/4] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-10-20 21:26 ` [PATCH v4 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-10-21 3:55 ` Bagas Sanjaya
2022-10-24 15:01 ` matthew.gerlach
2022-10-21 8:28 ` Ilpo Järvinen
2022-10-21 8:36 ` Ilpo Järvinen
2022-10-20 21:26 ` [PATCH v4 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-10-21 8:06 ` Ilpo Järvinen
2022-10-24 15:03 ` matthew.gerlach
2022-10-20 21:26 ` [PATCH v4 3/4] fpga: dfl: add basic support DFHv1 matthew.gerlach
2022-10-20 22:07 ` Andy Shevchenko
2022-10-24 14:56 ` matthew.gerlach
2022-10-21 8:58 ` Ilpo Järvinen
2022-10-24 15:09 ` matthew.gerlach
2022-10-21 9:07 ` Ilpo Järvinen
2022-10-29 13:08 ` Xu Yilun
2022-10-29 14:47 ` matthew.gerlach
2022-11-01 22:37 ` matthew.gerlach
2022-11-03 1:36 ` Xu Yilun
2022-10-30 22:06 ` Andy Shevchenko
2022-10-31 1:16 ` Xu Yilun
2022-10-31 15:34 ` Andy Shevchenko
2022-10-31 20:15 ` matthew.gerlach
2022-11-01 1:55 ` Xu Yilun
2022-10-20 21:26 ` [PATCH v4 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-10-20 22:13 ` Andy Shevchenko
2022-10-21 4:33 ` Greg KH
2022-10-21 9:24 ` Ilpo Järvinen [this message]
2022-10-29 15:24 ` Xu Yilun
2022-11-01 0:34 ` matthew.gerlach
2022-11-01 1:46 ` Xu Yilun
2022-11-01 16:04 ` matthew.gerlach
2022-11-01 16:30 ` Ilpo Järvinen
2022-11-01 17:39 ` matthew.gerlach
2022-11-02 9:57 ` Ilpo Järvinen
2022-11-08 12:48 ` Marco Pagani
2022-11-08 12:51 ` Ilpo Järvinen
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