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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Xu Yilun <yilun.xu@intel.com>
Cc: matthew.gerlach@linux.intel.com, hao.wu@intel.com,
	russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com,
	trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	tianfei.zhang@intel.com, corbet@lwn.net, jirislaby@kernel.org,
	geert+renesas@glider.be, niklas.soderlund+renesas@ragnatech.se,
	macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de,
	ilpo.jarvinen@linux.intel.com, marpagan@redhat.com
Subject: Re: [PATCH v4 3/4] fpga: dfl: add basic support DFHv1
Date: Mon, 31 Oct 2022 00:06:28 +0200	[thread overview]
Message-ID: <Y171ZEHpOydtR4dW@smile.fi.intel.com> (raw)
In-Reply-To: <Y10l3NkIn0gsdVZq@yilunxu-OptiPlex-7050>

On Sat, Oct 29, 2022 at 09:08:44PM +0800, Xu Yilun wrote:
> On 2022-10-20 at 14:26:09 -0700, matthew.gerlach@linux.intel.com wrote:

> >  struct dfl_feature_info {
> >  	u16 fid;
> >  	u8 revision;
> > +	u8 dfh_version;
> >  	struct resource mmio_res;
> >  	void __iomem *ioaddr;
> >  	struct list_head node;
> >  	unsigned int irq_base;
> >  	unsigned int nr_irqs;
> > +	unsigned int param_size;
> > +	u64 params[];
> >  };

...

> > +	finfo = kzalloc(sizeof(*finfo) + dfh_psize, GFP_KERNEL);


This probably may use something from overflow.h.

> The u64 flexible array in the structure, but seems dfh_get_psize could
> not garantee 64bit aligned size.
> 
> What's the mandatory alignment of param data? If 64bit aligned, bit 33-34
> of PARAM_HDR should be reserved. If 32bit aligned, finfo:params should be
> u32[].

Isn't it guaranteed by the C standard / architecture ABI?

-- 
With Best Regards,
Andy Shevchenko



  parent reply	other threads:[~2022-10-30 22:06 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-20 21:26 [PATCH v4 0/4] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-10-20 21:26 ` [PATCH v4 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-10-21  3:55   ` Bagas Sanjaya
2022-10-24 15:01     ` matthew.gerlach
2022-10-21  8:28   ` Ilpo Järvinen
2022-10-21  8:36     ` Ilpo Järvinen
2022-10-20 21:26 ` [PATCH v4 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-10-21  8:06   ` Ilpo Järvinen
2022-10-24 15:03     ` matthew.gerlach
2022-10-20 21:26 ` [PATCH v4 3/4] fpga: dfl: add basic support DFHv1 matthew.gerlach
2022-10-20 22:07   ` Andy Shevchenko
2022-10-24 14:56     ` matthew.gerlach
2022-10-21  8:58   ` Ilpo Järvinen
2022-10-24 15:09     ` matthew.gerlach
2022-10-21  9:07   ` Ilpo Järvinen
2022-10-29 13:08   ` Xu Yilun
2022-10-29 14:47     ` matthew.gerlach
2022-11-01 22:37       ` matthew.gerlach
2022-11-03  1:36         ` Xu Yilun
2022-10-30 22:06     ` Andy Shevchenko [this message]
2022-10-31  1:16       ` Xu Yilun
2022-10-31 15:34         ` Andy Shevchenko
2022-10-31 20:15           ` matthew.gerlach
2022-11-01  1:55           ` Xu Yilun
2022-10-20 21:26 ` [PATCH v4 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-10-20 22:13   ` Andy Shevchenko
2022-10-21  4:33   ` Greg KH
2022-10-21  9:24   ` Ilpo Järvinen
2022-10-29 15:24   ` Xu Yilun
2022-11-01  0:34     ` matthew.gerlach
2022-11-01  1:46       ` Xu Yilun
2022-11-01 16:04         ` matthew.gerlach
2022-11-01 16:30           ` Ilpo Järvinen
2022-11-01 17:39             ` matthew.gerlach
2022-11-02  9:57               ` Ilpo Järvinen
2022-11-08 12:48                 ` Marco Pagani
2022-11-08 12:51                   ` Ilpo Järvinen

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