From: "Garmin Chang (張家銘)" <Garmin.Chang@mediatek.com> To: "matthias.bgg@gmail.com" <matthias.bgg@gmail.com>, "sboyd@kernel.org" <sboyd@kernel.org>, "krzysztof.kozlowski@linaro.org" <krzysztof.kozlowski@linaro.org>, "mturquette@baylibre.com" <mturquette@baylibre.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzysztof.kozlowski+dt@linaro.org" <krzysztof.kozlowski+dt@linaro.org>, "richardcochran@gmail.com" <richardcochran@gmail.com> Cc: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-mediatek@lists.infradead.org" <linux-mediatek@lists.infradead.org>, Project_Global_Chrome_Upstream_Group <Project_Global_Chrome_Upstream_Group@mediatek.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org> Subject: Re: [PATCH v2 01/19] dt-bindings: ARM: MediaTek: Add new document bindings of MT8188 clock Date: Fri, 23 Dec 2022 08:20:18 +0000 [thread overview] Message-ID: <374127db954e43d47032f980bb7d9704a5bd2a1d.camel@mediatek.com> (raw) In-Reply-To: <9092152a-35c9-1f80-8674-ea4124a1bb36@linaro.org> On Thu, 2022-10-27 at 09:42 -0400, Krzysztof Kozlowski wrote: > On 24/10/2022 05:42, Garmin.Chang wrote: > > Add the new binding documentation for system clock > > and functional clock on MediaTek MT8188. > > > > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> > > --- > > .../arm/mediatek/mediatek,mt8188-clock.yaml | 70 ++ > > .../mediatek/mediatek,mt8188-sys-clock.yaml | 55 ++ > > .../dt-bindings/clock/mediatek,mt8188-clk.h | 733 > > ++++++++++++++++++ > > 3 files changed, 858 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys- > > clock.yaml > > create mode 100644 include/dt-bindings/clock/mediatek,mt8188-clk.h > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > new file mode 100644 > > index 000000000000..49dc681e6601 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > @@ -0,0 +1,70 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDuCceTAZs$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDuHuGTk0U$ > > > > + > > +title: MediaTek Functional Clock Controller for MT8188 > > + > > +maintainers: > > + - Garmin Chang <garmin.chang@mediatek.com> > > + > > +description: | > > + The clock architecture in MediaTek like below > > + PLLs --> > > + dividers --> > > + muxes > > + --> > > + clock gate > > + > > + The devices provide clock gate control in different IP blocks. > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt8188-adsp_audio26m > > No underscores in compatibles. > > > + - mediatek,mt8188-imp_iic_wrap_c > > + - mediatek,mt8188-imp_iic_wrap_en > > + - mediatek,mt8188-imp_iic_wrap_w > > + - mediatek,mt8188-mfgcfg > > + - mediatek,mt8188-vppsys0 > > + - mediatek,mt8188-wpesys > > + - mediatek,mt8188-wpesys_vpp0 > > + - mediatek,mt8188-vppsys1 > > + - mediatek,mt8188-imgsys > > + - mediatek,mt8188-imgsys_wpe1 > > + - mediatek,mt8188-imgsys_wpe2 > > + - mediatek,mt8188-imgsys_wpe3 > > + - mediatek,mt8188-imgsys1_dip_top > > + - mediatek,mt8188-imgsys1_dip_nr > > + - mediatek,mt8188-ipesys > > + - mediatek,mt8188-camsys > > + - mediatek,mt8188-camsys_rawa > > + - mediatek,mt8188-camsys_yuva > > + - mediatek,mt8188-camsys_rawb > > + - mediatek,mt8188-camsys_yuvb > > + - mediatek,mt8188-ccusys > > + - mediatek,mt8188-vdecsys_soc > > + - mediatek,mt8188-vdecsys > > + - mediatek,mt8188-vencsys > > Blank line here > > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + imp_iic_wrap_c: clock-controller@11283000 { > > Drop the label, not used, > > > + compatible = "mediatek,mt8188-imp_iic_wrap_c"; > > + reg = <0x11283000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > new file mode 100644 > > index 000000000000..35962b3746e1 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > @@ -0,0 +1,55 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-sys-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDu6W88Oqk$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDuHuGTk0U$ > > > > + > > +title: MediaTek System Clock Controller for MT8188 > > + > > +maintainers: > > + - Garmin Chang <garmin.chang@mediatek.com> > > + > > +description: | > > + The clock architecture in MediaTek like below > > + PLLs --> > > + dividers --> > > + muxes > > + --> > > + clock gate > > + > > + The apmixedsys provides most of PLLs which generated from SoC > > 26m. > > + The topckgen provides dividers and muxes which provide the clock > > source to other IP blocks. > > + The infracfg_ao provides clock gate in peripheral and > > infrastructure IP blocks. > > + The mcusys provides mux control to select the clock source in AP > > MCU. > > + The device nodes also provide the system control capacity for > > configuration. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8188-topckgen > > + - mediatek,mt8188-infracfg_ao > > Same comment. > > > + - mediatek,mt8188-apmixedsys > > + - mediatek,mt8188-pericfg_ao > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + topckgen: syscon@10000000 { > > Drop label. > > > + compatible = "mediatek,mt8188-topckgen", "syscon"; > > + reg = <0x10000000 0x1000>; > > + #clock-cells = <1>; > > Best regards, > Krzysztof > Thank you for your suggestions. I will modify underscores in compatibles, add blank line and drop label. > Thanks, > Best Regards, > Garmin
WARNING: multiple messages have this Message-ID (diff)
From: "Garmin Chang (張家銘)" <Garmin.Chang@mediatek.com> To: "matthias.bgg@gmail.com" <matthias.bgg@gmail.com>, "sboyd@kernel.org" <sboyd@kernel.org>, "krzysztof.kozlowski@linaro.org" <krzysztof.kozlowski@linaro.org>, "mturquette@baylibre.com" <mturquette@baylibre.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzysztof.kozlowski+dt@linaro.org" <krzysztof.kozlowski+dt@linaro.org>, "richardcochran@gmail.com" <richardcochran@gmail.com> Cc: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-mediatek@lists.infradead.org" <linux-mediatek@lists.infradead.org>, Project_Global_Chrome_Upstream_Group <Project_Global_Chrome_Upstream_Group@mediatek.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org> Subject: Re: [PATCH v2 01/19] dt-bindings: ARM: MediaTek: Add new document bindings of MT8188 clock Date: Fri, 23 Dec 2022 08:20:18 +0000 [thread overview] Message-ID: <374127db954e43d47032f980bb7d9704a5bd2a1d.camel@mediatek.com> (raw) In-Reply-To: <9092152a-35c9-1f80-8674-ea4124a1bb36@linaro.org> On Thu, 2022-10-27 at 09:42 -0400, Krzysztof Kozlowski wrote: > On 24/10/2022 05:42, Garmin.Chang wrote: > > Add the new binding documentation for system clock > > and functional clock on MediaTek MT8188. > > > > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> > > --- > > .../arm/mediatek/mediatek,mt8188-clock.yaml | 70 ++ > > .../mediatek/mediatek,mt8188-sys-clock.yaml | 55 ++ > > .../dt-bindings/clock/mediatek,mt8188-clk.h | 733 > > ++++++++++++++++++ > > 3 files changed, 858 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys- > > clock.yaml > > create mode 100644 include/dt-bindings/clock/mediatek,mt8188-clk.h > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > new file mode 100644 > > index 000000000000..49dc681e6601 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > @@ -0,0 +1,70 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDuCceTAZs$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDuHuGTk0U$ > > > > + > > +title: MediaTek Functional Clock Controller for MT8188 > > + > > +maintainers: > > + - Garmin Chang <garmin.chang@mediatek.com> > > + > > +description: | > > + The clock architecture in MediaTek like below > > + PLLs --> > > + dividers --> > > + muxes > > + --> > > + clock gate > > + > > + The devices provide clock gate control in different IP blocks. > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt8188-adsp_audio26m > > No underscores in compatibles. > > > + - mediatek,mt8188-imp_iic_wrap_c > > + - mediatek,mt8188-imp_iic_wrap_en > > + - mediatek,mt8188-imp_iic_wrap_w > > + - mediatek,mt8188-mfgcfg > > + - mediatek,mt8188-vppsys0 > > + - mediatek,mt8188-wpesys > > + - mediatek,mt8188-wpesys_vpp0 > > + - mediatek,mt8188-vppsys1 > > + - mediatek,mt8188-imgsys > > + - mediatek,mt8188-imgsys_wpe1 > > + - mediatek,mt8188-imgsys_wpe2 > > + - mediatek,mt8188-imgsys_wpe3 > > + - mediatek,mt8188-imgsys1_dip_top > > + - mediatek,mt8188-imgsys1_dip_nr > > + - mediatek,mt8188-ipesys > > + - mediatek,mt8188-camsys > > + - mediatek,mt8188-camsys_rawa > > + - mediatek,mt8188-camsys_yuva > > + - mediatek,mt8188-camsys_rawb > > + - mediatek,mt8188-camsys_yuvb > > + - mediatek,mt8188-ccusys > > + - mediatek,mt8188-vdecsys_soc > > + - mediatek,mt8188-vdecsys > > + - mediatek,mt8188-vencsys > > Blank line here > > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + imp_iic_wrap_c: clock-controller@11283000 { > > Drop the label, not used, > > > + compatible = "mediatek,mt8188-imp_iic_wrap_c"; > > + reg = <0x11283000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > new file mode 100644 > > index 000000000000..35962b3746e1 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > @@ -0,0 +1,55 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-sys-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDu6W88Oqk$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!wZzNWz-zx7aQt1mTYTK-EfPEClJbCe_W0mEIFXwO3yquqcZp6T7_NpqtvnDuHuGTk0U$ > > > > + > > +title: MediaTek System Clock Controller for MT8188 > > + > > +maintainers: > > + - Garmin Chang <garmin.chang@mediatek.com> > > + > > +description: | > > + The clock architecture in MediaTek like below > > + PLLs --> > > + dividers --> > > + muxes > > + --> > > + clock gate > > + > > + The apmixedsys provides most of PLLs which generated from SoC > > 26m. > > + The topckgen provides dividers and muxes which provide the clock > > source to other IP blocks. > > + The infracfg_ao provides clock gate in peripheral and > > infrastructure IP blocks. > > + The mcusys provides mux control to select the clock source in AP > > MCU. > > + The device nodes also provide the system control capacity for > > configuration. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8188-topckgen > > + - mediatek,mt8188-infracfg_ao > > Same comment. > > > + - mediatek,mt8188-apmixedsys > > + - mediatek,mt8188-pericfg_ao > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + topckgen: syscon@10000000 { > > Drop label. > > > + compatible = "mediatek,mt8188-topckgen", "syscon"; > > + reg = <0x10000000 0x1000>; > > + #clock-cells = <1>; > > Best regards, > Krzysztof > Thank you for your suggestions. I will modify underscores in compatibles, add blank line and drop label. > Thanks, > Best Regards, > Garmin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-12-23 8:20 UTC|newest] Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-24 9:42 [PATCH v2 00/19] MediaTek MT8188 clock support Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 01/19] dt-bindings: ARM: MediaTek: Add new document bindings of MT8188 clock Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-27 13:42 ` Krzysztof Kozlowski 2022-10-27 13:42 ` Krzysztof Kozlowski 2022-12-23 8:20 ` Garmin Chang (張家銘) [this message] 2022-12-23 8:20 ` Garmin Chang (張家銘) 2022-10-24 9:42 ` [PATCH v2 02/19] clk: mediatek: Add MT8188 apmixedsys clock support Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-27 8:21 ` AngeloGioacchino Del Regno 2022-10-27 8:21 ` AngeloGioacchino Del Regno 2022-12-23 7:35 ` Garmin Chang (張家銘) 2022-12-23 7:35 ` Garmin Chang (張家銘) 2022-10-24 9:42 ` [PATCH v2 03/19] clk: mediatek: Add MT8188 topckgen " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-27 8:21 ` AngeloGioacchino Del Regno 2022-10-27 8:21 ` AngeloGioacchino Del Regno 2022-12-23 7:36 ` Garmin Chang (張家銘) 2022-12-23 7:36 ` Garmin Chang (張家銘) 2022-10-24 9:42 ` [PATCH v2 04/19] clk: mediatek: Add MT8188 peripheral " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-27 8:22 ` AngeloGioacchino Del Regno 2022-10-27 8:22 ` AngeloGioacchino Del Regno 2022-12-23 7:33 ` Garmin Chang (張家銘) 2022-12-23 7:33 ` Garmin Chang (張家銘) 2022-10-24 9:42 ` [PATCH v2 05/19] clk: mediatek: Add MT8188 infrastructure " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 06/19] clk: mediatek: Add MT8188 camsys " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 07/19] clk: mediatek: Add MT8188 ccusys " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 08/19] clk: mediatek: Add MT8188 imgsys " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-27 8:25 ` AngeloGioacchino Del Regno 2022-10-27 8:25 ` AngeloGioacchino Del Regno 2022-12-12 7:53 ` Garmin Chang (張家銘) 2022-12-12 7:53 ` Garmin Chang (張家銘) 2022-10-24 9:42 ` [PATCH v2 09/19] clk: mediatek: Add MT8188 ipesys " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 10/19] clk: mediatek: Add MT8188 mfgcfg " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-27 8:23 ` AngeloGioacchino Del Regno 2022-10-27 8:23 ` AngeloGioacchino Del Regno 2022-12-23 1:36 ` Garmin Chang (張家銘) 2022-12-23 1:36 ` Garmin Chang (張家銘) 2022-10-24 9:42 ` [PATCH v2 11/19] clk: mediatek: Add MT8188 vdecsys " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 12/19] clk: mediatek: Add MT8188 vdosys0 " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 13/19] clk: mediatek: Add MT8188 vdosys1 " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 14/19] clk: mediatek: Add MT8188 vencsys " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 15/19] clk: mediatek: Add MT8188 vppsys0 " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 16/19] clk: mediatek: Add MT8188 vppsys1 " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 17/19] clk: mediatek: Add MT8188 wpesys " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 18/19] clk: mediatek: Add MT8188 imp i2c wrapper " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang 2022-10-24 9:42 ` [PATCH v2 19/19] clk: mediatek: Add MT8188 adsp " Garmin.Chang 2022-10-24 9:42 ` Garmin.Chang
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