* [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont
@ 2017-02-10 7:23 kan.liang
2017-03-08 15:17 ` Liang, Kan
2017-03-16 11:22 ` [tip:perf/core] perf/x86: " tip-bot for Kan Liang
0 siblings, 2 replies; 3+ messages in thread
From: kan.liang @ 2017-02-10 7:23 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: eranian, ak, Kan Liang
From: Kan Liang <kan.liang@intel.com>
Goldmont supports full Top Down level 1 metrics (FrontendBound,
Retiring, Backend Bound and Bad Speculation).
It has 3 wide pipeline.
Signed-off-by: Kan Liang <kan.liang@intel.com>
---
Changes since V1:
- Change event list style
arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index eb1484c..4244bed 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -1553,6 +1553,27 @@ static __initconst const u64 slm_hw_cache_event_ids
},
};
+EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
+EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
+/* UOPS_NOT_DELIVERED.ANY */
+EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
+/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
+EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
+/* UOPS_RETIRED.ANY */
+EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
+/* UOPS_ISSUED.ANY */
+EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
+
+static struct attribute *glm_events_attrs[] = {
+ EVENT_PTR(td_total_slots_glm),
+ EVENT_PTR(td_total_slots_scale_glm),
+ EVENT_PTR(td_fetch_bubbles_glm),
+ EVENT_PTR(td_recovery_bubbles_glm),
+ EVENT_PTR(td_slots_issued_glm),
+ EVENT_PTR(td_slots_retired_glm),
+ NULL
+};
+
static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
@@ -3750,6 +3771,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_prec_dist = true;
x86_pmu.lbr_pt_coexist = true;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
+ x86_pmu.cpu_events = glm_events_attrs;
pr_cont("Goldmont events, ");
break;
--
2.4.3
^ permalink raw reply related [flat|nested] 3+ messages in thread* RE: [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont
2017-02-10 7:23 [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont kan.liang
@ 2017-03-08 15:17 ` Liang, Kan
2017-03-16 11:22 ` [tip:perf/core] perf/x86: " tip-bot for Kan Liang
1 sibling, 0 replies; 3+ messages in thread
From: Liang, Kan @ 2017-03-08 15:17 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: eranian, ak
Ping.
Any comments for this patch?
Thanks,
Kan
>
> From: Kan Liang <kan.liang@intel.com>
>
> Goldmont supports full Top Down level 1 metrics (FrontendBound,
> Retiring, Backend Bound and Bad Speculation).
> It has 3 wide pipeline.
>
> Signed-off-by: Kan Liang <kan.liang@intel.com>
> ---
>
> Changes since V1:
> - Change event list style
>
> arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index eb1484c..4244bed 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -1553,6 +1553,27 @@ static __initconst const u64
> slm_hw_cache_event_ids
> },
> };
>
> +EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
> +EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
> +/* UOPS_NOT_DELIVERED.ANY */
> +EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm,
> "event=0x9c");
> +/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
> +EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm,
> "event=0xca,umask=0x02");
> +/* UOPS_RETIRED.ANY */
> +EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm,
> "event=0xc2");
> +/* UOPS_ISSUED.ANY */
> +EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm,
> "event=0x0e");
> +
> +static struct attribute *glm_events_attrs[] = {
> + EVENT_PTR(td_total_slots_glm),
> + EVENT_PTR(td_total_slots_scale_glm),
> + EVENT_PTR(td_fetch_bubbles_glm),
> + EVENT_PTR(td_recovery_bubbles_glm),
> + EVENT_PTR(td_slots_issued_glm),
> + EVENT_PTR(td_slots_retired_glm),
> + NULL
> +};
> +
> static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
> /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
> INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0,
> 0x760005ffbfull, RSP_0),
> @@ -3750,6 +3771,7 @@ __init int intel_pmu_init(void)
> x86_pmu.pebs_prec_dist = true;
> x86_pmu.lbr_pt_coexist = true;
> x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> + x86_pmu.cpu_events = glm_events_attrs;
> pr_cont("Goldmont events, ");
> break;
>
> --
> 2.4.3
^ permalink raw reply [flat|nested] 3+ messages in thread* [tip:perf/core] perf/x86: Add Top Down events to Intel Goldmont
2017-02-10 7:23 [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont kan.liang
2017-03-08 15:17 ` Liang, Kan
@ 2017-03-16 11:22 ` tip-bot for Kan Liang
1 sibling, 0 replies; 3+ messages in thread
From: tip-bot for Kan Liang @ 2017-03-16 11:22 UTC (permalink / raw)
To: linux-tip-commits
Cc: alexander.shishkin, tglx, eranian, linux-kernel, peterz,
torvalds, vincent.weaver, kan.liang, mingo, acme, jolsa, hpa
Commit-ID: ed827adb009490673c9c63e0b716e0fa36afbcc1
Gitweb: http://git.kernel.org/tip/ed827adb009490673c9c63e0b716e0fa36afbcc1
Author: Kan Liang <kan.liang@intel.com>
AuthorDate: Fri, 10 Feb 2017 02:23:58 -0500
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 16 Mar 2017 09:51:10 +0100
perf/x86: Add Top Down events to Intel Goldmont
Goldmont supports full Top Down level 1 metrics (FrontendBound,
Retiring, Backend Bound and Bad Speculation).
It has 3 wide pipeline.
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1486711438-80058-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index eb1484c..4244bed 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -1553,6 +1553,27 @@ static __initconst const u64 slm_hw_cache_event_ids
},
};
+EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
+EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
+/* UOPS_NOT_DELIVERED.ANY */
+EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
+/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
+EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
+/* UOPS_RETIRED.ANY */
+EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
+/* UOPS_ISSUED.ANY */
+EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
+
+static struct attribute *glm_events_attrs[] = {
+ EVENT_PTR(td_total_slots_glm),
+ EVENT_PTR(td_total_slots_scale_glm),
+ EVENT_PTR(td_fetch_bubbles_glm),
+ EVENT_PTR(td_recovery_bubbles_glm),
+ EVENT_PTR(td_slots_issued_glm),
+ EVENT_PTR(td_slots_retired_glm),
+ NULL
+};
+
static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
@@ -3750,6 +3771,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_prec_dist = true;
x86_pmu.lbr_pt_coexist = true;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
+ x86_pmu.cpu_events = glm_events_attrs;
pr_cont("Goldmont events, ");
break;
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2017-02-10 7:23 [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont kan.liang
2017-03-08 15:17 ` Liang, Kan
2017-03-16 11:22 ` [tip:perf/core] perf/x86: " tip-bot for Kan Liang
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