From: Stafford Horne <shorne@gmail.com> To: LKML <linux-kernel@vger.kernel.org> Cc: Openrisc <openrisc@lists.librecores.org>, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>, Stafford Horne <shorne@gmail.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Jonas Bonn <jonas@southpole.se>, Krzysztof Kozlowski <krzk@kernel.org>, devicetree@vger.kernel.org Subject: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Date: Thu, 31 Aug 2017 07:03:11 +0900 [thread overview] Message-ID: <37f0d48de4690694c18be3d32483dafee0730859.1504129273.git.shorne@gmail.com> (raw) In-Reply-To: <cover.1504129273.git.shorne@gmail.com> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Simple enough to be compatible with simulation environments, such as verilated systems, QEMU and other targets supporting OpenRISC SMP. This also supports our base FPGA SoC's if the cpu frequency is upped to 50Mhz. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: Added defconfig] Signed-off-by: Stafford Horne <shorne@gmail.com> --- arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++ arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/openrisc/boot/dts/simple_smp.dts create mode 100644 arch/openrisc/configs/simple_smp_defconfig diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts new file mode 100644 index 000000000000..47c54101baae --- /dev/null +++ b/arch/openrisc/boot/dts/simple_smp.dts @@ -0,0 +1,58 @@ +/dts-v1/; +/ { + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + cpu@1 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <1>; + clock-frequency = <20000000>; + }; + }; + + ompic: ompic { + compatible = "ompic"; + reg = <0x98000000 16>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <1>; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic-level"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <20000000>; + }; + +}; diff --git a/arch/openrisc/configs/simple_smp_defconfig b/arch/openrisc/configs/simple_smp_defconfig new file mode 100644 index 000000000000..b6e3c7e158e7 --- /dev/null +++ b/arch/openrisc/configs/simple_smp_defconfig @@ -0,0 +1,66 @@ +CONFIG_CROSS_COMPILE="or1k-linux-" +CONFIG_LOCALVERSION="-simple-smp" +CONFIG_NO_HZ=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_EPOLL is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +CONFIG_MODULES=y +# CONFIG_BLOCK is not set +CONFIG_OPENRISC_BUILTIN_DTB="simple_smp" +CONFIG_SMP=y +CONFIG_HZ_100=y +CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_CUBIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_NETDEVICES=y +CONFIG_ETHOC=y +CONFIG_MICREL_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_XZ_DEC=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_RCU_TRACE is not set -- 2.13.5
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com> To: openrisc@lists.librecores.org Subject: [OpenRISC] [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Date: Thu, 31 Aug 2017 07:03:11 +0900 [thread overview] Message-ID: <37f0d48de4690694c18be3d32483dafee0730859.1504129273.git.shorne@gmail.com> (raw) In-Reply-To: <cover.1504129273.git.shorne@gmail.com> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Simple enough to be compatible with simulation environments, such as verilated systems, QEMU and other targets supporting OpenRISC SMP. This also supports our base FPGA SoC's if the cpu frequency is upped to 50Mhz. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne at gmail.com: Added defconfig] Signed-off-by: Stafford Horne <shorne@gmail.com> --- arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++ arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/openrisc/boot/dts/simple_smp.dts create mode 100644 arch/openrisc/configs/simple_smp_defconfig diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts new file mode 100644 index 000000000000..47c54101baae --- /dev/null +++ b/arch/openrisc/boot/dts/simple_smp.dts @@ -0,0 +1,58 @@ +/dts-v1/; +/ { + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory at 0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu at 0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + cpu at 1 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <1>; + clock-frequency = <20000000>; + }; + }; + + ompic: ompic { + compatible = "ompic"; + reg = <0x98000000 16>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <1>; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic-level"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial at 90000000 { + compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <20000000>; + }; + +}; diff --git a/arch/openrisc/configs/simple_smp_defconfig b/arch/openrisc/configs/simple_smp_defconfig new file mode 100644 index 000000000000..b6e3c7e158e7 --- /dev/null +++ b/arch/openrisc/configs/simple_smp_defconfig @@ -0,0 +1,66 @@ +CONFIG_CROSS_COMPILE="or1k-linux-" +CONFIG_LOCALVERSION="-simple-smp" +CONFIG_NO_HZ=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_EPOLL is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +CONFIG_MODULES=y +# CONFIG_BLOCK is not set +CONFIG_OPENRISC_BUILTIN_DTB="simple_smp" +CONFIG_SMP=y +CONFIG_HZ_100=y +CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_CUBIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_NETDEVICES=y +CONFIG_ETHOC=y +CONFIG_MICREL_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_XZ_DEC=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_RCU_TRACE is not set -- 2.13.5
next prev parent reply other threads:[~2017-08-30 22:03 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne 2017-08-30 21:58 ` [OpenRISC] " Stafford Horne 2017-08-30 21:58 ` [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne 2017-08-30 21:58 ` [OpenRISC] " Stafford Horne 2017-09-01 8:02 ` Geert Uytterhoeven 2017-09-01 8:02 ` Geert Uytterhoeven 2017-09-01 8:03 ` Geert Uytterhoeven 2017-09-01 8:03 ` Geert Uytterhoeven 2017-09-01 8:26 ` Stafford Horne 2017-09-01 8:26 ` Stafford Horne 2017-08-30 21:58 ` [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne 2017-08-30 21:58 ` [OpenRISC] " Stafford Horne 2017-09-01 8:06 ` Geert Uytterhoeven 2017-09-01 8:06 ` Geert Uytterhoeven 2017-09-01 8:28 ` Stafford Horne 2017-09-01 8:28 ` Stafford Horne 2017-08-30 21:58 ` [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne 2017-08-30 21:58 ` [OpenRISC] " Stafford Horne 2017-08-31 7:46 ` Peter Zijlstra 2017-08-31 7:46 ` [OpenRISC] " Peter Zijlstra 2017-08-31 9:01 ` Stafford Horne 2017-08-31 9:01 ` [OpenRISC] " Stafford Horne 2017-08-30 21:58 ` [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne 2017-08-30 21:58 ` [OpenRISC] " Stafford Horne 2017-08-30 21:58 ` [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne 2017-08-30 21:58 ` [OpenRISC] " Stafford Horne 2017-08-30 21:58 ` Stafford Horne 2017-08-31 9:28 ` Marc Zyngier 2017-08-31 9:28 ` [OpenRISC] " Marc Zyngier 2017-08-31 9:28 ` Marc Zyngier 2017-09-01 1:24 ` Stafford Horne 2017-09-01 1:24 ` [OpenRISC] " Stafford Horne 2017-09-01 1:24 ` Stafford Horne 2017-09-01 17:25 ` Marc Zyngier 2017-09-01 17:25 ` [OpenRISC] " Marc Zyngier 2017-09-03 22:12 ` Stafford Horne 2017-09-03 22:12 ` [OpenRISC] " Stafford Horne 2017-09-03 22:12 ` Stafford Horne 2017-09-04 7:35 ` Marc Zyngier 2017-09-04 7:35 ` [OpenRISC] " Marc Zyngier 2017-09-04 7:35 ` Marc Zyngier 2017-08-31 10:59 ` Mark Rutland 2017-08-31 10:59 ` [OpenRISC] " Mark Rutland 2017-08-31 10:59 ` Mark Rutland 2017-09-01 13:59 ` Stafford Horne 2017-09-01 13:59 ` [OpenRISC] " Stafford Horne 2017-08-30 21:58 ` [PATCH 06/13] openrisc: initial SMP support Stafford Horne 2017-08-30 21:58 ` [OpenRISC] " Stafford Horne 2017-08-30 22:02 ` [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne 2017-08-30 22:02 ` [OpenRISC] " Stafford Horne 2017-08-30 22:02 ` [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne 2017-08-30 22:02 ` [OpenRISC] " Stafford Horne 2017-08-30 22:02 ` [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne 2017-08-30 22:02 ` [OpenRISC] " Stafford Horne 2017-08-30 22:03 ` Stafford Horne [this message] 2017-08-30 22:03 ` [OpenRISC] [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne 2017-08-31 10:41 ` Mark Rutland 2017-08-31 10:41 ` [OpenRISC] " Mark Rutland 2017-08-31 10:41 ` Mark Rutland 2017-08-31 13:05 ` Stafford Horne 2017-08-31 13:05 ` [OpenRISC] " Stafford Horne 2017-09-11 22:37 ` Pavel Machek 2017-09-11 22:37 ` [OpenRISC] " Pavel Machek 2017-09-11 22:37 ` Pavel Machek 2017-09-11 22:55 ` Stafford Horne 2017-09-11 22:55 ` [OpenRISC] " Stafford Horne 2017-09-11 22:55 ` Stafford Horne 2017-09-12 7:47 ` Pavel Machek 2017-09-12 7:47 ` [OpenRISC] " Pavel Machek 2017-09-12 7:47 ` Pavel Machek 2017-09-12 22:15 ` Stafford Horne 2017-09-12 22:15 ` [OpenRISC] " Stafford Horne 2017-08-30 22:03 ` [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne 2017-08-30 22:03 ` [OpenRISC] " Stafford Horne 2017-08-30 22:03 ` [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne 2017-08-30 22:03 ` [OpenRISC] " Stafford Horne 2017-08-30 22:03 ` [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne 2017-08-30 22:03 ` [OpenRISC] " Stafford Horne
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