[PATCH v4 0/2] GMBUS changes

[PATCH v4 0/2] GMBUS changes

[Ramalingam C]

I am not aware if there is a reason for restricting the Bytes per GMBUS
WR/RD to 256 at present. But HW has 9Bits for Total Byte count for a
single read or Write cycle. Means we can extend a cycle of RD/WR to
511Bytes.

At present nothing much as ROI, as most of the usecases are for less
than 256Bytes. On GLK tested for 300Bytes on single normal read, found
to be working fine.

First patch does it. But I have restricted the extension to Gen9 onwards,
as I am not sure about the legacy platforms.

And second patch is enabling the burst read for all GMBUS read of more
than 511Bytes, on supported platforms. Basically this Burst read is
enabled in HW for HDCP2.2 compliance requirement. Instead of enabling
the burst read only for HDCP on special API this patch enables it for
all GMBUS read of >511Bytes, on capable platforms.

Changes in V4:
  --Extra variable and brackets are removed. [ville]
  --Implemented the handling of the 512Bytes Burst read. [ville]
  --GMBUS0 values are passed as parameters. [ville]

Ramalingam C (2):
  drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
  drm/i915/gmbus: Enable burst read

 drivers/gpu/drm/i915/i915_drv.h  |  3 ++
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_i2c.c | 61 ++++++++++++++++++++++++++++++++--------
 3 files changed, 55 insertions(+), 11 deletions(-)

-- 
2.7.4

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[PATCH v4 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Ramalingam C]

GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of
enabling the 511Bytes per RD/WR cycle on legacy platforms for no
absolute ROIs, this change allows the max bytes per op upto 511Bytes
from Gen9 onwards.

v2:
  No Change.
v3:
  Inline function for max_xfer_size and renaming of the macro.[Jani]
v4:
  Extra brackets removed [ville]
  Commit msg is modified.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_i2c.c | 11 +++++++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c08fd4ded688..df998c10c48e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3025,6 +3025,7 @@ enum i915_power_well_id {
 #define   GMBUS_CYCLE_STOP	(4<<25)
 #define   GMBUS_BYTE_COUNT_SHIFT 16
 #define   GMBUS_BYTE_COUNT_MAX   256U
+#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
 #define   GMBUS_SLAVE_INDEX_SHIFT 8
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ	(1<<0)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e6875509bcd9..1c0f6b56b209 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -361,6 +361,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+static inline
+unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
+{
+	return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
+	       GMBUS_BYTE_COUNT_MAX;
+}
+
 static int
 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		      unsigned short addr, u8 *buf, unsigned int len,
@@ -400,7 +407,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
+		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 
 		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
 					    buf, len, gmbus1_index);
@@ -462,7 +469,7 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
+		len = min(tx_size, gmbus_max_xfer_size(dev_priv));
 
 		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
 					     gmbus1_index);
-- 
2.7.4

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[PATCH v4 2/2] drm/i915/gmbus: Enable burst read

[Ramalingam C]

Support for Burst read in HW is added for HDCP2.2 compliance
requirement.

This patch enables the burst read for all the gmbus read of more than
511Bytes, on capable platforms.

v2:
  Extra line is removed.
v3:
  Macro is added for detecting the BURST_READ Support [Jani]
  Runtime detection of the need for burst_read [Jani]
  Calculation enhancement.
v4:
  GMBUS0 reg val is passed from caller [ville]
  Removed a extra var [ville]
  Extra brackets are removed [ville]
  Implemented the handling of 512Bytes Burst Read.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +++
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_i2c.c | 52 ++++++++++++++++++++++++++++++++--------
 3 files changed, 46 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 028691108125..14293fc1a142 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2552,6 +2552,9 @@ intel_info(const struct drm_i915_private *dev_priv)
  */
 #define HAS_AUX_IRQ(dev_priv)   true
 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+					IS_GEMINILAKE(dev_priv) || \
+					IS_KABYLAKE(dev_priv))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df998c10c48e..1166a24aff48 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2996,6 +2996,7 @@ enum i915_power_well_id {
 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
 #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
 #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
+#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
 #define   GMBUS_PIN_DISABLED	0
 #define   GMBUS_PIN_SSC		1
 #define   GMBUS_PIN_VGADDC	2
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1c0f6b56b209..2b59f8db42f2 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -371,12 +371,30 @@ unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
 static int
 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		      unsigned short addr, u8 *buf, unsigned int len,
-		      u32 gmbus1_index)
+		      u32 gmbus0_reg, u32 gmbus1_index)
 {
+	unsigned int size = len;
+	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
+	bool extra_byte_added = false;
+
+	if (burst_read) {
+
+		/*
+		 * As per HW Spec, for 512Bytes need to read extra Byte and
+		 * Ignore the extra byte read.
+		 */
+		if (len == 512) {
+			extra_byte_added = true;
+			len++;
+		}
+		size = len % 256 + 256;
+		I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
+	}
+
 	I915_WRITE_FW(GMBUS1,
 		      gmbus1_index |
 		      GMBUS_CYCLE_WAIT |
-		      (len << GMBUS_BYTE_COUNT_SHIFT) |
+		      (size << GMBUS_BYTE_COUNT_SHIFT) |
 		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 		      GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 	while (len) {
@@ -389,9 +407,16 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 
 		val = I915_READ_FW(GMBUS3);
 		do {
+			if (extra_byte_added && len == 1)
+				break;
+
 			*buf++ = val & 0xff;
 			val >>= 8;
 		} while (--len && ++loop < 4);
+
+		if (burst_read && len == size - 4)
+			/* Reset the override bit */
+			I915_WRITE_FW(GMBUS0, gmbus0_reg);
 	}
 
 	return 0;
@@ -399,7 +424,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 
 static int
 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
-		u32 gmbus1_index)
+		u32 gmbus0_reg, u32 gmbus1_index)
 {
 	u8 *buf = msg->buf;
 	unsigned int rx_size = msg->len;
@@ -407,10 +432,13 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
+		if (HAS_GMBUS_BURST_READ(dev_priv))
+			len = rx_size;
+		else
+			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 
-		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
-					    buf, len, gmbus1_index);
+		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
+					    gmbus0_reg, gmbus1_index);
 		if (ret)
 			return ret;
 
@@ -498,7 +526,8 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
 }
 
 static int
-gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
+gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
+		 u32 gmbus0_reg)
 {
 	u32 gmbus1_index = 0;
 	u32 gmbus5 = 0;
@@ -516,7 +545,8 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 		I915_WRITE_FW(GMBUS5, gmbus5);
 
 	if (msgs[1].flags & I2C_M_RD)
-		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
+		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
+				      gmbus1_index);
 	else
 		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
 
@@ -551,10 +581,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
 	for (; i < num; i += inc) {
 		inc = 1;
 		if (gmbus_is_index_xfer(msgs, i, num)) {
-			ret = gmbus_index_xfer(dev_priv, &msgs[i]);
+			ret = gmbus_index_xfer(dev_priv, &msgs[i],
+					       gmbus0_source | bus->reg0);
 			inc = 2; /* an index transmission is two msgs */
 		} else if (msgs[i].flags & I2C_M_RD) {
-			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
+			ret = gmbus_xfer_read(dev_priv, &msgs[i],
+					      gmbus0_source | bus->reg0, 0);
 		} else {
 			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
 		}
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for GMBUS changes (rev4)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev4)
URL   : https://patchwork.freedesktop.org/series/41632/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7ef555142951 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
3e623cbfe855 drm/i915/gmbus: Enable burst read
-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#34: FILE: drivers/gpu/drm/i915/i915_drv.h:2563:
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+					IS_GEMINILAKE(dev_priv) || \
+					IS_KABYLAKE(dev_priv))

-:48: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#48: FILE: drivers/gpu/drm/i915/i915_reg.h:2999:
+#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
                                     ^

-:68: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#68: FILE: drivers/gpu/drm/i915/intel_i2c.c:381:
+	if (burst_read) {
+

total: 0 errors, 0 warnings, 3 checks, 120 lines checked

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✗ Fi.CI.SPARSE: warning for GMBUS changes (rev4)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev4)
URL   : https://patchwork.freedesktop.org/series/41632/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
-O:drivers/gpu/drm/i915/intel_i2c.c:403:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_i2c.c:465:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void)

Commit: drm/i915/gmbus: Enable burst read
-O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:438:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:438:31: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3654:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3657:16: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for GMBUS changes (rev4)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev4)
URL   : https://patchwork.freedesktop.org/series/41632/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8962 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8962 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8962, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41632/revisions/4/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8962:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_8962 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106097)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         PASS -> INCOMPLETE (fdo#103927)

    igt@prime_vgem@basic-fence-flip:
      fi-ilk-650:         PASS -> FAIL (fdo#104008)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload-inject:
      fi-glk-j4005:       DMESG-WARN (fdo#106248) -> PASS

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-hsw-4770r:       FAIL (fdo#100368) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248


== Participating hosts (41 -> 37) ==

  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4163 -> Patchwork_8962

  CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8962: 3e623cbfe855623913aefc4cdefdddd9c719141d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit


== Linux commits ==

3e623cbfe855 drm/i915/gmbus: Enable burst read
7ef555142951 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8962/issues.html
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✓ Fi.CI.IGT: success for GMBUS changes (rev4)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev4)
URL   : https://patchwork.freedesktop.org/series/41632/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8962_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8962_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8962_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41632/revisions/4/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8962_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd2:
      shard-kbl:          SKIP -> PASS +2

    igt@gem_mocs_settings@mocs-rc6-vebox:
      shard-kbl:          PASS -> SKIP +1

    igt@kms_force_connector_basic@force-connector-state:
      shard-snb:          PASS -> SKIP

    igt@kms_properties@plane-properties-legacy:
      shard-snb:          SKIP -> PASS +4

    
== Known issues ==

  Here are the changes found in Patchwork_8962_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@plain-flip-ts-check-interruptible:
      shard-glk:          PASS -> FAIL (fdo#100368) +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
      shard-apl:          PASS -> FAIL (fdo#103167, fdo#104724)

    
    ==== Possible fixes ====

    igt@kms_flip@absolute-wf_vblank-interruptible:
      shard-glk:          FAIL (fdo#106087) -> PASS

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-apl:          FAIL (fdo#105363, fdo#102887) -> PASS

    igt@kms_flip@wf_vblank-ts-check-interruptible:
      shard-glk:          FAIL (fdo#100368) -> PASS
      shard-apl:          FAIL (fdo#100368) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4163 -> Patchwork_8962

  CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8962: 3e623cbfe855623913aefc4cdefdddd9c719141d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8962/shards.html
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Re: [PATCH v4 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Jani Nikula]

On Wed, 09 May 2018, Ramalingam C <ramalingam.c@intel.com> wrote:
> GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of
> enabling the 511Bytes per RD/WR cycle on legacy platforms for no
> absolute ROIs, this change allows the max bytes per op upto 511Bytes
> from Gen9 onwards.
>
> v2:
>   No Change.
> v3:
>   Inline function for max_xfer_size and renaming of the macro.[Jani]
> v4:
>   Extra brackets removed [ville]
>   Commit msg is modified.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_i2c.c | 11 +++++++++--
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c08fd4ded688..df998c10c48e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3025,6 +3025,7 @@ enum i915_power_well_id {
>  #define   GMBUS_CYCLE_STOP	(4<<25)
>  #define   GMBUS_BYTE_COUNT_SHIFT 16
>  #define   GMBUS_BYTE_COUNT_MAX   256U
> +#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
>  #define   GMBUS_SLAVE_INDEX_SHIFT 8
>  #define   GMBUS_SLAVE_ADDR_SHIFT 1
>  #define   GMBUS_SLAVE_READ	(1<<0)
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index e6875509bcd9..1c0f6b56b209 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -361,6 +361,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
>  	return ret;
>  }
>  
> +static inline
> +unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
> +{
> +	return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
> +	       GMBUS_BYTE_COUNT_MAX;
> +}
> +
>  static int
>  gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>  		      unsigned short addr, u8 *buf, unsigned int len,
> @@ -400,7 +407,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>  	int ret;
>  
>  	do {
> -		len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
> +		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
>  
>  		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
>  					    buf, len, gmbus1_index);
> @@ -462,7 +469,7 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>  	int ret;
>  
>  	do {
> -		len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
> +		len = min(tx_size, gmbus_max_xfer_size(dev_priv));
>  
>  		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
>  					     gmbus1_index);

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH v5 2/2] drm/i915/gmbus: Enable burst read

[Ramalingam C]

Support for Burst read in HW is added for HDCP2.2 compliance
requirement.

This patch enables the burst read for all the gmbus read of more than
511Bytes, on capable platforms.

v2:
  Extra line is removed.
v3:
  Macro is added for detecting the BURST_READ Support [Jani]
  Runtime detection of the need for burst_read [Jani]
  Calculation enhancement.
v4:
  GMBUS0 reg val is passed from caller [ville]
  Removed a extra var [ville]
  Extra brackets are removed [ville]
  Implemented the handling of 512Bytes Burst Read.
v5:
  Burst read max length is fixed at 767Bytes [Ville]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 ++
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_i2c.c | 62 +++++++++++++++++++++++++++++++++-------
 3 files changed, 56 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 028691108125..14293fc1a142 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2552,6 +2552,9 @@ intel_info(const struct drm_i915_private *dev_priv)
  */
 #define HAS_AUX_IRQ(dev_priv)   true
 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+					IS_GEMINILAKE(dev_priv) || \
+					IS_KABYLAKE(dev_priv))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ebdf7c9d816e..575d9495f3e2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2996,6 +2996,7 @@ enum i915_power_well_id {
 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
 #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
 #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
+#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
 #define   GMBUS_PIN_DISABLED	0
 #define   GMBUS_PIN_SSC		1
 #define   GMBUS_PIN_VGADDC	2
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1c0f6b56b209..9e1142a2f81b 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -371,12 +371,30 @@ unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
 static int
 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		      unsigned short addr, u8 *buf, unsigned int len,
-		      u32 gmbus1_index)
+		      u32 gmbus0_reg, u32 gmbus1_index)
 {
+	unsigned int size = len;
+	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
+	bool extra_byte_added = false;
+
+	if (burst_read) {
+
+		/*
+		 * As per HW Spec, for 512Bytes need to read extra Byte and
+		 * Ignore the extra byte read.
+		 */
+		if (len == 512) {
+			extra_byte_added = true;
+			len++;
+		}
+		size = len % 256 + 256;
+		I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
+	}
+
 	I915_WRITE_FW(GMBUS1,
 		      gmbus1_index |
 		      GMBUS_CYCLE_WAIT |
-		      (len << GMBUS_BYTE_COUNT_SHIFT) |
+		      (size << GMBUS_BYTE_COUNT_SHIFT) |
 		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 		      GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 	while (len) {
@@ -389,17 +407,34 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 
 		val = I915_READ_FW(GMBUS3);
 		do {
+			if (extra_byte_added && len == 1)
+				break;
+
 			*buf++ = val & 0xff;
 			val >>= 8;
 		} while (--len && ++loop < 4);
+
+		if (burst_read && len == size - 4)
+			/* Reset the override bit */
+			I915_WRITE_FW(GMBUS0, gmbus0_reg);
 	}
 
 	return 0;
 }
 
+/*
+ * HW spec says that 512Bytes in Burst read need special treatment.
+ * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
+ * an I2C slave, which supports such a lengthy burst read too for experiments.
+ *
+ * So until things get clarified on HW support, to avoid the burst read length
+ * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
+ */
+#define INTEL_GMBUS_BURST_READ_MAX_LEN		767U
+
 static int
 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
-		u32 gmbus1_index)
+		u32 gmbus0_reg, u32 gmbus1_index)
 {
 	u8 *buf = msg->buf;
 	unsigned int rx_size = msg->len;
@@ -407,10 +442,13 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
+		if (HAS_GMBUS_BURST_READ(dev_priv))
+			len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
+		else
+			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 
-		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
-					    buf, len, gmbus1_index);
+		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
+					    gmbus0_reg, gmbus1_index);
 		if (ret)
 			return ret;
 
@@ -498,7 +536,8 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
 }
 
 static int
-gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
+gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
+		 u32 gmbus0_reg)
 {
 	u32 gmbus1_index = 0;
 	u32 gmbus5 = 0;
@@ -516,7 +555,8 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 		I915_WRITE_FW(GMBUS5, gmbus5);
 
 	if (msgs[1].flags & I2C_M_RD)
-		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
+		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
+				      gmbus1_index);
 	else
 		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
 
@@ -551,10 +591,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
 	for (; i < num; i += inc) {
 		inc = 1;
 		if (gmbus_is_index_xfer(msgs, i, num)) {
-			ret = gmbus_index_xfer(dev_priv, &msgs[i]);
+			ret = gmbus_index_xfer(dev_priv, &msgs[i],
+					       gmbus0_source | bus->reg0);
 			inc = 2; /* an index transmission is two msgs */
 		} else if (msgs[i].flags & I2C_M_RD) {
-			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
+			ret = gmbus_xfer_read(dev_priv, &msgs[i],
+					      gmbus0_source | bus->reg0, 0);
 		} else {
 			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
 		}
-- 
2.7.4

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Re: [PATCH v4 2/2] drm/i915/gmbus: Enable burst read

[Ramalingam C]

As per the discussion at #intel-gfx IRC, I have submitted v5 with the 
max burst read length fixed to 767Bytes. Gist of the discussion: As per 
HW spec HW supports burst for all the msg length above 511Bytes. But for 
512 there is a special handling. Reasoning for this special handling is 
not clear. because of this we are not sure whether other msg lengths in 
multiples of 256 also will have problem or not. As of now, In real world 
we couldn't have an I2C slave on DDC Bus whoc an provide msgs of 
 >511Bytes. Except 534Byte HDCP2.2 Cert Msg. So it is not possible to 
test and confirm the HW capability for n*256Bytes where as n is >= 3. so 
until we get further clarity, we are limiting the burst read support to 
the msgs of length 512Bytes to 767Bytes. --Ram


On Wednesday 09 May 2018 07:15 PM, Ramalingam C wrote:
> Support for Burst read in HW is added for HDCP2.2 compliance
> requirement.
>
> This patch enables the burst read for all the gmbus read of more than
> 511Bytes, on capable platforms.
>
> v2:
>    Extra line is removed.
> v3:
>    Macro is added for detecting the BURST_READ Support [Jani]
>    Runtime detection of the need for burst_read [Jani]
>    Calculation enhancement.
> v4:
>    GMBUS0 reg val is passed from caller [ville]
>    Removed a extra var [ville]
>    Extra brackets are removed [ville]
>    Implemented the handling of 512Bytes Burst Read.
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h  |  3 +++
>   drivers/gpu/drm/i915/i915_reg.h  |  1 +
>   drivers/gpu/drm/i915/intel_i2c.c | 52 ++++++++++++++++++++++++++++++++--------
>   3 files changed, 46 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 028691108125..14293fc1a142 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2552,6 +2552,9 @@ intel_info(const struct drm_i915_private *dev_priv)
>    */
>   #define HAS_AUX_IRQ(dev_priv)   true
>   #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
> +#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
> +					IS_GEMINILAKE(dev_priv) || \
> +					IS_KABYLAKE(dev_priv))
>   
>   /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>    * rows, which changed the alignment requirements and fence programming.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index df998c10c48e..1166a24aff48 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2996,6 +2996,7 @@ enum i915_power_well_id {
>   #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
>   #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
>   #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
> +#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
>   #define   GMBUS_PIN_DISABLED	0
>   #define   GMBUS_PIN_SSC		1
>   #define   GMBUS_PIN_VGADDC	2
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 1c0f6b56b209..2b59f8db42f2 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -371,12 +371,30 @@ unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
>   static int
>   gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>   		      unsigned short addr, u8 *buf, unsigned int len,
> -		      u32 gmbus1_index)
> +		      u32 gmbus0_reg, u32 gmbus1_index)
>   {
> +	unsigned int size = len;
> +	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
> +	bool extra_byte_added = false;
> +
> +	if (burst_read) {
> +
> +		/*
> +		 * As per HW Spec, for 512Bytes need to read extra Byte and
> +		 * Ignore the extra byte read.
> +		 */
> +		if (len == 512) {
> +			extra_byte_added = true;
> +			len++;
> +		}
> +		size = len % 256 + 256;
> +		I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
> +	}
> +
>   	I915_WRITE_FW(GMBUS1,
>   		      gmbus1_index |
>   		      GMBUS_CYCLE_WAIT |
> -		      (len << GMBUS_BYTE_COUNT_SHIFT) |
> +		      (size << GMBUS_BYTE_COUNT_SHIFT) |
>   		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
>   		      GMBUS_SLAVE_READ | GMBUS_SW_RDY);
>   	while (len) {
> @@ -389,9 +407,16 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>   
>   		val = I915_READ_FW(GMBUS3);
>   		do {
> +			if (extra_byte_added && len == 1)
> +				break;
> +
>   			*buf++ = val & 0xff;
>   			val >>= 8;
>   		} while (--len && ++loop < 4);
> +
> +		if (burst_read && len == size - 4)
> +			/* Reset the override bit */
> +			I915_WRITE_FW(GMBUS0, gmbus0_reg);
>   	}
>   
>   	return 0;
> @@ -399,7 +424,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>   
>   static int
>   gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
> -		u32 gmbus1_index)
> +		u32 gmbus0_reg, u32 gmbus1_index)
>   {
>   	u8 *buf = msg->buf;
>   	unsigned int rx_size = msg->len;
> @@ -407,10 +432,13 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>   	int ret;
>   
>   	do {
> -		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
> +		if (HAS_GMBUS_BURST_READ(dev_priv))
> +			len = rx_size;
> +		else
> +			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
>   
> -		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
> -					    buf, len, gmbus1_index);
> +		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
> +					    gmbus0_reg, gmbus1_index);
>   		if (ret)
>   			return ret;
>   
> @@ -498,7 +526,8 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
>   }
>   
>   static int
> -gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
> +gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
> +		 u32 gmbus0_reg)
>   {
>   	u32 gmbus1_index = 0;
>   	u32 gmbus5 = 0;
> @@ -516,7 +545,8 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
>   		I915_WRITE_FW(GMBUS5, gmbus5);
>   
>   	if (msgs[1].flags & I2C_M_RD)
> -		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
> +		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
> +				      gmbus1_index);
>   	else
>   		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
>   
> @@ -551,10 +581,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
>   	for (; i < num; i += inc) {
>   		inc = 1;
>   		if (gmbus_is_index_xfer(msgs, i, num)) {
> -			ret = gmbus_index_xfer(dev_priv, &msgs[i]);
> +			ret = gmbus_index_xfer(dev_priv, &msgs[i],
> +					       gmbus0_source | bus->reg0);
>   			inc = 2; /* an index transmission is two msgs */
>   		} else if (msgs[i].flags & I2C_M_RD) {
> -			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
> +			ret = gmbus_xfer_read(dev_priv, &msgs[i],
> +					      gmbus0_source | bus->reg0, 0);
>   		} else {
>   			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
>   		}

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✗ Fi.CI.CHECKPATCH: warning for GMBUS changes (rev5)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev5)
URL   : https://patchwork.freedesktop.org/series/41632/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
cc8aaf86e7e8 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
f91237f2fdac drm/i915/gmbus: Enable burst read
-:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#36: FILE: drivers/gpu/drm/i915/i915_drv.h:2573:
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+					IS_GEMINILAKE(dev_priv) || \
+					IS_KABYLAKE(dev_priv))

-:50: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#50: FILE: drivers/gpu/drm/i915/i915_reg.h:2999:
+#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
                                     ^

-:70: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#70: FILE: drivers/gpu/drm/i915/intel_i2c.c:381:
+	if (burst_read) {
+

total: 0 errors, 0 warnings, 3 checks, 131 lines checked

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✗ Fi.CI.SPARSE: warning for GMBUS changes (rev5)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev5)
URL   : https://patchwork.freedesktop.org/series/41632/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
-O:drivers/gpu/drm/i915/intel_i2c.c:403:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_i2c.c:465:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void)

Commit: drm/i915/gmbus: Enable burst read
-O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:446:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:448:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:448:31: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3664:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3667:16: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for GMBUS changes (rev5)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev5)
URL   : https://patchwork.freedesktop.org/series/41632/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4204 -> Patchwork_9045 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9045 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9045, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41632/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9045:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9045 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-4200u:       PASS -> DMESG-FAIL (fdo#106103, fdo#102614)

    
    ==== Possible fixes ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-cnl-psr:         FAIL (fdo#100368) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (42 -> 39) ==

  Additional (1): fi-byt-j1900 
  Missing    (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4204 -> Patchwork_9045

  CI_DRM_4204: 1bffedaef627748248914f5a043e379fee0b121d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9045: f91237f2fdac166a3483e40ba7c673949c0057fe @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit


== Linux commits ==

f91237f2fdac drm/i915/gmbus: Enable burst read
cc8aaf86e7e8 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9045/issues.html
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✓ Fi.CI.IGT: success for GMBUS changes (rev5)

[Patchwork]

== Series Details ==

Series: GMBUS changes (rev5)
URL   : https://patchwork.freedesktop.org/series/41632/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4204_full -> Patchwork_9045_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9045_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9045_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41632/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9045_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd2:
      shard-kbl:          PASS -> SKIP +1

    igt@gem_exec_schedule@deep-vebox:
      shard-kbl:          SKIP -> PASS +1

    igt@kms_cursor_crc@cursor-256x256-offscreen:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_9045_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      shard-kbl:          PASS -> DMESG-FAIL (fdo#106560)

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-glk:          PASS -> FAIL (fdo#105703)

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#105707)

    igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#100368)

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724, fdo#103822) +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
      shard-glk:          PASS -> DMESG-WARN (fdo#106247) +1

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
      shard-hsw:          FAIL (fdo#100368) -> PASS

    igt@kms_flip@blocking-wf_vblank:
      shard-hsw:          FAIL (fdo#103928) -> PASS

    igt@kms_flip@plain-flip-ts-check-interruptible:
      shard-glk:          FAIL (fdo#100368) -> PASS +1

    igt@kms_rotation_crc@primary-rotation-90:
      shard-apl:          FAIL (fdo#104724, fdo#103925) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4204 -> Patchwork_9045

  CI_DRM_4204: 1bffedaef627748248914f5a043e379fee0b121d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9045: f91237f2fdac166a3483e40ba7c673949c0057fe @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9045/shards.html
_______________________________________________
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Re: [PATCH v5 2/2] drm/i915/gmbus: Enable burst read

[Ville Syrjälä]

On Fri, May 18, 2018 at 02:54:53PM +0530, Ramalingam C wrote:
> Support for Burst read in HW is added for HDCP2.2 compliance
> requirement.
> 
> This patch enables the burst read for all the gmbus read of more than
> 511Bytes, on capable platforms.
> 
> v2:
>   Extra line is removed.
> v3:
>   Macro is added for detecting the BURST_READ Support [Jani]
>   Runtime detection of the need for burst_read [Jani]
>   Calculation enhancement.
> v4:
>   GMBUS0 reg val is passed from caller [ville]
>   Removed a extra var [ville]
>   Extra brackets are removed [ville]
>   Implemented the handling of 512Bytes Burst Read.
> v5:
>   Burst read max length is fixed at 767Bytes [Ville]
> 
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  3 ++
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_i2c.c | 62 +++++++++++++++++++++++++++++++++-------
>  3 files changed, 56 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 028691108125..14293fc1a142 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2552,6 +2552,9 @@ intel_info(const struct drm_i915_private *dev_priv)
>   */
>  #define HAS_AUX_IRQ(dev_priv)   true
>  #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
> +#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
> +					IS_GEMINILAKE(dev_priv) || \
> +					IS_KABYLAKE(dev_priv))

Note 100% sure about these. The spec say some late stepping SPT has this
already. But I suppose this KBL+ match means just KBP+?

Hmm. Did I ask this already before? Getting some dejavu here.

>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ebdf7c9d816e..575d9495f3e2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2996,6 +2996,7 @@ enum i915_power_well_id {
>  #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
>  #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
>  #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
> +#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
>  #define   GMBUS_PIN_DISABLED	0
>  #define   GMBUS_PIN_SSC		1
>  #define   GMBUS_PIN_VGADDC	2
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 1c0f6b56b209..9e1142a2f81b 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -371,12 +371,30 @@ unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
>  static int
>  gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>  		      unsigned short addr, u8 *buf, unsigned int len,
> -		      u32 gmbus1_index)
> +		      u32 gmbus0_reg, u32 gmbus1_index)
>  {
> +	unsigned int size = len;
> +	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
> +	bool extra_byte_added = false;
> +
> +	if (burst_read) {
> +

Stray newline.

Otherwise this looks good to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


> +		/*
> +		 * As per HW Spec, for 512Bytes need to read extra Byte and
> +		 * Ignore the extra byte read.
> +		 */
> +		if (len == 512) {
> +			extra_byte_added = true;
> +			len++;
> +		}
> +		size = len % 256 + 256;
> +		I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
> +	}
> +
>  	I915_WRITE_FW(GMBUS1,
>  		      gmbus1_index |
>  		      GMBUS_CYCLE_WAIT |
> -		      (len << GMBUS_BYTE_COUNT_SHIFT) |
> +		      (size << GMBUS_BYTE_COUNT_SHIFT) |
>  		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
>  		      GMBUS_SLAVE_READ | GMBUS_SW_RDY);
>  	while (len) {
> @@ -389,17 +407,34 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>  
>  		val = I915_READ_FW(GMBUS3);
>  		do {
> +			if (extra_byte_added && len == 1)
> +				break;
> +
>  			*buf++ = val & 0xff;
>  			val >>= 8;
>  		} while (--len && ++loop < 4);
> +
> +		if (burst_read && len == size - 4)
> +			/* Reset the override bit */
> +			I915_WRITE_FW(GMBUS0, gmbus0_reg);
>  	}
>  
>  	return 0;
>  }
>  
> +/*
> + * HW spec says that 512Bytes in Burst read need special treatment.
> + * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
> + * an I2C slave, which supports such a lengthy burst read too for experiments.
> + *
> + * So until things get clarified on HW support, to avoid the burst read length
> + * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
> + */
> +#define INTEL_GMBUS_BURST_READ_MAX_LEN		767U
> +
>  static int
>  gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
> -		u32 gmbus1_index)
> +		u32 gmbus0_reg, u32 gmbus1_index)
>  {
>  	u8 *buf = msg->buf;
>  	unsigned int rx_size = msg->len;
> @@ -407,10 +442,13 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>  	int ret;
>  
>  	do {
> -		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
> +		if (HAS_GMBUS_BURST_READ(dev_priv))
> +			len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
> +		else
> +			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
>  
> -		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
> -					    buf, len, gmbus1_index);
> +		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
> +					    gmbus0_reg, gmbus1_index);
>  		if (ret)
>  			return ret;
>  
> @@ -498,7 +536,8 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
>  }
>  
>  static int
> -gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
> +gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
> +		 u32 gmbus0_reg)
>  {
>  	u32 gmbus1_index = 0;
>  	u32 gmbus5 = 0;
> @@ -516,7 +555,8 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
>  		I915_WRITE_FW(GMBUS5, gmbus5);
>  
>  	if (msgs[1].flags & I2C_M_RD)
> -		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
> +		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
> +				      gmbus1_index);
>  	else
>  		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
>  
> @@ -551,10 +591,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
>  	for (; i < num; i += inc) {
>  		inc = 1;
>  		if (gmbus_is_index_xfer(msgs, i, num)) {
> -			ret = gmbus_index_xfer(dev_priv, &msgs[i]);
> +			ret = gmbus_index_xfer(dev_priv, &msgs[i],
> +					       gmbus0_source | bus->reg0);
>  			inc = 2; /* an index transmission is two msgs */
>  		} else if (msgs[i].flags & I2C_M_RD) {
> -			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
> +			ret = gmbus_xfer_read(dev_priv, &msgs[i],
> +					      gmbus0_source | bus->reg0, 0);
>  		} else {
>  			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
>  		}
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel
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Re: [PATCH v5 2/2] drm/i915/gmbus: Enable burst read

[Ramalingam C]

On Tuesday 29 May 2018 11:35 PM, Ville Syrjälä wrote:
> On Fri, May 18, 2018 at 02:54:53PM +0530, Ramalingam C wrote:
>> Support for Burst read in HW is added for HDCP2.2 compliance
>> requirement.
>>
>> This patch enables the burst read for all the gmbus read of more than
>> 511Bytes, on capable platforms.
>>
>> v2:
>>    Extra line is removed.
>> v3:
>>    Macro is added for detecting the BURST_READ Support [Jani]
>>    Runtime detection of the need for burst_read [Jani]
>>    Calculation enhancement.
>> v4:
>>    GMBUS0 reg val is passed from caller [ville]
>>    Removed a extra var [ville]
>>    Extra brackets are removed [ville]
>>    Implemented the handling of 512Bytes Burst Read.
>> v5:
>>    Burst read max length is fixed at 767Bytes [Ville]
>>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h  |  3 ++
>>   drivers/gpu/drm/i915/i915_reg.h  |  1 +
>>   drivers/gpu/drm/i915/intel_i2c.c | 62 +++++++++++++++++++++++++++++++++-------
>>   3 files changed, 56 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 028691108125..14293fc1a142 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2552,6 +2552,9 @@ intel_info(const struct drm_i915_private *dev_priv)
>>    */
>>   #define HAS_AUX_IRQ(dev_priv)   true
>>   #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
>> +#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
>> +					IS_GEMINILAKE(dev_priv) || \
>> +					IS_KABYLAKE(dev_priv))
> Note 100% sure about these. The spec say some late stepping SPT has this
> already. But I suppose this KBL+ match means just KBP+?
>
> Hmm. Did I ask this already before? Getting some dejavu here.
Ville,

All product sku of KBL will have the WA. And we are enabling this from 
gen10+ including KBL and GLK for HDCP2.2 requirement.
Thats the reasoning behind this.


>
>>   /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>>    * rows, which changed the alignment requirements and fence programming.
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index ebdf7c9d816e..575d9495f3e2 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2996,6 +2996,7 @@ enum i915_power_well_id {
>>   #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
>>   #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
>>   #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
>> +#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
>>   #define   GMBUS_PIN_DISABLED	0
>>   #define   GMBUS_PIN_SSC		1
>>   #define   GMBUS_PIN_VGADDC	2
>> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>> index 1c0f6b56b209..9e1142a2f81b 100644
>> --- a/drivers/gpu/drm/i915/intel_i2c.c
>> +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> @@ -371,12 +371,30 @@ unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
>>   static int
>>   gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>>   		      unsigned short addr, u8 *buf, unsigned int len,
>> -		      u32 gmbus1_index)
>> +		      u32 gmbus0_reg, u32 gmbus1_index)
>>   {
>> +	unsigned int size = len;
>> +	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
>> +	bool extra_byte_added = false;
>> +
>> +	if (burst_read) {
>> +
> Stray newline.
With this newline removed, I will submit the next version with your 
reviewed-by.

Thanks
Ram
>
> Otherwise this looks good to me.
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>
>> +		/*
>> +		 * As per HW Spec, for 512Bytes need to read extra Byte and
>> +		 * Ignore the extra byte read.
>> +		 */
>> +		if (len == 512) {
>> +			extra_byte_added = true;
>> +			len++;
>> +		}
>> +		size = len % 256 + 256;
>> +		I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
>> +	}
>> +
>>   	I915_WRITE_FW(GMBUS1,
>>   		      gmbus1_index |
>>   		      GMBUS_CYCLE_WAIT |
>> -		      (len << GMBUS_BYTE_COUNT_SHIFT) |
>> +		      (size << GMBUS_BYTE_COUNT_SHIFT) |
>>   		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
>>   		      GMBUS_SLAVE_READ | GMBUS_SW_RDY);
>>   	while (len) {
>> @@ -389,17 +407,34 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>>   
>>   		val = I915_READ_FW(GMBUS3);
>>   		do {
>> +			if (extra_byte_added && len == 1)
>> +				break;
>> +
>>   			*buf++ = val & 0xff;
>>   			val >>= 8;
>>   		} while (--len && ++loop < 4);
>> +
>> +		if (burst_read && len == size - 4)
>> +			/* Reset the override bit */
>> +			I915_WRITE_FW(GMBUS0, gmbus0_reg);
>>   	}
>>   
>>   	return 0;
>>   }
>>   
>> +/*
>> + * HW spec says that 512Bytes in Burst read need special treatment.
>> + * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
>> + * an I2C slave, which supports such a lengthy burst read too for experiments.
>> + *
>> + * So until things get clarified on HW support, to avoid the burst read length
>> + * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
>> + */
>> +#define INTEL_GMBUS_BURST_READ_MAX_LEN		767U
>> +
>>   static int
>>   gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>> -		u32 gmbus1_index)
>> +		u32 gmbus0_reg, u32 gmbus1_index)
>>   {
>>   	u8 *buf = msg->buf;
>>   	unsigned int rx_size = msg->len;
>> @@ -407,10 +442,13 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>>   	int ret;
>>   
>>   	do {
>> -		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
>> +		if (HAS_GMBUS_BURST_READ(dev_priv))
>> +			len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
>> +		else
>> +			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
>>   
>> -		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
>> -					    buf, len, gmbus1_index);
>> +		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
>> +					    gmbus0_reg, gmbus1_index);
>>   		if (ret)
>>   			return ret;
>>   
>> @@ -498,7 +536,8 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
>>   }
>>   
>>   static int
>> -gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
>> +gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
>> +		 u32 gmbus0_reg)
>>   {
>>   	u32 gmbus1_index = 0;
>>   	u32 gmbus5 = 0;
>> @@ -516,7 +555,8 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
>>   		I915_WRITE_FW(GMBUS5, gmbus5);
>>   
>>   	if (msgs[1].flags & I2C_M_RD)
>> -		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
>> +		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
>> +				      gmbus1_index);
>>   	else
>>   		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
>>   
>> @@ -551,10 +591,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
>>   	for (; i < num; i += inc) {
>>   		inc = 1;
>>   		if (gmbus_is_index_xfer(msgs, i, num)) {
>> -			ret = gmbus_index_xfer(dev_priv, &msgs[i]);
>> +			ret = gmbus_index_xfer(dev_priv, &msgs[i],
>> +					       gmbus0_source | bus->reg0);
>>   			inc = 2; /* an index transmission is two msgs */
>>   		} else if (msgs[i].flags & I2C_M_RD) {
>> -			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
>> +			ret = gmbus_xfer_read(dev_priv, &msgs[i],
>> +					      gmbus0_source | bus->reg0, 0);
>>   		} else {
>>   			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
>>   		}
>> -- 
>> 2.7.4

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