* [PATCH v1½ 01/13] drm/i915/dp: use known correct array size in rate_to_index
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 02/13] drm/i915/dp: return errors from rate_to_index() Jani Nikula
` (13 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
I can't think of a real world bug this could cause now, but this will be
required in follow-up work. While at it, change the parameter order to
be slightly more sensible.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0fafbec6dacf..08eeb33cf63e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1542,12 +1542,12 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
return true;
}
-static int rate_to_index(int find, const int *rates)
+static int rate_to_index(const int *rates, int len, int rate)
{
- int i = 0;
+ int i;
- for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
- if (find == rates[i])
+ for (i = 0; i < len; i++)
+ if (rate == rates[i])
break;
return i;
@@ -1568,7 +1568,8 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
- return rate_to_index(rate, intel_dp->sink_rates);
+ return rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
+ rate);
}
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
--
2.1.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 02/13] drm/i915/dp: return errors from rate_to_index()
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 01/13] drm/i915/dp: use known correct array size in rate_to_index Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse Jani Nikula
` (12 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We shouldn't silently use the first element if we can't find the rate
we're looking for. Make rate_to_index() more generally useful, and
fallback to the first element in the caller, with a big warning.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 08eeb33cf63e..1d66737a3a0f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1548,9 +1548,9 @@ static int rate_to_index(const int *rates, int len, int rate)
for (i = 0; i < len; i++)
if (rate == rates[i])
- break;
+ return i;
- return i;
+ return -1;
}
int
@@ -1568,8 +1568,13 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
- return rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
- rate);
+ int i = rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
+ rate);
+
+ if (WARN_ON(i < 0))
+ i = 0;
+
+ return i;
}
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
--
2.1.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 01/13] drm/i915/dp: use known correct array size in rate_to_index Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 02/13] drm/i915/dp: return errors from rate_to_index() Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-02-01 21:46 ` Pandiyan, Dhinakaran
2017-01-26 19:44 ` [PATCH v1½ 04/13] drm/i915/dp: cache source rates at init Jani Nikula
` (11 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Rename the function, move it at the top, and reuse in
intel_dp_link_rate_index(). If there was a reason in the past to use
reverse search order here, there isn't now.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++-------------------
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1d66737a3a0f..f3068ff670a1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -266,6 +266,17 @@ static int intersect_rates(const int *source_rates, int source_len,
return k;
}
+static int intel_dp_find_rate(const int *rates, int len, int rate)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ if (rate == rates[i])
+ return i;
+
+ return -1;
+}
+
static int intel_dp_common_rates(struct intel_dp *intel_dp,
int *common_rates)
{
@@ -284,15 +295,10 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
int *common_rates, int link_rate)
{
int common_len;
- int index;
common_len = intel_dp_common_rates(intel_dp, common_rates);
- for (index = 0; index < common_len; index++) {
- if (link_rate == common_rates[common_len - index - 1])
- return common_len - index - 1;
- }
- return -1;
+ return intel_dp_find_rate(common_rates, common_len, link_rate);
}
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
@@ -1542,17 +1548,6 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
return true;
}
-static int rate_to_index(const int *rates, int len, int rate)
-{
- int i;
-
- for (i = 0; i < len; i++)
- if (rate == rates[i])
- return i;
-
- return -1;
-}
-
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
@@ -1568,8 +1563,8 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
- int i = rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
- rate);
+ int i = intel_dp_find_rate(intel_dp->sink_rates,
+ intel_dp->num_sink_rates, rate);
if (WARN_ON(i < 0))
i = 0;
--
2.1.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
2017-01-26 19:44 ` [PATCH v1½ 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse Jani Nikula
@ 2017-02-01 21:46 ` Pandiyan, Dhinakaran
2017-02-02 8:44 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-02-01 21:46 UTC (permalink / raw)
To: Nikula, Jani; +Cc: intel-gfx
On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote:
> Rename the function, move it at the top, and reuse in
> intel_dp_link_rate_index(). If there was a reason in the past to use
> reverse search order here, there isn't now.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++-------------------
> 1 file changed, 14 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1d66737a3a0f..f3068ff670a1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -266,6 +266,17 @@ static int intersect_rates(const int *source_rates, int source_len,
> return k;
> }
>
> +static int intel_dp_find_rate(const int *rates, int len, int rate)
I wonder if the function name can be more intuitive. The argument is
rate and the function name indicates it also returns rate. I can't tell
what the function does by it's name. Feel free to ignore this comment as
I might be missing some context.
-DK
> +{
> + int i;
> +
> + for (i = 0; i < len; i++)
> + if (rate == rates[i])
> + return i;
> +
> + return -1;
> +}
> +
> static int intel_dp_common_rates(struct intel_dp *intel_dp,
> int *common_rates)
> {
> @@ -284,15 +295,10 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
> int *common_rates, int link_rate)
> {
> int common_len;
> - int index;
>
> common_len = intel_dp_common_rates(intel_dp, common_rates);
> - for (index = 0; index < common_len; index++) {
> - if (link_rate == common_rates[common_len - index - 1])
> - return common_len - index - 1;
> - }
>
> - return -1;
> + return intel_dp_find_rate(common_rates, common_len, link_rate);
> }
>
> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> @@ -1542,17 +1548,6 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
> return true;
> }
>
> -static int rate_to_index(const int *rates, int len, int rate)
> -{
> - int i;
> -
> - for (i = 0; i < len; i++)
> - if (rate == rates[i])
> - return i;
> -
> - return -1;
> -}
> -
> int
> intel_dp_max_link_rate(struct intel_dp *intel_dp)
> {
> @@ -1568,8 +1563,8 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
>
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> {
> - int i = rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
> - rate);
> + int i = intel_dp_find_rate(intel_dp->sink_rates,
> + intel_dp->num_sink_rates, rate);
>
> if (WARN_ON(i < 0))
> i = 0;
_______________________________________________
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
2017-02-01 21:46 ` Pandiyan, Dhinakaran
@ 2017-02-02 8:44 ` Jani Nikula
2017-02-07 18:38 ` Pandiyan, Dhinakaran
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2017-02-02 8:44 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx
On Wed, 01 Feb 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote:
>> Rename the function, move it at the top, and reuse in
>> intel_dp_link_rate_index(). If there was a reason in the past to use
>> reverse search order here, there isn't now.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++-------------------
>> 1 file changed, 14 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 1d66737a3a0f..f3068ff670a1 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -266,6 +266,17 @@ static int intersect_rates(const int *source_rates, int source_len,
>> return k;
>> }
>>
>> +static int intel_dp_find_rate(const int *rates, int len, int rate)
>
> I wonder if the function name can be more intuitive. The argument is
> rate and the function name indicates it also returns rate. I can't tell
> what the function does by it's name. Feel free to ignore this comment as
> I might be missing some context.
Naming is hard. intel_dp_rate_index?
BR,
Jani.
>
> -DK
>
>> +{
>> + int i;
>> +
>> + for (i = 0; i < len; i++)
>> + if (rate == rates[i])
>> + return i;
>> +
>> + return -1;
>> +}
>> +
>> static int intel_dp_common_rates(struct intel_dp *intel_dp,
>> int *common_rates)
>> {
>> @@ -284,15 +295,10 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
>> int *common_rates, int link_rate)
>> {
>> int common_len;
>> - int index;
>>
>> common_len = intel_dp_common_rates(intel_dp, common_rates);
>> - for (index = 0; index < common_len; index++) {
>> - if (link_rate == common_rates[common_len - index - 1])
>> - return common_len - index - 1;
>> - }
>>
>> - return -1;
>> + return intel_dp_find_rate(common_rates, common_len, link_rate);
>> }
>>
>> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>> @@ -1542,17 +1548,6 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
>> return true;
>> }
>>
>> -static int rate_to_index(const int *rates, int len, int rate)
>> -{
>> - int i;
>> -
>> - for (i = 0; i < len; i++)
>> - if (rate == rates[i])
>> - return i;
>> -
>> - return -1;
>> -}
>> -
>> int
>> intel_dp_max_link_rate(struct intel_dp *intel_dp)
>> {
>> @@ -1568,8 +1563,8 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
>>
>> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
>> {
>> - int i = rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
>> - rate);
>> + int i = intel_dp_find_rate(intel_dp->sink_rates,
>> + intel_dp->num_sink_rates, rate);
>>
>> if (WARN_ON(i < 0))
>> i = 0;
>
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
2017-02-02 8:44 ` Jani Nikula
@ 2017-02-07 18:38 ` Pandiyan, Dhinakaran
0 siblings, 0 replies; 31+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-02-07 18:38 UTC (permalink / raw)
To: Nikula, Jani; +Cc: intel-gfx
On Thu, 2017-02-02 at 10:44 +0200, Jani Nikula wrote:
> On Wed, 01 Feb 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> > On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote:
> >> Rename the function, move it at the top, and reuse in
> >> intel_dp_link_rate_index(). If there was a reason in the past to use
> >> reverse search order here, there isn't now.
> >>
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++-------------------
> >> 1 file changed, 14 insertions(+), 19 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> index 1d66737a3a0f..f3068ff670a1 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -266,6 +266,17 @@ static int intersect_rates(const int *source_rates, int source_len,
> >> return k;
> >> }
> >>
> >> +static int intel_dp_find_rate(const int *rates, int len, int rate)
> >
> > I wonder if the function name can be more intuitive. The argument is
> > rate and the function name indicates it also returns rate. I can't tell
> > what the function does by it's name. Feel free to ignore this comment as
> > I might be missing some context.
>
> Naming is hard. intel_dp_rate_index?
>
> BR,
> Jani.
>
>
That does sounds good.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >
> > -DK
> >
> >> +{
> >> + int i;
> >> +
> >> + for (i = 0; i < len; i++)
> >> + if (rate == rates[i])
> >> + return i;
> >> +
> >> + return -1;
> >> +}
> >> +
> >> static int intel_dp_common_rates(struct intel_dp *intel_dp,
> >> int *common_rates)
> >> {
> >> @@ -284,15 +295,10 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
> >> int *common_rates, int link_rate)
> >> {
> >> int common_len;
> >> - int index;
> >>
> >> common_len = intel_dp_common_rates(intel_dp, common_rates);
> >> - for (index = 0; index < common_len; index++) {
> >> - if (link_rate == common_rates[common_len - index - 1])
> >> - return common_len - index - 1;
> >> - }
> >>
> >> - return -1;
> >> + return intel_dp_find_rate(common_rates, common_len, link_rate);
> >> }
> >>
> >> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> >> @@ -1542,17 +1548,6 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
> >> return true;
> >> }
> >>
> >> -static int rate_to_index(const int *rates, int len, int rate)
> >> -{
> >> - int i;
> >> -
> >> - for (i = 0; i < len; i++)
> >> - if (rate == rates[i])
> >> - return i;
> >> -
> >> - return -1;
> >> -}
> >> -
> >> int
> >> intel_dp_max_link_rate(struct intel_dp *intel_dp)
> >> {
> >> @@ -1568,8 +1563,8 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
> >>
> >> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> >> {
> >> - int i = rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
> >> - rate);
> >> + int i = intel_dp_find_rate(intel_dp->sink_rates,
> >> + intel_dp->num_sink_rates, rate);
> >>
> >> if (WARN_ON(i < 0))
> >> i = 0;
> >
>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v1½ 04/13] drm/i915/dp: cache source rates at init
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (2 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 Jani Nikula
` (10 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We need the source rates array so often that it makes sense to set it
once at init. This reduces function calls when we need the rates, making
the code easier to follow.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 35 +++++++++++++++++++++--------------
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f3068ff670a1..cc2523363c8d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -218,21 +218,25 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
return (intel_dp->max_sink_link_bw >> 3) + 1;
}
-static int
-intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
+static void
+intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ const int *source_rates;
int size;
+ /* This should only be done once */
+ WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
+
if (IS_GEN9_LP(dev_priv)) {
- *source_rates = bxt_rates;
+ source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
} else if (IS_GEN9_BC(dev_priv)) {
- *source_rates = skl_rates;
+ source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
} else {
- *source_rates = default_rates;
+ source_rates = default_rates;
size = ARRAY_SIZE(default_rates);
}
@@ -240,7 +244,8 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
if (!intel_dp_source_supports_hbr2(intel_dp))
size--;
- return size;
+ intel_dp->source_rates = source_rates;
+ intel_dp->num_source_rates = size;
}
static int intersect_rates(const int *source_rates, int source_len,
@@ -280,13 +285,13 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
static int intel_dp_common_rates(struct intel_dp *intel_dp,
int *common_rates)
{
- const int *source_rates, *sink_rates;
- int source_len, sink_len;
+ const int *sink_rates;
+ int sink_len;
sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
- source_len = intel_dp_source_rates(intel_dp, &source_rates);
- return intersect_rates(source_rates, source_len,
+ return intersect_rates(intel_dp->source_rates,
+ intel_dp->num_source_rates,
sink_rates, sink_len,
common_rates);
}
@@ -1496,16 +1501,16 @@ static void snprintf_int_array(char *str, size_t len,
static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
- const int *source_rates, *sink_rates;
- int source_len, sink_len, common_len;
+ const int *sink_rates;
+ int sink_len, common_len;
int common_rates[DP_MAX_SUPPORTED_RATES];
char str[128]; /* FIXME: too big for stack? */
if ((drm_debug & DRM_UT_KMS) == 0)
return;
- source_len = intel_dp_source_rates(intel_dp, &source_rates);
- snprintf_int_array(str, sizeof(str), source_rates, source_len);
+ snprintf_int_array(str, sizeof(str),
+ intel_dp->source_rates, intel_dp->num_source_rates);
DRM_DEBUG_KMS("source rates: %s\n", str);
sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
@@ -5919,6 +5924,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
intel_dig_port->max_lanes, port_name(port)))
return false;
+ intel_dp_set_source_rates(intel_dp);
+
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 393f24340e74..f132d4aea1ad 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -930,6 +930,9 @@ struct intel_dp {
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ /* source rates */
+ int num_source_rates;
+ const int *source_rates;
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (3 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 04/13] drm/i915/dp: cache source rates at init Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-27 17:28 ` Ville Syrjälä
2017-01-28 10:16 ` [PATCH v2] " Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 06/13] drm/i915/dp: use the sink rates array for max sink rates Jani Nikula
` (9 subsequent siblings)
14 siblings, 2 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
There is some conflation related to sink rates, making this change more
complicated than it would otherwise have to be. There are three changes
here that are rather difficult to split up:
1) Use the intel_dp->sink_rates array for all DP, not just eDP 1.4. We
initialize it from DPCD on eDP 1.4 like before, but generate it based
on DP_MAX_LINK_RATE on others. This reduces code complexity when we
need to use the sink rates; they are all always in the sink_rates
array.
2) Update the sink rate array whenever we read DPCD, and use the
information from there. This increases code readability when we need
the sink rates.
3) Disentangle fallback rate limiting from sink rates. In the code, the
max rate is a dynamic property of the *link*, not of the *sink*. Do
the limiting after intersecting the source and sink rates, which are
static properties of the devices.
This paves the way for follow-up refactoring that I've refrained from
doing here to keep this change as simple as it possibly can.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 76 ++++++++++++++++++---------
drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 4 +-
3 files changed, 55 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cc2523363c8d..d13ce6746542 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -133,6 +133,34 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_num_rates(u8 link_bw_code)
+{
+ switch (link_bw_code) {
+ default:
+ WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
+ link_bw_code);
+ case DP_LINK_BW_1_62:
+ return 1;
+ case DP_LINK_BW_2_7:
+ return 2;
+ case DP_LINK_BW_5_4:
+ return 3;
+ }
+}
+
+/* update sink rates from dpcd */
+static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
+{
+ int i, num_rates;
+
+ num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+
+ for (i = 0; i < num_rates; i++)
+ intel_dp->sink_rates[i] = default_rates[i];
+
+ intel_dp->num_sink_rates = num_rates;
+}
+
static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
@@ -205,19 +233,6 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
return max_dotclk;
}
-static int
-intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
-{
- if (intel_dp->num_sink_rates) {
- *sink_rates = intel_dp->sink_rates;
- return intel_dp->num_sink_rates;
- }
-
- *sink_rates = default_rates;
-
- return (intel_dp->max_sink_link_bw >> 3) + 1;
-}
-
static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
@@ -285,15 +300,22 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
static int intel_dp_common_rates(struct intel_dp *intel_dp,
int *common_rates)
{
- const int *sink_rates;
- int sink_len;
+ int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
+ int i, common_len;
- sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
+ common_len = intersect_rates(intel_dp->source_rates,
+ intel_dp->num_source_rates,
+ intel_dp->sink_rates,
+ intel_dp->num_sink_rates,
+ common_rates);
- return intersect_rates(intel_dp->source_rates,
- intel_dp->num_source_rates,
- sink_rates, sink_len,
- common_rates);
+ /* Limit results by potentially reduced max rate */
+ for (i = 0; i < common_len; i++) {
+ if (common_rates[common_len - i - 1] <= max_rate)
+ return common_len - i;
+ }
+
+ return 0;
}
static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
@@ -1501,8 +1523,7 @@ static void snprintf_int_array(char *str, size_t len,
static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
- const int *sink_rates;
- int sink_len, common_len;
+ int common_len;
int common_rates[DP_MAX_SUPPORTED_RATES];
char str[128]; /* FIXME: too big for stack? */
@@ -1513,8 +1534,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
intel_dp->source_rates, intel_dp->num_source_rates);
DRM_DEBUG_KMS("source rates: %s\n", str);
- sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
- snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
+ snprintf_int_array(str, sizeof(str),
+ intel_dp->sink_rates, intel_dp->num_sink_rates);
DRM_DEBUG_KMS("sink rates: %s\n", str);
common_len = intel_dp_common_rates(intel_dp, common_rates);
@@ -1580,7 +1601,8 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
uint8_t *link_bw, uint8_t *rate_select)
{
- if (intel_dp->num_sink_rates) {
+ /* eDP 1.4 rate select method. */
+ if (is_edp(intel_dp) && intel_dp->edp_dpcd[0] >= 0x03) {
*link_bw = 0;
*rate_select =
intel_dp_rate_select(intel_dp, port_clock);
@@ -3713,6 +3735,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp->sink_rates[i] = (val * 200) / 10;
}
intel_dp->num_sink_rates = i;
+ } else {
+ intel_dp_set_sink_rates(intel_dp);
}
return true;
@@ -3725,6 +3749,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
if (!intel_dp_read_dpcd(intel_dp))
return false;
+ intel_dp_set_sink_rates(intel_dp);
+
if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
&intel_dp->sink_count, 1) < 0)
return false;
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0048b520baf7..694ad0ffb523 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -146,7 +146,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
- if (intel_dp->num_sink_rates)
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
&rate_select, 1);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f132d4aea1ad..b914dd543362 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -933,8 +933,8 @@ struct intel_dp {
/* source rates */
int num_source_rates;
const int *source_rates;
- /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
- uint8_t num_sink_rates;
+ /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
+ int num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
/* Max lane count for the sink as per DPCD registers */
uint8_t max_sink_lane_count;
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4
2017-01-26 19:44 ` [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 Jani Nikula
@ 2017-01-27 17:28 ` Ville Syrjälä
2017-01-27 19:52 ` Jani Nikula
2017-01-28 10:16 ` [PATCH v2] " Jani Nikula
1 sibling, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2017-01-27 17:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Jan 26, 2017 at 09:44:19PM +0200, Jani Nikula wrote:
> There is some conflation related to sink rates, making this change more
> complicated than it would otherwise have to be. There are three changes
> here that are rather difficult to split up:
>
> 1) Use the intel_dp->sink_rates array for all DP, not just eDP 1.4. We
> initialize it from DPCD on eDP 1.4 like before, but generate it based
> on DP_MAX_LINK_RATE on others. This reduces code complexity when we
> need to use the sink rates; they are all always in the sink_rates
> array.
>
> 2) Update the sink rate array whenever we read DPCD, and use the
> information from there. This increases code readability when we need
> the sink rates.
>
> 3) Disentangle fallback rate limiting from sink rates. In the code, the
> max rate is a dynamic property of the *link*, not of the *sink*. Do
> the limiting after intersecting the source and sink rates, which are
> static properties of the devices.
>
> This paves the way for follow-up refactoring that I've refrained from
> doing here to keep this change as simple as it possibly can.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 76 ++++++++++++++++++---------
> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> 3 files changed, 55 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cc2523363c8d..d13ce6746542 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -133,6 +133,34 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
> enum pipe pipe);
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>
> +static int intel_dp_num_rates(u8 link_bw_code)
> +{
> + switch (link_bw_code) {
> + default:
> + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
> + link_bw_code);
> + case DP_LINK_BW_1_62:
> + return 1;
> + case DP_LINK_BW_2_7:
> + return 2;
> + case DP_LINK_BW_5_4:
> + return 3;
> + }
> +}
> +
> +/* update sink rates from dpcd */
> +static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> +{
> + int i, num_rates;
> +
> + num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
> +
> + for (i = 0; i < num_rates; i++)
> + intel_dp->sink_rates[i] = default_rates[i];
> +
> + intel_dp->num_sink_rates = num_rates;
> +}
> +
> static int
> intel_dp_max_link_bw(struct intel_dp *intel_dp)
> {
> @@ -205,19 +233,6 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
> return max_dotclk;
> }
>
> -static int
> -intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
> -{
> - if (intel_dp->num_sink_rates) {
> - *sink_rates = intel_dp->sink_rates;
> - return intel_dp->num_sink_rates;
> - }
> -
> - *sink_rates = default_rates;
> -
> - return (intel_dp->max_sink_link_bw >> 3) + 1;
> -}
> -
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> @@ -285,15 +300,22 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
> static int intel_dp_common_rates(struct intel_dp *intel_dp,
> int *common_rates)
> {
> - const int *sink_rates;
> - int sink_len;
> + int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
> + int i, common_len;
>
> - sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> + common_len = intersect_rates(intel_dp->source_rates,
> + intel_dp->num_source_rates,
> + intel_dp->sink_rates,
> + intel_dp->num_sink_rates,
> + common_rates);
>
> - return intersect_rates(intel_dp->source_rates,
> - intel_dp->num_source_rates,
> - sink_rates, sink_len,
> - common_rates);
> + /* Limit results by potentially reduced max rate */
> + for (i = 0; i < common_len; i++) {
> + if (common_rates[common_len - i - 1] <= max_rate)
> + return common_len - i;
> + }
> +
> + return 0;
> }
>
> static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
> @@ -1501,8 +1523,7 @@ static void snprintf_int_array(char *str, size_t len,
>
> static void intel_dp_print_rates(struct intel_dp *intel_dp)
> {
> - const int *sink_rates;
> - int sink_len, common_len;
> + int common_len;
> int common_rates[DP_MAX_SUPPORTED_RATES];
> char str[128]; /* FIXME: too big for stack? */
>
> @@ -1513,8 +1534,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
> intel_dp->source_rates, intel_dp->num_source_rates);
> DRM_DEBUG_KMS("source rates: %s\n", str);
>
> - sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> - snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
> + snprintf_int_array(str, sizeof(str),
> + intel_dp->sink_rates, intel_dp->num_sink_rates);
> DRM_DEBUG_KMS("sink rates: %s\n", str);
>
> common_len = intel_dp_common_rates(intel_dp, common_rates);
> @@ -1580,7 +1601,8 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> uint8_t *link_bw, uint8_t *rate_select)
> {
> - if (intel_dp->num_sink_rates) {
> + /* eDP 1.4 rate select method. */
> + if (is_edp(intel_dp) && intel_dp->edp_dpcd[0] >= 0x03) {
I was convinced that this wasn't a mandatory feature, but the spec does
seem to say "The table must contain at least one non-zero value at the
first (lowest DPCD address) location."
But given historical evidence I'm still 99% convinced we'll eventually
run into some panel somewhere that does this wrong, so I don't really
like this idea.
> *link_bw = 0;
> *rate_select =
> intel_dp_rate_select(intel_dp, port_clock);
> @@ -3713,6 +3735,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> intel_dp->sink_rates[i] = (val * 200) / 10;
> }
> intel_dp->num_sink_rates = i;
> + } else {
> + intel_dp_set_sink_rates(intel_dp);
> }
>
> return true;
> @@ -3725,6 +3749,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> if (!intel_dp_read_dpcd(intel_dp))
> return false;
>
> + intel_dp_set_sink_rates(intel_dp);
> +
> if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
> &intel_dp->sink_count, 1) < 0)
> return false;
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 0048b520baf7..694ad0ffb523 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -146,7 +146,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>
> - if (intel_dp->num_sink_rates)
> + /* eDP 1.4 rate select method. */
> + if (!link_bw)
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> &rate_select, 1);
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f132d4aea1ad..b914dd543362 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -933,8 +933,8 @@ struct intel_dp {
> /* source rates */
> int num_source_rates;
> const int *source_rates;
> - /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
> - uint8_t num_sink_rates;
> + /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
> + int num_sink_rates;
> int sink_rates[DP_MAX_SUPPORTED_RATES];
> /* Max lane count for the sink as per DPCD registers */
> uint8_t max_sink_lane_count;
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4
2017-01-27 17:28 ` Ville Syrjälä
@ 2017-01-27 19:52 ` Jani Nikula
2017-01-27 20:00 ` Ville Syrjälä
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2017-01-27 19:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, 27 Jan 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Jan 26, 2017 at 09:44:19PM +0200, Jani Nikula wrote:
>> There is some conflation related to sink rates, making this change more
>> complicated than it would otherwise have to be. There are three changes
>> here that are rather difficult to split up:
>>
>> 1) Use the intel_dp->sink_rates array for all DP, not just eDP 1.4. We
>> initialize it from DPCD on eDP 1.4 like before, but generate it based
>> on DP_MAX_LINK_RATE on others. This reduces code complexity when we
>> need to use the sink rates; they are all always in the sink_rates
>> array.
>>
>> 2) Update the sink rate array whenever we read DPCD, and use the
>> information from there. This increases code readability when we need
>> the sink rates.
>>
>> 3) Disentangle fallback rate limiting from sink rates. In the code, the
>> max rate is a dynamic property of the *link*, not of the *sink*. Do
>> the limiting after intersecting the source and sink rates, which are
>> static properties of the devices.
>>
>> This paves the way for follow-up refactoring that I've refrained from
>> doing here to keep this change as simple as it possibly can.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 76 ++++++++++++++++++---------
>> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
>> drivers/gpu/drm/i915/intel_drv.h | 4 +-
>> 3 files changed, 55 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index cc2523363c8d..d13ce6746542 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -133,6 +133,34 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
>> enum pipe pipe);
>> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>>
>> +static int intel_dp_num_rates(u8 link_bw_code)
>> +{
>> + switch (link_bw_code) {
>> + default:
>> + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
>> + link_bw_code);
>> + case DP_LINK_BW_1_62:
>> + return 1;
>> + case DP_LINK_BW_2_7:
>> + return 2;
>> + case DP_LINK_BW_5_4:
>> + return 3;
>> + }
>> +}
>> +
>> +/* update sink rates from dpcd */
>> +static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
>> +{
>> + int i, num_rates;
>> +
>> + num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>> +
>> + for (i = 0; i < num_rates; i++)
>> + intel_dp->sink_rates[i] = default_rates[i];
>> +
>> + intel_dp->num_sink_rates = num_rates;
>> +}
>> +
>> static int
>> intel_dp_max_link_bw(struct intel_dp *intel_dp)
>> {
>> @@ -205,19 +233,6 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
>> return max_dotclk;
>> }
>>
>> -static int
>> -intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>> -{
>> - if (intel_dp->num_sink_rates) {
>> - *sink_rates = intel_dp->sink_rates;
>> - return intel_dp->num_sink_rates;
>> - }
>> -
>> - *sink_rates = default_rates;
>> -
>> - return (intel_dp->max_sink_link_bw >> 3) + 1;
>> -}
>> -
>> static void
>> intel_dp_set_source_rates(struct intel_dp *intel_dp)
>> {
>> @@ -285,15 +300,22 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
>> static int intel_dp_common_rates(struct intel_dp *intel_dp,
>> int *common_rates)
>> {
>> - const int *sink_rates;
>> - int sink_len;
>> + int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
>> + int i, common_len;
>>
>> - sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
>> + common_len = intersect_rates(intel_dp->source_rates,
>> + intel_dp->num_source_rates,
>> + intel_dp->sink_rates,
>> + intel_dp->num_sink_rates,
>> + common_rates);
>>
>> - return intersect_rates(intel_dp->source_rates,
>> - intel_dp->num_source_rates,
>> - sink_rates, sink_len,
>> - common_rates);
>> + /* Limit results by potentially reduced max rate */
>> + for (i = 0; i < common_len; i++) {
>> + if (common_rates[common_len - i - 1] <= max_rate)
>> + return common_len - i;
>> + }
>> +
>> + return 0;
>> }
>>
>> static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
>> @@ -1501,8 +1523,7 @@ static void snprintf_int_array(char *str, size_t len,
>>
>> static void intel_dp_print_rates(struct intel_dp *intel_dp)
>> {
>> - const int *sink_rates;
>> - int sink_len, common_len;
>> + int common_len;
>> int common_rates[DP_MAX_SUPPORTED_RATES];
>> char str[128]; /* FIXME: too big for stack? */
>>
>> @@ -1513,8 +1534,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
>> intel_dp->source_rates, intel_dp->num_source_rates);
>> DRM_DEBUG_KMS("source rates: %s\n", str);
>>
>> - sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
>> - snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
>> + snprintf_int_array(str, sizeof(str),
>> + intel_dp->sink_rates, intel_dp->num_sink_rates);
>> DRM_DEBUG_KMS("sink rates: %s\n", str);
>>
>> common_len = intel_dp_common_rates(intel_dp, common_rates);
>> @@ -1580,7 +1601,8 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
>> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>> uint8_t *link_bw, uint8_t *rate_select)
>> {
>> - if (intel_dp->num_sink_rates) {
>> + /* eDP 1.4 rate select method. */
>> + if (is_edp(intel_dp) && intel_dp->edp_dpcd[0] >= 0x03) {
>
> I was convinced that this wasn't a mandatory feature, but the spec does
> seem to say "The table must contain at least one non-zero value at the
> first (lowest DPCD address) location."
>
> But given historical evidence I'm still 99% convinced we'll eventually
> run into some panel somewhere that does this wrong, so I don't really
> like this idea.
Then I think this should be fixed in intel_edp_init_dpcd() by a)
checking that there is at least one non-zero value, falling back to
intel_dp_set_source_rates() if not, and b) setting a new
intel_dp->use_rate_selet field at that time, which will be used instead
of (is_edp(intel_dp) && intel_dp->edp_dpcd[0] >= 0x03). Sound good?
BR,
Jani.
>
>> *link_bw = 0;
>> *rate_select =
>> intel_dp_rate_select(intel_dp, port_clock);
>> @@ -3713,6 +3735,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>> intel_dp->sink_rates[i] = (val * 200) / 10;
>> }
>> intel_dp->num_sink_rates = i;
>> + } else {
>> + intel_dp_set_sink_rates(intel_dp);
>> }
>>
>> return true;
>> @@ -3725,6 +3749,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>> if (!intel_dp_read_dpcd(intel_dp))
>> return false;
>>
>> + intel_dp_set_sink_rates(intel_dp);
>> +
>> if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
>> &intel_dp->sink_count, 1) < 0)
>> return false;
>> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> index 0048b520baf7..694ad0ffb523 100644
>> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> @@ -146,7 +146,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>> link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>>
>> - if (intel_dp->num_sink_rates)
>> + /* eDP 1.4 rate select method. */
>> + if (!link_bw)
>> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> &rate_select, 1);
>>
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index f132d4aea1ad..b914dd543362 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -933,8 +933,8 @@ struct intel_dp {
>> /* source rates */
>> int num_source_rates;
>> const int *source_rates;
>> - /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
>> - uint8_t num_sink_rates;
>> + /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
>> + int num_sink_rates;
>> int sink_rates[DP_MAX_SUPPORTED_RATES];
>> /* Max lane count for the sink as per DPCD registers */
>> uint8_t max_sink_lane_count;
>> --
>> 2.1.4
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4
2017-01-27 19:52 ` Jani Nikula
@ 2017-01-27 20:00 ` Ville Syrjälä
0 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjälä @ 2017-01-27 20:00 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Jan 27, 2017 at 09:52:05PM +0200, Jani Nikula wrote:
> On Fri, 27 Jan 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Jan 26, 2017 at 09:44:19PM +0200, Jani Nikula wrote:
> >> There is some conflation related to sink rates, making this change more
> >> complicated than it would otherwise have to be. There are three changes
> >> here that are rather difficult to split up:
> >>
> >> 1) Use the intel_dp->sink_rates array for all DP, not just eDP 1.4. We
> >> initialize it from DPCD on eDP 1.4 like before, but generate it based
> >> on DP_MAX_LINK_RATE on others. This reduces code complexity when we
> >> need to use the sink rates; they are all always in the sink_rates
> >> array.
> >>
> >> 2) Update the sink rate array whenever we read DPCD, and use the
> >> information from there. This increases code readability when we need
> >> the sink rates.
> >>
> >> 3) Disentangle fallback rate limiting from sink rates. In the code, the
> >> max rate is a dynamic property of the *link*, not of the *sink*. Do
> >> the limiting after intersecting the source and sink rates, which are
> >> static properties of the devices.
> >>
> >> This paves the way for follow-up refactoring that I've refrained from
> >> doing here to keep this change as simple as it possibly can.
> >>
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_dp.c | 76 ++++++++++++++++++---------
> >> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
> >> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> >> 3 files changed, 55 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> index cc2523363c8d..d13ce6746542 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -133,6 +133,34 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
> >> enum pipe pipe);
> >> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> >>
> >> +static int intel_dp_num_rates(u8 link_bw_code)
> >> +{
> >> + switch (link_bw_code) {
> >> + default:
> >> + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
> >> + link_bw_code);
> >> + case DP_LINK_BW_1_62:
> >> + return 1;
> >> + case DP_LINK_BW_2_7:
> >> + return 2;
> >> + case DP_LINK_BW_5_4:
> >> + return 3;
> >> + }
> >> +}
> >> +
> >> +/* update sink rates from dpcd */
> >> +static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> >> +{
> >> + int i, num_rates;
> >> +
> >> + num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
> >> +
> >> + for (i = 0; i < num_rates; i++)
> >> + intel_dp->sink_rates[i] = default_rates[i];
> >> +
> >> + intel_dp->num_sink_rates = num_rates;
> >> +}
> >> +
> >> static int
> >> intel_dp_max_link_bw(struct intel_dp *intel_dp)
> >> {
> >> @@ -205,19 +233,6 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
> >> return max_dotclk;
> >> }
> >>
> >> -static int
> >> -intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
> >> -{
> >> - if (intel_dp->num_sink_rates) {
> >> - *sink_rates = intel_dp->sink_rates;
> >> - return intel_dp->num_sink_rates;
> >> - }
> >> -
> >> - *sink_rates = default_rates;
> >> -
> >> - return (intel_dp->max_sink_link_bw >> 3) + 1;
> >> -}
> >> -
> >> static void
> >> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> >> {
> >> @@ -285,15 +300,22 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
> >> static int intel_dp_common_rates(struct intel_dp *intel_dp,
> >> int *common_rates)
> >> {
> >> - const int *sink_rates;
> >> - int sink_len;
> >> + int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
> >> + int i, common_len;
> >>
> >> - sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> >> + common_len = intersect_rates(intel_dp->source_rates,
> >> + intel_dp->num_source_rates,
> >> + intel_dp->sink_rates,
> >> + intel_dp->num_sink_rates,
> >> + common_rates);
> >>
> >> - return intersect_rates(intel_dp->source_rates,
> >> - intel_dp->num_source_rates,
> >> - sink_rates, sink_len,
> >> - common_rates);
> >> + /* Limit results by potentially reduced max rate */
> >> + for (i = 0; i < common_len; i++) {
> >> + if (common_rates[common_len - i - 1] <= max_rate)
> >> + return common_len - i;
> >> + }
> >> +
> >> + return 0;
> >> }
> >>
> >> static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
> >> @@ -1501,8 +1523,7 @@ static void snprintf_int_array(char *str, size_t len,
> >>
> >> static void intel_dp_print_rates(struct intel_dp *intel_dp)
> >> {
> >> - const int *sink_rates;
> >> - int sink_len, common_len;
> >> + int common_len;
> >> int common_rates[DP_MAX_SUPPORTED_RATES];
> >> char str[128]; /* FIXME: too big for stack? */
> >>
> >> @@ -1513,8 +1534,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
> >> intel_dp->source_rates, intel_dp->num_source_rates);
> >> DRM_DEBUG_KMS("source rates: %s\n", str);
> >>
> >> - sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> >> - snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
> >> + snprintf_int_array(str, sizeof(str),
> >> + intel_dp->sink_rates, intel_dp->num_sink_rates);
> >> DRM_DEBUG_KMS("sink rates: %s\n", str);
> >>
> >> common_len = intel_dp_common_rates(intel_dp, common_rates);
> >> @@ -1580,7 +1601,8 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> >> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> >> uint8_t *link_bw, uint8_t *rate_select)
> >> {
> >> - if (intel_dp->num_sink_rates) {
> >> + /* eDP 1.4 rate select method. */
> >> + if (is_edp(intel_dp) && intel_dp->edp_dpcd[0] >= 0x03) {
> >
> > I was convinced that this wasn't a mandatory feature, but the spec does
> > seem to say "The table must contain at least one non-zero value at the
> > first (lowest DPCD address) location."
> >
> > But given historical evidence I'm still 99% convinced we'll eventually
> > run into some panel somewhere that does this wrong, so I don't really
> > like this idea.
>
> Then I think this should be fixed in intel_edp_init_dpcd() by a)
> checking that there is at least one non-zero value, falling back to
> intel_dp_set_source_rates() if not, and b) setting a new
> intel_dp->use_rate_selet field at that time, which will be used instead
> of (is_edp(intel_dp) && intel_dp->edp_dpcd[0] >= 0x03). Sound good?
Yep. That should preserve the current behaviour.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4
2017-01-26 19:44 ` [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 Jani Nikula
2017-01-27 17:28 ` Ville Syrjälä
@ 2017-01-28 10:16 ` Jani Nikula
1 sibling, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-28 10:16 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
There is some conflation related to sink rates, making this change more
complicated than it would otherwise have to be. There are three changes
here that are rather difficult to split up:
1) Use the intel_dp->sink_rates array for all DP, not just eDP 1.4. We
initialize it from DPCD on eDP 1.4 like before, but generate it based
on DP_MAX_LINK_RATE on others. This reduces code complexity when we
need to use the sink rates; they are all always in the sink_rates
array.
2) Update the sink rate array whenever we read DPCD, and use the
information from there. This increases code readability when we need
the sink rates.
3) Disentangle fallback rate limiting from sink rates. In the code, the
max rate is a dynamic property of the *link*, not of the *sink*. Do
the limiting after intersecting the source and sink rates, which are
static properties of the devices.
This paves the way for follow-up refactoring that I've refrained from
doing here to keep this change as simple as it possibly can.
v2: introduce use_rate_select and handle non-confirming eDP (Ville)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 79 ++++++++++++++++++---------
drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 5 +-
3 files changed, 59 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2e0592377cab..ec89e1fcd641 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -133,6 +133,34 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_num_rates(u8 link_bw_code)
+{
+ switch (link_bw_code) {
+ default:
+ WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
+ link_bw_code);
+ case DP_LINK_BW_1_62:
+ return 1;
+ case DP_LINK_BW_2_7:
+ return 2;
+ case DP_LINK_BW_5_4:
+ return 3;
+ }
+}
+
+/* update sink rates from dpcd */
+static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
+{
+ int i, num_rates;
+
+ num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+
+ for (i = 0; i < num_rates; i++)
+ intel_dp->sink_rates[i] = default_rates[i];
+
+ intel_dp->num_sink_rates = num_rates;
+}
+
static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
@@ -205,19 +233,6 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
return max_dotclk;
}
-static int
-intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
-{
- if (intel_dp->num_sink_rates) {
- *sink_rates = intel_dp->sink_rates;
- return intel_dp->num_sink_rates;
- }
-
- *sink_rates = default_rates;
-
- return (intel_dp->max_sink_link_bw >> 3) + 1;
-}
-
static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
@@ -285,15 +300,22 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
static int intel_dp_common_rates(struct intel_dp *intel_dp,
int *common_rates)
{
- const int *sink_rates;
- int sink_len;
+ int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
+ int i, common_len;
- sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
+ common_len = intersect_rates(intel_dp->source_rates,
+ intel_dp->num_source_rates,
+ intel_dp->sink_rates,
+ intel_dp->num_sink_rates,
+ common_rates);
- return intersect_rates(intel_dp->source_rates,
- intel_dp->num_source_rates,
- sink_rates, sink_len,
- common_rates);
+ /* Limit results by potentially reduced max rate */
+ for (i = 0; i < common_len; i++) {
+ if (common_rates[common_len - i - 1] <= max_rate)
+ return common_len - i;
+ }
+
+ return 0;
}
static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
@@ -1501,8 +1523,7 @@ static void snprintf_int_array(char *str, size_t len,
static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
- const int *sink_rates;
- int sink_len, common_len;
+ int common_len;
int common_rates[DP_MAX_SUPPORTED_RATES];
char str[128]; /* FIXME: too big for stack? */
@@ -1513,8 +1534,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
intel_dp->source_rates, intel_dp->num_source_rates);
DRM_DEBUG_KMS("source rates: %s\n", str);
- sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
- snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
+ snprintf_int_array(str, sizeof(str),
+ intel_dp->sink_rates, intel_dp->num_sink_rates);
DRM_DEBUG_KMS("sink rates: %s\n", str);
common_len = intel_dp_common_rates(intel_dp, common_rates);
@@ -1580,7 +1601,8 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
uint8_t *link_bw, uint8_t *rate_select)
{
- if (intel_dp->num_sink_rates) {
+ /* eDP 1.4 rate select method. */
+ if (intel_dp->use_rate_select) {
*link_bw = 0;
*rate_select =
intel_dp_rate_select(intel_dp, port_clock);
@@ -3717,6 +3739,11 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp->num_sink_rates = i;
}
+ if (intel_dp->num_sink_rates)
+ intel_dp->use_rate_select = true;
+ else
+ intel_dp_set_sink_rates(intel_dp);
+
return true;
}
@@ -3727,6 +3754,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
if (!intel_dp_read_dpcd(intel_dp))
return false;
+ intel_dp_set_sink_rates(intel_dp);
+
if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
&intel_dp->sink_count, 1) < 0)
return false;
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0048b520baf7..694ad0ffb523 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -146,7 +146,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
- if (intel_dp->num_sink_rates)
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
&rate_select, 1);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f132d4aea1ad..3a6f092a2ec3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -933,9 +933,10 @@ struct intel_dp {
/* source rates */
int num_source_rates;
const int *source_rates;
- /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
- uint8_t num_sink_rates;
+ /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
+ int num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
+ bool use_rate_select;
/* Max lane count for the sink as per DPCD registers */
uint8_t max_sink_lane_count;
/* Max link BW for the sink as per DPCD registers */
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1½ 06/13] drm/i915/dp: use the sink rates array for max sink rates
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (4 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 07/13] drm/i915/dp: cache common rates with " Jani Nikula
` (8 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Looking at DPCD DP_MAX_LINK_RATE may be completely bogus for eDP 1.4
which is allowed to use link rate select method and have 0 in max link
rate. With this change, it makes sense to store the max rate as the
actual rate rather than as a bw code.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 28 +++++++---------------------
drivers/gpu/drm/i915/intel_drv.h | 2 +-
2 files changed, 8 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d13ce6746542..f163391e61fa 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -161,23 +161,9 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
intel_dp->num_sink_rates = num_rates;
}
-static int
-intel_dp_max_link_bw(struct intel_dp *intel_dp)
+static int intel_dp_max_sink_rate(struct intel_dp *intel_dp)
{
- int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
-
- switch (max_link_bw) {
- case DP_LINK_BW_1_62:
- case DP_LINK_BW_2_7:
- case DP_LINK_BW_5_4:
- break;
- default:
- WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
- max_link_bw);
- max_link_bw = DP_LINK_BW_1_62;
- break;
- }
- return max_link_bw;
+ return intel_dp->sink_rates[intel_dp->num_sink_rates - 1];
}
static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
@@ -300,7 +286,7 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
static int intel_dp_common_rates(struct intel_dp *intel_dp,
int *common_rates)
{
- int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
+ int max_rate = intel_dp->max_sink_link_rate;
int i, common_len;
common_len = intersect_rates(intel_dp->source_rates,
@@ -338,10 +324,10 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
common_rates,
link_rate);
if (link_rate_index > 0) {
- intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
+ intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
intel_dp->max_sink_lane_count = lane_count;
} else if (lane_count > 1) {
- intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
+ intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
intel_dp->max_sink_lane_count = lane_count >> 1;
} else {
DRM_ERROR("Link Training Unsuccessful\n");
@@ -4657,8 +4643,8 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
/* Set the max lane count for sink */
intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
- /* Set the max link BW for sink */
- intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
+ /* Set the max link rate for sink */
+ intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
intel_dp_print_rates(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b914dd543362..ae7259eda420 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -939,7 +939,7 @@ struct intel_dp {
/* Max lane count for the sink as per DPCD registers */
uint8_t max_sink_lane_count;
/* Max link BW for the sink as per DPCD registers */
- int max_sink_link_bw;
+ int max_sink_link_rate;
/* sink or branch descriptor */
struct intel_dp_desc desc;
struct drm_dp_aux aux;
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 07/13] drm/i915/dp: cache common rates with sink rates
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (5 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 06/13] drm/i915/dp: use the sink rates array for max sink rates Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-02-01 22:08 ` Pandiyan, Dhinakaran
2017-01-26 19:44 ` [PATCH v1½ 08/13] drm/i915/dp: do not limit rate seek when not needed Jani Nikula
` (7 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Now that source rates are static and sink rates are updated whenever
DPCD is updated, we can do and cache the intersection of them whenever
sink rates are updated. This reduces code complexity, as we don't have
to keep calling the functions to intersect. We also get rid of several
common rates arrays on stack.
Limiting the common rates by a max link rate can be done by picking the
first N elements of the cached common rates.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++------------------
drivers/gpu/drm/i915/intel_drv.h | 3 ++
2 files changed, 40 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f163391e61fa..7d3ff92000c3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -283,17 +283,29 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
return -1;
}
-static int intel_dp_common_rates(struct intel_dp *intel_dp,
- int *common_rates)
+static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
{
- int max_rate = intel_dp->max_sink_link_rate;
- int i, common_len;
+ WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
- common_len = intersect_rates(intel_dp->source_rates,
- intel_dp->num_source_rates,
- intel_dp->sink_rates,
- intel_dp->num_sink_rates,
- common_rates);
+ intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
+ intel_dp->num_source_rates,
+ intel_dp->sink_rates,
+ intel_dp->num_sink_rates,
+ intel_dp->common_rates);
+
+ /* Paranoia, there should always be something in common. */
+ if (WARN_ON(intel_dp->num_common_rates == 0)) {
+ intel_dp->common_rates[0] = default_rates[0];
+ intel_dp->num_common_rates = 1;
+ }
+}
+
+/* get length of common rates potentially limited by max_rate */
+static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
+ int max_rate)
+{
+ const int *common_rates = intel_dp->common_rates;
+ int i, common_len = intel_dp->num_common_rates;
/* Limit results by potentially reduced max rate */
for (i = 0; i < common_len; i++) {
@@ -304,25 +316,23 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp,
return 0;
}
-static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
- int *common_rates, int link_rate)
+static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int link_rate)
{
int common_len;
- common_len = intel_dp_common_rates(intel_dp, common_rates);
+ common_len = intel_dp_common_len_rate_limit(intel_dp,
+ intel_dp->max_sink_link_rate);
- return intel_dp_find_rate(common_rates, common_len, link_rate);
+ return intel_dp_find_rate(intel_dp->common_rates, common_len, link_rate);
}
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
int link_rate, uint8_t lane_count)
{
- int common_rates[DP_MAX_SUPPORTED_RATES];
+ const int *common_rates = intel_dp->common_rates;
int link_rate_index;
- link_rate_index = intel_dp_link_rate_index(intel_dp,
- common_rates,
- link_rate);
+ link_rate_index = intel_dp_link_rate_index(intel_dp, link_rate);
if (link_rate_index > 0) {
intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
intel_dp->max_sink_lane_count = lane_count;
@@ -1509,8 +1519,6 @@ static void snprintf_int_array(char *str, size_t len,
static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
- int common_len;
- int common_rates[DP_MAX_SUPPORTED_RATES];
char str[128]; /* FIXME: too big for stack? */
if ((drm_debug & DRM_UT_KMS) == 0)
@@ -1524,8 +1532,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
intel_dp->sink_rates, intel_dp->num_sink_rates);
DRM_DEBUG_KMS("sink rates: %s\n", str);
- common_len = intel_dp_common_rates(intel_dp, common_rates);
- snprintf_int_array(str, sizeof(str), common_rates, common_len);
+ snprintf_int_array(str, sizeof(str),
+ intel_dp->common_rates, intel_dp->num_common_rates);
DRM_DEBUG_KMS("common rates: %s\n", str);
}
@@ -1563,14 +1571,14 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
- int rates[DP_MAX_SUPPORTED_RATES] = {};
int len;
- len = intel_dp_common_rates(intel_dp, rates);
+ len = intel_dp_common_len_rate_limit(intel_dp,
+ intel_dp->max_sink_link_rate);
if (WARN_ON(len <= 0))
return 162000;
- return rates[len - 1];
+ return intel_dp->common_rates[len - 1];
}
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
@@ -1639,11 +1647,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
int link_rate_index;
int bpp, mode_rate;
int link_avail, link_clock;
- int common_rates[DP_MAX_SUPPORTED_RATES] = {};
+ const int *common_rates = intel_dp->common_rates;
int common_len;
uint8_t link_bw, rate_select;
- common_len = intel_dp_common_rates(intel_dp, common_rates);
+ common_len = intel_dp_common_len_rate_limit(intel_dp,
+ intel_dp->max_sink_link_rate);
/* No common link rates between source and sink */
WARN_ON(common_len <= 0);
@@ -1681,7 +1690,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
/* Use values requested by Compliance Test Request */
if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
link_rate_index = intel_dp_link_rate_index(intel_dp,
- common_rates,
intel_dp->compliance.test_link_rate);
if (link_rate_index >= 0)
min_clock = max_clock = link_rate_index;
@@ -3724,6 +3732,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
} else {
intel_dp_set_sink_rates(intel_dp);
}
+ intel_dp_set_common_rates(intel_dp);
return true;
}
@@ -3736,6 +3745,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
return false;
intel_dp_set_sink_rates(intel_dp);
+ intel_dp_set_common_rates(intel_dp);
if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
&intel_dp->sink_count, 1) < 0)
@@ -3958,7 +3968,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
int status = 0;
int min_lane_count = 1;
- int common_rates[DP_MAX_SUPPORTED_RATES] = {};
int link_rate_index, test_link_rate;
uint8_t test_lane_count, test_link_bw;
/* (DP CTS 1.2)
@@ -3987,7 +3996,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
/* Validate the requested link rate */
test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
link_rate_index = intel_dp_link_rate_index(intel_dp,
- common_rates,
test_link_rate);
if (link_rate_index < 0)
return DP_TEST_NAK;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ae7259eda420..3578a7dd584a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -936,6 +936,9 @@ struct intel_dp {
/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
int num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
+ /* intersection of source and sink rates */
+ int num_common_rates;
+ int common_rates[DP_MAX_SUPPORTED_RATES];
/* Max lane count for the sink as per DPCD registers */
uint8_t max_sink_lane_count;
/* Max link BW for the sink as per DPCD registers */
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 07/13] drm/i915/dp: cache common rates with sink rates
2017-01-26 19:44 ` [PATCH v1½ 07/13] drm/i915/dp: cache common rates with " Jani Nikula
@ 2017-02-01 22:08 ` Pandiyan, Dhinakaran
2017-02-02 8:38 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-02-01 22:08 UTC (permalink / raw)
To: Nikula, Jani; +Cc: intel-gfx
On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote:
> Now that source rates are static and sink rates are updated whenever
> DPCD is updated, we can do and cache the intersection of them whenever
> sink rates are updated. This reduces code complexity, as we don't have
> to keep calling the functions to intersect. We also get rid of several
> common rates arrays on stack.
>
> Limiting the common rates by a max link rate can be done by picking the
> first N elements of the cached common rates.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_drv.h | 3 ++
> 2 files changed, 40 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f163391e61fa..7d3ff92000c3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -283,17 +283,29 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
> return -1;
> }
>
> -static int intel_dp_common_rates(struct intel_dp *intel_dp,
> - int *common_rates)
> +static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
> {
> - int max_rate = intel_dp->max_sink_link_rate;
> - int i, common_len;
> + WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
>
> - common_len = intersect_rates(intel_dp->source_rates,
> - intel_dp->num_source_rates,
> - intel_dp->sink_rates,
> - intel_dp->num_sink_rates,
> - common_rates);
> + intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
> + intel_dp->num_source_rates,
> + intel_dp->sink_rates,
> + intel_dp->num_sink_rates,
> + intel_dp->common_rates);
Do we need to pass all these args given that all of them are now
available in intel_dp and intersect_rates() is not used anywhere else?
-DK
> +
> + /* Paranoia, there should always be something in common. */
> + if (WARN_ON(intel_dp->num_common_rates == 0)) {
> + intel_dp->common_rates[0] = default_rates[0];
> + intel_dp->num_common_rates = 1;
> + }
> +}
> +
> +/* get length of common rates potentially limited by max_rate */
> +static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
> + int max_rate)
> +{
> + const int *common_rates = intel_dp->common_rates;
> + int i, common_len = intel_dp->num_common_rates;
>
> /* Limit results by potentially reduced max rate */
> for (i = 0; i < common_len; i++) {
> @@ -304,25 +316,23 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp,
> return 0;
> }
>
> -static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
> - int *common_rates, int link_rate)
> +static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int link_rate)
> {
> int common_len;
>
> - common_len = intel_dp_common_rates(intel_dp, common_rates);
> + common_len = intel_dp_common_len_rate_limit(intel_dp,
> + intel_dp->max_sink_link_rate);
>
> - return intel_dp_find_rate(common_rates, common_len, link_rate);
> + return intel_dp_find_rate(intel_dp->common_rates, common_len, link_rate);
> }
>
> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> int link_rate, uint8_t lane_count)
> {
> - int common_rates[DP_MAX_SUPPORTED_RATES];
> + const int *common_rates = intel_dp->common_rates;
> int link_rate_index;
>
> - link_rate_index = intel_dp_link_rate_index(intel_dp,
> - common_rates,
> - link_rate);
> + link_rate_index = intel_dp_link_rate_index(intel_dp, link_rate);
> if (link_rate_index > 0) {
> intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
> intel_dp->max_sink_lane_count = lane_count;
> @@ -1509,8 +1519,6 @@ static void snprintf_int_array(char *str, size_t len,
>
> static void intel_dp_print_rates(struct intel_dp *intel_dp)
> {
> - int common_len;
> - int common_rates[DP_MAX_SUPPORTED_RATES];
> char str[128]; /* FIXME: too big for stack? */
>
> if ((drm_debug & DRM_UT_KMS) == 0)
> @@ -1524,8 +1532,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
> intel_dp->sink_rates, intel_dp->num_sink_rates);
> DRM_DEBUG_KMS("sink rates: %s\n", str);
>
> - common_len = intel_dp_common_rates(intel_dp, common_rates);
> - snprintf_int_array(str, sizeof(str), common_rates, common_len);
> + snprintf_int_array(str, sizeof(str),
> + intel_dp->common_rates, intel_dp->num_common_rates);
> DRM_DEBUG_KMS("common rates: %s\n", str);
> }
>
> @@ -1563,14 +1571,14 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
> int
> intel_dp_max_link_rate(struct intel_dp *intel_dp)
> {
> - int rates[DP_MAX_SUPPORTED_RATES] = {};
> int len;
>
> - len = intel_dp_common_rates(intel_dp, rates);
> + len = intel_dp_common_len_rate_limit(intel_dp,
> + intel_dp->max_sink_link_rate);
> if (WARN_ON(len <= 0))
> return 162000;
>
> - return rates[len - 1];
> + return intel_dp->common_rates[len - 1];
> }
>
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> @@ -1639,11 +1647,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> int link_rate_index;
> int bpp, mode_rate;
> int link_avail, link_clock;
> - int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> + const int *common_rates = intel_dp->common_rates;
> int common_len;
> uint8_t link_bw, rate_select;
>
> - common_len = intel_dp_common_rates(intel_dp, common_rates);
> + common_len = intel_dp_common_len_rate_limit(intel_dp,
> + intel_dp->max_sink_link_rate);
>
> /* No common link rates between source and sink */
> WARN_ON(common_len <= 0);
> @@ -1681,7 +1690,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> /* Use values requested by Compliance Test Request */
> if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> link_rate_index = intel_dp_link_rate_index(intel_dp,
> - common_rates,
> intel_dp->compliance.test_link_rate);
> if (link_rate_index >= 0)
> min_clock = max_clock = link_rate_index;
> @@ -3724,6 +3732,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> } else {
> intel_dp_set_sink_rates(intel_dp);
> }
> + intel_dp_set_common_rates(intel_dp);
>
> return true;
> }
> @@ -3736,6 +3745,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> return false;
>
> intel_dp_set_sink_rates(intel_dp);
> + intel_dp_set_common_rates(intel_dp);
>
> if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
> &intel_dp->sink_count, 1) < 0)
> @@ -3958,7 +3968,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> {
> int status = 0;
> int min_lane_count = 1;
> - int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> int link_rate_index, test_link_rate;
> uint8_t test_lane_count, test_link_bw;
> /* (DP CTS 1.2)
> @@ -3987,7 +3996,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> /* Validate the requested link rate */
> test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
> link_rate_index = intel_dp_link_rate_index(intel_dp,
> - common_rates,
> test_link_rate);
> if (link_rate_index < 0)
> return DP_TEST_NAK;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ae7259eda420..3578a7dd584a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -936,6 +936,9 @@ struct intel_dp {
> /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
> int num_sink_rates;
> int sink_rates[DP_MAX_SUPPORTED_RATES];
> + /* intersection of source and sink rates */
> + int num_common_rates;
> + int common_rates[DP_MAX_SUPPORTED_RATES];
> /* Max lane count for the sink as per DPCD registers */
> uint8_t max_sink_lane_count;
> /* Max link BW for the sink as per DPCD registers */
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 07/13] drm/i915/dp: cache common rates with sink rates
2017-02-01 22:08 ` Pandiyan, Dhinakaran
@ 2017-02-02 8:38 ` Jani Nikula
0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-02-02 8:38 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx
On Thu, 02 Feb 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote:
>> Now that source rates are static and sink rates are updated whenever
>> DPCD is updated, we can do and cache the intersection of them whenever
>> sink rates are updated. This reduces code complexity, as we don't have
>> to keep calling the functions to intersect. We also get rid of several
>> common rates arrays on stack.
>>
>> Limiting the common rates by a max link rate can be done by picking the
>> first N elements of the cached common rates.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++------------------
>> drivers/gpu/drm/i915/intel_drv.h | 3 ++
>> 2 files changed, 40 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index f163391e61fa..7d3ff92000c3 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -283,17 +283,29 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
>> return -1;
>> }
>>
>> -static int intel_dp_common_rates(struct intel_dp *intel_dp,
>> - int *common_rates)
>> +static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
>> {
>> - int max_rate = intel_dp->max_sink_link_rate;
>> - int i, common_len;
>> + WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
>>
>> - common_len = intersect_rates(intel_dp->source_rates,
>> - intel_dp->num_source_rates,
>> - intel_dp->sink_rates,
>> - intel_dp->num_sink_rates,
>> - common_rates);
>> + intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
>> + intel_dp->num_source_rates,
>> + intel_dp->sink_rates,
>> + intel_dp->num_sink_rates,
>> + intel_dp->common_rates);
>
>
> Do we need to pass all these args given that all of them are now
> available in intel_dp and intersect_rates() is not used anywhere else?
My reasoning is that with this interface intersect_rates remains
generic, independent of intel_dp or anything else, and you can be sure
it's stateless.
BR,
Jani.
>
> -DK
>> +
>> + /* Paranoia, there should always be something in common. */
>> + if (WARN_ON(intel_dp->num_common_rates == 0)) {
>> + intel_dp->common_rates[0] = default_rates[0];
>> + intel_dp->num_common_rates = 1;
>> + }
>> +}
>> +
>> +/* get length of common rates potentially limited by max_rate */
>> +static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
>> + int max_rate)
>> +{
>> + const int *common_rates = intel_dp->common_rates;
>> + int i, common_len = intel_dp->num_common_rates;
>>
>> /* Limit results by potentially reduced max rate */
>> for (i = 0; i < common_len; i++) {
>> @@ -304,25 +316,23 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp,
>> return 0;
>> }
>>
>> -static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
>> - int *common_rates, int link_rate)
>> +static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int link_rate)
>> {
>> int common_len;
>>
>> - common_len = intel_dp_common_rates(intel_dp, common_rates);
>> + common_len = intel_dp_common_len_rate_limit(intel_dp,
>> + intel_dp->max_sink_link_rate);
>>
>> - return intel_dp_find_rate(common_rates, common_len, link_rate);
>> + return intel_dp_find_rate(intel_dp->common_rates, common_len, link_rate);
>> }
>>
>> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>> int link_rate, uint8_t lane_count)
>> {
>> - int common_rates[DP_MAX_SUPPORTED_RATES];
>> + const int *common_rates = intel_dp->common_rates;
>> int link_rate_index;
>>
>> - link_rate_index = intel_dp_link_rate_index(intel_dp,
>> - common_rates,
>> - link_rate);
>> + link_rate_index = intel_dp_link_rate_index(intel_dp, link_rate);
>> if (link_rate_index > 0) {
>> intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
>> intel_dp->max_sink_lane_count = lane_count;
>> @@ -1509,8 +1519,6 @@ static void snprintf_int_array(char *str, size_t len,
>>
>> static void intel_dp_print_rates(struct intel_dp *intel_dp)
>> {
>> - int common_len;
>> - int common_rates[DP_MAX_SUPPORTED_RATES];
>> char str[128]; /* FIXME: too big for stack? */
>>
>> if ((drm_debug & DRM_UT_KMS) == 0)
>> @@ -1524,8 +1532,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
>> intel_dp->sink_rates, intel_dp->num_sink_rates);
>> DRM_DEBUG_KMS("sink rates: %s\n", str);
>>
>> - common_len = intel_dp_common_rates(intel_dp, common_rates);
>> - snprintf_int_array(str, sizeof(str), common_rates, common_len);
>> + snprintf_int_array(str, sizeof(str),
>> + intel_dp->common_rates, intel_dp->num_common_rates);
>> DRM_DEBUG_KMS("common rates: %s\n", str);
>> }
>>
>> @@ -1563,14 +1571,14 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
>> int
>> intel_dp_max_link_rate(struct intel_dp *intel_dp)
>> {
>> - int rates[DP_MAX_SUPPORTED_RATES] = {};
>> int len;
>>
>> - len = intel_dp_common_rates(intel_dp, rates);
>> + len = intel_dp_common_len_rate_limit(intel_dp,
>> + intel_dp->max_sink_link_rate);
>> if (WARN_ON(len <= 0))
>> return 162000;
>>
>> - return rates[len - 1];
>> + return intel_dp->common_rates[len - 1];
>> }
>>
>> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
>> @@ -1639,11 +1647,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> int link_rate_index;
>> int bpp, mode_rate;
>> int link_avail, link_clock;
>> - int common_rates[DP_MAX_SUPPORTED_RATES] = {};
>> + const int *common_rates = intel_dp->common_rates;
>> int common_len;
>> uint8_t link_bw, rate_select;
>>
>> - common_len = intel_dp_common_rates(intel_dp, common_rates);
>> + common_len = intel_dp_common_len_rate_limit(intel_dp,
>> + intel_dp->max_sink_link_rate);
>>
>> /* No common link rates between source and sink */
>> WARN_ON(common_len <= 0);
>> @@ -1681,7 +1690,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> /* Use values requested by Compliance Test Request */
>> if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
>> link_rate_index = intel_dp_link_rate_index(intel_dp,
>> - common_rates,
>> intel_dp->compliance.test_link_rate);
>> if (link_rate_index >= 0)
>> min_clock = max_clock = link_rate_index;
>> @@ -3724,6 +3732,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>> } else {
>> intel_dp_set_sink_rates(intel_dp);
>> }
>> + intel_dp_set_common_rates(intel_dp);
>>
>> return true;
>> }
>> @@ -3736,6 +3745,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>> return false;
>>
>> intel_dp_set_sink_rates(intel_dp);
>> + intel_dp_set_common_rates(intel_dp);
>>
>> if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
>> &intel_dp->sink_count, 1) < 0)
>> @@ -3958,7 +3968,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
>> {
>> int status = 0;
>> int min_lane_count = 1;
>> - int common_rates[DP_MAX_SUPPORTED_RATES] = {};
>> int link_rate_index, test_link_rate;
>> uint8_t test_lane_count, test_link_bw;
>> /* (DP CTS 1.2)
>> @@ -3987,7 +3996,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
>> /* Validate the requested link rate */
>> test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
>> link_rate_index = intel_dp_link_rate_index(intel_dp,
>> - common_rates,
>> test_link_rate);
>> if (link_rate_index < 0)
>> return DP_TEST_NAK;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index ae7259eda420..3578a7dd584a 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -936,6 +936,9 @@ struct intel_dp {
>> /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
>> int num_sink_rates;
>> int sink_rates[DP_MAX_SUPPORTED_RATES];
>> + /* intersection of source and sink rates */
>> + int num_common_rates;
>> + int common_rates[DP_MAX_SUPPORTED_RATES];
>> /* Max lane count for the sink as per DPCD registers */
>> uint8_t max_sink_lane_count;
>> /* Max link BW for the sink as per DPCD registers */
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v1½ 08/13] drm/i915/dp: do not limit rate seek when not needed
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (6 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 07/13] drm/i915/dp: cache common rates with " Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 09/13] drm/i915/dp: don't call the link parameters sink parameters Jani Nikula
` (6 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In link training fallback, we're trying to find a rate that we know is
in a sorted array of common link rates. We don't need to limit the array
using the max rate. For test request, the DP CTS doesn't say we should
limit the rate based on earlier fallback.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 31 ++++++++++++-------------------
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7d3ff92000c3..6404455a0ab5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -316,25 +316,16 @@ static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
return 0;
}
-static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int link_rate)
-{
- int common_len;
-
- common_len = intel_dp_common_len_rate_limit(intel_dp,
- intel_dp->max_sink_link_rate);
-
- return intel_dp_find_rate(intel_dp->common_rates, common_len, link_rate);
-}
-
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
int link_rate, uint8_t lane_count)
{
- const int *common_rates = intel_dp->common_rates;
- int link_rate_index;
+ int index;
- link_rate_index = intel_dp_link_rate_index(intel_dp, link_rate);
- if (link_rate_index > 0) {
- intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
+ index = intel_dp_find_rate(intel_dp->common_rates,
+ intel_dp->num_common_rates,
+ link_rate);
+ if (index > 0) {
+ intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1];
intel_dp->max_sink_lane_count = lane_count;
} else if (lane_count > 1) {
intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
@@ -1689,8 +1680,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
/* Use values requested by Compliance Test Request */
if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
- link_rate_index = intel_dp_link_rate_index(intel_dp,
- intel_dp->compliance.test_link_rate);
+ link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
+ intel_dp->num_common_rates,
+ intel_dp->compliance.test_link_rate);
if (link_rate_index >= 0)
min_clock = max_clock = link_rate_index;
min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
@@ -3995,8 +3987,9 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
}
/* Validate the requested link rate */
test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
- link_rate_index = intel_dp_link_rate_index(intel_dp,
- test_link_rate);
+ link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
+ intel_dp->num_common_rates,
+ test_link_rate);
if (link_rate_index < 0)
return DP_TEST_NAK;
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 09/13] drm/i915/dp: don't call the link parameters sink parameters
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (7 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 08/13] drm/i915/dp: do not limit rate seek when not needed Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 10/13] drm/i915/dp: add functions for max common link rate and lane count Jani Nikula
` (5 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
If we modify these on the fly depending on the link conditions, don't
pretend they are sink properties.
Some link vs. sink confusion still remains, but we'll take care of them
in follow-up patches.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 25 ++++++++++++-------------
drivers/gpu/drm/i915/intel_drv.h | 8 ++++----
2 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6404455a0ab5..af99d0926ca5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -172,7 +172,7 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
u8 source_max, sink_max;
source_max = intel_dig_port->max_lanes;
- sink_max = intel_dp->max_sink_lane_count;
+ sink_max = intel_dp->max_link_lane_count;
return min(source_max, sink_max);
}
@@ -325,11 +325,11 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
intel_dp->num_common_rates,
link_rate);
if (index > 0) {
- intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1];
- intel_dp->max_sink_lane_count = lane_count;
+ intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
+ intel_dp->max_link_lane_count = lane_count;
} else if (lane_count > 1) {
- intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
- intel_dp->max_sink_lane_count = lane_count >> 1;
+ intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
+ intel_dp->max_link_lane_count = lane_count >> 1;
} else {
DRM_ERROR("Link Training Unsuccessful\n");
return -1;
@@ -1564,8 +1564,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
int len;
- len = intel_dp_common_len_rate_limit(intel_dp,
- intel_dp->max_sink_link_rate);
+ len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
if (WARN_ON(len <= 0))
return 162000;
@@ -1643,7 +1642,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
uint8_t link_bw, rate_select;
common_len = intel_dp_common_len_rate_limit(intel_dp,
- intel_dp->max_sink_link_rate);
+ intel_dp->max_link_rate);
/* No common link rates between source and sink */
WARN_ON(common_len <= 0);
@@ -3976,7 +3975,7 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
test_lane_count &= DP_MAX_LANE_COUNT_MASK;
/* Validate the requested lane count */
if (test_lane_count < min_lane_count ||
- test_lane_count > intel_dp->max_sink_lane_count)
+ test_lane_count > intel_dp->max_link_lane_count)
return DP_TEST_NAK;
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
@@ -4641,11 +4640,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
yesno(intel_dp_source_supports_hbr2(intel_dp)),
yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
- /* Set the max lane count for sink */
- intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ /* Set the max lane count for link */
+ intel_dp->max_link_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
- /* Set the max link rate for sink */
- intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
+ /* Set the max link rate for link */
+ intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
intel_dp_print_rates(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3578a7dd584a..04868046c84f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -939,10 +939,10 @@ struct intel_dp {
/* intersection of source and sink rates */
int num_common_rates;
int common_rates[DP_MAX_SUPPORTED_RATES];
- /* Max lane count for the sink as per DPCD registers */
- uint8_t max_sink_lane_count;
- /* Max link BW for the sink as per DPCD registers */
- int max_sink_link_rate;
+ /* Max lane count for the current link */
+ int max_link_lane_count;
+ /* Max rate for the current link */
+ int max_link_rate;
/* sink or branch descriptor */
struct intel_dp_desc desc;
struct drm_dp_aux aux;
--
2.1.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 10/13] drm/i915/dp: add functions for max common link rate and lane count
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (8 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 09/13] drm/i915/dp: don't call the link parameters sink parameters Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 11/13] drm/i915/mst: use max link not sink " Jani Nikula
` (4 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
These are the theoretical maximums common for source and sink. These are
the maximums we should start with. They may be degraded in case of link
training failures, and the dynamic link values are stored separately.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index af99d0926ca5..84b8123a26d3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -161,22 +161,27 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
intel_dp->num_sink_rates = num_rates;
}
-static int intel_dp_max_sink_rate(struct intel_dp *intel_dp)
+/* Theoretical max between source and sink */
+static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
{
- return intel_dp->sink_rates[intel_dp->num_sink_rates - 1];
+ return intel_dp->common_rates[intel_dp->num_common_rates - 1];
}
-static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+/* Theoretical max between source and sink */
+static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- u8 source_max, sink_max;
-
- source_max = intel_dig_port->max_lanes;
- sink_max = intel_dp->max_link_lane_count;
+ int source_max = intel_dig_port->max_lanes;
+ int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
return min(source_max, sink_max);
}
+static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
+ return intel_dp->max_link_lane_count;
+}
+
int
intel_dp_link_required(int pixel_clock, int bpp)
{
@@ -328,7 +333,7 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
intel_dp->max_link_lane_count = lane_count;
} else if (lane_count > 1) {
- intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
+ intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->max_link_lane_count = lane_count >> 1;
} else {
DRM_ERROR("Link Training Unsuccessful\n");
@@ -4640,11 +4645,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
yesno(intel_dp_source_supports_hbr2(intel_dp)),
yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
- /* Set the max lane count for link */
- intel_dp->max_link_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ /* Initial max link lane count */
+ intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
- /* Set the max link rate for link */
- intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
+ /* Initial max link rate */
+ intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
intel_dp_print_rates(intel_dp);
--
2.1.4
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 11/13] drm/i915/mst: use max link not sink lane count
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (9 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 10/13] drm/i915/dp: add functions for max common link rate and lane count Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-01-26 19:44 ` [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more Jani Nikula
` (3 subsequent siblings)
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dhinakaran Pandiyan
The source might not support as many lanes as the sink, or the link
training might have failed at higher lane counts. Take these into
account.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 84b8123a26d3..7704d32286a3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -177,7 +177,7 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
return min(source_max, sink_max);
}
-static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
+int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
return intel_dp->max_link_lane_count;
}
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 95267fcef71b..dfdc32e11b44 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -56,7 +56,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
* for MST we always configure max link bw - the spec doesn't
* seem to suggest we should do otherwise.
*/
- lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ lane_count = intel_dp_max_lane_count(intel_dp);
pipe_config->lane_count = lane_count;
@@ -362,7 +362,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
int max_rate, mode_rate, max_lanes, max_link_clock;
max_link_clock = intel_dp_max_link_rate(intel_dp);
- max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+ max_lanes = intel_dp_max_lane_count(intel_dp);
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(mode->clock, bpp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 04868046c84f..ea07212e3154 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1467,6 +1467,7 @@ void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *co
void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev);
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
+int intel_dp_max_lane_count(struct intel_dp *intel_dp);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (10 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 11/13] drm/i915/mst: use max link not sink " Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-02-02 2:54 ` Manasi Navare
2017-01-26 19:44 ` [PATCH v1½ 13/13] drm/i915/dp: use readb and writeb calls for single byte DPCD access Jani Nikula
` (2 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Localize link_rate_index to the if block, and rename to just index to
reduce indent.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7704d32286a3..429dc70c251a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1639,7 +1639,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
/* Conveniently, the link BW constants become indices with a shift...*/
int min_clock = 0;
int max_clock;
- int link_rate_index;
int bpp, mode_rate;
int link_avail, link_clock;
const int *common_rates = intel_dp->common_rates;
@@ -1684,11 +1683,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
/* Use values requested by Compliance Test Request */
if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
- link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
- intel_dp->num_common_rates,
- intel_dp->compliance.test_link_rate);
- if (link_rate_index >= 0)
- min_clock = max_clock = link_rate_index;
+ int index;
+
+ index = intel_dp_find_rate(intel_dp->common_rates,
+ intel_dp->num_common_rates,
+ intel_dp->compliance.test_link_rate);
+ if (index >= 0)
+ min_clock = max_clock = index;
min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
}
DRM_DEBUG_KMS("DP link computation with max lane count %i "
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more
2017-01-26 19:44 ` [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more Jani Nikula
@ 2017-02-02 2:54 ` Manasi Navare
2017-02-02 8:42 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2017-02-02 2:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Jan 26, 2017 at 09:44:26PM +0200, Jani Nikula wrote:
> Localize link_rate_index to the if block, and rename to just index to
> reduce indent.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7704d32286a3..429dc70c251a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1639,7 +1639,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> /* Conveniently, the link BW constants become indices with a shift...*/
> int min_clock = 0;
> int max_clock;
> - int link_rate_index;
> int bpp, mode_rate;
> int link_avail, link_clock;
> const int *common_rates = intel_dp->common_rates;
> @@ -1684,11 +1683,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>
> /* Use values requested by Compliance Test Request */
> if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> - link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
> - intel_dp->num_common_rates,
> - intel_dp->compliance.test_link_rate);
Can we not pass just the common_rates as an argument to this function
since common_rates is already assigned intel_dp->common_rates.
Regards
Manasi
> - if (link_rate_index >= 0)
> - min_clock = max_clock = link_rate_index;
> + int index;
> +
> + index = intel_dp_find_rate(intel_dp->common_rates,
> + intel_dp->num_common_rates,
> + intel_dp->compliance.test_link_rate);
> + if (index >= 0)
> + min_clock = max_clock = index;
> min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
> }
> DRM_DEBUG_KMS("DP link computation with max lane count %i "
> --
> 2.1.4
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more
2017-02-02 2:54 ` Manasi Navare
@ 2017-02-02 8:42 ` Jani Nikula
2017-02-02 17:29 ` Manasi Navare
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2017-02-02 8:42 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, 02 Feb 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Thu, Jan 26, 2017 at 09:44:26PM +0200, Jani Nikula wrote:
>> Localize link_rate_index to the if block, and rename to just index to
>> reduce indent.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
>> 1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 7704d32286a3..429dc70c251a 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1639,7 +1639,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> /* Conveniently, the link BW constants become indices with a shift...*/
>> int min_clock = 0;
>> int max_clock;
>> - int link_rate_index;
>> int bpp, mode_rate;
>> int link_avail, link_clock;
>> const int *common_rates = intel_dp->common_rates;
>> @@ -1684,11 +1683,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>
>> /* Use values requested by Compliance Test Request */
>> if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
>> - link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
>> - intel_dp->num_common_rates,
>> - intel_dp->compliance.test_link_rate);
>
> Can we not pass just the common_rates as an argument to this function
> since common_rates is already assigned intel_dp->common_rates.
Do you mean just pass intel_dp to intel_dp_find_rate? If yes, I think
this keeps intel_dp_find_rate generic, independent of intel_dp or
anything else, and you can be sure it's stateless (same as
intersect_rates).
If you don't mean that, I don't know what you mean... please explain.
BR,
Jani.
>
> Regards
> Manasi
>
>
>> - if (link_rate_index >= 0)
>> - min_clock = max_clock = link_rate_index;
>> + int index;
>> +
>> + index = intel_dp_find_rate(intel_dp->common_rates,
>> + intel_dp->num_common_rates,
>> + intel_dp->compliance.test_link_rate);
>> + if (index >= 0)
>> + min_clock = max_clock = index;
>> min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
>> }
>> DRM_DEBUG_KMS("DP link computation with max lane count %i "
>> --
>> 2.1.4
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more
2017-02-02 8:42 ` Jani Nikula
@ 2017-02-02 17:29 ` Manasi Navare
2017-02-03 14:11 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2017-02-02 17:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 02, 2017 at 10:42:48AM +0200, Jani Nikula wrote:
> On Thu, 02 Feb 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > On Thu, Jan 26, 2017 at 09:44:26PM +0200, Jani Nikula wrote:
> >> Localize link_rate_index to the if block, and rename to just index to
> >> reduce indent.
> >>
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
> >> 1 file changed, 7 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> index 7704d32286a3..429dc70c251a 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -1639,7 +1639,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >> /* Conveniently, the link BW constants become indices with a shift...*/
> >> int min_clock = 0;
> >> int max_clock;
> >> - int link_rate_index;
> >> int bpp, mode_rate;
> >> int link_avail, link_clock;
> >> const int *common_rates = intel_dp->common_rates;
> >> @@ -1684,11 +1683,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >>
> >> /* Use values requested by Compliance Test Request */
> >> if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> >> - link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
> >> - intel_dp->num_common_rates,
> >> - intel_dp->compliance.test_link_rate);
> >
> > Can we not pass just the common_rates as an argument to this function
> > since common_rates is already assigned intel_dp->common_rates.
>
> Do you mean just pass intel_dp to intel_dp_find_rate? If yes, I think
> this keeps intel_dp_find_rate generic, independent of intel_dp or
> anything else, and you can be sure it's stateless (same as
> intersect_rates).
>
> If you don't mean that, I don't know what you mean... please explain.
>
> BR,
> Jani.
>
>
I agree that it needs to be stateless and hence we dont pass intel_dp directly.
What I was saying was that at the beginning of the function we do initialize
common_rates = intel_dp->common_rates;
so why cant we pass just common_rates to this function instead of intel_dp->common_rates?
Not sure if this optimization will make any big impact but just a thought.
Regards
Manasi
> >
> > Regards
> > Manasi
> >
> >
> >> - if (link_rate_index >= 0)
> >> - min_clock = max_clock = link_rate_index;
> >> + int index;
> >> +
> >> + index = intel_dp_find_rate(intel_dp->common_rates,
> >> + intel_dp->num_common_rates,
> >> + intel_dp->compliance.test_link_rate);
> >> + if (index >= 0)
> >> + min_clock = max_clock = index;
> >> min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
> >> }
> >> DRM_DEBUG_KMS("DP link computation with max lane count %i "
> >> --
> >> 2.1.4
> >>
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more
2017-02-02 17:29 ` Manasi Navare
@ 2017-02-03 14:11 ` Jani Nikula
0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-02-03 14:11 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, 02 Feb 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Thu, Feb 02, 2017 at 10:42:48AM +0200, Jani Nikula wrote:
>> On Thu, 02 Feb 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
>> > On Thu, Jan 26, 2017 at 09:44:26PM +0200, Jani Nikula wrote:
>> >> Localize link_rate_index to the if block, and rename to just index to
>> >> reduce indent.
>> >>
>> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
>> >> 1 file changed, 7 insertions(+), 6 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> >> index 7704d32286a3..429dc70c251a 100644
>> >> --- a/drivers/gpu/drm/i915/intel_dp.c
>> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> >> @@ -1639,7 +1639,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> >> /* Conveniently, the link BW constants become indices with a shift...*/
>> >> int min_clock = 0;
>> >> int max_clock;
>> >> - int link_rate_index;
>> >> int bpp, mode_rate;
>> >> int link_avail, link_clock;
>> >> const int *common_rates = intel_dp->common_rates;
>> >> @@ -1684,11 +1683,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> >>
>> >> /* Use values requested by Compliance Test Request */
>> >> if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
>> >> - link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
>> >> - intel_dp->num_common_rates,
>> >> - intel_dp->compliance.test_link_rate);
>> >
>> > Can we not pass just the common_rates as an argument to this function
>> > since common_rates is already assigned intel_dp->common_rates.
>>
>> Do you mean just pass intel_dp to intel_dp_find_rate? If yes, I think
>> this keeps intel_dp_find_rate generic, independent of intel_dp or
>> anything else, and you can be sure it's stateless (same as
>> intersect_rates).
>>
>> If you don't mean that, I don't know what you mean... please explain.
>>
>> BR,
>> Jani.
>>
>>
>
> I agree that it needs to be stateless and hence we dont pass intel_dp directly.
> What I was saying was that at the beginning of the function we do initialize
> common_rates = intel_dp->common_rates;
> so why cant we pass just common_rates to this function instead of intel_dp->common_rates?
> Not sure if this optimization will make any big impact but just a thought.
Due to the function already being so big and having so many local
variables, I ended up throwing the local common_rates away altogether,
and changing everything in the function to use intel_dp->common_rates.
BR,
Jani.
>
> Regards
> Manasi
>> >
>> > Regards
>> > Manasi
>> >
>> >
>> >> - if (link_rate_index >= 0)
>> >> - min_clock = max_clock = link_rate_index;
>> >> + int index;
>> >> +
>> >> + index = intel_dp_find_rate(intel_dp->common_rates,
>> >> + intel_dp->num_common_rates,
>> >> + intel_dp->compliance.test_link_rate);
>> >> + if (index >= 0)
>> >> + min_clock = max_clock = index;
>> >> min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
>> >> }
>> >> DRM_DEBUG_KMS("DP link computation with max lane count %i "
>> >> --
>> >> 2.1.4
>> >>
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v1½ 13/13] drm/i915/dp: use readb and writeb calls for single byte DPCD access
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (11 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more Jani Nikula
@ 2017-01-26 19:44 ` Jani Nikula
2017-02-01 19:04 ` [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Pandiyan, Dhinakaran
2017-02-01 19:40 ` Manasi Navare
14 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-01-26 19:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This is what we have the readb and writeb variants for. Do some minor
return value and variable cleanup while at it.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++--------------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 429dc70c251a..62e8ba12ff8a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3675,9 +3675,9 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
uint8_t frame_sync_cap;
dev_priv->psr.sink_support = true;
- drm_dp_dpcd_read(&intel_dp->aux,
- DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
- &frame_sync_cap, 1);
+ drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
+ &frame_sync_cap);
dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
/* PSR2 needs frame sync as well */
dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
@@ -3744,8 +3744,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
intel_dp_set_sink_rates(intel_dp);
intel_dp_set_common_rates(intel_dp);
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
- &intel_dp->sink_count, 1) < 0)
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT,
+ &intel_dp->sink_count) <= 0)
return false;
/*
@@ -3782,7 +3782,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
static bool
intel_dp_can_mst(struct intel_dp *intel_dp)
{
- u8 buf[1];
+ u8 mstm_cap;
if (!i915.enable_dp_mst)
return false;
@@ -3793,10 +3793,10 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
return false;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
return false;
- return buf[0] & DP_MST_CAP;
+ return mstm_cap & DP_MST_CAP;
}
static void
@@ -3942,9 +3942,8 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
- return drm_dp_dpcd_read(&intel_dp->aux,
- DP_DEVICE_SERVICE_IRQ_VECTOR,
- sink_irq_vector, 1) == 1;
+ return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
+ sink_irq_vector) == 1;
}
static bool
@@ -4007,13 +4006,13 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
uint8_t test_pattern;
- uint16_t test_misc;
+ uint8_t test_misc;
__be16 h_width, v_height;
int status = 0;
/* Read the TEST_PATTERN (DP CTS 3.1.5) */
- status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
- &test_pattern, 1);
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
+ &test_pattern);
if (status <= 0) {
DRM_DEBUG_KMS("Test pattern read failed\n");
return DP_TEST_NAK;
@@ -4035,8 +4034,8 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
return DP_TEST_NAK;
}
- status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0,
- &test_misc, 1);
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
+ &test_misc);
if (status <= 0) {
DRM_DEBUG_KMS("TEST MISC read failed\n");
return DP_TEST_NAK;
@@ -4095,10 +4094,8 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
*/
block += intel_connector->detect_edid->extensions;
- if (!drm_dp_dpcd_write(&intel_dp->aux,
- DP_TEST_EDID_CHECKSUM,
- &block->checksum,
- 1))
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
+ block->checksum) <= 0)
DRM_DEBUG_KMS("Failed to write EDID checksum\n");
test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (12 preceding siblings ...)
2017-01-26 19:44 ` [PATCH v1½ 13/13] drm/i915/dp: use readb and writeb calls for single byte DPCD access Jani Nikula
@ 2017-02-01 19:04 ` Pandiyan, Dhinakaran
2017-02-01 19:40 ` Manasi Navare
14 siblings, 0 replies; 31+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-02-01 19:04 UTC (permalink / raw)
To: Nikula, Jani; +Cc: intel-gfx
On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote:
> This is kind of version 1½ of [1], basically just rebased on current git
Looks like this version didn't make it into patchwork.
-DK
> (including Manasi's test automation patches) and a couple of more
> cleanups slammed on top.
>
> BR,
> Jani.
>
>
> [1] http://mid.mail-archive.com/cover.1485015599.git.jani.nikula@intel.com
>
>
> Jani Nikula (13):
> drm/i915/dp: use known correct array size in rate_to_index
> drm/i915/dp: return errors from rate_to_index()
> drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
> drm/i915/dp: cache source rates at init
> drm/i915/dp: generate and cache sink rate array for all DP, not just
> eDP 1.4
> drm/i915/dp: use the sink rates array for max sink rates
> drm/i915/dp: cache common rates with sink rates
> drm/i915/dp: do not limit rate seek when not needed
> drm/i915/dp: don't call the link parameters sink parameters
> drm/i915/dp: add functions for max common link rate and lane count
> drm/i915/mst: use max link not sink lane count
> drm/i915/dp: localize link rate index variable more
> drm/i915/dp: use readb and writeb calls for single byte DPCD access
>
> drivers/gpu/drm/i915/intel_dp.c | 275 ++++++++++++++------------
> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
> drivers/gpu/drm/i915/intel_dp_mst.c | 4 +-
> drivers/gpu/drm/i915/intel_drv.h | 19 +-
> 4 files changed, 166 insertions(+), 135 deletions(-)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring
2017-01-26 19:44 [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
` (13 preceding siblings ...)
2017-02-01 19:04 ` [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring Pandiyan, Dhinakaran
@ 2017-02-01 19:40 ` Manasi Navare
2017-02-02 19:01 ` Manasi Navare
14 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2017-02-01 19:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
Are you planning on submitting a v2 for these pretty soon
that can make it to patchwork/
Regards
Manasi
On Thu, Jan 26, 2017 at 09:44:14PM +0200, Jani Nikula wrote:
> This is kind of version 1½ of [1], basically just rebased on current git
> (including Manasi's test automation patches) and a couple of more
> cleanups slammed on top.
>
> BR,
> Jani.
>
>
> [1] http://mid.mail-archive.com/cover.1485015599.git.jani.nikula@intel.com
>
>
> Jani Nikula (13):
> drm/i915/dp: use known correct array size in rate_to_index
> drm/i915/dp: return errors from rate_to_index()
> drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
> drm/i915/dp: cache source rates at init
> drm/i915/dp: generate and cache sink rate array for all DP, not just
> eDP 1.4
> drm/i915/dp: use the sink rates array for max sink rates
> drm/i915/dp: cache common rates with sink rates
> drm/i915/dp: do not limit rate seek when not needed
> drm/i915/dp: don't call the link parameters sink parameters
> drm/i915/dp: add functions for max common link rate and lane count
> drm/i915/mst: use max link not sink lane count
> drm/i915/dp: localize link rate index variable more
> drm/i915/dp: use readb and writeb calls for single byte DPCD access
>
> drivers/gpu/drm/i915/intel_dp.c | 275 ++++++++++++++------------
> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
> drivers/gpu/drm/i915/intel_dp_mst.c | 4 +-
> drivers/gpu/drm/i915/intel_drv.h | 19 +-
> 4 files changed, 166 insertions(+), 135 deletions(-)
>
> --
> 2.1.4
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring
2017-02-01 19:40 ` Manasi Navare
@ 2017-02-02 19:01 ` Manasi Navare
2017-02-03 14:16 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2017-02-02 19:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 01, 2017 at 11:40:06AM -0800, Manasi Navare wrote:
> Are you planning on submitting a v2 for these pretty soon
> that can make it to patchwork/
>
> Regards
> Manasi
>
> On Thu, Jan 26, 2017 at 09:44:14PM +0200, Jani Nikula wrote:
> > This is kind of version 1½ of [1], basically just rebased on current git
> > (including Manasi's test automation patches) and a couple of more
> > cleanups slammed on top.
> >
> > BR,
> > Jani.
> >
So the problem we still have with link rate fallback after link failure->uevent->
fetch new modes->link retrain is that after we send a uevent, userspace fetches new modes
which calls drm_helper_probe_single_connector_modes() that calls dp_detect which ends up
calling intel_dp_long_pulse(). So while userspace is just trying to fetch new modes
it overwrites the max_link_rate and max_lane_count values through intel_dp_long_pulse().
So while retraining, when it calls intel_dp_compute_config(), it will use the overwritten
values of common_rates/max_link_rate/max_lane_count as opposed to the ones
set in intel_dp_get_fallback_values().
I wonder if this patch series solves this problem somehow...
else, do you have any insight on how we can solve this?
Regards
Manasi
> >
> > [1] http://mid.mail-archive.com/cover.1485015599.git.jani.nikula@intel.com
> >
> >
> > Jani Nikula (13):
> > drm/i915/dp: use known correct array size in rate_to_index
> > drm/i915/dp: return errors from rate_to_index()
> > drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
> > drm/i915/dp: cache source rates at init
> > drm/i915/dp: generate and cache sink rate array for all DP, not just
> > eDP 1.4
> > drm/i915/dp: use the sink rates array for max sink rates
> > drm/i915/dp: cache common rates with sink rates
> > drm/i915/dp: do not limit rate seek when not needed
> > drm/i915/dp: don't call the link parameters sink parameters
> > drm/i915/dp: add functions for max common link rate and lane count
> > drm/i915/mst: use max link not sink lane count
> > drm/i915/dp: localize link rate index variable more
> > drm/i915/dp: use readb and writeb calls for single byte DPCD access
> >
> > drivers/gpu/drm/i915/intel_dp.c | 275 ++++++++++++++------------
> > drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
> > drivers/gpu/drm/i915/intel_dp_mst.c | 4 +-
> > drivers/gpu/drm/i915/intel_drv.h | 19 +-
> > 4 files changed, 166 insertions(+), 135 deletions(-)
> >
> > --
> > 2.1.4
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring
2017-02-02 19:01 ` Manasi Navare
@ 2017-02-03 14:16 ` Jani Nikula
0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2017-02-03 14:16 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, 02 Feb 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Wed, Feb 01, 2017 at 11:40:06AM -0800, Manasi Navare wrote:
>> Are you planning on submitting a v2 for these pretty soon
>> that can make it to patchwork/
>>
>> Regards
>> Manasi
>>
>> On Thu, Jan 26, 2017 at 09:44:14PM +0200, Jani Nikula wrote:
>> > This is kind of version 1½ of [1], basically just rebased on current git
>> > (including Manasi's test automation patches) and a couple of more
>> > cleanups slammed on top.
>> >
>> > BR,
>> > Jani.
>> >
>
> So the problem we still have with link rate fallback after link
> failure->uevent-> fetch new modes->link retrain is that after we send
> a uevent, userspace fetches new modes which calls
> drm_helper_probe_single_connector_modes() that calls dp_detect which
> ends up calling intel_dp_long_pulse(). So while userspace is just
> trying to fetch new modes it overwrites the max_link_rate and
> max_lane_count values through intel_dp_long_pulse(). So while
> retraining, when it calls intel_dp_compute_config(), it will use the
> overwritten values of common_rates/max_link_rate/max_lane_count as
> opposed to the ones set in intel_dp_get_fallback_values().
> I wonder if this patch series solves this problem somehow...
> else, do you have any insight on how we can solve this?
I'm not sure this does solve that, but this series certainly makes it
easier to follow through the code and see what happens where. ;)
Writing this patch has also highlighted the problem with merging
preparatory patches that don't actually do anything, in this case the
intel_dp_get_link_train_fallback_values() function. How is one supposed
to know how it can be refactored when it doesn't have a single user?
BR,
Jani.
>
> Regards
> Manasi
>
>
>> >
>> > [1] http://mid.mail-archive.com/cover.1485015599.git.jani.nikula@intel.com
>> >
>> >
>> > Jani Nikula (13):
>> > drm/i915/dp: use known correct array size in rate_to_index
>> > drm/i915/dp: return errors from rate_to_index()
>> > drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
>> > drm/i915/dp: cache source rates at init
>> > drm/i915/dp: generate and cache sink rate array for all DP, not just
>> > eDP 1.4
>> > drm/i915/dp: use the sink rates array for max sink rates
>> > drm/i915/dp: cache common rates with sink rates
>> > drm/i915/dp: do not limit rate seek when not needed
>> > drm/i915/dp: don't call the link parameters sink parameters
>> > drm/i915/dp: add functions for max common link rate and lane count
>> > drm/i915/mst: use max link not sink lane count
>> > drm/i915/dp: localize link rate index variable more
>> > drm/i915/dp: use readb and writeb calls for single byte DPCD access
>> >
>> > drivers/gpu/drm/i915/intel_dp.c | 275 ++++++++++++++------------
>> > drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
>> > drivers/gpu/drm/i915/intel_dp_mst.c | 4 +-
>> > drivers/gpu/drm/i915/intel_drv.h | 19 +-
>> > 4 files changed, 166 insertions(+), 135 deletions(-)
>> >
>> > --
>> > 2.1.4
>> >
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread