From: Harry Wentland <harry.wentland@amd.com>
To: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>,
nicholas.kazlauskas@amd.com, hersenxs.wu@amd.com,
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV
Date: Tue, 24 Nov 2020 15:08:48 -0500 [thread overview]
Message-ID: <393ee532-7690-ce76-4b36-75a65656173b@amd.com> (raw)
In-Reply-To: <20201124155508.2096060-1-Pratik.Vishwakarma@amd.com>
On 2020-11-24 10:55 a.m., Pratik Vishwakarma wrote:
> [Why]
> Changes in video resolution during playback cause
> dispclk to ramp higher but sets incompatile fclk
> and dcfclk values for MPO.
>
> [How]
> Check for MPO and set proper min clk values
> for this case also. This was missed during previous
> patch.
>
> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
> ---
> .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> index 75b8240ed059..ed087a9e73bb 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> @@ -275,9 +275,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
> if (pp_smu->set_hard_min_fclk_by_freq &&
> pp_smu->set_hard_min_dcfclk_by_freq &&
> pp_smu->set_min_deep_sleep_dcfclk) {
> - pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
> - pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
> - pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> + // Only increase clocks when display is active and MPO is enabled
Why do we want to only do this when MPO is enabled?
Harry
> + if (display_count && is_mpo_enabled(context)) {
> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> + ((new_clocks->fclk_khz / 1000) * 101) / 100);
> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> + ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> + (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> + } else {
> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> + new_clocks->fclk_khz / 1000);
> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> + new_clocks->dcfclk_khz / 1000);
> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> + (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> + }
> }
> }
>
>
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next prev parent reply other threads:[~2020-11-24 20:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 15:55 [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV Pratik Vishwakarma
2020-11-24 20:08 ` Harry Wentland [this message]
2020-11-25 4:32 ` Pratik Vishwakarma
2020-11-27 4:23 ` Pratik Vishwakarma
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