* [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV
@ 2020-11-24 15:55 Pratik Vishwakarma
2020-11-24 20:08 ` Harry Wentland
0 siblings, 1 reply; 4+ messages in thread
From: Pratik Vishwakarma @ 2020-11-24 15:55 UTC (permalink / raw)
To: nicholas.kazlauskas, hersenxs.wu, amd-gfx
[Why]
Changes in video resolution during playback cause
dispclk to ramp higher but sets incompatile fclk
and dcfclk values for MPO.
[How]
Check for MPO and set proper min clk values
for this case also. This was missed during previous
patch.
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 75b8240ed059..ed087a9e73bb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -275,9 +275,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
if (pp_smu->set_hard_min_fclk_by_freq &&
pp_smu->set_hard_min_dcfclk_by_freq &&
pp_smu->set_min_deep_sleep_dcfclk) {
- pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
- pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
- pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ // Only increase clocks when display is active and MPO is enabled
+ if (display_count && is_mpo_enabled(context)) {
+ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+ ((new_clocks->fclk_khz / 1000) * 101) / 100);
+ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+ ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
+ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+ (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ } else {
+ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+ new_clocks->fclk_khz / 1000);
+ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+ new_clocks->dcfclk_khz / 1000);
+ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+ (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ }
}
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV
2020-11-24 15:55 [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV Pratik Vishwakarma
@ 2020-11-24 20:08 ` Harry Wentland
2020-11-25 4:32 ` Pratik Vishwakarma
0 siblings, 1 reply; 4+ messages in thread
From: Harry Wentland @ 2020-11-24 20:08 UTC (permalink / raw)
To: Pratik Vishwakarma, nicholas.kazlauskas, hersenxs.wu, amd-gfx
On 2020-11-24 10:55 a.m., Pratik Vishwakarma wrote:
> [Why]
> Changes in video resolution during playback cause
> dispclk to ramp higher but sets incompatile fclk
> and dcfclk values for MPO.
>
> [How]
> Check for MPO and set proper min clk values
> for this case also. This was missed during previous
> patch.
>
> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
> ---
> .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> index 75b8240ed059..ed087a9e73bb 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> @@ -275,9 +275,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
> if (pp_smu->set_hard_min_fclk_by_freq &&
> pp_smu->set_hard_min_dcfclk_by_freq &&
> pp_smu->set_min_deep_sleep_dcfclk) {
> - pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
> - pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
> - pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> + // Only increase clocks when display is active and MPO is enabled
Why do we want to only do this when MPO is enabled?
Harry
> + if (display_count && is_mpo_enabled(context)) {
> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> + ((new_clocks->fclk_khz / 1000) * 101) / 100);
> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> + ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> + (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> + } else {
> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> + new_clocks->fclk_khz / 1000);
> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> + new_clocks->dcfclk_khz / 1000);
> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> + (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> + }
> }
> }
>
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV
2020-11-24 20:08 ` Harry Wentland
@ 2020-11-25 4:32 ` Pratik Vishwakarma
2020-11-27 4:23 ` Pratik Vishwakarma
0 siblings, 1 reply; 4+ messages in thread
From: Pratik Vishwakarma @ 2020-11-25 4:32 UTC (permalink / raw)
To: Harry Wentland, Pratik Vishwakarma, nicholas.kazlauskas,
hersenxs.wu, amd-gfx
On 25/11/20 1:38 am, Harry Wentland wrote:
> On 2020-11-24 10:55 a.m., Pratik Vishwakarma wrote:
>> [Why]
>> Changes in video resolution during playback cause
>> dispclk to ramp higher but sets incompatile fclk
>> and dcfclk values for MPO.
>>
>> [How]
>> Check for MPO and set proper min clk values
>> for this case also. This was missed during previous
>> patch.
>>
>> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
>> ---
>> .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 19 ++++++++++++++++---
>> 1 file changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>> index 75b8240ed059..ed087a9e73bb 100644
>> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>> @@ -275,9 +275,22 @@ static void rv1_update_clocks(struct clk_mgr
>> *clk_mgr_base,
>> if (pp_smu->set_hard_min_fclk_by_freq &&
>> pp_smu->set_hard_min_dcfclk_by_freq &&
>> pp_smu->set_min_deep_sleep_dcfclk) {
>> - pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
>> new_clocks->fclk_khz / 1000);
>> - pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
>> new_clocks->dcfclk_khz / 1000);
>> - pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
>> (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
>> + // Only increase clocks when display is active and MPO
>> is enabled
>
> Why do we want to only do this when MPO is enabled?
>
> Harry
Hi Harry,
When MPO is enabled and system moves to lower clock state, clock values
are not sufficient and we see flash lines across entire screen.
This issue is not observed when MPO is disabled or not active.
Regards,
Pratik
>
>> + if (display_count && is_mpo_enabled(context)) {
>> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
>> + ((new_clocks->fclk_khz / 1000) * 101) / 100);
>> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
>> + ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
>> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
>> + (new_clocks->dcfclk_deep_sleep_khz + 999) /
>> 1000);
>> + } else {
>> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
>> + new_clocks->fclk_khz / 1000);
>> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
>> + new_clocks->dcfclk_khz / 1000);
>> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
>> + (new_clocks->dcfclk_deep_sleep_khz + 999) /
>> 1000);
>> + }
>> }
>> }
>>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV
2020-11-25 4:32 ` Pratik Vishwakarma
@ 2020-11-27 4:23 ` Pratik Vishwakarma
0 siblings, 0 replies; 4+ messages in thread
From: Pratik Vishwakarma @ 2020-11-27 4:23 UTC (permalink / raw)
To: Harry Wentland, Pratik Vishwakarma, nicholas.kazlauskas,
hersenxs.wu, amd-gfx, roman.li
Friendly ping.
Please help review.
Regards
Pratik
On 25/11/20 10:02 am, Pratik Vishwakarma wrote:
> On 25/11/20 1:38 am, Harry Wentland wrote:
>> On 2020-11-24 10:55 a.m., Pratik Vishwakarma wrote:
>>> [Why]
>>> Changes in video resolution during playback cause
>>> dispclk to ramp higher but sets incompatile fclk
>>> and dcfclk values for MPO.
>>>
>>> [How]
>>> Check for MPO and set proper min clk values
>>> for this case also. This was missed during previous
>>> patch.
>>>
>>> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
>>> ---
>>> .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 19
>>> ++++++++++++++++---
>>> 1 file changed, 16 insertions(+), 3 deletions(-)
>>>
>>> diff --git
>>> a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>>> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>>> index 75b8240ed059..ed087a9e73bb 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>>> @@ -275,9 +275,22 @@ static void rv1_update_clocks(struct clk_mgr
>>> *clk_mgr_base,
>>> if (pp_smu->set_hard_min_fclk_by_freq &&
>>> pp_smu->set_hard_min_dcfclk_by_freq &&
>>> pp_smu->set_min_deep_sleep_dcfclk) {
>>> - pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
>>> new_clocks->fclk_khz / 1000);
>>> - pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
>>> new_clocks->dcfclk_khz / 1000);
>>> - pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
>>> (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
>>> + // Only increase clocks when display is active and MPO
>>> is enabled
>>
>> Why do we want to only do this when MPO is enabled?
>>
>> Harry
>
> Hi Harry,
>
> When MPO is enabled and system moves to lower clock state, clock
> values are not sufficient and we see flash lines across entire screen.
>
> This issue is not observed when MPO is disabled or not active.
>
> Regards,
>
> Pratik
>
>>
>>> + if (display_count && is_mpo_enabled(context)) {
>>> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
>>> + ((new_clocks->fclk_khz / 1000) * 101) / 100);
>>> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
>>> + ((new_clocks->dcfclk_khz / 1000) * 101) /
>>> 100);
>>> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
>>> + (new_clocks->dcfclk_deep_sleep_khz + 999) /
>>> 1000);
>>> + } else {
>>> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
>>> + new_clocks->fclk_khz / 1000);
>>> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
>>> + new_clocks->dcfclk_khz / 1000);
>>> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
>>> + (new_clocks->dcfclk_deep_sleep_khz + 999) /
>>> 1000);
>>> + }
>>> }
>>> }
>>>
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2020-11-24 15:55 [PATCH] drm/amd/display: Extends Tune min clk for MPO for RV Pratik Vishwakarma
2020-11-24 20:08 ` Harry Wentland
2020-11-25 4:32 ` Pratik Vishwakarma
2020-11-27 4:23 ` Pratik Vishwakarma
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