SATA FSL and upstreaming

SATA FSL and upstreaming

[Benjamin Herrenschmidt]

Hi folks !

So I was trying to use my 5020ds to test some stuff today. Since I
hadn't used it in a while, I decided to "upgrade" it to the latest NOR
etc...

Interestingly I discovered that the SATA (which was supposedly dead on
the rev1 chip) was actually working with the SDK kernel, while it's
still completely busted upstream.

A quick git compare shows about 5 or 6 commits in the SDK tree, some as
old as 2011, fixing various erratas in that chip, that never made their
way upstream.

Any reason for that ? Being GPL, I can submit them to Tejun myself but
it would be better form if you guys did :-)

BTW. Also what's the status with getting the network working upstream ?
Even if sub-standard the code could at least go into staging...

Cheers,
Ben.

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 14:47 +1000, Benjamin Herrenschmidt wrote:
> Hi folks !
> 
> So I was trying to use my 5020ds to test some stuff today. Since I
> hadn't used it in a while, I decided to "upgrade" it to the latest NOR
> etc...

On another note, I can't seem to get any PCIe card recognized in any
slot...

Can you give me an example config of the DIP switches that is known to
work with some slots ? Is there some EEPROM config needed ? If yes, any
pointers ? (I can't quite make sense of either u-boot or the doc there).

Thanks,
Ben.

Re: SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 01:45 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 14:47 +1000, Benjamin Herrenschmidt wrote:
>> Hi folks !
>>
>> So I was trying to use my 5020ds to test some stuff today. Since I
>> hadn't used it in a while, I decided to "upgrade" it to the latest NOR
>> etc...
>
> On another note, I can't seem to get any PCIe card recognized in any
> slot...

This should depend on the RCW.

As I recall, slot 7 or slot 4 can be configured to support PCIe for P5020DS. And 
you can know this information according to RCW's README.

Tiejun

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

For PCIe issue, I might be related to your RCW (Reset Configuration Word).
Can you help to provide the u-boot log?
Roy

> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Benjamin
> Herrenschmidt
> Sent: Thursday, May 16, 2013 1:46 PM
> To: Liu Qiang-B32616
> Cc: linuxppc-dev@lists.ozlabs.org; Fleming Andy-AFLEMING; Xie Shaohui-
> B21989
> Subject: Re: SATA FSL and upstreaming
>=20
> On Thu, 2013-05-16 at 14:47 +1000, Benjamin Herrenschmidt wrote:
> > Hi folks !
> >
> > So I was trying to use my 5020ds to test some stuff today. Since I
> > hadn't used it in a while, I decided to "upgrade" it to the latest NOR
> > etc...
>=20
> On another note, I can't seem to get any PCIe card recognized in any
> slot...
>=20
> Can you give me an example config of the DIP switches that is known to
> work with some slots ? Is there some EEPROM config needed ? If yes, any
> pointers ? (I can't quite make sense of either u-boot or the doc there).
>=20
> Thanks,
> Ben.
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev

RE: SATA FSL and upstreaming

[Bhushan Bharat-R65777]

[-- Attachment #1: Type: text/plain, Size: 1200 bytes --]



> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+bharat.bhushan=freescale.com@lists.ozlabs.org] On Behalf Of Benjamin
> Herrenschmidt
> Sent: Thursday, May 16, 2013 11:16 AM
> To: Liu Qiang-B32616
> Cc: linuxppc-dev@lists.ozlabs.org; Fleming Andy-AFLEMING; Xie Shaohui-B21989
> Subject: Re: SATA FSL and upstreaming
> 
> On Thu, 2013-05-16 at 14:47 +1000, Benjamin Herrenschmidt wrote:
> > Hi folks !
> >
> > So I was trying to use my 5020ds to test some stuff today. Since I
> > hadn't used it in a while, I decided to "upgrade" it to the latest NOR
> > etc...
> 
> On another note, I can't seem to get any PCIe card recognized in any slot...
> 
> Can you give me an example config of the DIP switches that is known to work with
> some slots ? Is there some EEPROM config needed ? If yes, any pointers ? (I
> can't quite make sense of either u-boot or the doc there).

Can you give RCW dump?
Or can try the attached RCW.

Thanks
-Bharat

> 
> Thanks,
> Ben.
> 
> 
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev


[-- Attachment #2: rcw_15g_2000mhz.rcw --]
[-- Type: application/octet-stream, Size: 794 bytes --]

/*
 * 15g configuration -- 3 SGMII 1g ports  + 2 RGMII + 1 XAUI
 *
 * Frequencies:
 *
 * Sys Clock -- 133.33 Mhz
 * SDREFCLK1_FSEL: 100 MHz
 * SDREFCLK2_FSEL: 125 MHz
 * SDREFCLK3_FSEL: 125 MHz
 *
 * Core -- 2000 MHz (Mul 15)
 * Platform - 800 MHz (Mul 6)
 * DDR -- 1333.33 MHz (Mul 10)
 * FMAN -- 600 MHz (CC2 PLL)/2 (Mul 9)
 *
 * Serdes Bank1 -- Clock Ratio 50:1 /2 for PCIe and 50:1/1 for SGMII
 * LANE A, B, C, D /2 for PCIe
 * Bank2    -- 25:1 /1
 * Bank3   -- 24:1 /1
 */

#include <p5020.rcwi>

SYS_PLL_RAT=6
MEM_PLL_CFG=1
MEM_PLL_RAT=10
CC1_PLL_RAT=15
CC2_PLL_RAT=9
SRDS_PRTCL=54
SRDS_RATIO_B1=4
SRDS_DIV_B1=24
SRDS_RATIO_B2=2
SRDS_RATIO_B3=5
SRDS_LPD_B1=4
SRDS_LPD_B3=12
SRDS_EN=1
PBI_SRC=0b1101
BOOT_LOC=29
FM_CLK_SEL=1
DRAM_LAT=1
I2C=4
GPIO=1
UART=6

// #include "../../a004580.rcw"

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Bhushan Bharat-
> R65777
> Sent: Thursday, May 16, 2013 2:02 PM
> To: Benjamin Herrenschmidt; Liu Qiang-B32616
> Cc: Fleming Andy-AFLEMING; linuxppc-dev@lists.ozlabs.org; Xie Shaohui-
> B21989
> Subject: RE: SATA FSL and upstreaming
>=20
>=20
>=20
> > -----Original Message-----
> > From: Linuxppc-dev [mailto:linuxppc-dev-
> > bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of
> > bounces+Benjamin
> > Herrenschmidt
> > Sent: Thursday, May 16, 2013 11:16 AM
> > To: Liu Qiang-B32616
> > Cc: linuxppc-dev@lists.ozlabs.org; Fleming Andy-AFLEMING; Xie
> > Shaohui-B21989
> > Subject: Re: SATA FSL and upstreaming
> >
> > On Thu, 2013-05-16 at 14:47 +1000, Benjamin Herrenschmidt wrote:
> > > Hi folks !
> > >
> > > So I was trying to use my 5020ds to test some stuff today. Since I
> > > hadn't used it in a while, I decided to "upgrade" it to the latest
> > > NOR etc...
> >
> > On another note, I can't seem to get any PCIe card recognized in any
> slot...
> >
> > Can you give me an example config of the DIP switches that is known to
> > work with some slots ? Is there some EEPROM config needed ? If yes,
> > any pointers ? (I can't quite make sense of either u-boot or the doc
> there).
>=20
> Can you give RCW dump?
> Or can try the attached RCW.
I do not suggest changing the RCW. If the RCW is broken on Ben's side, it i=
s not easy to recover for him.
Let's check the U-boot output first.
Thanks.
Roy

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 13:55 +0800, tiejun.chen wrote:
> This should depend on the RCW.
> 
> As I recall, slot 7 or slot 4 can be configured to support PCIe for
> P5020DS. And 
> you can know this information according to RCW's README.

Somebody can hand hold me on irc ?

Cheers,
Ben.

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote:
> I do not suggest changing the RCW. If the RCW is broken on Ben's side,
> it is not easy to recover for him.
> Let's check the U-boot output first.

U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16)

CPU0:  P5020E, Version: 1.0, (0x82280010)
Core:  E5500, Version: 1.0, (0x80240010)
Clock Configuration:
       CPU0:2000 MHz, CPU1:2000 MHz, 
       CCB:800  MHz,
       DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100  MHz
       FMAN1: 600 MHz
       QMAN:  400 MHz
       PME:   400 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
Reset Configuration Word (RCW):
       00000000: 0c540000 00000000 1e120000 00000000
       00000010: d8984a01 03002000 de800000 41000000
       00000020: 00000000 00000000 00000000 10070000
       00000030: 00000000 00000000 00000000 00000000
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz 
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM i-DIMM
Detected UDIMM i-DIMM
2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=9, ECC on)
       DDR Controller Interleaving Mode: cache line
       DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped

POST memory PASSED
Flash: 128 MiB
L2:    512 KB enabled
Corenet Platform Cache: 2048 KB enabled
SRIO1: disabled
SRIO2: disabled
NAND:  1024 MiB
MMC:  FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: Root Complex, no link, regs @ 0xfe200000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe202000
PCIe3: Bus 01 - 01
PCIe4: disabled
In:    serial
Out:   serial
Err:   serial
Net:   Initializing Fman
Fman1: Uploading microcode version 106.1.7
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, FM1@TGEC1
Hit any key to stop autoboot:  0 
=> 

Cheers,
Ben.

Re: SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 02:09 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote:
>> I do not suggest changing the RCW. If the RCW is broken on Ben's side,
>> it is not easy to recover for him.
>> Let's check the U-boot output first.
>
> U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16)
>
> CPU0:  P5020E, Version: 1.0, (0x82280010)
> Core:  E5500, Version: 1.0, (0x80240010)
> Clock Configuration:
>         CPU0:2000 MHz, CPU1:2000 MHz,
>         CCB:800  MHz,
>         DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100  MHz
>         FMAN1: 600 MHz
>         QMAN:  400 MHz
>         PME:   400 MHz
> L1:    D-cache 32 kB enabled
>         I-cache 32 kB enabled
> Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
> Reset Configuration Word (RCW):
>         00000000: 0c540000 00000000 1e120000 00000000
>         00000010: d8984a01 03002000 de800000 41000000
>         00000020: 00000000 00000000 00000000 10070000
>         00000030: 00000000 00000000 00000000 00000000

I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then please take 
a look at this:

The RCW directories names for the p5020ds board conform to the following naming
convention:

ab_bcdefghi_j:

a = 'R' if RGMII@DTSEC4 is supported / 'N' if not available/not used
b = 'R' if RGMII@DTSEC5 is supported / 'N" if not available/not used

c = What is available in Slot 1 or SATA
d = What is available in Slot 2
e = What is available in Slot 3
f = What is available in Slot 4
g = What is available in Slot 5
h = What is available in Slot 6
i = What is available in Slot 7

For the Slots (c..i):
  'N' if not available/not used
  'P' if PCIe
  'X' if XAUI
  'R' if SRIO
  'S' if SGMII
  'H' if SATA
  'A' is AURORA

j = 'hex value of serdes protocol value'

So NR_HXAPNSP_0x36 means:
  - no RGMII@DTSEC4
  - RGMII@DTSEC5
  - SATA [Slot 1 not used]
  - XAUI on Slot 2
  - AURORA on Slot 3
  - PCIE on Slot 4
  - SGMII on Slot 6
  - PCIE on Slot 7

Slot 5 is not used, and the SERDES Protocol is 0x36.

So slot 7 and slot 4 can be as PCIe slot.

Tiejun

> SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
> I2C:   ready
> SPI:   ready
> DRAM:  Initializing....using SPD
> Detected UDIMM i-DIMM
> Detected UDIMM i-DIMM
> 2 GiB left unmapped
> 4 GiB (DDR3, 64-bit, CL=9, ECC on)
>         DDR Controller Interleaving Mode: cache line
>         DDR Chip-Select Interleaving Mode: CS0+CS1
> Testing 0x00000000 - 0x7fffffff
> Testing 0x80000000 - 0xffffffff
> Remap DDR 2 GiB left unmapped
>
> POST memory PASSED
> Flash: 128 MiB
> L2:    512 KB enabled
> Corenet Platform Cache: 2048 KB enabled
> SRIO1: disabled
> SRIO2: disabled
> NAND:  1024 MiB
> MMC:  FSL_SDHC: 0
> EEPROM: NXID v1
> PCIe1: Root Complex, no link, regs @ 0xfe200000
> PCIe1: Bus 00 - 00
> PCIe2: disabled
> PCIe3: Root Complex, no link, regs @ 0xfe202000
> PCIe3: Bus 01 - 01
> PCIe4: disabled
> In:    serial
> Out:   serial
> Err:   serial
> Net:   Initializing Fman
> Fman1: Uploading microcode version 106.1.7
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, FM1@TGEC1
> Hit any key to stop autoboot:  0
> =>
>
> Cheers,
> Ben.
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
>

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

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RE: SATA FSL and upstreaming

[Zang Roy-R61911]

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NykgYW5kIFBDSWUzIChzbG90NCkuDQpSb3kNCg==

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
> please take 
> a look at this:

Ok, how do I update my RCW to bse Bharat's ?

Any DIP switch setting I need to be aware of ?

Thanks !

Cheers,
Ben.

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:17 +0000, Zang Roy-R61911 wrote:
> Do you try slot7?
> PCIe1 connects to slot7 directly.

I tried all slots. None of them sees any card. The card also doesn't
seem to be powered up (none of the LEDs blink, it's an e1000 since I
don't have networking with upstream).

I also tried a different card and uboot is pretty adamant at saying "no
link" :-)

I'll try to update the RCW when I know how to do it :-)

Cheers,
Ben.

> Roy
> 
> > -----Original Message-----
> > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > Sent: Thursday, May 16, 2013 2:09 PM
> > To: Zang Roy-R61911
> > Cc: Bhushan Bharat-R65777; Liu Qiang-B32616; Fleming Andy-AFLEMING;
> > linuxppc-dev@lists.ozlabs.org; Xie Shaohui-B21989
> > Subject: Re: SATA FSL and upstreaming
> > 
> > On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote:
> > > I do not suggest changing the RCW. If the RCW is broken on Ben's side,
> > > it is not easy to recover for him.
> > > Let's check the U-boot output first.
> > 
> > U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16)
> > 
> > CPU0:  P5020E, Version: 1.0, (0x82280010)
> > Core:  E5500, Version: 1.0, (0x80240010)
> > Clock Configuration:
> >        CPU0:2000 MHz, CPU1:2000 MHz,
> >        CCB:800  MHz,
> >        DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100
> > MHz
> >        FMAN1: 600 MHz
> >        QMAN:  400 MHz
> >        PME:   400 MHz
> > L1:    D-cache 32 kB enabled
> >        I-cache 32 kB enabled
> > Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
> > Reset Configuration Word (RCW):
> >        00000000: 0c540000 00000000 1e120000 00000000
> >        00000010: d8984a01 03002000 de800000 41000000
> >        00000020: 00000000 00000000 00000000 10070000
> >        00000030: 00000000 00000000 00000000 00000000
> > SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
> > I2C:   ready
> > SPI:   ready
> > DRAM:  Initializing....using SPD
> > Detected UDIMM i-DIMM
> > Detected UDIMM i-DIMM
> > 2 GiB left unmapped
> > 4 GiB (DDR3, 64-bit, CL=9, ECC on)
> >        DDR Controller Interleaving Mode: cache line
> >        DDR Chip-Select Interleaving Mode: CS0+CS1
> > Testing 0x00000000 - 0x7fffffff
> > Testing 0x80000000 - 0xffffffff
> > Remap DDR 2 GiB left unmapped
> > 
> > POST memory PASSED
> > Flash: 128 MiB
> > L2:    512 KB enabled
> > Corenet Platform Cache: 2048 KB enabled
> > SRIO1: disabled
> > SRIO2: disabled
> > NAND:  1024 MiB
> > MMC:  FSL_SDHC: 0
> > EEPROM: NXID v1
> > PCIe1: Root Complex, no link, regs @ 0xfe200000
> > PCIe1: Bus 00 - 00
> > PCIe2: disabled
> > PCIe3: Root Complex, no link, regs @ 0xfe202000
> > PCIe3: Bus 01 - 01
> > PCIe4: disabled
> > In:    serial
> > Out:   serial
> > Err:   serial
> > Net:   Initializing Fman
> > Fman1: Uploading microcode version 106.1.7
> > PHY reset timed out
> > PHY reset timed out
> > PHY reset timed out
> > PHY reset timed out
> > FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, FM1@TGEC1
> > Hit any key to stop autoboot:  0
> > =>
> > 
> > Cheers,
> > Ben.
> > 
> > 
> 

RE: SATA FSL and upstreaming

[Xie Shaohui-B21989]

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IENoZWVycywNCj4gQmVuLg0KPiANCj4gDQoNCg==

Re: SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 02:20 PM, Zang Roy-R61911 wrote:
>
>
>> -----Original Message-----
>> From: tiejun.chen [mailto:tiejun.chen@windriver.com]
>> Sent: Thursday, May 16, 2013 2:18 PM
>> To: Benjamin Herrenschmidt
>> Cc: Zang Roy-R61911; Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
>> dev@lists.ozlabs.org; Xie Shaohui-B21989; Bhushan Bharat-R65777
>> Subject: Re: SATA FSL and upstreaming
>>
>> On 05/16/2013 02:09 PM, Benjamin Herrenschmidt wrote:
>>> On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote:
>>>> I do not suggest changing the RCW. If the RCW is broken on Ben's
>>>> side, it is not easy to recover for him.
>>>> Let's check the U-boot output first.
>>>
>>> U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16)
>>>
>>> CPU0:  P5020E, Version: 1.0, (0x82280010)
>>> Core:  E5500, Version: 1.0, (0x80240010) Clock Configuration:
>>>          CPU0:2000 MHz, CPU1:2000 MHz,
>>>          CCB:800  MHz,
>>>          DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous),
>> LBC:100  MHz
>>>          FMAN1: 600 MHz
>>>          QMAN:  400 MHz
>>>          PME:   400 MHz
>>> L1:    D-cache 32 kB enabled
>>>          I-cache 32 kB enabled
>>> Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
>>> Reset Configuration Word (RCW):
>>>          00000000: 0c540000 00000000 1e120000 00000000
>>>          00000010: d8984a01 03002000 de800000 41000000
>>>          00000020: 00000000 00000000 00000000 10070000
>>>          00000030: 00000000 00000000 00000000 00000000
>>
>> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
>> please take a look at this:
> Why?

I just believe Bharat should pick a proper RCW from SDK.

> Ben's on board RCW protocol is 0x36, which should work for PCIe1 (slot 7) and PCIe3 (slot4).

Didn't you see I'm also saying to use slot 7 and slot 4?

Tiejun

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:20 +0000, Zang Roy-R61911 wrote:
> Why?
> Ben's on board RCW protocol is 0x36, which should work for PCIe1 (slot 7) and PCIe3 (slot4).
> Roy

I've put a card in slot 7 and a card in slot 4 and I still get:

PCIe1: Root Complex, no link, regs @ 0xfe200000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe202000
PCIe3: Bus 01 - 01
PCIe4: disabled

And nothing in Linux... Could there be another issue (DIP ? jumpers ?)

Cheers,
Ben.

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:24 +0000, Xie Shaohui-B21989 wrote:
> Hi, Ben,
> 
> Since the p5020ds you tested is a rev1 chip, I think the most possibility that SATA not work
> is due to a SATA erratum, which is fixed in rev1.1, we have a policy that patches for errata that 
> are present only on early silicon revisions, typically only rev1 silicon will not send upstream.
> You can find the patch at below link:
> http://git.freescale.com/git/cgit.cgi/ppc/sdk/linux.git/commit/?id=b79a8a0528b8a0008cb76f339806b1200b5d8f63

Well, the chip I have is rev1... since I'm the maintainer I might pull a
"Linus" and just apply the damn patch to make it work for me :-) Though
I'm being told that a rev2 chip is on its way to me ... I'll wait a few
more days see if that arrives.

Cheers,
Ben.

> Since it is not sent to upstream, it may need to be rebased if apply it to latest tree.
> 
> Also there might be another issue(SATA & USB) if you test 64 bit kernel on p5020ds with DRR > 4G, we have a patch
> Sent to upstream, but not accepted yet. Link as below:
> http://patchwork.ozlabs.org/patch/179828/
> 
> There are online documents of SDK, for the p5020ds hardware please see the link:
> http://www.freescale.com/infocenter/index.jsp?topic=%2FQORIQSDK%2F2989554.html
> 
> 
> Best Regards, 
> Shaohui Xie
> > -----Original Message-----
> > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > Sent: Thursday, May 16, 2013 12:48 PM
> > To: Liu Qiang-B32616; Xie Shaohui-B21989; Fleming Andy-AFLEMING
> > Cc: linuxppc-dev@lists.ozlabs.org; Kumar Gala
> > Subject: SATA FSL and upstreaming
> > 
> > Hi folks !
> > 
> > So I was trying to use my 5020ds to test some stuff today. Since I hadn't
> > used it in a while, I decided to "upgrade" it to the latest NOR etc...
> > 
> > Interestingly I discovered that the SATA (which was supposedly dead on
> > the rev1 chip) was actually working with the SDK kernel, while it's still
> > completely busted upstream.
> > 
> > A quick git compare shows about 5 or 6 commits in the SDK tree, some as
> > old as 2011, fixing various erratas in that chip, that never made their
> > way upstream.
> > 
> > Any reason for that ? Being GPL, I can submit them to Tejun myself but it
> > would be better form if you guys did :-)
> > 
> > BTW. Also what's the status with getting the network working upstream ?
> > Even if sub-standard the code could at least go into staging...
> > 
> > Cheers,
> > Ben.
> > 
> > 
> 

RE: SATA FSL and upstreaming

[Bhushan Bharat-R65777]

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Cg0K

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:33 +0000, Bhushan Bharat-R65777 wrote:
> From bank 0
> ------------
> 
> tftp 0x1000000  rcw_2sgmii_1500mhz.bin
> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b
> 0x1000000 0xec000000 $filesize

Before I do something irreparable, what do you specifically mean by
"from bank 0" ? :-)

Cheers,
Ben.

Re: SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
>> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
>> please take
>> a look at this:
>
> Ok, how do I update my RCW to bse Bharat's ?


Firstly please check which flash bank is used since we have to know where should 
be updated RCW.

What is SW7[1:4]?

Or we have another simple way in u-boot prompt:

=> md.b ffdf002c
ffdf002c: 4f 00 fe 00 39 00 00 00 00 00 00 00 00 00 00 00    O...9...........
...

This means we're on bank4.

>
> Any DIP switch setting I need to be aware of ?

No.

Tiejun

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmh1c2hhbiBCaGFyYXQt
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azQuDQpSb3kNCg==

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:33 +0000, Bhushan Bharat-R65777 wrote:
> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b
> 0x1000000 0xec000000 $filesize

BTW, is it normal that the network in uboot is *extremely* unreliable ?
It takes dozens of tries if not more for it to "kick in", then it
eventually works.

I've given on dhcp and using fixed IPs but that doesn't help, tftp fails
several times until it eventually work ... if I'm in a lucky day.

Cheers,
Ben.

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogdGllanVuLmNoZW4gW21h
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Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 14:35 +0800, tiejun.chen wrote:
> On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
> > On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
> >> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
> >> please take
> >> a look at this:
> >
> > Ok, how do I update my RCW to bse Bharat's ?
> 
> 
> Firstly please check which flash bank is used since we have to know where should 
> be updated RCW.
> 
> What is SW7[1:4]?
> 
> Or we have another simple way in u-boot prompt:
> 
> => md.b ffdf002c
> ffdf002c: 4f 00 fe 00 39 00 00 00 00 00 00 00 00 00 00 00    O...9...........
> ...

ffdf002c: 0f 00 fe 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

> This means we're on bank4.

I assume that means bank0 ?

> >
> > Any DIP switch setting I need to be aware of ?
> 
> No.
> 
> Tiejun

Re: SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 02:37 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 06:33 +0000, Bhushan Bharat-R65777 wrote:
>> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b
>> 0x1000000 0xec000000 $filesize
>
> BTW, is it normal that the network in uboot is *extremely* unreliable ?

We can use serial port:

loadb   - load binary file over serial line (kermit mode)
loads   - load S-Record file over serial line
loady   - load binary file over serial line (ymodem mode)

Then please send the RCW with appropriate mode above in your terminal client.

Tiejun

Re: SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 02:40 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 14:35 +0800, tiejun.chen wrote:
>> On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
>>> On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
>>>> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
>>>> please take
>>>> a look at this:
>>>
>>> Ok, how do I update my RCW to bse Bharat's ?
>>
>>
>> Firstly please check which flash bank is used since we have to know where should
>> be updated RCW.
>>
>> What is SW7[1:4]?
>>
>> Or we have another simple way in u-boot prompt:
>>
>> => md.b ffdf002c
>> ffdf002c: 4f 00 fe 00 39 00 00 00 00 00 00 00 00 00 00 00    O...9...........
>> ...
>
> ffdf002c: 0f 00 fe 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
>
>> This means we're on bank4.
>
> I assume that means bank0 ?

Yes, RCW should be burned to 0xec000000.

In u-boot prompt:

=> loady
## Ready for binary (ymodem) download to 0x01000000 at 115200 bps...
C

Then send that RCW with ymodem in your terminal client.

Tiejun

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmh1c2hhbiBCaGFyYXQt
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aWQgYnJlYWtpbmcgYmFuazAuDQpUaGFua3MuDQpSb3kNCg==

RE: SATA FSL and upstreaming

[Bhushan Bharat-R65777]

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RE: SATA FSL and upstreaming

[Zang Roy-R61911]

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Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:48 +0000, Bhushan Bharat-R65777 wrote:

> 1) Load RCW as Tiejun on some address in DDR.
> 
> 2) Brun RCW at 0xec000000:
> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b 0x1000000 0xec000000 $filesize

Done.

> 3) run " pix altbak" command
> 
> 4) check you are on bank4

It stays on bank 0

Also, before I flashed the rcw, I tried messing with SW7[1:4] and got it
to book to bank 4 once (I think I changed DIP 2 or 3). Now, after the
new RCW is in, it won't boot with any other setting than bank 0 however.

Cheers,
Ben.

> 5) If you are luckier then networking will work for you.
> 
> Thanks
> -Bharat
> 
> > 
> > Tiejun
> 

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 06:49 +0000, Zang Roy-R61911 wrote:
> 

> Please also provide a RCW binary to Ben, if your guys insist updating  the RCW.

right, I just noticed it's ascii :-) That isn't going to work well...

Cheers,
Ben.

Re: SATA FSL and upstreaming

[tiejun.chen]

On 05/16/2013 02:53 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 06:49 +0000, Zang Roy-R61911 wrote:
>>
>
>> Please also provide a RCW binary to Ben, if your guys insist updating  the RCW.
>
> right, I just noticed it's ascii :-) That isn't going to work well...

Ben,

I already send my workable combination of u-boot and RCW privately to you, 
please take a try.

Tiejun

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

Ok, so I found this one on the SDK ISO: rcw_15g_2000mhz.bin

I flashed that, did pix altbank, I'm now booted from Bank 4 ... and PCIe
is still showing nothing. I have cards in slots 4 and 7 (assuming that's
the right numbering, ie, 7 is the top one).

Are we sure we don't have a problem with some DIP ? I saw some of them
control some SERDES stuff (SW5 iirc)

Cheers,
Ben.

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

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Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 07:01 +0000, Zang Roy-R61911 wrote:

> I just tried your RCW. one e1000 card works in slot7.
> we may need to check others ...

Tried 4 and 7 ...

Note that this *used* to work. Last year I had this machine up with 2
cards doing things. Not sure what changed, it's possible that the DIP
got inadvertently changed. Or somebody stole a jumper from it in the
lab :-)

> U-Boot 2013.01-00078-g2741c99 (May 03 2013 - 00:20:41)
> 
> CPU0:  P5020E, Version: 2.0, (0x82280020)
> Core:  E5500, Version: 1.2, (0x80240012)
> Clock Configuration:
>        CPU0:2000 MHz, CPU1:2000 MHz, 
>        CCB:800  MHz,
>        DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100  MHz
>        FMAN1: 600 MHz
>        QMAN:  400 MHz
>        PME:   400 MHz
> L1:    D-cache 32 kB enabled
>        I-cache 32 kB enabled
> Reset Configuration Word (RCW):
>        00000000: 0c540000 00000000 1e120000 00000000
>        00000010: d8984a01 03002000 de800000 41000000
>        00000020: 00000000 00000000 00000000 10070000
>        00000030: 00000000 00000000 00000000 00000000

My RCW is identical

> Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x02, FPGA Ver: 0x04, vBank: 4

Mine is:
Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 4                                                        

> SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz 

Same.

> I2C:   ready
> SPI:   ready
> DRAM:  Initializing....using SPD
> Detected UDIMM i-DIMM
> Detected UDIMM i-DIMM
> 2 GiB left unmapped
> 4 GiB (DDR3, 64-bit, CL=9, ECC on)
>        DDR Controller Interleaving Mode: cache line
>        DDR Chip-Select Interleaving Mode: CS0+CS1
> Testing 0x00000000 - 0x7fffffff
> Testing 0x80000000 - 0xffffffff
> Remap DDR 2 GiB left unmapped
> 
> POST memory PASSED
> Flash: 128 MiB
> L2:    512 KB enabled
> Corenet Platform Cache: 2048 KB enabled
> SRIO1: disabled
> SRIO2: disabled
> NAND:  1024 MiB
> MMC:  FSL_SDHC: 0
> EEPROM: Invalid ID (ff ff ff ff)
> PCIe1: Root Complex, x2, regs @ 0xfe200000
>   01:00.0     - 8086:105e - Network controller
>   01:00.1     - 8086:105e - Network controller
> PCIe1: Bus 00 - 01
> PCIe2: disabled
> PCIe3: Root Complex, no link, regs @ 0xfe202000
> PCIe3: Bus 02 - 02
> PCIe4: disabled

And I never see anything here anymore...

> In:    serial
> Out:   serial
> Err:   serial
> Net:   Initializing Fman
> Fman1: Uploading microcode version 106.1.6
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> e1000: 00:15:17:16:ce:b8
>        e1000: 00:15:17:16:ce:b9
>        FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4 [PRIME], FM1@DTSEC5, FM1@TGEC1, e1000#0
> Warning: e1000#0 MAC addresses don't match:
> Address in SROM is         00:15:17:16:ce:b8
> Address in environment is  00:1b:21:68:5e:d4
> , e1000#1
> Warning: e1000#1 using MAC address from net device
> 
> =>

RE: SATA FSL and upstreaming

[Bhushan Bharat-R65777]

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RE: SATA FSL and upstreaming

[Zang Roy-R61911]

> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Benjamin
> Herrenschmidt
> Sent: Thursday, May 16, 2013 2:59 PM
> To: Zang Roy-R61911
> Cc: Xie Shaohui-B21989; Liu Qiang-B32616; tiejun.chen; Fleming Andy-
> AFLEMING; Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
> Subject: Re: SATA FSL and upstreaming
>=20
> Ok, so I found this one on the SDK ISO: rcw_15g_2000mhz.bin
>=20
> I flashed that, did pix altbank, I'm now booted from Bank 4 ... and PCIe
> is still showing nothing. I have cards in slots 4 and 7 (assuming that's
> the right numbering, ie, 7 is the top one).
Right.
>=20
> Are we sure we don't have a problem with some DIP ? I saw some of them
> control some SERDES stuff (SW5 iirc)
Your serdes1 clock is 100MHz,which is correct.
Slot7 (PCIe1) does not need extra DIP to make it work.
Maybe you also need to update the U-boot.
Roy

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

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Lg0KUm95DQo=

RE: SATA FSL and upstreaming

[Xie Shaohui-B21989]

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dWkgWGllDQo=

RE: SATA FSL and upstreaming

[Bhushan Bharat-R65777]

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Cj4gDQo+IA0KDQo=

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 07:13 +0000, Bhushan Bharat-R65777 wrote:
> Ben, Which SDK you are using?

QorIQ-SDK-V1.3.2-PPC64E5500-20130325-yocto.iso

Cheers,
Ben.

Re: SATA FSL and upstreaming

[Timur Tabi]

On Thu, May 16, 2013 at 1:52 AM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
>> 3) run " pix altbak" command
>>
>> 4) check you are on bank4
>
> It stays on bank 0

pix altbank

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Thu, 2013-05-16 at 09:56 -0500, Timur Tabi wrote:
> On Thu, May 16, 2013 at 1:52 AM, Benjamin Herrenschmidt
> <benh@kernel.crashing.org> wrote:
> >> 3) run " pix altbak" command
> >>
> >> 4) check you are on bank4
> >
> > It stays on bank 0
> 
> pix altbank

So I got the rev2 chip today, put it in, and PCI-E is still not getting
a link. Since the LEDs of the e1000 aren't coming up at all, I *suspect*
the slots are getting no power.

Is there a power control somewhere ? Maybe some DIP or jumpers that
might have gone off ?

Cheers,
Ben.

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 13:52 +1000, Benjamin Herrenschmidt wrote:

> So I got the rev2 chip today, put it in, and PCI-E is still not getting
> a link. Since the LEDs of the e1000 aren't coming up at all, I *suspect*
> the slots are getting no power.
> 
> Is there a power control somewhere ? Maybe some DIP or jumpers that
> might have gone off ?

Forget it, reset all the jumpers to the default setup (found the doc !)
and they come up now in slot 4 and 7. It also looks like uBoot now
has an e1000 driver so I don't have to use fman (for which I believe
there is still no upstream driver right ?)

BTW. Is that normal during boot ?

Net:   Initializing Fman
Fman1: Uploading microcode version 106.1.7
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out

Cheers,
Ben.

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Benjamin
> Herrenschmidt
> Sent: Friday, June 07, 2013 12:40 PM
> To: Timur Tabi
> Cc: Xie Shaohui-B21989; Liu Qiang-B32616; Zang Roy-R61911; tiejun.chen;
> Fleming Andy-AFLEMING; Bhushan Bharat-R65777; linuxppc-
> dev@lists.ozlabs.org
> Subject: Re: SATA FSL and upstreaming
>=20
> On Fri, 2013-06-07 at 13:52 +1000, Benjamin Herrenschmidt wrote:
>=20
> > So I got the rev2 chip today, put it in, and PCI-E is still not
> > getting a link. Since the LEDs of the e1000 aren't coming up at all, I
> > *suspect* the slots are getting no power.
> >
> > Is there a power control somewhere ? Maybe some DIP or jumpers that
> > might have gone off ?
>=20
> Forget it, reset all the jumpers to the default setup (found the doc !)
> and they come up now in slot 4 and 7. It also looks like uBoot now has an
> e1000 driver so I don't have to use fman (for which I believe there is
> still no upstream driver right ?)
fman in u-boot has been up streamed.  It should work.
>=20
> BTW. Is that normal during boot ?
>=20
> Net:   Initializing Fman
> Fman1: Uploading microcode version 106.1.7 PHY reset timed out PHY reset
> timed out PHY reset timed out PHY reset timed out
You can ignore the timeout.=20
Do you plug other card (for example SGMII card) on the board?
u-boot detects some card in the slot and tries to init the PHY but fails.
Roy

Re: SATA FSL and upstreaming

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 04:45 +0000, Zang Roy-R61911 wrote:
> 
> > Forget it, reset all the jumpers to the default setup (found the doc !)
> > and they come up now in slot 4 and 7. It also looks like uBoot now has an
> > e1000 driver so I don't have to use fman (for which I believe there is
> > still no upstream driver right ?)

> fman in u-boot has been up streamed.  It should work.

I don't care much about u-boot :-) It's the kernel that matters to me.

> > 
> > BTW. Is that normal during boot ?
> > 
> > Net:   Initializing Fman
> > Fman1: Uploading microcode version 106.1.7 PHY reset timed out PHY reset
> > timed out PHY reset timed out PHY reset timed out
> You can ignore the timeout. 
> Do you plug other card (for example SGMII card) on the board?

No, only PCIe in slot 4 and 7.

> u-boot detects some card in the slot and tries to init the PHY but fails.

Cheers,
Ben.

RE: SATA FSL and upstreaming

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmVuamFtaW4gSGVycmVu
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aXMgdGhlIGZvY3VzIG5vdyAuLi4NCnRoYW5rcy4NClJveQ0K

FSL 64-bit DMA window question

[Benjamin Herrenschmidt]

Hi Folks !

Is there any specific reason why you chose 1T (40 bit) as the location
of the 64-bit DMA window ?

It happens that most current radeon adapters cannot DMA there, they have
a 40-bit DMA limit. I seem to be getting things to work fine using a
39-bit window, but I suppose that might collide with something else ?

Can you guys consider changing the default ?

Cheers,
Ben.

fsqrt

[Benjamin Herrenschmidt]

Another question...

Do you guys happen to have a patch to emulate fsqrt in the kernel ?

Fedora 19 seems to be using it ... among others.

Cheers,
Ben.

RE: fsqrt

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmVuamFtaW4gSGVycmVu
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L21hdGgtZW11L2ZzcXJ0LmMgPw0KWWVzLg0KUm95DQo=

Re: fsqrt

[tiejun.chen]

On 06/07/2013 03:41 PM, Benjamin Herrenschmidt wrote:
> Another question...
>
> Do you guys happen to have a patch to emulate fsqrt in the kernel ?

Seems this is already emulated:

arch/powerpc/math-emu/fsqrt.c

You can enable CONFIG_MATH_EMULATION to try.

Tiejun

RE: FSL 64-bit DMA window question

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmVuamFtaW4gSGVycmVu
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ciA0MGJpdD8NClJveQ0K

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 07:45 +0000, Zang Roy-R61911 wrote:
> 
> > -----Original Message-----
> > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > Another question...
> > 
> > Do you guys happen to have a patch to emulate fsqrt in the kernel ?
> > 
> > Fedora 19 seems to be using it ... among others.
> You mean this one
> arch/powerpc/math-emu/fsqrt.c ?

No. This is for setups that have no FPU, I don't think that will work
with an actual FPU.

fsqrt is an optional instruction in the architecture and FSL chips don't
use it. However it looks like Fedora is compiled with a toolchain that
generates it.

I've successfully launched the Fedora installer using this hack in the
kernel:

>From f75adba1ee91691d431e283184e15412114000d1 Mon Sep 17 00:00:00 2001
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Fri, 7 Jun 2013 18:42:44 +1000
Subject: [PATCH] Gross hack

---
 arch/powerpc/include/asm/ppc-opcode.h |    2 ++
 arch/powerpc/kernel/Makefile          |    4 ++-
 arch/powerpc/kernel/fsqrt-emu.c       |   44 +++++++++++++++++++++++++++++++++
 arch/powerpc/kernel/traps.c           |    7 ++++++
 4 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100644 arch/powerpc/kernel/fsqrt-emu.c

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index eccfc16..146c5e9 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -88,6 +88,8 @@
 #define PPC_INST_DCBA_MASK		0xfc0007fe
 #define PPC_INST_DCBAL			0x7c2005ec
 #define PPC_INST_DCBZL			0x7c2007ec
+#define PPC_INST_FSQRT			0xfc00002c
+#define PPC_INST_FSQRT_MASK		0xfc1f07fe
 #define PPC_INST_ICBT			0x7c00002c
 #define PPC_INST_ISEL			0x7c00001e
 #define PPC_INST_ISEL_MASK		0xfc00003e
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index f960a79..64c9962 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -26,6 +26,8 @@ CFLAGS_REMOVE_ftrace.o = -pg -mno-sched-epilog
 CFLAGS_REMOVE_time.o = -pg -mno-sched-epilog
 endif
 
+CFLAGS_REMOVE_fsqrt-emu.o = -msoft-float
+
 obj-y				:= cputable.o ptrace.o syscalls.o \
 				   irq.o align.o signal_32.o pmc.o vdso.o \
 				   process.o systbl.o idle.o \
@@ -34,7 +36,7 @@ obj-y				:= cputable.o ptrace.o syscalls.o \
 				   udbg.o misc.o io.o dma.o \
 				   misc_$(CONFIG_WORD_SIZE).o vdso32/
 obj-$(CONFIG_PPC64)		+= setup_64.o sys_ppc32.o \
-				   signal_64.o ptrace32.o \
+				   signal_64.o ptrace32.o fsqrt-emu.o \
 				   paca.o nvram_64.o firmware.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
 obj-$(CONFIG_PPC_BOOK3S_64)	+= cpu_setup_ppc970.o cpu_setup_pa6t.o
diff --git a/arch/powerpc/kernel/fsqrt-emu.c b/arch/powerpc/kernel/fsqrt-emu.c
new file mode 100644
index 0000000..2da4f71
--- /dev/null
+++ b/arch/powerpc/kernel/fsqrt-emu.c
@@ -0,0 +1,44 @@
+#include <linux/kernel.h>
+#include <linux/preempt.h>
+#include <linux/sched.h>
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/switch_to.h>
+
+static double crackpot_sqrt(double val)
+{
+    int i;
+    float x, y;
+    const float f = 1.5F;
+
+    x = val * 0.5F;
+    y  = val;
+    i  = * ( int * ) &y;
+    i  = 0x5f3759df - ( i >> 1 );
+    y  = * ( float * ) &i;
+    y  = y * ( f - ( x * y * y ) );
+    y  = y * ( f - ( x * y * y ) );
+    return val * y;
+}
+
+int emulate_fsqrt_inst(struct pt_regs *regs, u32 instword)
+{
+	unsigned int frt_r = (instword >> 21) & 0x1f;
+	unsigned int frb_r = (instword >> 21) & 0x1f;
+	double frt, frb;
+
+	/* XXX THIS WHOLE THING IS JUST A HACK ! */
+	preempt_disable();
+	enable_kernel_fp();
+	frb = current->thread.fpr[frb_r][0];
+	frt = crackpot_sqrt(frb);
+	current->thread.fpr[frt_r][0] = frt;
+	if (instword & 1)
+		regs->ccr &= 0xff00ffff;
+	preempt_enable();
+
+	return 0;
+}
+
+
+
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 6dfbb38..e677792 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -938,6 +938,8 @@ static int emulate_isel(struct pt_regs *regs, u32 instword)
 	return 0;
 }
 
+extern int emulate_fsqrt_inst(struct pt_regs *regs, u32 instword);
+
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
 {
@@ -1018,6 +1020,11 @@ static int emulate_instruction(struct pt_regs *regs)
 		return emulate_isel(regs, instword);
 	}
 
+	if ((instword & PPC_INST_FSQRT_MASK) == PPC_INST_FSQRT) {
+		PPC_WARN_EMULATED(isel, regs);
+		return emulate_fsqrt_inst(regs, instword);
+	}
+
 #ifdef CONFIG_PPC64
 	/* Emulate the mfspr rD, DSCR. */
 	if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
-- 
1.7.10.4

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 15:46 +0800, tiejun.chen wrote:
> On 06/07/2013 03:41 PM, Benjamin Herrenschmidt wrote:
> > Another question...
> >
> > Do you guys happen to have a patch to emulate fsqrt in the kernel ?
> 
> Seems this is already emulated:
> 
> arch/powerpc/math-emu/fsqrt.c
> 
> You can enable CONFIG_MATH_EMULATION to try.

Is math emu expected to work at all on top of a real FPU ? I though it
didn't ... maybe I'm wrong.

Cheers,
Ben.

Re: FSL 64-bit DMA window question

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 07:58 +0000, Zang Roy-R61911 wrote:
> 
> > -----Original Message-----
> > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > 
> > Hi Folks !
> > 
> > Is there any specific reason why you chose 1T (40 bit) as the location of
> > the 64-bit DMA window ?
> > 
> > It happens that most current radeon adapters cannot DMA there, they have
> > a 40-bit DMA limit. I seem to be getting things to work fine using a 39-
> > bit window, but I suppose that might collide with something else ?
> T4240 has 40bit physical address ability.
> "
> This chip's 40-bit, physical address map consists of local space and external address
> space. For the local address map, 32 local access windows (LAWs) define mapping
> within the local 40-bit (1 TB) address space. Inbound and outbound translation windows
> can map the chip into a larger system address space such as the RapidIO or PCIe 64-bit
> address environment. This functionality is included in the address translation and
> mapping units (ATMUs).
> 
> "
> That should be the reason to set the DMA window to 40-bit.

I see. However if the top half of that space isn't used by default with
whatever is our current setup, it makes sense to move down the 64-bit
DMA window to allow those adapters to function don't you think ?

I'm trying to turn those FSL boxes into nice ppc64 dev. workstations :-)

Cheers,
Ben.

> > 
> > Can you guys consider changing the default ?
> Any collide for 40bit?
> Roy

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 18:53 +1000, Benjamin Herrenschmidt wrote:

> +
> +static double crackpot_sqrt(double val)
> +{
> +    int i;
> +    float x, y;
> +    const float f = 1.5F;
> +
> +    x = val * 0.5F;
> +    y  = val;
> +    i  = * ( int * ) &y;
> +    i  = 0x5f3759df - ( i >> 1 );
> +    y  = * ( float * ) &i;
> +    y  = y * ( f - ( x * y * y ) );
> +    y  = y * ( f - ( x * y * y ) );
> +    return val * y;
> +}
> +

For those interested, this is the Quake3 sqrt from Carmack ... there's
plenty of literature about it one or two google clicks away :-)

Cheers,
Ben.

Re: fsqrt

[tiejun.chen]

On 06/07/2013 04:53 PM, Benjamin Herrenschmidt wrote:
> On Fri, 2013-06-07 at 15:46 +0800, tiejun.chen wrote:
>> On 06/07/2013 03:41 PM, Benjamin Herrenschmidt wrote:
>>> Another question...
>>>
>>> Do you guys happen to have a patch to emulate fsqrt in the kernel ?
>>
>> Seems this is already emulated:
>>
>> arch/powerpc/math-emu/fsqrt.c
>>
>> You can enable CONFIG_MATH_EMULATION to try.
>
> Is math emu expected to work at all on top of a real FPU ? I though it
> didn't ... maybe I'm wrong.

As I understand often the real FPU can't support all float instructions, so we 
have to enable this to emulate those unsupported float instructions in that 
scenario.

Tiejun

RE: FSL 64-bit DMA window question

[Zang Roy-R61911]

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RE: fsqrt

[David Laight]

> > +
> > +static double crackpot_sqrt(double val)
> > +{
> > +    int i;
> > +    float x, y;
> > +    const float f =3D 1.5F;
> > +
> > +    x =3D val * 0.5F;
> > +    y  =3D val;
> > +    i  =3D * ( int * ) &y;
> > +    i  =3D 0x5f3759df - ( i >> 1 );
> > +    y  =3D * ( float * ) &i;
> > +    y  =3D y * ( f - ( x * y * y ) );
> > +    y  =3D y * ( f - ( x * y * y ) );
> > +    return val * y;
> > +}
> > +
>=20
> For those interested, this is the Quake3 sqrt from Carmack ... there's
> plenty of literature about it one or two google clicks away :-)

I guess that is a rough enough approximation for graphics.

However it will be miscompiled unless i and y are put in a union.

	David

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 17:02 +0800, tiejun.chen wrote:
> On 06/07/2013 04:53 PM, Benjamin Herrenschmidt wrote:
> > On Fri, 2013-06-07 at 15:46 +0800, tiejun.chen wrote:
> >> On 06/07/2013 03:41 PM, Benjamin Herrenschmidt wrote:
> >>> Another question...
> >>>
> >>> Do you guys happen to have a patch to emulate fsqrt in the kernel ?
> >>
> >> Seems this is already emulated:
> >>
> >> arch/powerpc/math-emu/fsqrt.c
> >>
> >> You can enable CONFIG_MATH_EMULATION to try.
> >
> > Is math emu expected to work at all on top of a real FPU ? I though it
> > didn't ... maybe I'm wrong.
> 
> As I understand often the real FPU can't support all float instructions, so we 
> have to enable this to emulate those unsupported float instructions in that 
> scenario.

Ok, two things come to mind here:

  - do_mathemu doesn't do giveup_fpu() so the FPU state might still be
in the "live" FP registers and not in the thread_struct, so it can't
work... unless I missed something.

  - mathemu uses solely integers. For something like fsqrt it's going to
suck a lot more than implementing using floating points in the kernel.

Cheers,
Ben.

Re: FSL 64-bit DMA window question

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 09:44 +0000, Zang Roy-R61911 wrote:
> 
> > -----Original Message-----
> > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > 
> > On Fri, 2013-06-07 at 07:58 +0000, Zang Roy-R61911 wrote:
> > >
> > > > -----Original Message-----
> > > > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > > >
> > > > Hi Folks !
> > > >
> > > > Is there any specific reason why you chose 1T (40 bit) as the
> > location of
> > > > the 64-bit DMA window ?
> > > >
> > > > It happens that most current radeon adapters cannot DMA there, they
> > have
> > > > a 40-bit DMA limit. I seem to be getting things to work fine using a
> > 39-
> > > > bit window, but I suppose that might collide with something else ?
> > > T4240 has 40bit physical address ability.
> > > "
> > > This chip's 40-bit, physical address map consists of local space and
> > external address
> > > space. For the local address map, 32 local access windows (LAWs) define
> > mapping
> > > within the local 40-bit (1 TB) address space. Inbound and outbound
> > translation windows
> > > can map the chip into a larger system address space such as the RapidIO
> > or PCIe 64-bit
> > > address environment. This functionality is included in the address
> > translation and
> > > mapping units (ATMUs).
> > >
> > > "
> > > That should be the reason to set the DMA window to 40-bit.
> > I see. However if the top half of that space isn't used by default with
> > whatever is our current setup, it makes sense to move down the 64-bit
> > DMA window to allow those adapters to function don't you think ?
> Good to me.
> 40 bit DMA will prevent your radeon video card from working. Right?
> Your P5020 DS system only support 36 bit physical address.

We should probably put the "64-bit DMA" address in the device-tree,
that way if somebody wish to do differently they can.
> > 
> > I'm trying to turn those FSL boxes into nice ppc64 dev. workstations :-)
> That is good. I'd like to see how long it will build a kernel ...

I'll tell you when you send me a 24 cores e6500 :-)

In the meantime I'll build them on my 16-cores (64 threads) P7+ :-)

I'm more thinking about how to seed general community developers with
machines they can use to ensure things work fine on ppc64 without having
to get them a rack in their basement...

Cheers,
Ben.

> thanks.
> Roy

Re: SATA FSL and upstreaming

[Timur Tabi]

Benjamin Herrenschmidt wrote:
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out

This usually means that your RCW does not match your dip switch settings.

-- 
Timur Tabi

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 11:48 +0100, David Laight wrote:
> > For those interested, this is the Quake3 sqrt from Carmack ...
> there's
> > plenty of literature about it one or two google clicks away :-)
> 
> I guess that is a rough enough approximation for graphics.
> 
> However it will be miscompiled unless i and y are put in a union.

It won't in the kernel disables strict aliasing :-)

Anyway, that was just a hack and plenty enough to get anaconda going,
the bloody thing only uses fsqrt because it's python crappola does
something like exp(1.0) / sqrt(2.0) as part of its random number stuff.

Honestly I could have made it just return 1.0 and it would probably have
worked :-)

However, my point remains, it would be very much worthwhile for the
kernel to have some reasonable emulation of those missing instructions
(afaik only a handful) like we have for isel, popcnt* etc... especially
since distros seem to be keen on enabling the use of them in their
toolchain.

I don't personally have the bandwidth to do a clean implementation (that
handles FP exceptions, NaNs, FPSCR, etc...) but I believe it would be
valuable if somebody else did (hint hint hint :-) since without this,
Fedora ppc64 is basically going to be a non-started on those chips.

BTW. Did you guys (ie. FSL) finally add fsqrt to e6500 or it's still
out ? 

Cheers,
Ben.

Re: fsqrt

[Kumar Gala]

On Jun 7, 2013, at 7:14 AM, Benjamin Herrenschmidt wrote:

> On Fri, 2013-06-07 at 11:48 +0100, David Laight wrote:
>>> For those interested, this is the Quake3 sqrt from Carmack ...
>> there's
>>> plenty of literature about it one or two google clicks away :-)
>> 
>> I guess that is a rough enough approximation for graphics.
>> 
>> However it will be miscompiled unless i and y are put in a union.
> 
> It won't in the kernel disables strict aliasing :-)
> 
> Anyway, that was just a hack and plenty enough to get anaconda going,
> the bloody thing only uses fsqrt because it's python crappola does
> something like exp(1.0) / sqrt(2.0) as part of its random number stuff.
> 
> Honestly I could have made it just return 1.0 and it would probably have
> worked :-)
> 
> However, my point remains, it would be very much worthwhile for the
> kernel to have some reasonable emulation of those missing instructions
> (afaik only a handful) like we have for isel, popcnt* etc... especially
> since distros seem to be keen on enabling the use of them in their
> toolchain.
> 
> I don't personally have the bandwidth to do a clean implementation (that
> handles FP exceptions, NaNs, FPSCR, etc...) but I believe it would be
> valuable if somebody else did (hint hint hint :-) since without this,
> Fedora ppc64 is basically going to be a non-started on those chips.
> 
> BTW. Did you guys (ie. FSL) finally add fsqrt to e6500 or it's still
> out ? 
> 
> Cheers,
> Ben.

Pretty sure fsqrt is still out of e6500.

- k

Re: FSL 64-bit DMA window question

[Scott Wood]

On 06/07/2013 05:01:28 PM, Scott Wood wrote:
> On 06/07/2013 07:09:20 AM, Benjamin Herrenschmidt wrote:
>> On Fri, 2013-06-07 at 09:44 +0000, Zang Roy-R61911 wrote:
>> >
>> > > -----Original Message-----
>> > > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
>> > >
>> > > On Fri, 2013-06-07 at 07:58 +0000, Zang Roy-R61911 wrote:
>> > > >
>> > > > > -----Original Message-----
>> > > > > From: Benjamin Herrenschmidt =20
>> [mailto:benh@kernel.crashing.org]
>> > > > >
>> > > > > Hi Folks !
>> > > > >
>> > > > > Is there any specific reason why you chose 1T (40 bit) as the
>> > > location of
>> > > > > the 64-bit DMA window ?
>> > > > >
>> > > > > It happens that most current radeon adapters cannot DMA =20
>> there, they
>> > > have
>> > > > > a 40-bit DMA limit. I seem to be getting things to work fine =20
>> using a
>> > > 39-
>> > > > > bit window, but I suppose that might collide with something =20
>> else ?
>> > > > T4240 has 40bit physical address ability.
>> > > > "
>> > > > This chip's 40-bit, physical address map consists of local =20
>> space and
>> > > external address
>> > > > space. For the local address map, 32 local access windows =20
>> (LAWs) define
>> > > mapping
>> > > > within the local 40-bit (1 TB) address space. Inbound and =20
>> outbound
>> > > translation windows
>> > > > can map the chip into a larger system address space such as =20
>> the RapidIO
>> > > or PCIe 64-bit
>> > > > address environment. This functionality is included in the =20
>> address
>> > > translation and
>> > > > mapping units (ATMUs).
>> > > >
>> > > > "
>> > > > That should be the reason to set the DMA window to 40-bit.
>> > > I see. However if the top half of that space isn't used by =20
>> default with
>> > > whatever is our current setup, it makes sense to move down the =20
>> 64-bit
>> > > DMA window to allow those adapters to function don't you think ?
>> > Good to me.
>> > 40 bit DMA will prevent your radeon video card from working. Right?
>> > Your P5020 DS system only support 36 bit physical address.
>>=20
>> We should probably put the "64-bit DMA" address in the device-tree,
>> that way if somebody wish to do differently they can.
>=20
> I thought the device tree was for describing the hardware, rather =20
> than configuration? :-)
> A kernel command line option might be more appropriate, unless you =20
> just mean describing the difference between e6500 (which supports 40 =20
> bit addresses) and previous chips (which support 36 bits), rather =20
> than an ability to move it earlier even on e6500.
>=20
> That said, the current code looks broken -- it checks whether a card =20
> can do 40-bit DMA, and if it can, it sets the DMA offset to (1ULL << =20
> 40), thus requiring 41-bit DMA.  It should be > instead of >=3D in =20
> fsl_pci_dma_set_mask.
>=20
> Maybe we could by default use the size of actual RAM, rather than the =20
> physical address space.  Then only odd scenarios such as DMA to =20
> non-kernel-owned RAM would need manual adjustment (MSIs would still =20
> go through the special window below 4G).
>=20
> -Scott
=

Re: FSL 64-bit DMA window question

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 17:02 -0500, Scott Wood wrote:
> O
> > I thought the device tree was for describing the hardware, rather  
> > than configuration? :-)

A bit of both really. See things like /chosen etc...

Also to what extent a MAC address is HW vs. configuration ? :-)

The HW configuration for a given boards (ie, internal address map,
location of the various bridge windows etc...) is a fairly common thing
to put in a device-tree.

If the PCI outbound windows are there (and they are), why not the
inbound ones ? IE, it's not far fetched. 

> > A kernel command line option might be more appropriate, unless you  
> > just mean describing the difference between e6500 (which supports 40  
> > bit addresses) and previous chips (which support 36 bits), rather  
> > than an ability to move it earlier even on e6500.

Well, so we could indeed locate it at 36 on e5500 and that would clear
the current use case and break again on e6500... or we can make it
depend on the overall address map of the board, which is described
in the device-tree. IE, if you don't "locate" anything above 39-bit
in our address map, then using 39 for the window is ok. IE. It's a
choice. A server board setup that doesn't need gfx but want address
space for some other things wouldn't care.

A board wanting to use gfx (either desktop style, or some of the
military applications I've seen using FSL chips and radeons) would chose
the address map differently to allow the radeons to work.

> > That said, the current code looks broken -- it checks whether a card  
> > can do 40-bit DMA, and if it can, it sets the DMA offset to (1ULL <<  
> > 40), thus requiring 41-bit DMA.  It should be > instead of >= in  
> > fsl_pci_dma_set_mask.

Yes, this was broken for a while, I remember mentioning it a while back
but never actually sending a patch to fix it ... oops ;-)

> > Maybe we could by default use the size of actual RAM, rather than the  
> > physical address space.  Then only odd scenarios such as DMA to  
> > non-kernel-owned RAM would need manual adjustment (MSIs would still  
> > go through the special window below 4G).

You also need to account for other on-chip MMIOs no ? Or do you never
intend to let PCI devices hit them ?

If not, then top of RAM aligned to the next power of two sounds like a
great plan.

Also, those radeons are *also* broken for 64-bit MSIs (they advertize
support but are limited to 40-bit of address). We have added hacks to
deal with that in pseries that I was thinking of generalizing.

Cheers,
Ben.

Re: FSL 64-bit DMA window question

[Scott Wood]

On 06/07/2013 05:09:54 PM, Benjamin Herrenschmidt wrote:
> On Fri, 2013-06-07 at 17:02 -0500, Scott Wood wrote:
> > O
> > > I thought the device tree was for describing the hardware, rather
> > > than configuration? :-)
>=20
> A bit of both really. See things like /chosen etc...
>=20
> Also to what extent a MAC address is HW vs. configuration ? :-)

Normally I'd consider that hardware, unless you're overriding it for =20
some reason.

> The HW configuration for a given boards (ie, internal address map,
> location of the various bridge windows etc...) is a fairly common =20
> thing
> to put in a device-tree.

Sure, there's some stuff that is technically software config, but which =20
is easier to treat as a fixed property of the hardware once U-Boot is =20
done setting it up.  But U-Boot doesn't have anything to do with this =20
DMA window...

> If the PCI outbound windows are there (and they are), why not the
> inbound ones ? IE, it's not far fetched.

PCI outbound windows (and the LAWs that back them up) are set up by =20
U-Boot.  With the current FSL kernel code, if you set it to something =20
that isn't covered by a PCIe LAW from U-Boot, it won't work.

> > > A kernel command line option might be more appropriate, unless you
> > > just mean describing the difference between e6500 (which supports =20
> 40
> > > bit addresses) and previous chips (which support 36 bits), rather
> > > than an ability to move it earlier even on e6500.
>=20
> Well, so we could indeed locate it at 36 on e5500 and that would clear
> the current use case and break again on e6500... or we can make it
> depend on the overall address map of the board, which is described
> in the device-tree. IE, if you don't "locate" anything above 39-bit
> in our address map, then using 39 for the window is ok. IE. It's a
> choice. A server board setup that doesn't need gfx but want address
> space for some other things wouldn't care.

I suppose we could put in the device tree the highest address that has =20
been configured for anything...  though for that to be useful we'd need =20
to get out of the habit of putting CCSR near the top of the physical =20
address space.

> > > Maybe we could by default use the size of actual RAM, rather than =20
> the
> > > physical address space.  Then only odd scenarios such as DMA to
> > > non-kernel-owned RAM would need manual adjustment (MSIs would =20
> still
> > > go through the special window below 4G).
>=20
> You also need to account for other on-chip MMIOs no ? Or do you never
> intend to let PCI devices hit them ?

I don't think we normally need that (other than MSIs, which have a =20
special window under 4G)...  The question is whether it's better to let =20
odd use cases work without having to manually move the DMA window, at =20
the cost of decreased out-of-the-box performance with common PCIe cards.

-Scott=

Re: FSL 64-bit DMA window question

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 17:34 -0500, Scott Wood wrote:
> > You also need to account for other on-chip MMIOs no ? Or do you never
> > intend to let PCI devices hit them ?
> 
> I don't think we normally need that (other than MSIs, which have a  
> special window under 4G)...  The question is whether it's better to let  
> odd use cases work without having to manually move the DMA window, at  
> the cost of decreased out-of-the-box performance with common PCIe cards.

Sorry, I didn't parse what the tradeoff is here...

Putting the inbound window above memory seems like a reasonable option then
(at least as a default that the board can override).

I sincerely hope those radeons are the only remaining things with that sort of
limitation but you never know ... it's all x86 fault of course for never having
used high DMA windows :-)

Cheers,
Ben.

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 14:19 -0500, Kumar Gala wrote:
> > I don't personally have the bandwidth to do a clean implementation (that
> > handles FP exceptions, NaNs, FPSCR, etc...) but I believe it would be
> > valuable if somebody else did (hint hint hint :-) since without this,
> > Fedora ppc64 is basically going to be a non-started on those chips.
> > 
> > BTW. Did you guys (ie. FSL) finally add fsqrt to e6500 or it's still
> > out ? 
> > 
> > Cheers,
> > Ben.
> 
> Pretty sure fsqrt is still out of e6500.

Ok, thinking out loud... looks like we might be able to just use existing 
math-emu for that. From what I can tell, all it needs (other than enabling
the config option), is a call to flush_fp_to_thread(current);

While talking math-emu... we seem to have some duplication between the
code on do_mathemu which can be compiled without CONFIG_MATH_EMULATION and
in this case only just emulates loads/stores/fmr and the code in
arch/powerpc/kernel/softemu8xx.c.

Is there any reason we can't just get rid of the latter ?

Cheers,
Ben.

Re: fsqrt

[Benjamin Herrenschmidt]

On Sat, 2013-06-08 at 09:23 +1000, Benjamin Herrenschmidt wrote:
> Ok, thinking out loud... looks like we might be able to just use existing 
> math-emu for that. From what I can tell, all it needs (other than enabling
> the config option), is a call to flush_fp_to_thread(current);
> 
> While talking math-emu... we seem to have some duplication between the
> code on do_mathemu which can be compiled without CONFIG_MATH_EMULATION and
> in this case only just emulates loads/stores/fmr and the code in
> arch/powerpc/kernel/softemu8xx.c.
> 
> Is there any reason we can't just get rid of the latter ?

Or just git completely rid of that "minimal emulation" ...

Cheers,
Ben.

Re: FSL 64-bit DMA window question

[Scott Wood]

On 06/07/2013 05:39:53 PM, Benjamin Herrenschmidt wrote:
> On Fri, 2013-06-07 at 17:34 -0500, Scott Wood wrote:
> > > You also need to account for other on-chip MMIOs no ? Or do you =20
> never
> > > intend to let PCI devices hit them ?
> >
> > I don't think we normally need that (other than MSIs, which have a
> > special window under 4G)...  The question is whether it's better to =20
> let
> > odd use cases work without having to manually move the DMA window, =20
> at
> > the cost of decreased out-of-the-box performance with common PCIe =20
> cards.
>=20
> Sorry, I didn't parse what the tradeoff is here...

I just meant that a PCIe device targeting something other than RAM, =20
CCSR (it's not just MSIs that are mapped through the special window), =20
or another PCIe is a rather unusual case -- not something that you'd =20
see by just plugging in an ordinary PCIe card.  The tradeoff is that if =20
we accommodate this strange use case, boards like the radeon would need =20
to use swiotlb (once we fix the > versus >=3D bug) unless the user tweaks =20
the DMA window.

It may be best to stick with the default that makes everything work, =20
even if a broken PCIe card ends up being a bit slower out of the box, =20
even if the PCIe-to-MMIO use case is weird and would require custom =20
setup anyway.  OTOH, did we ever care about 32-bit DMA being able to =20
access MMIO?

> Putting the inbound window above memory seems like a reasonable =20
> option then
> (at least as a default that the board can override).
>=20
> I sincerely hope those radeons are the only remaining things with =20
> that sort of
> limitation but you never know ... it's all x86 fault of course for =20
> never having
> used high DMA windows :-)

Hmm... Why are we using this special window at all?  Can't we just have =20
one large identity mapping starting at zero, with the MSI window =20
presumably taking precedence?  The manual is a bit vague on whether =20
inbound windows can overlap with priority... in EP mode it says it =20
does, and the RC section is silent.  Do we currently ever overlap =20
PCICSRBAR with a real window?

-Scott=

Re: fsqrt

[Benjamin Herrenschmidt]

On Sat, 2013-06-08 at 09:25 +1000, Benjamin Herrenschmidt wrote:
> On Sat, 2013-06-08 at 09:23 +1000, Benjamin Herrenschmidt wrote:
> > Ok, thinking out loud... looks like we might be able to just use existing 
> > math-emu for that. From what I can tell, all it needs (other than enabling
> > the config option), is a call to flush_fp_to_thread(current);
> > 
> > While talking math-emu... we seem to have some duplication between the
> > code on do_mathemu which can be compiled without CONFIG_MATH_EMULATION and
> > in this case only just emulates loads/stores/fmr and the code in
> > arch/powerpc/kernel/softemu8xx.c.
> > 
> > Is there any reason we can't just get rid of the latter ?
> 
> Or just git completely rid of that "minimal emulation" ...

Right, looking more, the code really sucks. Either you use the existing
apparent ability for MATH_EMU to operate in minimal mode, ie,
load/store/fmr only (which seems to do exactly the same thing as the
code in softemu8xx.c which we can then get rid of), or just get rid of
that minimal mode alltogether.

And while at it make it a general config option for all soft-emu
processors (there is no bloody reason why that should be 8xx specfic) or
just get rid of the whole concept of half-emulation.

Ie. CONFIG_MATH_EMULATION/CONFIG_MATH_HALF_ASSED_EMULATION

Ben.

Re: FSL 64-bit DMA window question

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 18:29 -0500, Scott Wood wrote:

> I just meant that a PCIe device targeting something other than RAM,  
> CCSR (it's not just MSIs that are mapped through the special window),  
> or another PCIe is a rather unusual case -- not something that you'd  
> see by just plugging in an ordinary PCIe card.  The tradeoff is that if  
> we accommodate this strange use case, boards like the radeon would need  
> to use swiotlb (once we fix the > versus >= bug) unless the user tweaks  
> the DMA window.

Yeah, well, swiotlb won't work for radeon anyway. It has its own
"mmu" (a GART really) and will constantly want to pin pages in it,
swiotlb will be at best a mess and at worst will just not work.

> It may be best to stick with the default that makes everything work,  
> even if a broken PCIe card ends up being a bit slower out of the box,  
> even if the PCIe-to-MMIO use case is weird and would require custom  
> setup anyway.  OTOH, did we ever care about 32-bit DMA being able to  
> access MMIO?

Not that I know of.

> Hmm... Why are we using this special window at all?  Can't we just have  
> one large identity mapping starting at zero, with the MSI window  
> presumably taking precedence? 

Then you'd have to reserve the RAM covered by the MSI window, not
necessarily a big deal. It would also still allow swiotlb to work, so it
actually doesn't seem like a bad idea if you don't have an actual /
usable iommu.

So if it works, I like that idea even better.

>  The manual is a bit vague on whether  
> inbound windows can overlap with priority... in EP mode it says it  
> does, and the RC section is silent.  Do we currently ever overlap  
> PCICSRBAR with a real window?

Cheers,
Ben.

Re: fsqrt

[Dan Malek]

On Jun 7, 2013, at 4:30 PM, Benjamin Herrenschmidt =
<benh@kernel.crashing.org> wrote:

> Right, looking more, the code really sucks.

Hey!  :)

> =85.  Either you use the existing
> apparent ability for MATH_EMU to operate in minimal mode, ie,
> load/store/fmr only (which seems to do exactly the same thing as the
> code in softemu8xx.c which we can then get rid of), or just get rid of
> that minimal mode altogether.

The purpose for that "minimal code" was the signal handlers were =
hand-coded assembly that always did the FPU load/store regardless of =
compiler flags.  Over time, it became convenient to emulate a few =
others, even with user space math emulation, for similar reasons.

> And while at it make it a general config option for all soft-emu
> processors (there is no bloody reason why that should be 8xx specfic) =
or
> just get rid of the whole concept of half-emulation.

Looks like the code just evolved and the 8xx was never cleaned up.

The partial emulation is a convenience for the libraries that may still =
have FP instructions directly coded.  There are also permutations of =
real FPU but not all instructions, and no FPU to consider for fetching =
operands and storing results to be considered for the various =
configuration options.

Thanks.

	-- Dan

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 17:20 -0700, Dan Malek wrote:

> The purpose for that "minimal code" was the signal handlers were
> hand-coded assembly that always did the FPU load/store regardless of
> compiler flags.  Over time, it became convenient to emulate a few
> others, even with user space math emulation, for similar reasons.

The question is whether this is still relevant ? And if the answer is
yes, we still want that "minimum" emulation of load/stores/fmr as an
option, is there any reason why we can't replace the one in softemu8xx
with the existing (and unused) equivalent in do_mathemu ?

Cheers,
Ben.

Re: fsqrt

[Dan Malek]

Hi Ben.

On Jun 7, 2013, at 5:34 PM, Benjamin Herrenschmidt =
<benh@kernel.crashing.org> wrote:

> The question is whether this is still relevant ?

The only answer I could provide is that it's dependent upon the =
libraries and how the distributions are built.  It's also dependent upon =
processors with hardware FP that don't implement all instructions in =
hardware (who had that bright idea? :))  If distributions are fully all =
soft-fp in user space or all hardware FP, it removes the one reason that =
started the whole partial emulation option.

> =85  And if the answer is
> yes,

There are multiple options, but I believe they are solved today.  One is =
the libraries coded with hardware load/store that are used by soft-fp, =
another is hardware FP that doesn't implement all instructions in =
hardware (which it seems is the basis of this thread, although I thought =
was already solved).  The variation here is that in the first case you =
have to read/write user space soft-fp stack "registers," while in the =
latter you read/write real FP registers.  There used to be the third =
variation where the stack was allocated and the emulation had to write =
both places due to compiler function APIs or optimizations.  Of course, =
then there is the full-up kernel emulation where hardware is entirely =
lacking.

> =85 we still want that "minimum" emulation of load/stores/fmr as an
> option, is there any reason why we can't replace the one in softemu8xx
> with the existing (and unused) equivalent in do_mathemu ?

It appears to me that 8xx custom code can be removed.  I guess I should =
try to boot it up, if anyone even cares these days. :)

Thanks.

	-- Dan

Re: fsqrt

[Benjamin Herrenschmidt]

On Fri, 2013-06-07 at 18:13 -0700, Dan Malek wrote:
> Hi Ben.
> 
> On Jun 7, 2013, at 5:34 PM, Benjamin Herrenschmidt
> <benh@kernel.crashing.org> wrote:
> 
> > The question is whether this is still relevant ?
> 
> The only answer I could provide is that it's dependent upon the
> libraries and how the distributions are built.  It's also dependent
> upon processors with hardware FP that don't implement all instructions
> in hardware (who had that bright idea? :))  If distributions are fully
> all soft-fp in user space or all hardware FP, it removes the one
> reason that started the whole partial emulation option.

I'm not questioning the relevance of math-emu as a whole, but of the
tiny subset which is duplicated in math-emu and softemu8xx, which
emulates only load/stores/fmr.

If userspace is built with hard FP it is likely to use more than just
those handful of instructions...

> > …  And if the answer is
> > yes,
> 
> There are multiple options, but I believe they are solved today.  One
> is the libraries coded with hardware load/store that are used by
> soft-fp, another is hardware FP that doesn't implement all
> instructions in hardware (which it seems is the basis of this thread,
> although I thought was already solved). 

Yes, it's indeed the basis of that thread, and yes, I though it was
already solved as well but unless I missed something it is not, because
the current Program Check handler calls do_mathemu without first
flushing the hard FP state into the thread_struct.

However it's quite possible (I'll test when I get back to the office)
that this it the only fix necessary, which is a one liner, to make
CONFIG_MATH_EMULATION work just fine in that case.

> The variation here is that in the first case you have to read/write
> user space soft-fp stack "registers," while in the latter you
> read/write real FP registers. 

We never do any "user space soft-fp stack registers" handling in the
kernel. If we use full math emu (ie, no FP at all in HW), we simply use
the normal thread_struct storage of FPRs to store the "virtual" user FP
regs used by the emulation.

If use space uses full soft-fp (ie, -msoft-float), we should never see
any of it in the kernel.

>  There used to be the third variation where the stack was allocated
> and the emulation had to write both places due to compiler function
> APIs or optimizations.  Of course, then there is the full-up kernel
> emulation where hardware is entirely lacking.

I don't know anything about that "3rd option", it certainly doesn't have
any kernel impact that I can see :-) Full up emulation is of course
still there.

> > … we still want that "minimum" emulation of load/stores/fmr as an
> > option, is there any reason why we can't replace the one in
> softemu8xx
> > with the existing (and unused) equivalent in do_mathemu ?
> 
> It appears to me that 8xx custom code can be removed.  I guess I
> should try to boot it up, if anyone even cares these days. :)

Thanks,

Cheers,
Ben.

Re: fsqrt

[Benjamin Herrenschmidt]

The interesting thing I'm finding is that our math-emu is actually
quite busted :-)

For example look at fsqrt. It's defined as type AB which is incorrect,
it should be type XB. It ends up looking for it's arguments in the wrong
registers, same for fsrqts, fre, and a few others.

Also quite a few functions are simply left unimplemented... (fre is
completely missing from the decode, fres is there but returns -ENOSYS,
as does frsqrte, etc...)

I'll post a quick for for fsqrt{s} that I need for anaconda, but I
would strongly encourage somebody from FSL (primary users of that
stuff still) to have a close look at the rest. It shouldn't be terribly
hard to fix them up and add the few missing instructions, even if not
with the amount of precision requested by the spec (better than -ENOSYS)

Cheers,
Ben.