* [Intel-gfx] [PATCH v4 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
@ 2020-09-24 17:41 José Roberto de Souza
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: José Roberto de Souza @ 2020-09-24 17:41 UTC (permalink / raw)
To: intel-gfx
For platforms without selective fetch this register is reserved so
do not write 0 to it.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8a9d0bdde1bf..4e09ae61d4aa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -942,7 +942,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
}
- if (HAS_PSR_HW_TRACKING(dev_priv))
+ if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
dev_priv->psr.psr2_sel_fetch_enabled ?
IGNORE_PSR2_HW_TRACKING : 0);
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v4 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase
2020-09-24 17:41 [Intel-gfx] [PATCH v4 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
@ 2020-09-24 17:42 ` José Roberto de Souza
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: José Roberto de Souza @ 2020-09-24 17:42 UTC (permalink / raw)
To: intel-gfx
Due to the debugfs flag, has_psr2 in CRTC state could have a different
value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO
and selective fetch) to be set to not a expected state.
So here only taking in consideration the parameter and debugfs flag
when computing PSR state, this way the CRTC state will also have
the correct state.
intel_psr_fastset_force() was already broken as
intel_psr_compute_config() was already only enabling PSR when
psr_global_enabled() and all other PSR requirements are met.
So some changes was required in this function, now it iterates over
all connectors, if it is a eDP connector and is active force a modeset
in the CRTC driving this connector, what will cause the new PSR state
to be set based on the debugfs flag.
v2:
- end connector iterator in error cases
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 73 +++++++++++++-----------
1 file changed, 41 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e09ae61d4aa..02f74b0ddec1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -91,19 +91,14 @@ static bool psr_global_enabled(struct drm_i915_private *i915)
}
}
-static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
{
- /* Cannot enable DSC and PSR2 simultaneously */
- drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&
- crtc_state->has_psr2);
-
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DISABLE:
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
default:
- return crtc_state->has_psr2;
+ return true;
}
}
@@ -729,6 +724,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
+ if (!psr2_global_enabled(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
+ return false;
+ }
+
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
@@ -817,8 +817,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp != dev_priv->psr.dp)
return;
- if (!psr_global_enabled(dev_priv))
+ if (!psr_global_enabled(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
return;
+ }
+
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
@@ -959,7 +962,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
- dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
+ dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
@@ -1029,15 +1032,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
mutex_lock(&dev_priv->psr.lock);
-
- if (!psr_global_enabled(dev_priv)) {
- drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
- goto unlock;
- }
-
intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
-
-unlock:
mutex_unlock(&dev_priv->psr.lock);
}
@@ -1222,8 +1217,8 @@ void intel_psr_update(struct intel_dp *intel_dp,
mutex_lock(&dev_priv->psr.lock);
- enable = crtc_state->has_psr && psr_global_enabled(dev_priv);
- psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
+ enable = crtc_state->has_psr;
+ psr2_enable = crtc_state->has_psr2;
if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
@@ -1320,11 +1315,12 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
{
+ struct drm_connector_list_iter conn_iter;
struct drm_device *dev = &dev_priv->drm;
struct drm_modeset_acquire_ctx ctx;
struct drm_atomic_state *state;
- struct intel_crtc *crtc;
- int err;
+ struct drm_connector *conn;
+ int err = 0;
state = drm_atomic_state_alloc(dev);
if (!state)
@@ -1334,25 +1330,38 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
state->acquire_ctx = &ctx;
retry:
- for_each_intel_crtc(dev, crtc) {
- struct intel_crtc_state *crtc_state =
- intel_atomic_get_crtc_state(state, crtc);
- if (IS_ERR(crtc_state)) {
- err = PTR_ERR(crtc_state);
- goto error;
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(conn, &conn_iter) {
+ struct drm_connector_state *conn_state;
+ struct drm_crtc_state *crtc_state;
+
+ if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
+ continue;
+
+ conn_state = drm_atomic_get_connector_state(state, conn);
+ if (IS_ERR(conn_state)) {
+ err = PTR_ERR(conn_state);
+ break;
}
- if (crtc_state->hw.active && crtc_state->has_psr) {
- /* Mark mode as changed to trigger a pipe->update() */
- crtc_state->uapi.mode_changed = true;
+ if (!conn_state->crtc)
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
+ if (IS_ERR(crtc_state)) {
+ err = PTR_ERR(crtc_state);
break;
}
+
+ /* Mark mode as changed to trigger a pipe->update() */
+ crtc_state->mode_changed = true;
}
+ drm_connector_list_iter_end(&conn_iter);
- err = drm_atomic_commit(state);
+ if (err == 0)
+ err = drm_atomic_commit(state);
-error:
if (err == -EDEADLK) {
drm_atomic_state_clear(state);
err = drm_modeset_backoff(&ctx);
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-24 17:41 [Intel-gfx] [PATCH v4 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
@ 2020-09-24 17:42 ` José Roberto de Souza
2020-10-01 11:24 ` Mun, Gwan-gyeong
2020-09-24 18:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
2020-09-24 21:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: José Roberto de Souza @ 2020-09-24 17:42 UTC (permalink / raw)
To: intel-gfx
Another step towards PSR2 selective fetch, here programming plane
selective fetch registers and MAN_TRK_CTL enabling selective fetch but
for now it is fetching the whole area of the planes.
The damaged area calculation will come as next and final step.
v2:
- removed warn on when no plane is visible in state
- removed calculations using plane damaged area in
intel_psr2_program_plane_sel_fetch()
v3:
- do not shift 16 positions the plane dst coordinates, only src is
shifted
v4:
- only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in
PLANE_SEL_FETCH_CTL
BSpec: 55229
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/display/intel_psr.c | 118 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
4 files changed, 132 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5a9d933e425a..96bc515497c1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct intel_plane *plane,
if (INTEL_GEN(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
+ if (!needs_modeset(crtc_state))
+ intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
+
if (plane->cursor.base != base ||
plane->cursor.size != fbc_ctl ||
plane->cursor.cntl != cntl) {
@@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
}
- if (!mode_changed)
- intel_psr2_sel_fetch_update(state, crtc);
+ if (!mode_changed) {
+ ret = intel_psr2_sel_fetch_update(state, crtc);
+ if (ret)
+ return ret;
+ }
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 02f74b0ddec1..f6e0a192d5e5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1166,6 +1166,39 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
intel_psr_exit(dev_priv);
}
+void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+ u32 val;
+
+ if (!crtc_state->enable_psr2_sel_fetch)
+ return;
+
+ val = plane_state ? plane_state->ctl : 0;
+ val = plane->id == PLANE_CURSOR ? val & MCURSOR_MODE :
+ val & PLANE_SEL_FETCH_CTL_ENABLE;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
+ if (!val || plane->id == PLANE_CURSOR)
+ return;
+
+ val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
+
+ val = plane_state->color_plane[color_plane].y << 16;
+ val |= plane_state->color_plane[color_plane].x;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
+ val);
+
+ /* Sizes are 0 based */
+ val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) << 16;
+ val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+}
+
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1180,16 +1213,91 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
crtc_state->psr2_man_track_ctl);
}
-void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
+ struct drm_rect *clip, bool full_update)
+{
+ u32 val = PSR2_MAN_TRK_CTL_ENABLE;
+
+ if (full_update) {
+ val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ goto exit;
+ }
+
+ if (clip->y1 == -1)
+ goto exit;
+
+ val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1);
+exit:
+ crtc_state->psr2_man_track_ctl = val;
+}
+
+static void clip_area_update(struct drm_rect *overlap_damage_area,
+ struct drm_rect *damage_area)
+{
+ if (overlap_damage_area->y1 == -1) {
+ overlap_damage_area->y1 = damage_area->y1;
+ overlap_damage_area->y2 = damage_area->y2;
+ return;
+ }
+
+ if (damage_area->y1 < overlap_damage_area->y1)
+ overlap_damage_area->y1 = damage_area->y1;
+
+ if (damage_area->y2 > overlap_damage_area->y2)
+ overlap_damage_area->y2 = damage_area->y2;
+}
+
+int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_plane_state *new_plane_state, *old_plane_state;
+ struct drm_rect pipe_clip = { .y1 = -1 };
+ struct intel_plane *plane;
+ bool full_update = false;
+ int i, ret;
if (!crtc_state->enable_psr2_sel_fetch)
- return;
+ return 0;
+
+ ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
+ if (ret)
+ return ret;
+
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+ new_plane_state, i) {
+ struct drm_rect temp;
+
+ if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
+ continue;
- crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
- PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ /*
+ * TODO: Not clear how to handle planes with negative position,
+ * also planes are not updated if they have a negative X
+ * position so for now doing a full update in this cases
+ */
+ if (new_plane_state->uapi.dst.y1 < 0 ||
+ new_plane_state->uapi.dst.x1 < 0) {
+ full_update = true;
+ break;
+ }
+
+ if (!new_plane_state->uapi.visible)
+ continue;
+
+ /*
+ * For now doing a selective fetch in the whole plane area,
+ * optimizations will come in the future.
+ */
+ temp.y1 = new_plane_state->uapi.dst.y1;
+ temp.y2 = new_plane_state->uapi.dst.y2;
+ clip_area_update(&pipe_clip, &temp);
+ }
+
+ psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
+ return 0;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 6a83c8e682e6..3eca9dcec3c0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -15,6 +15,8 @@ struct intel_crtc_state;
struct intel_dp;
struct intel_crtc;
struct intel_atomic_state;
+struct intel_plane_state;
+struct intel_plane;
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
@@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
-void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
+void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int color_plane);
#endif /* __INTEL_PSR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 63040cb0d4e1..f12425b90607 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
(plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x);
+ if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
+ intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
+
/*
* The control register self-arms if the plane was previously
* disabled. Try to make the plane enable atomic by writing
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
2020-09-24 17:41 [Intel-gfx] [PATCH v4 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
@ 2020-09-24 18:34 ` Patchwork
2020-09-24 21:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-09-24 18:34 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6048 bytes --]
== Series Details ==
Series: series starting with [v4,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
URL : https://patchwork.freedesktop.org/series/82066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9050 -> Patchwork_18564
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/index.html
Known issues
------------
Here are the changes found in Patchwork_18564 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([i915#2203])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@vgem_basic@dmabuf-export:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-tgl-y/igt@vgem_basic@dmabuf-export.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-tgl-y/igt@vgem_basic@dmabuf-export.html
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-tgl-y/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-tgl-y/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
- fi-skl-guc: [DMESG-WARN][13] ([i915#2203]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-tgl-y/igt@prime_vgem@basic-read.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-tgl-y/igt@prime_vgem@basic-read.html
#### Warnings ####
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +5 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/fi-kbl-x1275/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/fi-kbl-x1275/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (46 -> 40)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9050 -> Patchwork_18564
CI-20190529: 20190529
CI_DRM_9050: 9a9b636c74cacd2a9fe8c693792998d8d5983e24 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18564: e295c73e50256e19a4fc5060e720d231e98bc0e7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e295c73e5025 drm/i915/display: Program PSR2 selective fetch registers
64951c036b10 drm/i915/display: Check PSR parameter and flag only in state compute phase
bd2acdb50147 drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/index.html
[-- Attachment #1.2: Type: text/html, Size: 7761 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
2020-09-24 17:41 [Intel-gfx] [PATCH v4 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
` (2 preceding siblings ...)
2020-09-24 18:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
@ 2020-09-24 21:49 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-09-24 21:49 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 14058 bytes --]
== Series Details ==
Series: series starting with [v4,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
URL : https://patchwork.freedesktop.org/series/82066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9050_full -> Patchwork_18564_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18564_full:
### Piglit changes ###
#### Possible regressions ####
* spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_frontsecondarycolor-smooth-distance (NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/pig-icl-1065g7/spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_frontsecondarycolor-smooth-distance.html
* spec@glsl-1.30@execution@interpolation@interpolation-smooth-other-smooth-distance (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][2] +7 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/pig-icl-1065g7/spec@glsl-1.30@execution@interpolation@interpolation-smooth-other-smooth-distance.html
New tests
---------
New tests have been introduced between CI_DRM_9050_full and Patchwork_18564_full:
### New Piglit tests (10) ###
* spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_backcolor-smooth-none:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_backsecondarycolor-flat-distance:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_frontcolor-flat-fixed:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_frontsecondarycolor-smooth-distance:
- Statuses : 1 crash(s)
- Exec time: [0.34] s
* spec@glsl-1.30@execution@interpolation@interpolation-none-gl_frontsecondarycolor-smooth-distance:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@interpolation@interpolation-noperspective-gl_backcolor-flat-fixed:
- Statuses : 1 crash(s)
- Exec time: [0.37] s
* spec@glsl-1.30@execution@interpolation@interpolation-noperspective-gl_backsecondarycolor-flat-vertex:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@interpolation@interpolation-noperspective-gl_frontcolor-flat-vertex:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@interpolation@interpolation-smooth-gl_backcolor-smooth-vertex:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@interpolation@interpolation-smooth-other-smooth-distance:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18564_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [PASS][3] -> [TIMEOUT][4] ([i915#1958])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl5/igt@gem_userptr_blits@unsync-unmap-cycles.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@i915_selftest@mock@contexts:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198] / [i915#2278])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl10/igt@i915_selftest@mock@contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl9/igt@i915_selftest@mock@contexts.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@busy-flip@b-hdmi-a2:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#275])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-glk8/igt@kms_flip@busy-flip@b-hdmi-a2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-glk2/igt@kms_flip@busy-flip@b-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#198]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#49])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-iclb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-iclb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
- shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-iclb2/igt@kms_psr2_su@page_flip.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-iclb8/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf@blocking:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#1542])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl1/igt@perf@blocking.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl5/igt@perf@blocking.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][27] ([i915#658]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-iclb3/igt@feature_discovery@psr2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_mmap_offset@blt-coherency:
- shard-apl: [FAIL][29] ([i915#1635]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-apl6/igt@gem_mmap_offset@blt-coherency.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-apl4/igt@gem_mmap_offset@blt-coherency.html
* igt@gem_workarounds@basic-read-context:
- shard-snb: [TIMEOUT][31] ([i915#1958]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-snb5/igt@gem_workarounds@basic-read-context.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-snb1/igt@gem_workarounds@basic-read-context.html
* igt@gem_workarounds@suspend-resume:
- shard-skl: [INCOMPLETE][33] ([i915#198]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl1/igt@gem_workarounds@suspend-resume.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl2/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][35] ([i915#1899]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-tglb: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-apl: [DMESG-WARN][39] ([i915#1635] / [i915#1982]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-apl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][41] ([i915#1188]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@sw_sync@alloc_fence:
- shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl5/igt@sw_sync@alloc_fence.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl10/igt@sw_sync@alloc_fence.html
#### Warnings ####
* igt@gen9_exec_parse@allowed-all:
- shard-kbl: [DMESG-WARN][47] ([i915#1436] / [i915#716]) -> [INCOMPLETE][48] ([i915#1436])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-kbl7/igt@gen9_exec_parse@allowed-all.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-kbl7/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [FAIL][49] ([i915#1899]) -> [FAIL][50] ([i915#454])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9050/shard-skl3/igt@i915_pm_dc@dc6-psr.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/shard-skl5/igt@i915_pm_dc@dc6-psr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#275]: https://gitlab.freedesktop.org/drm/intel/issues/275
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9050 -> Patchwork_18564
CI-20190529: 20190529
CI_DRM_9050: 9a9b636c74cacd2a9fe8c693792998d8d5983e24 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18564: e295c73e50256e19a4fc5060e720d231e98bc0e7 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18564/index.html
[-- Attachment #1.2: Type: text/html, Size: 16418 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
@ 2020-10-01 11:24 ` Mun, Gwan-gyeong
2020-10-01 17:14 ` Souza, Jose
0 siblings, 1 reply; 9+ messages in thread
From: Mun, Gwan-gyeong @ 2020-10-01 11:24 UTC (permalink / raw)
To: intel-gfx, Souza, Jose
On Thu, 2020-09-24 at 10:42 -0700, José Roberto de Souza wrote:
> Another step towards PSR2 selective fetch, here programming plane
> selective fetch registers and MAN_TRK_CTL enabling selective fetch
> but
> for now it is fetching the whole area of the planes.
> The damaged area calculation will come as next and final step.
>
> v2:
> - removed warn on when no plane is visible in state
> - removed calculations using plane damaged area in
> intel_psr2_program_plane_sel_fetch()
>
> v3:
> - do not shift 16 positions the plane dst coordinates, only src is
> shifted
>
> v4:
> - only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in
> PLANE_SEL_FETCH_CTL
>
> BSpec: 55229
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 118
> ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> 4 files changed, 132 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5a9d933e425a..96bc515497c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> intel_plane *plane,
> if (INTEL_GEN(dev_priv) >= 9)
> skl_write_cursor_wm(plane, crtc_state);
>
> + if (!needs_modeset(crtc_state))
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> plane_state, 0);
> +
> if (plane->cursor.base != base ||
> plane->cursor.size != fbc_ctl ||
> plane->cursor.cntl != cntl) {
> @@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct
> intel_atomic_state *state,
>
> }
>
> - if (!mode_changed)
> - intel_psr2_sel_fetch_update(state, crtc);
> + if (!mode_changed) {
> + ret = intel_psr2_sel_fetch_update(state, crtc);
> + if (ret)
> + return ret;
> + }
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 02f74b0ddec1..f6e0a192d5e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1166,6 +1166,39 @@ static void psr_force_hw_tracking_exit(struct
> drm_i915_private *dev_priv)
> intel_psr_exit(dev_priv);
> }
>
> +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> + const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> + u32 val;
> +
> + if (!crtc_state->enable_psr2_sel_fetch)
> + return;
> +
> + val = plane_state ? plane_state->ctl : 0;
> + val = plane->id == PLANE_CURSOR ? val & MCURSOR_MODE :
> + val &
> PLANE_SEL_FETCH_CTL_ENABLE;
I could not find details of MCURSOR_MODE for selective_fetch. (on bspec
50420) why do you set MCURSOR_MODE here?
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> >id), val);
> + if (!val || plane->id == PLANE_CURSOR)
> + return;
> +
in order to set just PLANE_SEL_FETCH_CTL_ENABLE bit, I suggest to use
like this
val = intel_de_read_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
>id));
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
val|PLANE_SEL_FETCH_CTL_ENABLE);
> + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> >uapi.dst.x1;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> >id), val);
> +
> + val = plane_state->color_plane[color_plane].y << 16;
> + val |= plane_state->color_plane[color_plane].x;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> + val);
> +
> + /* Sizes are 0 based */
> + val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> 16;
> + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> >id), val);
> +}
> +
> void intel_psr2_program_trans_man_trk_ctl(const struct
> intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1180,16 +1213,91 @@ void
> intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_st
> crtc_state->psr2_man_track_ctl);
> }
>
> -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> *crtc_state,
> + struct drm_rect *clip, bool
> full_update)
> +{
> + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> +
> + if (full_update) {
> + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> + goto exit;
> + }
> +
> + if (clip->y1 == -1)
> + goto exit;
> +
> + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> >y2, 4) + 1);
> +exit:
> + crtc_state->psr2_man_track_ctl = val;
> +}
> +
> +static void clip_area_update(struct drm_rect *overlap_damage_area,
> + struct drm_rect *damage_area)
> +{
> + if (overlap_damage_area->y1 == -1) {
> + overlap_damage_area->y1 = damage_area->y1;
> + overlap_damage_area->y2 = damage_area->y2;
> + return;
> + }
> +
> + if (damage_area->y1 < overlap_damage_area->y1)
> + overlap_damage_area->y1 = damage_area->y1;
> +
> + if (damage_area->y2 > overlap_damage_area->y2)
> + overlap_damage_area->y2 = damage_area->y2;
> +}
> +
> +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_plane_state *new_plane_state, *old_plane_state;
> + struct drm_rect pipe_clip = { .y1 = -1 };
> + struct intel_plane *plane;
> + bool full_update = false;
> + int i, ret;
>
> if (!crtc_state->enable_psr2_sel_fetch)
> - return;
> + return 0;
> +
> + ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> >base);
> + if (ret)
> + return ret;
> +
> + for_each_oldnew_intel_plane_in_state(state, plane,
> old_plane_state,
> + new_plane_state, i) {
> + struct drm_rect temp;
> +
> + if (new_plane_state->uapi.crtc != crtc_state-
> >uapi.crtc)
> + continue;
>
> - crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
> - PSR2_MAN_TRK_CTL_SF_SINGLE_FUL
> L_FRAME;
> + /*
> + * TODO: Not clear how to handle planes with negative
> position,
> + * also planes are not updated if they have a negative
> X
> + * position so for now doing a full update in this
> cases
> + */
> + if (new_plane_state->uapi.dst.y1 < 0 ||
> + new_plane_state->uapi.dst.x1 < 0) {
> + full_update = true;
> + break;
> + }
> +
> + if (!new_plane_state->uapi.visible)
> + continue;
> +
> + /*
> + * For now doing a selective fetch in the whole plane
> area,
> + * optimizations will come in the future.
> + */
> + temp.y1 = new_plane_state->uapi.dst.y1;
> + temp.y2 = new_plane_state->uapi.dst.y2;
> + clip_area_update(&pipe_clip, &temp);
> + }
> +
> + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
> + return 0;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 6a83c8e682e6..3eca9dcec3c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -15,6 +15,8 @@ struct intel_crtc_state;
> struct intel_dp;
> struct intel_crtc;
> struct intel_atomic_state;
> +struct intel_plane_state;
> +struct intel_plane;
>
> #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> >psr.sink_support)
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector
> *connector,
> struct drm_connector_state *old_state,
> struct drm_connector_state *new_state);
> void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
> -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void intel_psr2_program_trans_man_trk_ctl(const struct
> intel_crtc_state *crtc_state);
> +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> + const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state,
> + int color_plane);
>
> #endif /* __INTEL_PSR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 63040cb0d4e1..f12425b90607 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe,
> plane_id),
> (plane_state->color_plane[1].y << 16)
> | plane_state->color_plane[1].x);
>
> + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> plane_state, color_plane);
> +
> /*
> * The control register self-arms if the plane was previously
> * disabled. Try to make the plane enable atomic by writing
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-10-01 11:24 ` Mun, Gwan-gyeong
@ 2020-10-01 17:14 ` Souza, Jose
2020-10-07 12:58 ` Mun, Gwan-gyeong
0 siblings, 1 reply; 9+ messages in thread
From: Souza, Jose @ 2020-10-01 17:14 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Thu, 2020-10-01 at 12:24 +0100, Mun, Gwan-gyeong wrote:
> On Thu, 2020-09-24 at 10:42 -0700, José Roberto de Souza wrote:
> > Another step towards PSR2 selective fetch, here programming plane
> > selective fetch registers and MAN_TRK_CTL enabling selective fetch
> > but
> > for now it is fetching the whole area of the planes.
> > The damaged area calculation will come as next and final step.
> >
> > v2:
> > - removed warn on when no plane is visible in state
> > - removed calculations using plane damaged area in
> > intel_psr2_program_plane_sel_fetch()
> >
> > v3:
> > - do not shift 16 positions the plane dst coordinates, only src is
> > shifted
> >
> > v4:
> > - only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in
> > PLANE_SEL_FETCH_CTL
> >
> > BSpec: 55229
> > Cc: Gwan-gyeong Mun <
> > gwan-gyeong.mun@intel.com
> > >
> > Cc: Ville Syrjälä <
> > ville.syrjala@linux.intel.com
> > >
> > Signed-off-by: José Roberto de Souza <
> > jose.souza@intel.com
> > >
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 118
> > ++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> > 4 files changed, 132 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 5a9d933e425a..96bc515497c1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> > intel_plane *plane,
> > if (INTEL_GEN(dev_priv) >= 9)
> > skl_write_cursor_wm(plane, crtc_state);
> >
> > + if (!needs_modeset(crtc_state))
> > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > plane_state, 0);
> > +
> > if (plane->cursor.base != base ||
> > plane->cursor.size != fbc_ctl ||
> > plane->cursor.cntl != cntl) {
> > @@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct
> > intel_atomic_state *state,
> >
> > }
> >
> > - if (!mode_changed)
> > - intel_psr2_sel_fetch_update(state, crtc);
> > + if (!mode_changed) {
> > + ret = intel_psr2_sel_fetch_update(state, crtc);
> > + if (ret)
> > + return ret;
> > + }
> >
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 02f74b0ddec1..f6e0a192d5e5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1166,6 +1166,39 @@ static void psr_force_hw_tracking_exit(struct
> > drm_i915_private *dev_priv)
> > intel_psr_exit(dev_priv);
> > }
> >
> > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct intel_plane_state
> > *plane_state,
> > + int color_plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum pipe pipe = plane->pipe;
> > + u32 val;
> > +
> > + if (!crtc_state->enable_psr2_sel_fetch)
> > + return;
> > +
> > + val = plane_state ? plane_state->ctl : 0;
> > + val = plane->id == PLANE_CURSOR ? val & MCURSOR_MODE :
> > + val &
> > PLANE_SEL_FETCH_CTL_ENABLE;
>
> I could not find details of MCURSOR_MODE for selective_fetch. (on bspec
> 50420) why do you set MCURSOR_MODE here?
Bsepc: 55229
SEL_FETCH_CUR_CTL Cursor Mode Select = If update region, translated to pipe source coordinates, overlaps this cursor ? CUR_CTL Cursor Mode Select :
Disable
Oh and I missed this: Program the other fields in SEL_FETCH_CUR_CTL to match CUR_CTL.
So the v3 version of this patch is better, unless you still think that SEL_FETCH_PLANE_CTL only needs to have the bit 31 set, like I said spares are
different than reserved, we can set spares.
>
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > > id), val);
> >
> > + if (!val || plane->id == PLANE_CURSOR)
> > + return;
> > +
>
> in order to set just PLANE_SEL_FETCH_CTL_ENABLE bit, I suggest to use
> like this
> val = intel_de_read_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > id));
>
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> val|PLANE_SEL_FETCH_CTL_ENABLE);
All the plane and pipe programming must be fast to not evade vblank, so registers reads are not a good idea here.
Also why? plane_state->ctl will have the same value as the register for gen11+.
>
> > + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > uapi.dst.x1;
> >
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> > > id), val);
> >
> > +
> > + val = plane_state->color_plane[color_plane].y << 16;
> > + val |= plane_state->color_plane[color_plane].x;
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > id),
> >
> > + val);
> > +
> > + /* Sizes are 0 based */
> > + val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> > 16;
> > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> > > id), val);
> >
> > +}
> > +
> > void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -1180,16 +1213,91 @@ void
> > intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> > *crtc_st
> > crtc_state->psr2_man_track_ctl);
> > }
> >
> > -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc)
> > +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > *crtc_state,
> > + struct drm_rect *clip, bool
> > full_update)
> > +{
> > + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > +
> > + if (full_update) {
> > + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > + goto exit;
> > + }
> > +
> > + if (clip->y1 == -1)
> > + goto exit;
> > +
> > + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> > > y2, 4) + 1);
> >
> > +exit:
> > + crtc_state->psr2_man_track_ctl = val;
> > +}
> > +
> > +static void clip_area_update(struct drm_rect *overlap_damage_area,
> > + struct drm_rect *damage_area)
> > +{
> > + if (overlap_damage_area->y1 == -1) {
> > + overlap_damage_area->y1 = damage_area->y1;
> > + overlap_damage_area->y2 = damage_area->y2;
> > + return;
> > + }
> > +
> > + if (damage_area->y1 < overlap_damage_area->y1)
> > + overlap_damage_area->y1 = damage_area->y1;
> > +
> > + if (damage_area->y2 > overlap_damage_area->y2)
> > + overlap_damage_area->y2 = damage_area->y2;
> > +}
> > +
> > +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > {
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + struct intel_plane_state *new_plane_state, *old_plane_state;
> > + struct drm_rect pipe_clip = { .y1 = -1 };
> > + struct intel_plane *plane;
> > + bool full_update = false;
> > + int i, ret;
> >
> > if (!crtc_state->enable_psr2_sel_fetch)
> > - return;
> > + return 0;
> > +
> > + ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > > base);
> >
> > + if (ret)
> > + return ret;
> > +
> > + for_each_oldnew_intel_plane_in_state(state, plane,
> > old_plane_state,
> > + new_plane_state, i) {
> > + struct drm_rect temp;
> > +
> > + if (new_plane_state->uapi.crtc != crtc_state-
> > > uapi.crtc)
> >
> > + continue;
> >
> > - crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
> > - PSR2_MAN_TRK_CTL_SF_SINGLE_FUL
> > L_FRAME;
> > + /*
> > + * TODO: Not clear how to handle planes with negative
> > position,
> > + * also planes are not updated if they have a negative
> > X
> > + * position so for now doing a full update in this
> > cases
> > + */
> > + if (new_plane_state->uapi.dst.y1 < 0 ||
> > + new_plane_state->uapi.dst.x1 < 0) {
> > + full_update = true;
> > + break;
> > + }
> > +
> > + if (!new_plane_state->uapi.visible)
> > + continue;
> > +
> > + /*
> > + * For now doing a selective fetch in the whole plane
> > area,
> > + * optimizations will come in the future.
> > + */
> > + temp.y1 = new_plane_state->uapi.dst.y1;
> > + temp.y2 = new_plane_state->uapi.dst.y2;
> > + clip_area_update(&pipe_clip, &temp);
> > + }
> > +
> > + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
> > + return 0;
> > }
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 6a83c8e682e6..3eca9dcec3c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -15,6 +15,8 @@ struct intel_crtc_state;
> > struct intel_dp;
> > struct intel_crtc;
> > struct intel_atomic_state;
> > +struct intel_plane_state;
> > +struct intel_plane;
> >
> > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> > > psr.sink_support)
> >
> > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector
> > *connector,
> > struct drm_connector_state *old_state,
> > struct drm_connector_state *new_state);
> > void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
> > -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc);
> > +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc);
> > void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state);
> > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct intel_plane_state
> > *plane_state,
> > + int color_plane);
> >
> > #endif /* __INTEL_PSR_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 63040cb0d4e1..f12425b90607 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe,
> > plane_id),
> > (plane_state->color_plane[1].y << 16)
> > > plane_state->color_plane[1].x);
> >
> >
> > + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > plane_state, color_plane);
> > +
> > /*
> > * The control register self-arms if the plane was previously
> > * disabled. Try to make the plane enable atomic by writing
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-10-01 17:14 ` Souza, Jose
@ 2020-10-07 12:58 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 9+ messages in thread
From: Mun, Gwan-gyeong @ 2020-10-07 12:58 UTC (permalink / raw)
To: intel-gfx, Souza, Jose
On Thu, 2020-10-01 at 10:14 -0700, Souza, Jose wrote:
> On Thu, 2020-10-01 at 12:24 +0100, Mun, Gwan-gyeong wrote:
> > On Thu, 2020-09-24 at 10:42 -0700, José Roberto de Souza wrote:
> > > Another step towards PSR2 selective fetch, here programming plane
> > > selective fetch registers and MAN_TRK_CTL enabling selective
> > > fetch
> > > but
> > > for now it is fetching the whole area of the planes.
> > > The damaged area calculation will come as next and final step.
> > >
> > > v2:
> > > - removed warn on when no plane is visible in state
> > > - removed calculations using plane damaged area in
> > > intel_psr2_program_plane_sel_fetch()
> > >
> > > v3:
> > > - do not shift 16 positions the plane dst coordinates, only src
> > > is
> > > shifted
> > >
> > > v4:
> > > - only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in
> > > PLANE_SEL_FETCH_CTL
> > >
> > > BSpec: 55229
> > > Cc: Gwan-gyeong Mun <
> > > gwan-gyeong.mun@intel.com
> > > Cc: Ville Syrjälä <
> > > ville.syrjala@linux.intel.com
> > > Signed-off-by: José Roberto de Souza <
> > > jose.souza@intel.com
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > > drivers/gpu/drm/i915/display/intel_psr.c | 118
> > > ++++++++++++++++++-
> > > drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> > > 4 files changed, 132 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 5a9d933e425a..96bc515497c1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> > > intel_plane *plane,
> > > if (INTEL_GEN(dev_priv) >= 9)
> > > skl_write_cursor_wm(plane, crtc_state);
> > >
> > > + if (!needs_modeset(crtc_state))
> > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > > plane_state, 0);
> > > +
> > > if (plane->cursor.base != base ||
> > > plane->cursor.size != fbc_ctl ||
> > > plane->cursor.cntl != cntl) {
> > > @@ -12823,8 +12826,11 @@ static int
> > > intel_crtc_atomic_check(struct
> > > intel_atomic_state *state,
> > >
> > > }
> > >
> > > - if (!mode_changed)
> > > - intel_psr2_sel_fetch_update(state, crtc);
> > > + if (!mode_changed) {
> > > + ret = intel_psr2_sel_fetch_update(state, crtc);
> > > + if (ret)
> > > + return ret;
> > > + }
> > >
> > > return 0;
> > > }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 02f74b0ddec1..f6e0a192d5e5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1166,6 +1166,39 @@ static void
> > > psr_force_hw_tracking_exit(struct
> > > drm_i915_private *dev_priv)
> > > intel_psr_exit(dev_priv);
> > > }
> > >
> > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane
> > > *plane,
> > > + const struct intel_crtc_state
> > > *crtc_state,
> > > + const struct intel_plane_state
> > > *plane_state,
> > > + int color_plane)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > + enum pipe pipe = plane->pipe;
> > > + u32 val;
> > > +
> > > + if (!crtc_state->enable_psr2_sel_fetch)
> > > + return;
> > > +
> > > + val = plane_state ? plane_state->ctl : 0;
> > > + val = plane->id == PLANE_CURSOR ? val & MCURSOR_MODE :
> > > + val &
> > > PLANE_SEL_FETCH_CTL_ENABLE;
> >
> > I could not find details of MCURSOR_MODE for selective_fetch. (on
> > bspec
> > 50420) why do you set MCURSOR_MODE here?
>
> Bsepc: 55229
>
> SEL_FETCH_CUR_CTL Cursor Mode Select = If update region, translated
> to pipe source coordinates, overlaps this cursor ? CUR_CTL Cursor
> Mode Select :
> Disable
> Oh and I missed this: Program the other fields in SEL_FETCH_CUR_CTL
> to match CUR_CTL.
>
> So the v3 version of this patch is better, unless you still think
> that SEL_FETCH_PLANE_CTL only needs to have the bit 31 set, like I
> said spares are
> different than reserved, we can set spares.
>
>
Thank you for explaining.
But the v3 missed setting of PLANE_SEL_FETCH_CTL_ENABLE for normal
plane.
if you don't mind I suggest this.
val = plane->id == PLANE_CURSOR ? val : val &
PLANE_SEL_FETCH_CTL_ENABLE;
except for this, the rest of the parts seems good to me.
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > > > id), val);
> > >
> > > + if (!val || plane->id == PLANE_CURSOR)
> > > + return;
> > > +
> >
> > in order to set just PLANE_SEL_FETCH_CTL_ENABLE bit, I suggest to
> > use
> > like this
> > val = intel_de_read_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > > id));
> >
> > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> > val|PLANE_SEL_FETCH_CTL_ENABLE);
>
> All the plane and pipe programming must be fast to not evade vblank,
> so registers reads are not a good idea here.
> Also why? plane_state->ctl will have the same value as the register
> for gen11+.
>
>
> > > + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > > uapi.dst.x1;
> > >
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> > > > id), val);
> > >
> > > +
> > > + val = plane_state->color_plane[color_plane].y << 16;
> > > + val |= plane_state->color_plane[color_plane].x;
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > > id),
> > >
> > > + val);
> > > +
> > > + /* Sizes are 0 based */
> > > + val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> > > 16;
> > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> > > > id), val);
> > >
> > > +}
> > > +
> > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state *crtc_state)
> > > {
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > @@ -1180,16 +1213,91 @@ void
> > > intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state
> > > *crtc_st
> > > crtc_state->psr2_man_track_ctl);
> > > }
> > >
> > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > *state,
> > > - struct intel_crtc *crtc)
> > > +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > > *crtc_state,
> > > + struct drm_rect *clip, bool
> > > full_update)
> > > +{
> > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > > +
> > > + if (full_update) {
> > > + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > + goto exit;
> > > + }
> > > +
> > > + if (clip->y1 == -1)
> > > + goto exit;
> > > +
> > > + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > > + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> > > > y2, 4) + 1);
> > >
> > > +exit:
> > > + crtc_state->psr2_man_track_ctl = val;
> > > +}
> > > +
> > > +static void clip_area_update(struct drm_rect
> > > *overlap_damage_area,
> > > + struct drm_rect *damage_area)
> > > +{
> > > + if (overlap_damage_area->y1 == -1) {
> > > + overlap_damage_area->y1 = damage_area->y1;
> > > + overlap_damage_area->y2 = damage_area->y2;
> > > + return;
> > > + }
> > > +
> > > + if (damage_area->y1 < overlap_damage_area->y1)
> > > + overlap_damage_area->y1 = damage_area->y1;
> > > +
> > > + if (damage_area->y2 > overlap_damage_area->y2)
> > > + overlap_damage_area->y2 = damage_area->y2;
> > > +}
> > > +
> > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > *state,
> > > + struct intel_crtc *crtc)
> > > {
> > > struct intel_crtc_state *crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > + struct intel_plane_state *new_plane_state, *old_plane_state;
> > > + struct drm_rect pipe_clip = { .y1 = -1 };
> > > + struct intel_plane *plane;
> > > + bool full_update = false;
> > > + int i, ret;
> > >
> > > if (!crtc_state->enable_psr2_sel_fetch)
> > > - return;
> > > + return 0;
> > > +
> > > + ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > > > base);
> > >
> > > + if (ret)
> > > + return ret;
> > > +
> > > + for_each_oldnew_intel_plane_in_state(state, plane,
> > > old_plane_state,
> > > + new_plane_state, i) {
> > > + struct drm_rect temp;
> > > +
> > > + if (new_plane_state->uapi.crtc != crtc_state-
> > > > uapi.crtc)
> > >
> > > + continue;
> > >
> > > - crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
> > > - PSR2_MAN_TRK_CTL_SF_SINGLE_FUL
> > > L_FRAME;
> > > + /*
> > > + * TODO: Not clear how to handle planes with negative
> > > position,
> > > + * also planes are not updated if they have a negative
> > > X
> > > + * position so for now doing a full update in this
> > > cases
> > > + */
> > > + if (new_plane_state->uapi.dst.y1 < 0 ||
> > > + new_plane_state->uapi.dst.x1 < 0) {
> > > + full_update = true;
> > > + break;
> > > + }
> > > +
> > > + if (!new_plane_state->uapi.visible)
> > > + continue;
> > > +
> > > + /*
> > > + * For now doing a selective fetch in the whole plane
> > > area,
> > > + * optimizations will come in the future.
> > > + */
> > > + temp.y1 = new_plane_state->uapi.dst.y1;
> > > + temp.y2 = new_plane_state->uapi.dst.y2;
> > > + clip_area_update(&pipe_clip, &temp);
> > > + }
> > > +
> > > + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
> > > + return 0;
> > > }
> > >
> > > /**
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index 6a83c8e682e6..3eca9dcec3c0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -15,6 +15,8 @@ struct intel_crtc_state;
> > > struct intel_dp;
> > > struct intel_crtc;
> > > struct intel_atomic_state;
> > > +struct intel_plane_state;
> > > +struct intel_plane;
> > >
> > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> > > > psr.sink_support)
> > >
> > > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > > @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct
> > > drm_connector
> > > *connector,
> > > struct drm_connector_state *old_state,
> > > struct drm_connector_state *new_state);
> > > void intel_psr_set_force_mode_changed(struct intel_dp
> > > *intel_dp);
> > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > *state,
> > > - struct intel_crtc *crtc);
> > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > *state,
> > > + struct intel_crtc *crtc);
> > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state *crtc_state);
> > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane
> > > *plane,
> > > + const struct intel_crtc_state
> > > *crtc_state,
> > > + const struct intel_plane_state
> > > *plane_state,
> > > + int color_plane);
> > >
> > > #endif /* __INTEL_PSR_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index 63040cb0d4e1..f12425b90607 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe,
> > > plane_id),
> > > (plane_state->color_plane[1].y << 16)
> > > > plane_state->color_plane[1].x);
> > >
> > >
> > > + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > > plane_state, color_plane);
> > > +
> > > /*
> > > * The control register self-arms if the plane was previously
> > > * disabled. Try to make the plane enable atomic by writing
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers
@ 2020-09-28 21:58 kernel test robot
0 siblings, 0 replies; 9+ messages in thread
From: kernel test robot @ 2020-09-28 21:58 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 6082 bytes --]
CC: kbuild-all(a)lists.01.org
In-Reply-To: <20200924174201.44021-3-jose.souza@intel.com>
References: <20200924174201.44021-3-jose.souza@intel.com>
TO: "José Roberto de Souza" <jose.souza@intel.com>
TO: intel-gfx(a)lists.freedesktop.org
Hi "José,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20200928]
[cannot apply to v5.9-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Jos-Roberto-de-Souza/drm-i915-display-Ignore-IGNORE_PSR2_HW_TRACKING-for-platforms-without-sel-fetch/20200925-014158
base: git://anongit.freedesktop.org/drm-intel for-linux-next
:::::: branch date: 4 days ago
:::::: commit date: 4 days ago
config: x86_64-randconfig-m001-20200928 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/gpu/drm/i915/display/intel_psr.c:1188 intel_psr2_program_plane_sel_fetch() error: we previously assumed 'plane_state' could be null (see line 1181)
vim +/plane_state +1188 drivers/gpu/drm/i915/display/intel_psr.c
88e05aff355e34 drivers/gpu/drm/i915/intel_psr.c José Roberto de Souza 2019-03-07 1168
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1169 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1170 const struct intel_crtc_state *crtc_state,
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1171 const struct intel_plane_state *plane_state,
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1172 int color_plane)
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1173 {
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1174 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1175 enum pipe pipe = plane->pipe;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1176 u32 val;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1177
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1178 if (!crtc_state->enable_psr2_sel_fetch)
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1179 return;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1180
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 @1181 val = plane_state ? plane_state->ctl : 0;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1182 val = plane->id == PLANE_CURSOR ? val & MCURSOR_MODE :
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1183 val & PLANE_SEL_FETCH_CTL_ENABLE;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1184 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1185 if (!val || plane->id == PLANE_CURSOR)
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1186 return;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1187
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 @1188 val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1189 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1190
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1191 val = plane_state->color_plane[color_plane].y << 16;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1192 val |= plane_state->color_plane[color_plane].x;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1193 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1194 val);
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1195
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1196 /* Sizes are 0 based */
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1197 val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) << 16;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1198 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1199 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1200 }
9af2c1f60dfa66 drivers/gpu/drm/i915/display/intel_psr.c José Roberto de Souza 2020-09-24 1201
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-10-07 12:58 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-24 17:41 [Intel-gfx] [PATCH v4 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
2020-09-24 17:42 ` [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
2020-10-01 11:24 ` Mun, Gwan-gyeong
2020-10-01 17:14 ` Souza, Jose
2020-10-07 12:58 ` Mun, Gwan-gyeong
2020-09-24 18:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
2020-09-24 21:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-09-28 21:58 [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers kernel test robot
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