* [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
@ 2020-12-21 12:26 ` qii.wang
0 siblings, 0 replies; 7+ messages in thread
From: qii.wang @ 2020-12-21 12:26 UTC (permalink / raw)
To: robh+dt
Cc: matthias.bgg, mark.rutland, devicetree, linux-arm-kernel,
linux-kernel, linux-mediatek, srv_heupstream, leilk.liu,
qii.wang
From: Qii Wang <qii.wang@mediatek.com>
imp wrapper clock is the i2c source clock of MT8192
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 43 ++++++++++++++++++++++++--------
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d9..9c194a8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -17,6 +17,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -593,7 +606,8 @@
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -612,7 +626,8 @@
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -625,7 +640,8 @@
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -638,7 +654,8 @@
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -657,7 +674,8 @@
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -670,7 +688,8 @@
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -683,7 +702,8 @@
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -702,7 +722,8 @@
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -721,7 +742,8 @@
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -734,7 +756,8 @@
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
@ 2020-12-21 12:26 ` qii.wang
0 siblings, 0 replies; 7+ messages in thread
From: qii.wang @ 2020-12-21 12:26 UTC (permalink / raw)
To: robh+dt
Cc: mark.rutland, devicetree, srv_heupstream, leilk.liu,
linux-kernel, linux-mediatek, qii.wang, matthias.bgg,
linux-arm-kernel
From: Qii Wang <qii.wang@mediatek.com>
imp wrapper clock is the i2c source clock of MT8192
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 43 ++++++++++++++++++++++++--------
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d9..9c194a8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -17,6 +17,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -593,7 +606,8 @@
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -612,7 +626,8 @@
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -625,7 +640,8 @@
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -638,7 +654,8 @@
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -657,7 +674,8 @@
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -670,7 +688,8 @@
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -683,7 +702,8 @@
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -702,7 +722,8 @@
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -721,7 +742,8 @@
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -734,7 +756,8 @@
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
--
1.9.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
@ 2020-12-21 12:26 ` qii.wang
0 siblings, 0 replies; 7+ messages in thread
From: qii.wang @ 2020-12-21 12:26 UTC (permalink / raw)
To: robh+dt
Cc: mark.rutland, devicetree, srv_heupstream, leilk.liu,
linux-kernel, linux-mediatek, qii.wang, matthias.bgg,
linux-arm-kernel
From: Qii Wang <qii.wang@mediatek.com>
imp wrapper clock is the i2c source clock of MT8192
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 43 ++++++++++++++++++++++++--------
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d9..9c194a8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -17,6 +17,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -593,7 +606,8 @@
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -612,7 +626,8 @@
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -625,7 +640,8 @@
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -638,7 +654,8 @@
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -657,7 +674,8 @@
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -670,7 +688,8 @@
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -683,7 +702,8 @@
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -702,7 +722,8 @@
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -721,7 +742,8 @@
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -734,7 +756,8 @@
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
--
1.9.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
2020-12-21 12:26 ` qii.wang
(?)
@ 2020-12-27 11:42 ` kernel test robot
-1 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-12-27 11:42 UTC (permalink / raw)
To: qii.wang, robh+dt
Cc: kbuild-all, matthias.bgg, mark.rutland, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
leilk.liu, qii.wang
[-- Attachment #1: Type: text/plain, Size: 1823 bytes --]
Hi,
I love your patch! Yet something to improve:
[auto build test ERROR on soc/for-next]
[also build test ERROR on next-20201223]
[cannot apply to robh/for-next arm/for-next keystone/next rockchip/for-next arm64/for-next/core shawnguo/for-next xlnx/master kvmarm/next mediatek/for-next v5.10]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/qii-wang-mediatek-com/arm64-dts-mediatek-Correct-i2c-clock-of-MT8192/20201221-203038
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/aa3c0f956c1f7a9f1275c1e13281033e67ce4f37
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review qii-wang-mediatek-com/arm64-dts-mediatek-Correct-i2c-clock-of-MT8192/20201221-203038
git checkout aa3c0f956c1f7a9f1275c1e13281033e67ce4f37
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/mediatek/mt8192.dtsi:400.30-31 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 75535 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
@ 2020-12-27 11:42 ` kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-12-27 11:42 UTC (permalink / raw)
To: qii.wang, robh+dt
Cc: mark.rutland, devicetree, kbuild-all, srv_heupstream, leilk.liu,
linux-kernel, linux-mediatek, qii.wang, matthias.bgg,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1823 bytes --]
Hi,
I love your patch! Yet something to improve:
[auto build test ERROR on soc/for-next]
[also build test ERROR on next-20201223]
[cannot apply to robh/for-next arm/for-next keystone/next rockchip/for-next arm64/for-next/core shawnguo/for-next xlnx/master kvmarm/next mediatek/for-next v5.10]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/qii-wang-mediatek-com/arm64-dts-mediatek-Correct-i2c-clock-of-MT8192/20201221-203038
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/aa3c0f956c1f7a9f1275c1e13281033e67ce4f37
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review qii-wang-mediatek-com/arm64-dts-mediatek-Correct-i2c-clock-of-MT8192/20201221-203038
git checkout aa3c0f956c1f7a9f1275c1e13281033e67ce4f37
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/mediatek/mt8192.dtsi:400.30-31 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 75535 bytes --]
[-- Attachment #3: Type: text/plain, Size: 170 bytes --]
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
@ 2020-12-27 11:42 ` kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-12-27 11:42 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1861 bytes --]
Hi,
I love your patch! Yet something to improve:
[auto build test ERROR on soc/for-next]
[also build test ERROR on next-20201223]
[cannot apply to robh/for-next arm/for-next keystone/next rockchip/for-next arm64/for-next/core shawnguo/for-next xlnx/master kvmarm/next mediatek/for-next v5.10]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/qii-wang-mediatek-com/arm64-dts-mediatek-Correct-i2c-clock-of-MT8192/20201221-203038
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/aa3c0f956c1f7a9f1275c1e13281033e67ce4f37
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review qii-wang-mediatek-com/arm64-dts-mediatek-Correct-i2c-clock-of-MT8192/20201221-203038
git checkout aa3c0f956c1f7a9f1275c1e13281033e67ce4f37
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/mediatek/mt8192.dtsi:400.30-31 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 75535 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
2020-12-21 12:26 ` qii.wang
` (2 preceding siblings ...)
(?)
@ 2021-01-31 14:15 ` Matthias Brugger
-1 siblings, 0 replies; 7+ messages in thread
From: Matthias Brugger @ 2021-01-31 14:15 UTC (permalink / raw)
To: qii.wang, robh+dt
Cc: mark.rutland, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, leilk.liu
On 21/12/2020 13:26, qii.wang@mediatek.com wrote:
> From: Qii Wang <qii.wang@mediatek.com>
>
> imp wrapper clock is the i2c source clock of MT8192
>
> Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> ---
Thanks for your patch. The next time please provide information about any
out-of-tree series that are needed to apply cleanly.
Regards,
Matthias
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 43 ++++++++++++++++++++++++--------
> 1 file changed, 33 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index faea0d9..9c194a8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -17,6 +17,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -593,7 +606,8 @@
> reg = <0 0x11cb0000 0 0x1000>,
> <0 0x10217300 0 0x80>;
> interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -612,7 +626,8 @@
> reg = <0 0x11d00000 0 0x1000>,
> <0 0x10217600 0 0x180>;
> interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -625,7 +640,8 @@
> reg = <0 0x11d01000 0 0x1000>,
> <0 0x10217780 0 0x180>;
> interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -638,7 +654,8 @@
> reg = <0 0x11d02000 0 0x1000>,
> <0 0x10217900 0 0x180>;
> interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -657,7 +674,8 @@
> reg = <0 0x11d20000 0 0x1000>,
> <0 0x10217100 0 0x80>;
> interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -670,7 +688,8 @@
> reg = <0 0x11d21000 0 0x1000>,
> <0 0x10217180 0 0x180>;
> interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -683,7 +702,8 @@
> reg = <0 0x11d22000 0 0x1000>,
> <0 0x10217380 0 0x180>;
> interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -702,7 +722,8 @@
> reg = <0 0x11e00000 0 0x1000>,
> <0 0x10217500 0 0x80>;
> interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -721,7 +742,8 @@
> reg = <0 0x11f00000 0 0x1000>,
> <0 0x10217080 0 0x80>;
> interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -734,7 +756,8 @@
> reg = <0 0x11f01000 0 0x1000>,
> <0 0x10217580 0 0x80>;
> interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-01-31 15:24 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-21 12:26 [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192 qii.wang
2020-12-21 12:26 ` qii.wang
2020-12-21 12:26 ` qii.wang
2020-12-27 11:42 ` kernel test robot
2020-12-27 11:42 ` kernel test robot
2020-12-27 11:42 ` kernel test robot
2021-01-31 14:15 ` Matthias Brugger
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