* [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G
@ 2018-10-18 18:30 Michal Wajdeczko
2018-10-18 18:30 ` [PATCH v3 2/2] HAX: Enable GuC for CI Michal Wajdeczko
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Michal Wajdeczko @ 2018-10-18 18:30 UTC (permalink / raw)
To: intel-gfx
We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.
v2: No message from host to GuC uses more than 8 registers and
the GuC FW itself uses an 8-element array to store the H2G message,
so we may reduce our send array to just 8 registers (Daniele)
v3: use explicit define
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_guc.c | 3 ++-
drivers/gpu/drm/i915/intel_guc_fwif.h | 5 ++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 4c61eb9..9b00cdf 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
unsigned int i;
guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
- guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
+ guc->send_regs.count = GUC_MMIO_MSG_LEN;
+ BUILD_BUG_ON(GUC_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
for (i = 0; i < guc->send_regs.count; i++) {
fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index d1bbaba..cc997ef 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -601,7 +601,8 @@ struct guc_shared_ctx_data {
* registers, where first register holds data treated as message header,
* and other registers are used to hold message payload.
*
- * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8
+ * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, but
+ * the GuC FW itself uses an 8-element array to store the H2G message.
*
* +-----------+---------+---------+---------+
* | MMIO[0] | MMIO[1] | ... | MMIO[n] |
@@ -633,6 +634,8 @@ struct guc_shared_ctx_data {
* field.
*/
+#define GUC_MMIO_MSG_LEN 8
+
#define INTEL_GUC_MSG_TYPE_SHIFT 28
#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
#define INTEL_GUC_MSG_DATA_SHIFT 16
--
1.9.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v3 2/2] HAX: Enable GuC for CI
2018-10-18 18:30 [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
@ 2018-10-18 18:30 ` Michal Wajdeczko
2018-10-18 18:51 ` [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Daniele Ceraolo Spurio
2018-10-18 19:06 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Michal Wajdeczko @ 2018-10-18 18:30 UTC (permalink / raw)
To: intel-gfx
GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
1.9.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G
2018-10-18 18:30 [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-18 18:30 ` [PATCH v3 2/2] HAX: Enable GuC for CI Michal Wajdeczko
@ 2018-10-18 18:51 ` Daniele Ceraolo Spurio
2018-10-18 19:06 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-10-18 18:51 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 18/10/18 11:30, Michal Wajdeczko wrote:
> We wrongly assumed that GuC is only using last scratch register
> for G2H messages, but in fact it is also using register [14] to
> report sleep state status. Remove that register from our H2G
> send registers pool.
>
> v2: No message from host to GuC uses more than 8 registers and
> the GuC FW itself uses an 8-element array to store the H2G message,
> so we may reduce our send array to just 8 registers (Daniele)
> v3: use explicit define
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_guc.c | 3 ++-
> drivers/gpu/drm/i915/intel_guc_fwif.h | 5 ++++-
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 4c61eb9..9b00cdf 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
> unsigned int i;
>
> guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> - guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
> + guc->send_regs.count = GUC_MMIO_MSG_LEN;
> + BUILD_BUG_ON(GUC_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
>
> for (i = 0; i < guc->send_regs.count; i++) {
> fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index d1bbaba..cc997ef 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -601,7 +601,8 @@ struct guc_shared_ctx_data {
> * registers, where first register holds data treated as message header,
> * and other registers are used to hold message payload.
> *
> - * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8
> + * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, but
> + * the GuC FW itself uses an 8-element array to store the H2G message.
I think our justification here should be that no commands takes more
than 8 dwords more than what GuC FW does internally (which can reinforce
the point but not make it IMO).
> *
> * +-----------+---------+---------+---------+
> * | MMIO[0] | MMIO[1] | ... | MMIO[n] |
> @@ -633,6 +634,8 @@ struct guc_shared_ctx_data {
> * field.
> */
>
> +#define GUC_MMIO_MSG_LEN 8
> +
I'd prefer GUC_MAX_MMIO_MSG_LEN, but I can live with this.
With the improved comment:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> #define INTEL_GUC_MSG_TYPE_SHIFT 28
> #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
> #define INTEL_GUC_MSG_DATA_SHIFT 16
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread* ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] drm/i915/guc: Limit number of scratch registers used for H2G
2018-10-18 18:30 [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-18 18:30 ` [PATCH v3 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-10-18 18:51 ` [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Daniele Ceraolo Spurio
@ 2018-10-18 19:06 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-10-18 19:06 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/guc: Limit number of scratch registers used for H2G
URL : https://patchwork.freedesktop.org/series/51206/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10505 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10505 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10505, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51206/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10505:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_hangcheck:
fi-whl-u: PASS -> INCOMPLETE
==== Warnings ====
igt@drv_selftest@live_guc:
fi-apl-guc: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10505 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
fi-cfl-8109u: PASS -> INCOMPLETE (fdo#106070)
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: PASS -> FAIL (fdo#103841, fdo#102672)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
==== Possible fixes ====
igt@drv_selftest@live_execlists:
fi-apl-guc: INCOMPLETE (fdo#106693) -> PASS
igt@kms_flip@basic-plain-flip:
fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-icl-u2: FAIL (fdo#103167) -> PASS
fi-byt-clapper: FAIL (fdo#103167) -> PASS
igt@pm_rpm@module-reload:
fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
== Participating hosts (43 -> 39) ==
Missing (4): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
== Build changes ==
* Linux: CI_DRM_5010 -> Patchwork_10505
CI_DRM_5010: 27a4f334d3ec8882d50227c26ae4e393d7d1f4a1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4683: 7766b1e2348b32cc8ed58a972c6fd53b20279549 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10505: fbab94c61bf18e7fd9a98e8df6c68c804cb740f2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fbab94c61bf1 HAX: Enable GuC for CI
8abd97636b8a drm/i915/guc: Limit number of scratch registers used for H2G
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10505/issues.html
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2018-10-18 18:30 [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-18 18:30 ` [PATCH v3 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-10-18 18:51 ` [PATCH v3 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Daniele Ceraolo Spurio
2018-10-18 19:06 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] " Patchwork
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