* [RFC PATCH v4 01/30] target/loongarch: Update README
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-15 12:42 ` Mark Cave-Ayland
2022-01-08 9:13 ` [RFC PATCH v4 02/30] target/loongarch: Add CSR registers definition Xiaojuan Yang
` (30 subsequent siblings)
31 siblings, 2 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Mainly introduce how to run the softmmu
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/README | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/loongarch/README b/target/loongarch/README
index d5780c5918..337ba55f33 100644
--- a/target/loongarch/README
+++ b/target/loongarch/README
@@ -72,6 +72,31 @@
./qemu-loongarch64 /opt/clfs/usr/bin/pwd
...
+- Softmmu emulation
+
+ Add support softmmu emulation support in the following series patches.
+ Mainly emulate a virt 3A5000 board and ls7a bridge that is not exactly
+ the same as the host. Kernel code and uefi code is on the github.
+ All required binaries can get from github for test.
+
+ 1.Download kernel and the cross-tools.(vmlinux)
+
+ https://github.com/loongson/linux/tree/loongarch-next
+ https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-20211202-cross-tools.tar.xz
+
+ 2.Download uefi code.(loongarch_bios.bin)
+
+ https://github.com/loongson/edk2/tree/LoongArch
+ https://github.com/loongson/edk2-platforms
+
+ 3.Download the clfs-system and make a ramdisk with busybox.(ramdisk)
+
+ 4.Run with command,eg:
+
+ ./build/qemu-system-loongarch64 -m 4G -smp 4 --cpu Loongson-3A5000 --machine loongson3-ls7a -kernel ./vmlinux -initrd ./ramdisk -append "root=/dev/ram console=ttyS0,115200 rdinit=/sbin/init loglevel=8" -monitor tcp::4000,server,nowait -nographic
+
+The vmlinux, ramdisk and uefi binary loongarch_bios.bin can get from :
+ git clone https://github.com/yangxiaojuan-loongson/qemu-binary
- Note.
We can get the latest LoongArch documents or LoongArch tools at https://github.com/loongson/
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 01/30] target/loongarch: Update README
2022-01-08 9:13 ` [RFC PATCH v4 01/30] target/loongarch: Update README Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
2022-01-15 12:42 ` Mark Cave-Ayland
1 sibling, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> Mainly introduce how to run the softmmu
This sentence serves little purpose and is broken English, so it is
better removed.
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/README | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/target/loongarch/README b/target/loongarch/README
> index d5780c5918..337ba55f33 100644
> --- a/target/loongarch/README
> +++ b/target/loongarch/README
> @@ -72,6 +72,31 @@
> ./qemu-loongarch64 /opt/clfs/usr/bin/pwd
> ...
>
> +- Softmmu emulation
You may mean "System emulation" instead?
> +
> + Add support softmmu emulation support in the following series patches.
People don't care about patch series when they look at this file after
everything is merged; they are NOT looking at Patchew or mailing lists
when browsing code either locally or on GitLab/GitHub. You may just drop
this sentence.
> + Mainly emulate a virt 3A5000 board and ls7a bridge that is not exactly
> + the same as the host. Kernel code and uefi code is on the github.
So what exactly is the difference? And does it affect general use?
> + All required binaries can get from github for test.
English problem; "You can get all required binaries from GitHub for
testing."
> +
> + 1.Download kernel and the cross-tools.(vmlinux)
> +
> +https://github.com/loongson/linux/tree/loongarch-next
> +https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-20211202-cross-tools.tar.xz
> +
> + 2.Download uefi code.(loongarch_bios.bin)
> +
> +https://github.com/loongson/edk2/tree/LoongArch
> +https://github.com/loongson/edk2-platforms
> +
> + 3.Download the clfs-system and make a ramdisk with busybox.(ramdisk)
How do we make the ramdisk, or is it prebuilt too? It's not clear from
the description.
> +
> + 4.Run with command,eg:
> +
> + ./build/qemu-system-loongarch64 -m 4G -smp 4 --cpu Loongson-3A5000 --machine loongson3-ls7a -kernel ./vmlinux -initrd ./ramdisk -append "root=/dev/ram console=ttyS0,115200 rdinit=/sbin/init loglevel=8" -monitor tcp::4000,server,nowait -nographic
> +
> +The vmlinux, ramdisk and uefi binary loongarch_bios.bin can get from :
Broken English too.
> + git clonehttps://github.com/yangxiaojuan-loongson/qemu-binary
>
> - Note.
> We can get the latest LoongArch documents or LoongArch tools athttps://github.com/loongson/
Overall the English is so badly written that I cannot easily comprehend
some of the sentences, even as a native Chinese speaker, familiar with
common Chinglish patterns.
I suggest just rewriting the whole thing, possibly with help from
someone else more familiar with technical English in your company. You'd
want to check your other usages of English throughout the series, too.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH v4 01/30] target/loongarch: Update README
2022-01-08 9:13 ` [RFC PATCH v4 01/30] target/loongarch: Update README Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
@ 2022-01-15 12:42 ` Mark Cave-Ayland
1 sibling, 0 replies; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 12:42 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: richard.henderson, philmd, Song Gao
On 08/01/2022 09:13, Xiaojuan Yang wrote:
> Mainly introduce how to run the softmmu
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> target/loongarch/README | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/target/loongarch/README b/target/loongarch/README
> index d5780c5918..337ba55f33 100644
> --- a/target/loongarch/README
> +++ b/target/loongarch/README
> @@ -72,6 +72,31 @@
> ./qemu-loongarch64 /opt/clfs/usr/bin/pwd
> ...
>
> +- Softmmu emulation
> +
> + Add support softmmu emulation support in the following series patches.
> + Mainly emulate a virt 3A5000 board and ls7a bridge that is not exactly
> + the same as the host. Kernel code and uefi code is on the github.
> + All required binaries can get from github for test.
> +
> + 1.Download kernel and the cross-tools.(vmlinux)
> +
> + https://github.com/loongson/linux/tree/loongarch-next
> + https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-20211202-cross-tools.tar.xz
> +
> + 2.Download uefi code.(loongarch_bios.bin)
> +
> + https://github.com/loongson/edk2/tree/LoongArch
> + https://github.com/loongson/edk2-platforms
> +
> + 3.Download the clfs-system and make a ramdisk with busybox.(ramdisk)
> +
> + 4.Run with command,eg:
> +
> + ./build/qemu-system-loongarch64 -m 4G -smp 4 --cpu Loongson-3A5000 --machine loongson3-ls7a -kernel ./vmlinux -initrd ./ramdisk -append "root=/dev/ram console=ttyS0,115200 rdinit=/sbin/init loglevel=8" -monitor tcp::4000,server,nowait -nographic
> +
> +The vmlinux, ramdisk and uefi binary loongarch_bios.bin can get from :
> + git clone https://github.com/yangxiaojuan-loongson/qemu-binary
>
> - Note.
> We can get the latest LoongArch documents or LoongArch tools at https://github.com/loongson/
This target/loongarch/README file doesn't exist in git master, so presumably this is
based upon another series, possibly introducing linux-user support?
Is the plan to merge the linux-user support first? If so then you should add a
Based-on tag to the cover letter referencing the corresponding linux-user patch series.
Also: I don't see a URL for a git repo containing the complete patchset which can
help making some bits of review easier.
ATB,
Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 02/30] target/loongarch: Add CSR registers definition
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
2022-01-08 9:13 ` [RFC PATCH v4 01/30] target/loongarch: Update README Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-08 9:13 ` [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
` (29 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu-csr.h | 236 +++++++++++++++++++++++++++++++++++++
target/loongarch/cpu.c | 35 ++++++
target/loongarch/cpu.h | 57 +++++++++
3 files changed, 328 insertions(+)
create mode 100644 target/loongarch/cpu-csr.h
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
new file mode 100644
index 0000000000..7a57b7ea36
--- /dev/null
+++ b/target/loongarch/cpu-csr.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch CPU CSR registers
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_CPU_CSR_H
+#define LOONGARCH_CPU_CSR_H
+
+/* Base on: kernal: arch/loongarch/include/asm/loongarch.h */
+
+/* Basic CSR register */
+#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
+FIELD(CSR_CRMD, PLV, 0, 2)
+FIELD(CSR_CRMD, IE, 2, 1)
+FIELD(CSR_CRMD, DA, 3, 1)
+FIELD(CSR_CRMD, PG, 4, 1)
+FIELD(CSR_CRMD, DATF, 5, 2)
+FIELD(CSR_CRMD, DATM, 7, 2)
+FIELD(CSR_CRMD, WE, 9, 1)
+
+#define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
+FIELD(CSR_PRMD, PPLV, 0, 2)
+FIELD(CSR_PRMD, PIE, 2, 1)
+FIELD(CSR_PRMD, PWE, 3, 1)
+
+#define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
+FIELD(CSR_EUEN, FPE, 0, 1)
+FIELD(CSR_EUEN, SXE, 1, 1)
+FIELD(CSR_EUEN, ASXE, 2, 1)
+FIELD(CSR_EUEN, BTE, 3, 1)
+
+#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
+
+#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
+FIELD(CSR_ECFG, LIE, 0, 13)
+FIELD(CSR_ECFG, VS, 16, 3)
+
+#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
+FIELD(CSR_ESTAT, IS, 0, 13)
+FIELD(CSR_ESTAT, ECODE, 16, 6)
+FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
+
+#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
+#define EXCCODE_INT 0
+#define EXCCODE_PIL 1
+#define EXCCODE_PIS 2
+#define EXCCODE_PIF 3
+#define EXCCODE_PME 4
+#define EXCCODE_PNR 5
+#define EXCCODE_PNX 6
+#define EXCCODE_PPI 7
+#define EXCCODE_ADEF 8 /* Have different expsubcode */
+#define EXCCODE_ADEM 8 /* Have different expsubcode */
+#define EXCCODE_ALE 9
+#define EXCCODE_BCE 10
+#define EXCCODE_SYS 11
+#define EXCCODE_BRK 12
+#define EXCCODE_INE 13
+#define EXCCODE_IPE 14
+#define EXCCODE_FPD 15
+#define EXCCODE_SXD 16
+#define EXCCODE_ASXD 17
+#define EXCCODE_FPE 18 /* Have different expsubcode */
+#define EXCCODE_VFPE 18
+#define EXCCODE_WPEF 19 /* Have different expsubcode */
+#define EXCCODE_WPEM 19
+#define EXCCODE_BTD 20
+#define EXCCODE_BTE 21
+#define EXCCODE_DBP 26 /* Reserved decode used for debug */
+
+#define LOONGARCH_CSR_ERA 0x6 /* Exception return address */
+
+#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
+
+#define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
+
+#define LOONGARCH_CSR_EENTRY 0xc /* Exception enter base address */
+
+/* TLB related CSR register */
+#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
+FIELD(CSR_TLBIDX, INDEX, 0, 12)
+FIELD(CSR_TLBIDX, PS, 24, 6)
+FIELD(CSR_TLBIDX, NE, 31, 1)
+
+#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi without ASID */
+FIELD(CSR_TLBEHI, VPPN, 13, 35)
+
+#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
+#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
+FIELD(TLBENTRY, V, 0, 1)
+FIELD(TLBENTRY, D, 1, 1)
+FIELD(TLBENTRY, PLV, 2, 2)
+FIELD(TLBENTRY, MAT, 4, 2)
+FIELD(TLBENTRY, G, 6, 1)
+FIELD(TLBENTRY, PPN, 12, 36)
+FIELD(TLBENTRY, NR, 61, 1)
+FIELD(TLBENTRY, NX, 62, 1)
+FIELD(TLBENTRY, RPLV, 63, 1)
+
+#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
+FIELD(CSR_ASID, ASID, 0, 10)
+FIELD(CSR_ASID, ASIDBITS, 16, 8)
+
+/* Page table base address when badv[47] = 0 */
+#define LOONGARCH_CSR_PGDL 0x19
+/* Page table base address when badv[47] = 1 */
+#define LOONGARCH_CSR_PGDH 0x1a
+
+#define LOONGARCH_CSR_PGD 0x1b /* Page table base */
+
+/* Page walk controller's low addr */
+#define LOONGARCH_CSR_PWCL 0x1c
+FIELD(CSR_PWCL, PTBASE, 0, 5)
+FIELD(CSR_PWCL, PTWIDTH, 5, 5)
+FIELD(CSR_PWCL, DIR1_BASE, 10, 5)
+FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5)
+FIELD(CSR_PWCL, DIR2_BASE, 20, 5)
+FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5)
+FIELD(CSR_PWCL, PTEWIDTH, 30, 2)
+
+/* Page walk controller's high addr */
+#define LOONGARCH_CSR_PWCH 0x1d
+FIELD(CSR_PWCH, DIR3_BASE, 0, 6)
+FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6)
+FIELD(CSR_PWCH, DIR4_BASE, 12, 6)
+FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
+
+#define LOONGARCH_CSR_STLBPS 0x1e /*Stlb page size*/
+FIELD(CSR_STLBPS, PS, 0, 5)
+
+#define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address config */
+FIELD(CSR_RVACFG, RBITS, 0, 4)
+
+/* Config CSR registers */
+#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
+
+#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
+FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4)
+FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8)
+FIELD(CSR_PRCFG1, VSMAX, 12, 3)
+
+#define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
+
+#define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
+FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4)
+FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8)
+FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8)
+FIELD(CSR_PRCFG3, STLB_SETS, 20, 8)
+
+/*
+ * Save registers count can read from PRCFG1.SAVE_NUM
+ * The Min count is 1. Max count is 15.
+ */
+#define LOONGARCH_CSR_SAVE(N) (0x30 + N)
+
+/* Timer registers */
+#define LOONGARCH_CSR_TID 0x40 /* Timer ID */
+
+#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
+FIELD(CSR_TCFG, EN, 0, 1)
+FIELD(CSR_TCFG, PERIODIC, 1, 1)
+FIELD(CSR_TCFG, INIT_VAL, 2, 46)
+
+#define LOONGARCH_CSR_TVAL 0x42 /* Timer ticks remain */
+
+#define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
+
+#define LOONGARCH_CSR_TICLR 0x44 /* Timer interrupt clear */
+
+/* LLBCTL register */
+#define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
+FIELD(CSR_LLBCTL, ROLLB, 0, 1)
+FIELD(CSR_LLBCTL, WCLLB, 1, 1)
+FIELD(CSR_LLBCTL, KLO, 2, 1)
+
+/* Implement dependent */
+#define LOONGARCH_CSR_IMPCTL1 0x80 /* LoongArch config1 */
+
+#define LOONGARCH_CSR_IMPCTL2 0x81 /* LoongArch config2*/
+
+/* TLB Refill registers */
+#define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */
+#define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
+#define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
+#define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */
+FIELD(CSR_TLBRERA, ISTLBR, 0, 1)
+FIELD(CSR_TLBRERA, PC, 2, 62)
+#define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
+#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
+#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
+FIELD(CSR_TLBREHI, PS, 0, 6)
+FIELD(CSR_TLBREHI, VPPN, 13, 35)
+#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
+FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
+FIELD(CSR_TLBRPRMD, PIE, 2, 1)
+FIELD(CSR_TLBRPRMD, PWE, 4, 1)
+
+/* Machine Error registers */
+#define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */
+FIELD(CSR_MERRCTL, ISMERR, 0, 1)
+#define LOONGARCH_CSR_MERRINFO1 0x91
+#define LOONGARCH_CSR_MERRINFO2 0x92
+#define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception base */
+#define LOONGARCH_CSR_MERRERA 0x94 /* MError exception PC */
+#define LOONGARCH_CSR_MERRSAVE 0x95 /* KScratch for error exception */
+
+#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
+
+/* Direct map windows */
+#define LOONGARCH_CSR_DMW(N) (0x180 + N) /* direct map win MEM & IF */
+FIELD(CSR_DMW, PLV0, 0, 1)
+FIELD(CSR_DMW, PLV1, 1, 1)
+FIELD(CSR_DMW, PLV2, 2, 1)
+FIELD(CSR_DMW, PLV3, 3, 1)
+FIELD(CSR_DMW, MAT, 4, 2)
+FIELD(CSR_DMW, VSEG, 60, 4)
+
+#define dmw_va2pa(va) \
+ (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
+
+/* Debug registers */
+#define LOONGARCH_CSR_DBG 0x500 /* debug config */
+FIELD(CSR_DBG, DST, 0, 1)
+FIELD(CSR_DBG, DREV, 1, 7)
+FIELD(CSR_DBG, DEI, 8, 1)
+FIELD(CSR_DBG, DCL, 9, 1)
+FIELD(CSR_DBG, DFW, 10, 1)
+FIELD(CSR_DBG, DMW, 11, 1)
+FIELD(CSR_DBG, ECODE, 16, 6)
+
+#define LOONGARCH_CSR_DERA 0x501 /* Debug era */
+#define LOONGARCH_CSR_DSAVE 0x502 /* Debug save */
+
+#endif /* LOONGARCH_CPU_CSR_H */
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 883c6c623f..ed03ec2986 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -156,6 +156,8 @@ static void loongarch_3a5000_initfn(Object *obj)
data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 0xf00f);
data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 0x60);
env->cpucfg[20] = data;
+
+ env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
}
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
@@ -179,12 +181,45 @@ static void loongarch_cpu_reset(DeviceState *dev)
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
CPULoongArchState *env = &cpu->env;
+ int n;
lacc->parent_reset(dev);
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
env->fcsr0 = 0x0;
+ /* Set csr registers value after reset */
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1);
+
+ env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
+ env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
+ env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
+ env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);
+
+ env->CSR_MISC = 0;
+
+ env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
+ env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);
+
+ env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
+ env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
+ env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
+ env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
+ env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
+ env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
+
+ for (n = 0; n < 4; n++) {
+ env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
+ env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
+ env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
+ env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
+ }
+
restore_fp_status(env);
cs->exception_index = EXCP_NONE;
}
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index b036cdee5f..cf7fc46f72 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -11,6 +11,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "hw/registerfields.h"
+#include "cpu-csr.h"
#define TCG_GUEST_DEFAULT_MO (0)
@@ -170,6 +171,62 @@ struct CPULoongArchState {
uint64_t llval;
uint64_t badaddr;
+
+ /* LoongArch CSR registers */
+ uint64_t CSR_CRMD;
+ uint64_t CSR_PRMD;
+ uint64_t CSR_EUEN;
+ uint64_t CSR_MISC;
+ uint64_t CSR_ECFG;
+ uint64_t CSR_ESTAT;
+ uint64_t CSR_ERA;
+ uint64_t CSR_BADV;
+ uint64_t CSR_BADI;
+ uint64_t CSR_EENTRY;
+ uint64_t CSR_TLBIDX;
+ uint64_t CSR_TLBEHI;
+ uint64_t CSR_TLBELO0;
+ uint64_t CSR_TLBELO1;
+ uint64_t CSR_ASID;
+ uint64_t CSR_PGDL;
+ uint64_t CSR_PGDH;
+ uint64_t CSR_PGD;
+ uint64_t CSR_PWCL;
+ uint64_t CSR_PWCH;
+ uint64_t CSR_STLBPS;
+ uint64_t CSR_RVACFG;
+ uint64_t CSR_CPUID;
+ uint64_t CSR_PRCFG1;
+ uint64_t CSR_PRCFG2;
+ uint64_t CSR_PRCFG3;
+ uint64_t CSR_SAVE[16];
+ uint64_t CSR_TID;
+ uint64_t CSR_TCFG;
+ uint64_t CSR_TVAL;
+ uint64_t CSR_CNTC;
+ uint64_t CSR_TICLR;
+ uint64_t CSR_LLBCTL;
+ uint64_t CSR_IMPCTL1;
+ uint64_t CSR_IMPCTL2;
+ uint64_t CSR_TLBRENTRY;
+ uint64_t CSR_TLBRBADV;
+ uint64_t CSR_TLBRERA;
+ uint64_t CSR_TLBRSAVE;
+ uint64_t CSR_TLBRELO0;
+ uint64_t CSR_TLBRELO1;
+ uint64_t CSR_TLBREHI;
+ uint64_t CSR_TLBRPRMD;
+ uint64_t CSR_MERRCTL;
+ uint64_t CSR_MERRINFO1;
+ uint64_t CSR_MERRINFO2;
+ uint64_t CSR_MERRENTRY;
+ uint64_t CSR_MERRERA;
+ uint64_t CSR_MERRSAVE;
+ uint64_t CSR_CTAG;
+ uint64_t CSR_DMW[4];
+ uint64_t CSR_DBG;
+ uint64_t CSR_DERA;
+ uint64_t CSR_DSAVE;
};
/**
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 02/30] target/loongarch: Add CSR registers definition
2022-01-08 9:13 ` [RFC PATCH v4 02/30] target/loongarch: Add CSR registers definition Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> 1.Define All the CSR registers and its field.
> 2.Set some default csr values.
Unnecessary explanation; the code addition itself should be obvious
enough as to its intention.
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/cpu-csr.h | 236 +++++++++++++++++++++++++++++++++++++
> target/loongarch/cpu.c | 35 ++++++
> target/loongarch/cpu.h | 57 +++++++++
> 3 files changed, 328 insertions(+)
> create mode 100644 target/loongarch/cpu-csr.h
>
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> new file mode 100644
> index 0000000000..7a57b7ea36
> --- /dev/null
> +++ b/target/loongarch/cpu-csr.h
> @@ -0,0 +1,236 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch CPU CSR registers
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef LOONGARCH_CPU_CSR_H
> +#define LOONGARCH_CPU_CSR_H
> +
> +/* Base on: kernal: arch/loongarch/include/asm/loongarch.h */
"Based on kernel definitions: ..."
> +
> +/* Basic CSR register */
> +#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
Do we really need all these ad-hoc translated names when people could
easily be pointed to the manuals? This way translation errors can be
avoided, such as...
> +FIELD(CSR_CRMD, PLV, 0, 2)
> +FIELD(CSR_CRMD, IE, 2, 1)
> +FIELD(CSR_CRMD, DA, 3, 1)
> +FIELD(CSR_CRMD, PG, 4, 1)
> +FIELD(CSR_CRMD, DATF, 5, 2)
> +FIELD(CSR_CRMD, DATM, 7, 2)
> +FIELD(CSR_CRMD, WE, 9, 1)
> +
> +#define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
> +FIELD(CSR_PRMD, PPLV, 0, 2)
> +FIELD(CSR_PRMD, PIE, 2, 1)
> +FIELD(CSR_PRMD, PWE, 3, 1)
> +
> +#define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
> +FIELD(CSR_EUEN, FPE, 0, 1)
> +FIELD(CSR_EUEN, SXE, 1, 1)
> +FIELD(CSR_EUEN, ASXE, 2, 1)
> +FIELD(CSR_EUEN, BTE, 3, 1)
> +
> +#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
> +
> +#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
> +FIELD(CSR_ECFG, LIE, 0, 13)
> +FIELD(CSR_ECFG, VS, 16, 3)
> +
> +#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
> +FIELD(CSR_ESTAT, IS, 0, 13)
> +FIELD(CSR_ESTAT, ECODE, 16, 6)
> +FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
> +
> +#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
what's "plus external interrupt"?
> +#define EXCCODE_INT 0
> +#define EXCCODE_PIL 1
> +#define EXCCODE_PIS 2
> +#define EXCCODE_PIF 3
> +#define EXCCODE_PME 4
> +#define EXCCODE_PNR 5
> +#define EXCCODE_PNX 6
> +#define EXCCODE_PPI 7
> +#define EXCCODE_ADEF 8 /* Have different expsubcode */
"different exception subcodes"
> +#define EXCCODE_ADEM 8 /* Have different expsubcode */
> +#define EXCCODE_ALE 9
> +#define EXCCODE_BCE 10
> +#define EXCCODE_SYS 11
> +#define EXCCODE_BRK 12
> +#define EXCCODE_INE 13
> +#define EXCCODE_IPE 14
> +#define EXCCODE_FPD 15
> +#define EXCCODE_SXD 16
> +#define EXCCODE_ASXD 17
> +#define EXCCODE_FPE 18 /* Have different expsubcode */
> +#define EXCCODE_VFPE 18
> +#define EXCCODE_WPEF 19 /* Have different expsubcode */
> +#define EXCCODE_WPEM 19
> +#define EXCCODE_BTD 20
> +#define EXCCODE_BTE 21
> +#define EXCCODE_DBP 26 /* Reserved decode used for debug */
"decode"? also "used for debugging"?
> +
> +#define LOONGARCH_CSR_ERA 0x6 /* Exception return address */
> +
> +#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
> +
> +#define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
> +
> +#define LOONGARCH_CSR_EENTRY 0xc /* Exception enter base address */
"exception entrypoint"?
> +
> +/* TLB related CSR register */
"CSR register" is duplication; "R" is already "register". Also "CSRs"...
> +#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
> +FIELD(CSR_TLBIDX, INDEX, 0, 12)
> +FIELD(CSR_TLBIDX, PS, 24, 6)
> +FIELD(CSR_TLBIDX, NE, 31, 1)
> +
> +#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi without ASID */
I cannot find the "without ASID" part in the Chinese manual...
> +FIELD(CSR_TLBEHI, VPPN, 13, 35)
> +
> +#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
> +#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
> +FIELD(TLBENTRY, V, 0, 1)
> +FIELD(TLBENTRY, D, 1, 1)
> +FIELD(TLBENTRY, PLV, 2, 2)
> +FIELD(TLBENTRY, MAT, 4, 2)
> +FIELD(TLBENTRY, G, 6, 1)
> +FIELD(TLBENTRY, PPN, 12, 36)
> +FIELD(TLBENTRY, NR, 61, 1)
> +FIELD(TLBENTRY, NX, 62, 1)
> +FIELD(TLBENTRY, RPLV, 63, 1)
> +
> +#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
> +FIELD(CSR_ASID, ASID, 0, 10)
> +FIELD(CSR_ASID, ASIDBITS, 16, 8)
> +
> +/* Page table base address when badv[47] = 0 */
> +#define LOONGARCH_CSR_PGDL 0x19
> +/* Page table base address when badv[47] = 1 */
> +#define LOONGARCH_CSR_PGDH 0x1a
> +
> +#define LOONGARCH_CSR_PGD 0x1b /* Page table base */
> +
> +/* Page walk controller's low addr */
> +#define LOONGARCH_CSR_PWCL 0x1c
> +FIELD(CSR_PWCL, PTBASE, 0, 5)
> +FIELD(CSR_PWCL, PTWIDTH, 5, 5)
> +FIELD(CSR_PWCL, DIR1_BASE, 10, 5)
> +FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5)
> +FIELD(CSR_PWCL, DIR2_BASE, 20, 5)
> +FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5)
> +FIELD(CSR_PWCL, PTEWIDTH, 30, 2)
> +
> +/* Page walk controller's high addr */
> +#define LOONGARCH_CSR_PWCH 0x1d
> +FIELD(CSR_PWCH, DIR3_BASE, 0, 6)
> +FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6)
> +FIELD(CSR_PWCH, DIR4_BASE, 12, 6)
> +FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
> +
> +#define LOONGARCH_CSR_STLBPS 0x1e /*Stlb page size*/
Spaces around the comment text...
> +FIELD(CSR_STLBPS, PS, 0, 5)
> +
> +#define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address config */
> +FIELD(CSR_RVACFG, RBITS, 0, 4)
> +
> +/* Config CSR registers */
> +#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
> +
> +#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
> +FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4)
> +FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8)
> +FIELD(CSR_PRCFG1, VSMAX, 12, 3)
> +
> +#define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
> +
> +#define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
> +FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4)
> +FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8)
> +FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8)
> +FIELD(CSR_PRCFG3, STLB_SETS, 20, 8)
> +
> +/*
> + * Save registers count can read from PRCFG1.SAVE_NUM
> + * The Min count is 1. Max count is 15.
> + */
> +#define LOONGARCH_CSR_SAVE(N) (0x30 + N)
> +
> +/* Timer registers */
> +#define LOONGARCH_CSR_TID 0x40 /* Timer ID */
> +
> +#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
> +FIELD(CSR_TCFG, EN, 0, 1)
> +FIELD(CSR_TCFG, PERIODIC, 1, 1)
> +FIELD(CSR_TCFG, INIT_VAL, 2, 46)
> +
> +#define LOONGARCH_CSR_TVAL 0x42 /* Timer ticks remain */
> +
> +#define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
> +
> +#define LOONGARCH_CSR_TICLR 0x44 /* Timer interrupt clear */
> +
> +/* LLBCTL register */
> +#define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
> +FIELD(CSR_LLBCTL, ROLLB, 0, 1)
> +FIELD(CSR_LLBCTL, WCLLB, 1, 1)
> +FIELD(CSR_LLBCTL, KLO, 2, 1)
> +
> +/* Implement dependent */
> +#define LOONGARCH_CSR_IMPCTL1 0x80 /* LoongArch config1 */
> +
> +#define LOONGARCH_CSR_IMPCTL2 0x81 /* LoongArch config2*/
Space after "control"...
> +
> +/* TLB Refill registers */
> +#define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */
> +#define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
Proper casing, this seems to just be "BADV" according to the manual.
> +#define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
> +#define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */
> +FIELD(CSR_TLBRERA, ISTLBR, 0, 1)
> +FIELD(CSR_TLBRERA, PC, 2, 62)
> +#define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
> +#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
> +#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
> +FIELD(CSR_TLBREHI, PS, 0, 6)
> +FIELD(CSR_TLBREHI, VPPN, 13, 35)
> +#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
> +FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
> +FIELD(CSR_TLBRPRMD, PIE, 2, 1)
> +FIELD(CSR_TLBRPRMD, PWE, 4, 1)
> +
> +/* Machine Error registers */
> +#define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */
> +FIELD(CSR_MERRCTL, ISMERR, 0, 1)
> +#define LOONGARCH_CSR_MERRINFO1 0x91
> +#define LOONGARCH_CSR_MERRINFO2 0x92
> +#define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception base */
> +#define LOONGARCH_CSR_MERRERA 0x94 /* MError exception PC */
> +#define LOONGARCH_CSR_MERRSAVE 0x95 /* KScratch for error exception */
> +
> +#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
This "TagLo + TagHi" is not present in the manual either.
> +
> +/* Direct map windows */
> +#define LOONGARCH_CSR_DMW(N) (0x180 + N) /* direct map win MEM & IF */
> +FIELD(CSR_DMW, PLV0, 0, 1)
> +FIELD(CSR_DMW, PLV1, 1, 1)
> +FIELD(CSR_DMW, PLV2, 2, 1)
> +FIELD(CSR_DMW, PLV3, 3, 1)
> +FIELD(CSR_DMW, MAT, 4, 2)
> +FIELD(CSR_DMW, VSEG, 60, 4)
> +
> +#define dmw_va2pa(va) \
> + (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
> +
> +/* Debug registers */
> +#define LOONGARCH_CSR_DBG 0x500 /* debug config */
> +FIELD(CSR_DBG, DST, 0, 1)
> +FIELD(CSR_DBG, DREV, 1, 7)
> +FIELD(CSR_DBG, DEI, 8, 1)
> +FIELD(CSR_DBG, DCL, 9, 1)
> +FIELD(CSR_DBG, DFW, 10, 1)
> +FIELD(CSR_DBG, DMW, 11, 1)
> +FIELD(CSR_DBG, ECODE, 16, 6)
> +
> +#define LOONGARCH_CSR_DERA 0x501 /* Debug era */
> +#define LOONGARCH_CSR_DSAVE 0x502 /* Debug save */
> +
> +#endif /* LOONGARCH_CPU_CSR_H */
As pointed out in the numerous comments above, there are so many errors
and inconsistencies in the comments, that it's probably better to just
remove all of them. People working with this low level piece of software
are expected to be familiar with the manuals, so the comments really
don't serve any purpose if all they did were explaining the abbreviations.
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 883c6c623f..ed03ec2986 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -156,6 +156,8 @@ static void loongarch_3a5000_initfn(Object *obj)
> data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 0xf00f);
> data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 0x60);
> env->cpucfg[20] = data;
> +
> + env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
> }
>
> static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
> @@ -179,12 +181,45 @@ static void loongarch_cpu_reset(DeviceState *dev)
> LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
> CPULoongArchState *env = &cpu->env;
> + int n;
>
> lacc->parent_reset(dev);
>
> env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
> env->fcsr0 = 0x0;
>
> + /* Set csr registers value after reset */
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1);
> +
> + env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
> + env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
> + env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
> + env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);
> +
> + env->CSR_MISC = 0;
> +
> + env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
> + env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);
> +
> + env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
> + env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
> + env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
> + env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
> + env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
> + env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
> +
> + for (n = 0; n < 4; n++) {
> + env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
> + env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
> + env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
> + env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
> + }
> +
> restore_fp_status(env);
> cs->exception_index = EXCP_NONE;
> }
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index b036cdee5f..cf7fc46f72 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -11,6 +11,7 @@
> #include "exec/cpu-defs.h"
> #include "fpu/softfloat-types.h"
> #include "hw/registerfields.h"
> +#include "cpu-csr.h"
>
> #define TCG_GUEST_DEFAULT_MO (0)
>
> @@ -170,6 +171,62 @@ struct CPULoongArchState {
> uint64_t llval;
>
> uint64_t badaddr;
> +
> + /* LoongArch CSR registers */
> + uint64_t CSR_CRMD;
> + uint64_t CSR_PRMD;
> + uint64_t CSR_EUEN;
> + uint64_t CSR_MISC;
> + uint64_t CSR_ECFG;
> + uint64_t CSR_ESTAT;
> + uint64_t CSR_ERA;
> + uint64_t CSR_BADV;
> + uint64_t CSR_BADI;
> + uint64_t CSR_EENTRY;
> + uint64_t CSR_TLBIDX;
> + uint64_t CSR_TLBEHI;
> + uint64_t CSR_TLBELO0;
> + uint64_t CSR_TLBELO1;
> + uint64_t CSR_ASID;
> + uint64_t CSR_PGDL;
> + uint64_t CSR_PGDH;
> + uint64_t CSR_PGD;
> + uint64_t CSR_PWCL;
> + uint64_t CSR_PWCH;
> + uint64_t CSR_STLBPS;
> + uint64_t CSR_RVACFG;
> + uint64_t CSR_CPUID;
> + uint64_t CSR_PRCFG1;
> + uint64_t CSR_PRCFG2;
> + uint64_t CSR_PRCFG3;
> + uint64_t CSR_SAVE[16];
> + uint64_t CSR_TID;
> + uint64_t CSR_TCFG;
> + uint64_t CSR_TVAL;
> + uint64_t CSR_CNTC;
> + uint64_t CSR_TICLR;
> + uint64_t CSR_LLBCTL;
> + uint64_t CSR_IMPCTL1;
> + uint64_t CSR_IMPCTL2;
> + uint64_t CSR_TLBRENTRY;
> + uint64_t CSR_TLBRBADV;
> + uint64_t CSR_TLBRERA;
> + uint64_t CSR_TLBRSAVE;
> + uint64_t CSR_TLBRELO0;
> + uint64_t CSR_TLBRELO1;
> + uint64_t CSR_TLBREHI;
> + uint64_t CSR_TLBRPRMD;
> + uint64_t CSR_MERRCTL;
> + uint64_t CSR_MERRINFO1;
> + uint64_t CSR_MERRINFO2;
> + uint64_t CSR_MERRENTRY;
> + uint64_t CSR_MERRERA;
> + uint64_t CSR_MERRSAVE;
> + uint64_t CSR_CTAG;
> + uint64_t CSR_DMW[4];
> + uint64_t CSR_DBG;
> + uint64_t CSR_DERA;
> + uint64_t CSR_DSAVE;
Field names should be lower-case snake_case form, as is the case for
overwhelming majority of target CPUState definitions I checked (except
MIPS, which you might be basing your code on). For sake of consistency,
please change all of them to snake_case.
> };
>
> /**
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
2022-01-08 9:13 ` [RFC PATCH v4 01/30] target/loongarch: Update README Xiaojuan Yang
2022-01-08 9:13 ` [RFC PATCH v4 02/30] target/loongarch: Add CSR registers definition Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-15 12:52 ` Mark Cave-Ayland
2022-01-08 9:13 ` [RFC PATCH v4 04/30] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
` (28 subsequent siblings)
31 siblings, 2 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch introduce vmstate_loongarch_cpu
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.c | 3 ++
target/loongarch/internals.h | 4 ++
target/loongarch/machine.c | 84 ++++++++++++++++++++++++++++++++++++
target/loongarch/meson.build | 6 +++
4 files changed, 97 insertions(+)
create mode 100644 target/loongarch/machine.c
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ed03ec2986..6e3dc5e6fa 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->has_work = loongarch_cpu_has_work;
cc->dump_state = loongarch_cpu_dump_state;
cc->set_pc = loongarch_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ dc->vmsd = &vmstate_loongarch_cpu;
+#endif
cc->disas_set_info = loongarch_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops = &loongarch_tcg_ops;
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 774a87ec80..c8e6f7012c 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
void restore_fp_status(CPULoongArchState *env);
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_loongarch_cpu;
+#endif
+
#endif
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
new file mode 100644
index 0000000000..b9effe6db2
--- /dev/null
+++ b/target/loongarch/machine.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch machine State
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+/* LoongArch CPU state */
+
+const VMStateDescription vmstate_loongarch_cpu = {
+ .name = "cpu",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+
+ VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
+ VMSTATE_UINTTL(env.pc, LoongArchCPU),
+ VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
+ VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
+
+ /* Remaining CSR registers */
+ VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
+ VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
+ VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
+ VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
+ /* debug */
+ VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
+
+ VMSTATE_END_OF_LIST()
+ },
+};
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index bcb076e55f..103f36ee15 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -14,6 +14,12 @@ loongarch_tcg_ss.add(files(
))
loongarch_tcg_ss.add(zlib)
+loongarch_softmmu_ss = ss.source_set()
+loongarch_softmmu_ss.add(files(
+ 'machine.c',
+))
+
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
target_arch += {'loongarch': loongarch_ss}
+target_softmmu_arch += {'loongarch': loongarch_softmmu_ss}
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.
2022-01-08 9:13 ` [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
2022-01-15 12:52 ` Mark Cave-Ayland
1 sibling, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This patch introduce vmstate_loongarch_cpu
Again, pointless commit message.
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> Reviewed-by: Richard Henderson<richard.henderson@linaro.org>
> ---
> target/loongarch/cpu.c | 3 ++
> target/loongarch/internals.h | 4 ++
> target/loongarch/machine.c | 84 ++++++++++++++++++++++++++++++++++++
> target/loongarch/meson.build | 6 +++
> 4 files changed, 97 insertions(+)
> create mode 100644 target/loongarch/machine.c
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index ed03ec2986..6e3dc5e6fa 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
> cc->has_work = loongarch_cpu_has_work;
> cc->dump_state = loongarch_cpu_dump_state;
> cc->set_pc = loongarch_cpu_set_pc;
> +#ifndef CONFIG_USER_ONLY
> + dc->vmsd = &vmstate_loongarch_cpu;
> +#endif
> cc->disas_set_info = loongarch_cpu_disas_set_info;
> #ifdef CONFIG_TCG
> cc->tcg_ops = &loongarch_tcg_ops;
> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
> index 774a87ec80..c8e6f7012c 100644
> --- a/target/loongarch/internals.h
> +++ b/target/loongarch/internals.h
> @@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
>
> void restore_fp_status(CPULoongArchState *env);
>
> +#ifndef CONFIG_USER_ONLY
> +extern const VMStateDescription vmstate_loongarch_cpu;
> +#endif
> +
> #endif
> diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
> new file mode 100644
> index 0000000000..b9effe6db2
> --- /dev/null
> +++ b/target/loongarch/machine.c
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch machine State
Use consistent casing; "machine state" or "Machine State".
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "migration/cpu.h"
> +
> +/* LoongArch CPU state */
> +
> +const VMStateDescription vmstate_loongarch_cpu = {
> + .name = "cpu",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .fields = (VMStateField[]) {
> +
> + VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
> + VMSTATE_UINTTL(env.pc, LoongArchCPU),
> + VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
> + VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
> +
> + /* Remaining CSR registers */
"Remaining CSRs"
> + VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
> + VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
> + VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
> + VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
> + /* debug */
"debug registers"
> + VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
> +
> + VMSTATE_END_OF_LIST()
> + },
> +};
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index bcb076e55f..103f36ee15 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -14,6 +14,12 @@ loongarch_tcg_ss.add(files(
> ))
> loongarch_tcg_ss.add(zlib)
>
> +loongarch_softmmu_ss = ss.source_set()
> +loongarch_softmmu_ss.add(files(
> + 'machine.c',
> +))
> +
> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
>
> target_arch += {'loongarch': loongarch_ss}
> +target_softmmu_arch += {'loongarch': loongarch_softmmu_ss}
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.
2022-01-08 9:13 ` [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
@ 2022-01-15 12:52 ` Mark Cave-Ayland
2022-01-27 10:01 ` yangxiaojuan
1 sibling, 1 reply; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 12:52 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: richard.henderson, philmd, Song Gao
On 08/01/2022 09:13, Xiaojuan Yang wrote:
> This patch introduce vmstate_loongarch_cpu
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/loongarch/cpu.c | 3 ++
> target/loongarch/internals.h | 4 ++
> target/loongarch/machine.c | 84 ++++++++++++++++++++++++++++++++++++
> target/loongarch/meson.build | 6 +++
> 4 files changed, 97 insertions(+)
> create mode 100644 target/loongarch/machine.c
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index ed03ec2986..6e3dc5e6fa 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
> cc->has_work = loongarch_cpu_has_work;
> cc->dump_state = loongarch_cpu_dump_state;
> cc->set_pc = loongarch_cpu_set_pc;
> +#ifndef CONFIG_USER_ONLY
> + dc->vmsd = &vmstate_loongarch_cpu;
> +#endif
Do we need CONFIG_USER_ONLY guards around dc->vmsd? I'd expect this to simply be
ignored in linux-user mode. Again it's a bit hard to see the full context without
having the complete series available in git somewhere.
> cc->disas_set_info = loongarch_cpu_disas_set_info;
> #ifdef CONFIG_TCG
> cc->tcg_ops = &loongarch_tcg_ops;
> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
> index 774a87ec80..c8e6f7012c 100644
> --- a/target/loongarch/internals.h
> +++ b/target/loongarch/internals.h
> @@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
>
> void restore_fp_status(CPULoongArchState *env);
>
> +#ifndef CONFIG_USER_ONLY
> +extern const VMStateDescription vmstate_loongarch_cpu;
> +#endif
> +
> #endif
> diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
> new file mode 100644
> index 0000000000..b9effe6db2
> --- /dev/null
> +++ b/target/loongarch/machine.c
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch machine State
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "migration/cpu.h"
> +
> +/* LoongArch CPU state */
> +
> +const VMStateDescription vmstate_loongarch_cpu = {
> + .name = "cpu",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .fields = (VMStateField[]) {
> +
> + VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
> + VMSTATE_UINTTL(env.pc, LoongArchCPU),
> + VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
> + VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
> +
> + /* Remaining CSR registers */
> + VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
> + VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
> + VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
> + VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
> + /* debug */
> + VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
> + VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
> +
> + VMSTATE_END_OF_LIST()
> + },
> +};
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index bcb076e55f..103f36ee15 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -14,6 +14,12 @@ loongarch_tcg_ss.add(files(
> ))
> loongarch_tcg_ss.add(zlib)
>
> +loongarch_softmmu_ss = ss.source_set()
> +loongarch_softmmu_ss.add(files(
> + 'machine.c',
> +))
> +
> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
>
> target_arch += {'loongarch': loongarch_ss}
> +target_softmmu_arch += {'loongarch': loongarch_softmmu_ss}
ATB,
Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.
2022-01-15 12:52 ` Mark Cave-Ayland
@ 2022-01-27 10:01 ` yangxiaojuan
0 siblings, 0 replies; 56+ messages in thread
From: yangxiaojuan @ 2022-01-27 10:01 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel; +Cc: richard.henderson, Song Gao
Hi, Mark
在 2022年01月15日 20:52, Mark Cave-Ayland 写道:
> On 08/01/2022 09:13, Xiaojuan Yang wrote:
>
>> This patch introduce vmstate_loongarch_cpu
>>
>> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/loongarch/cpu.c | 3 ++
>> target/loongarch/internals.h | 4 ++
>> target/loongarch/machine.c | 84 ++++++++++++++++++++++++++++++++++++
>> target/loongarch/meson.build | 6 +++
>> 4 files changed, 97 insertions(+)
>> create mode 100644 target/loongarch/machine.c
>>
>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index ed03ec2986..6e3dc5e6fa 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
>> cc->has_work = loongarch_cpu_has_work;
>> cc->dump_state = loongarch_cpu_dump_state;
>> cc->set_pc = loongarch_cpu_set_pc;
>> +#ifndef CONFIG_USER_ONLY
>> + dc->vmsd = &vmstate_loongarch_cpu;
>> +#endif
>
> Do we need CONFIG_USER_ONLY guards around dc->vmsd? I'd expect this to simply be ignored in linux-user mode. Again it's a bit hard to see the full context without having the complete series available in git somewhere.
I have reorganized the patch and prepare to send the V5 patch.
Here we define the vmsd struct in the machine.c which only used by system mode. So we need the CONFIG_USER_ONLY.
You can get LoongArch qemu series code like this:
git clone https://github.com/loongson/qemu.git
git checkout branch tcg-dev
xiaojuan,
thanks
>
>> cc->disas_set_info = loongarch_cpu_disas_set_info;
>> #ifdef CONFIG_TCG
>> cc->tcg_ops = &loongarch_tcg_ops;
>> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
>> index 774a87ec80..c8e6f7012c 100644
>> --- a/target/loongarch/internals.h
>> +++ b/target/loongarch/internals.h
>> @@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
>> void restore_fp_status(CPULoongArchState *env);
>> +#ifndef CONFIG_USER_ONLY
>> +extern const VMStateDescription vmstate_loongarch_cpu;
>> +#endif
>> +
>> #endif
>> diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
>> new file mode 100644
>> index 0000000000..b9effe6db2
>> --- /dev/null
>> +++ b/target/loongarch/machine.c
>> @@ -0,0 +1,84 @@
>> +/* SPDX-License-Identifier: GPL-2.0-or-later */
>> +/*
>> + * QEMU LoongArch machine State
>> + *
>> + * Copyright (c) 2021 Loongson Technology Corporation Limited
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "cpu.h"
>> +#include "migration/cpu.h"
>> +
>> +/* LoongArch CPU state */
>> +
>> +const VMStateDescription vmstate_loongarch_cpu = {
>> + .name = "cpu",
>> + .version_id = 0,
>> + .minimum_version_id = 0,
>> + .fields = (VMStateField[]) {
>> +
>> + VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
>> + VMSTATE_UINTTL(env.pc, LoongArchCPU),
>> + VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
>> + VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
>> +
>> + /* Remaining CSR registers */
>> + VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
>> + VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
>> + VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
>> + VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
>> + /* debug */
>> + VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
>> + VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
>> +
>> + VMSTATE_END_OF_LIST()
>> + },
>> +};
>> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
>> index bcb076e55f..103f36ee15 100644
>> --- a/target/loongarch/meson.build
>> +++ b/target/loongarch/meson.build
>> @@ -14,6 +14,12 @@ loongarch_tcg_ss.add(files(
>> ))
>> loongarch_tcg_ss.add(zlib)
>> +loongarch_softmmu_ss = ss.source_set()
>> +loongarch_softmmu_ss.add(files(
>> + 'machine.c',
>> +))
>> +
>> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
>> target_arch += {'loongarch': loongarch_ss}
>> +target_softmmu_arch += {'loongarch': loongarch_softmmu_ss}
>
>
> ATB,
>
> Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 04/30] target/loongarch: Implement qmp_query_cpu_definitions()
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (2 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-08 9:13 ` [RFC PATCH v4 05/30] target/loongarch: Add constant timer support Xiaojuan Yang
` (27 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch introduce qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
qapi/machine-target.json | 6 ++++--
target/loongarch/cpu.c | 26 ++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index f5ec4bc172..682dc86b42 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -324,7 +324,8 @@
'TARGET_ARM',
'TARGET_I386',
'TARGET_S390X',
- 'TARGET_MIPS' ] } }
+ 'TARGET_MIPS',
+ 'TARGET_LOONGARCH64' ] } }
##
# @query-cpu-definitions:
@@ -340,4 +341,5 @@
'TARGET_ARM',
'TARGET_I386',
'TARGET_S390X',
- 'TARGET_MIPS' ] } }
+ 'TARGET_MIPS',
+ 'TARGET_LOONGARCH64' ] } }
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 6e3dc5e6fa..690eeea2e6 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -351,3 +351,29 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
};
DEFINE_TYPES(loongarch_cpu_type_infos)
+
+static void loongarch_cpu_add_definition(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CpuDefinitionInfoList **cpu_list = user_data;
+ CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1);
+ const char *typename = object_class_get_name(oc);
+
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU));
+ info->q_typename = g_strdup(typename);
+
+ QAPI_LIST_PREPEND(*cpu_list, info);
+}
+
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+{
+ CpuDefinitionInfoList *cpu_list = NULL;
+ GSList *list;
+
+ list = object_class_get_list(TYPE_LOONGARCH_CPU, false);
+ g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list);
+ g_slist_free(list);
+
+ return cpu_list;
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 04/30] target/loongarch: Implement qmp_query_cpu_definitions()
2022-01-08 9:13 ` [RFC PATCH v4 04/30] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This patch introduce qmp_query_cpu_definitions interface.
"implments"; however the whole sentence becomes nearly identical to the
title, so it's better to remove this sentence after all.
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> Reviewed-by: Richard Henderson<richard.henderson@linaro.org>
> ---
> qapi/machine-target.json | 6 ++++--
> target/loongarch/cpu.c | 26 ++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/qapi/machine-target.json b/qapi/machine-target.json
> index f5ec4bc172..682dc86b42 100644
> --- a/qapi/machine-target.json
> +++ b/qapi/machine-target.json
> @@ -324,7 +324,8 @@
> 'TARGET_ARM',
> 'TARGET_I386',
> 'TARGET_S390X',
> - 'TARGET_MIPS' ] } }
> + 'TARGET_MIPS',
> + 'TARGET_LOONGARCH64' ] } }
>
> ##
> # @query-cpu-definitions:
> @@ -340,4 +341,5 @@
> 'TARGET_ARM',
> 'TARGET_I386',
> 'TARGET_S390X',
> - 'TARGET_MIPS' ] } }
> + 'TARGET_MIPS',
> + 'TARGET_LOONGARCH64' ] } }
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 6e3dc5e6fa..690eeea2e6 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -351,3 +351,29 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
> };
>
> DEFINE_TYPES(loongarch_cpu_type_infos)
> +
> +static void loongarch_cpu_add_definition(gpointer data, gpointer user_data)
> +{
> + ObjectClass *oc = data;
> + CpuDefinitionInfoList **cpu_list = user_data;
> + CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1);
> + const char *typename = object_class_get_name(oc);
> +
> + info->name = g_strndup(typename,
> + strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU));
> + info->q_typename = g_strdup(typename);
> +
> + QAPI_LIST_PREPEND(*cpu_list, info);
> +}
> +
> +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
> +{
> + CpuDefinitionInfoList *cpu_list = NULL;
> + GSList *list;
> +
> + list = object_class_get_list(TYPE_LOONGARCH_CPU, false);
> + g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list);
> + g_slist_free(list);
> +
> + return cpu_list;
> +}
After removing the commit message body:
Reviewed-by: WANG Xuerui <git@xen0n.name>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 05/30] target/loongarch: Add constant timer support
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (3 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 04/30] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-15 13:02 ` Mark Cave-Ayland
2022-01-08 9:13 ` [RFC PATCH v4 06/30] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
` (26 subsequent siblings)
31 siblings, 2 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/constant_timer.c | 63 +++++++++++++++++++++++++++++++
target/loongarch/cpu.c | 9 +++++
target/loongarch/cpu.h | 10 +++++
target/loongarch/meson.build | 1 +
4 files changed, 83 insertions(+)
create mode 100644 target/loongarch/constant_timer.c
diff --git a/target/loongarch/constant_timer.c b/target/loongarch/constant_timer.c
new file mode 100644
index 0000000000..e7d0f5ffe7
--- /dev/null
+++ b/target/loongarch/constant_timer.c
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch constant timer support
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/loongarch/loongarch.h"
+#include "qemu/timer.h"
+#include "cpu.h"
+
+#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
+#define CONSTANT_TIMER_TICK_MASK 0xfffffffffffcUL
+#define CONSTANT_TIMER_ENABLE 0x1UL
+
+/* LoongArch timer */
+uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu)
+{
+ return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD;
+}
+
+uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu)
+{
+ uint64_t now, expire;
+
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ expire = timer_expire_time_ns(&cpu->timer);
+
+ return (expire - now) / TIMER_PERIOD;
+}
+
+void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
+ uint64_t value)
+{
+ CPULoongArchState *env = &cpu->env;
+ uint64_t now, next;
+
+ env->CSR_TCFG = value;
+ if (value & CONSTANT_TIMER_ENABLE) {
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ next = now + (value & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
+ timer_mod(&cpu->timer, next);
+ }
+}
+
+void loongarch_constant_timer_cb(void *opaque)
+{
+ LoongArchCPU *cpu = opaque;
+ CPULoongArchState *env = &cpu->env;
+ uint64_t now, next;
+
+ if (FIELD_EX64(env->CSR_TCFG, CSR_TCFG, PERIODIC)) {
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ next = now + (env->CSR_TCFG & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
+ timer_mod(&cpu->timer, next);
+ } else {
+ env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
+ }
+
+ env->CSR_ESTAT |= 1 << IRQ_TIMER;
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+}
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 690eeea2e6..823951dddd 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -235,12 +235,21 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
Error *local_err = NULL;
+#ifndef CONFIG_USER_ONLY
+ LoongArchCPU *cpu = LOONGARCH_CPU(dev);
+#endif
+
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
+#ifndef CONFIG_USER_ONLY
+ timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
+ &loongarch_constant_timer_cb, cpu);
+#endif
+
cpu_reset(cs);
qemu_init_vcpu(cs);
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index cf7fc46f72..ef84584678 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -12,6 +12,7 @@
#include "fpu/softfloat-types.h"
#include "hw/registerfields.h"
#include "cpu-csr.h"
+#include "qemu/timer.h"
#define TCG_GUEST_DEFAULT_MO (0)
@@ -148,6 +149,9 @@ FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
extern const char * const regnames[32];
extern const char * const fregnames[32];
+#define N_IRQS 14
+#define IRQ_TIMER 11
+
typedef struct CPULoongArchState CPULoongArchState;
struct CPULoongArchState {
uint64_t gpr[32];
@@ -242,6 +246,7 @@ struct LoongArchCPU {
CPUNegativeOffsetState neg;
CPULoongArchState env;
+ QEMUTimer timer; /* Internal timer */
};
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
@@ -306,4 +311,9 @@ enum {
#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
+void loongarch_constant_timer_cb(void *opaque);
+uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
+uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
+void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
+ uint64_t value);
#endif /* LOONGARCH_CPU_H */
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 103f36ee15..6168e910a0 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -17,6 +17,7 @@ loongarch_tcg_ss.add(zlib)
loongarch_softmmu_ss = ss.source_set()
loongarch_softmmu_ss.add(files(
'machine.c',
+ 'constant_timer.c',
))
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 05/30] target/loongarch: Add constant timer support
2022-01-08 9:13 ` [RFC PATCH v4 05/30] target/loongarch: Add constant timer support Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
2022-01-15 13:02 ` Mark Cave-Ayland
1 sibling, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/constant_timer.c | 63 +++++++++++++++++++++++++++++++
> target/loongarch/cpu.c | 9 +++++
> target/loongarch/cpu.h | 10 +++++
> target/loongarch/meson.build | 1 +
> 4 files changed, 83 insertions(+)
> create mode 100644 target/loongarch/constant_timer.c
>
> diff --git a/target/loongarch/constant_timer.c b/target/loongarch/constant_timer.c
> new file mode 100644
> index 0000000000..e7d0f5ffe7
> --- /dev/null
> +++ b/target/loongarch/constant_timer.c
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch constant timer support
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "qemu/timer.h"
> +#include "cpu.h"
> +
> +#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
"MHz"
> +#define CONSTANT_TIMER_TICK_MASK 0xfffffffffffcUL
> +#define CONSTANT_TIMER_ENABLE 0x1UL
> +
> +/* LoongArch timer */
Looks like this comment is for some type definitions, but the function
below is just an accessor, so remove it? The whole file is about the
"LoongArch timer" after all.
> +uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu)
> +{
> + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD;
> +}
> +
> +uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu)
> +{
> + uint64_t now, expire;
> +
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + expire = timer_expire_time_ns(&cpu->timer);
> +
> + return (expire - now) / TIMER_PERIOD;
> +}
> +
> +void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
> + uint64_t value)
> +{
> + CPULoongArchState *env = &cpu->env;
> + uint64_t now, next;
> +
> + env->CSR_TCFG = value;
> + if (value & CONSTANT_TIMER_ENABLE) {
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + next = now + (value & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
> + timer_mod(&cpu->timer, next);
> + }
> +}
> +
> +void loongarch_constant_timer_cb(void *opaque)
> +{
> + LoongArchCPU *cpu = opaque;
> + CPULoongArchState *env = &cpu->env;
> + uint64_t now, next;
> +
> + if (FIELD_EX64(env->CSR_TCFG, CSR_TCFG, PERIODIC)) {
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + next = now + (env->CSR_TCFG & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
> + timer_mod(&cpu->timer, next);
> + } else {
> + env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
> + }
> +
> + env->CSR_ESTAT |= 1 << IRQ_TIMER;
> + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> +}
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 690eeea2e6..823951dddd 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -235,12 +235,21 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
> LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
> Error *local_err = NULL;
>
> +#ifndef CONFIG_USER_ONLY
> + LoongArchCPU *cpu = LOONGARCH_CPU(dev);
> +#endif
> +
> cpu_exec_realizefn(cs, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> return;
> }
>
> +#ifndef CONFIG_USER_ONLY
> + timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
> + &loongarch_constant_timer_cb, cpu);
> +#endif
> +
> cpu_reset(cs);
> qemu_init_vcpu(cs);
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index cf7fc46f72..ef84584678 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -12,6 +12,7 @@
> #include "fpu/softfloat-types.h"
> #include "hw/registerfields.h"
> #include "cpu-csr.h"
> +#include "qemu/timer.h"
>
> #define TCG_GUEST_DEFAULT_MO (0)
>
> @@ -148,6 +149,9 @@ FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
> extern const char * const regnames[32];
> extern const char * const fregnames[32];
>
> +#define N_IRQS 14
> +#define IRQ_TIMER 11
> +
> typedef struct CPULoongArchState CPULoongArchState;
> struct CPULoongArchState {
> uint64_t gpr[32];
> @@ -242,6 +246,7 @@ struct LoongArchCPU {
>
> CPUNegativeOffsetState neg;
> CPULoongArchState env;
> + QEMUTimer timer; /* Internal timer */
What do you mean by "internal", is there any "external" counterpart? If
there isn't one, I think you may be referring to the "architectural"
timer instead (as is defined by LoongArch, instead of any concrete
implementation), and this would have to be changed accordingly.
> };
>
> #define TYPE_LOONGARCH_CPU "loongarch-cpu"
> @@ -306,4 +311,9 @@ enum {
> #define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
> #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
>
> +void loongarch_constant_timer_cb(void *opaque);
> +uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
> +uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
> +void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
> + uint64_t value);
> #endif /* LOONGARCH_CPU_H */
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index 103f36ee15..6168e910a0 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -17,6 +17,7 @@ loongarch_tcg_ss.add(zlib)
> loongarch_softmmu_ss = ss.source_set()
> loongarch_softmmu_ss.add(files(
> 'machine.c',
> + 'constant_timer.c',
Why not alphabetical order? Is there any requirement for ordering here?
I don't think there is one.
> ))
>
> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 05/30] target/loongarch: Add constant timer support
2022-01-08 9:13 ` [RFC PATCH v4 05/30] target/loongarch: Add constant timer support Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
@ 2022-01-15 13:02 ` Mark Cave-Ayland
1 sibling, 0 replies; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 13:02 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: richard.henderson, philmd, Song Gao
On 08/01/2022 09:13, Xiaojuan Yang wrote:
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> target/loongarch/constant_timer.c | 63 +++++++++++++++++++++++++++++++
> target/loongarch/cpu.c | 9 +++++
> target/loongarch/cpu.h | 10 +++++
> target/loongarch/meson.build | 1 +
> 4 files changed, 83 insertions(+)
> create mode 100644 target/loongarch/constant_timer.c
>
> diff --git a/target/loongarch/constant_timer.c b/target/loongarch/constant_timer.c
> new file mode 100644
> index 0000000000..e7d0f5ffe7
> --- /dev/null
> +++ b/target/loongarch/constant_timer.c
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch constant timer support
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "qemu/timer.h"
> +#include "cpu.h"
> +
> +#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
> +#define CONSTANT_TIMER_TICK_MASK 0xfffffffffffcUL
> +#define CONSTANT_TIMER_ENABLE 0x1UL
> +
> +/* LoongArch timer */
> +uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu)
> +{
> + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD;
> +}
> +
> +uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu)
> +{
> + uint64_t now, expire;
> +
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + expire = timer_expire_time_ns(&cpu->timer);
> +
> + return (expire - now) / TIMER_PERIOD;
> +}
> +
> +void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
> + uint64_t value)
> +{
> + CPULoongArchState *env = &cpu->env;
> + uint64_t now, next;
> +
> + env->CSR_TCFG = value;
> + if (value & CONSTANT_TIMER_ENABLE) {
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + next = now + (value & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
> + timer_mod(&cpu->timer, next);
> + }
> +}
> +
> +void loongarch_constant_timer_cb(void *opaque)
> +{
> + LoongArchCPU *cpu = opaque;
> + CPULoongArchState *env = &cpu->env;
> + uint64_t now, next;
> +
> + if (FIELD_EX64(env->CSR_TCFG, CSR_TCFG, PERIODIC)) {
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + next = now + (env->CSR_TCFG & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
> + timer_mod(&cpu->timer, next);
> + } else {
> + env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
> + }
> +
> + env->CSR_ESTAT |= 1 << IRQ_TIMER;
> + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> +}
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 690eeea2e6..823951dddd 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -235,12 +235,21 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
> LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
> Error *local_err = NULL;
>
> +#ifndef CONFIG_USER_ONLY
> + LoongArchCPU *cpu = LOONGARCH_CPU(dev);
> +#endif
> +
> cpu_exec_realizefn(cs, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> return;
> }
>
> +#ifndef CONFIG_USER_ONLY
> + timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
> + &loongarch_constant_timer_cb, cpu);
> +#endif
> +
As I mentioned previously, I'm not convinced that adding the CONFIG_USER_ONLY guards
is the right thing to do here.
For SPARC64 there is a separate sparc64_cpu_devinit() function that is only called in
sysemu mode (via the machine init() function) which sets up the timers. Have a look
at hw/sparc64/sparc64.c and hw/sparc64/sun4u.c for an existing reference as to how
this is done.
This suggests that a similar function would need to exist in hw/loongarch/loongson3.c.
> cpu_reset(cs);
> qemu_init_vcpu(cs);
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index cf7fc46f72..ef84584678 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -12,6 +12,7 @@
> #include "fpu/softfloat-types.h"
> #include "hw/registerfields.h"
> #include "cpu-csr.h"
> +#include "qemu/timer.h"
>
> #define TCG_GUEST_DEFAULT_MO (0)
>
> @@ -148,6 +149,9 @@ FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
> extern const char * const regnames[32];
> extern const char * const fregnames[32];
>
> +#define N_IRQS 14
> +#define IRQ_TIMER 11
> +
> typedef struct CPULoongArchState CPULoongArchState;
> struct CPULoongArchState {
> uint64_t gpr[32];
> @@ -242,6 +246,7 @@ struct LoongArchCPU {
>
> CPUNegativeOffsetState neg;
> CPULoongArchState env;
> + QEMUTimer timer; /* Internal timer */
> };
>
> #define TYPE_LOONGARCH_CPU "loongarch-cpu"
> @@ -306,4 +311,9 @@ enum {
> #define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
> #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
>
> +void loongarch_constant_timer_cb(void *opaque);
> +uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
> +uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
> +void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
> + uint64_t value);
> #endif /* LOONGARCH_CPU_H */
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index 103f36ee15..6168e910a0 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -17,6 +17,7 @@ loongarch_tcg_ss.add(zlib)
> loongarch_softmmu_ss = ss.source_set()
> loongarch_softmmu_ss.add(files(
> 'machine.c',
> + 'constant_timer.c',
> ))
>
> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
ATB,
Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 06/30] target/loongarch: Add MMU support for LoongArch CPU.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (4 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 05/30] target/loongarch: Add constant timer support Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-08 9:13 ` [RFC PATCH v4 07/30] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
` (25 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch introduces basic TLB interfaces.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu-param.h | 2 +-
target/loongarch/cpu.c | 32 ++++
target/loongarch/cpu.h | 45 ++++-
target/loongarch/internals.h | 10 ++
target/loongarch/machine.c | 17 ++
target/loongarch/meson.build | 1 +
target/loongarch/op_helper.c | 8 +
target/loongarch/tlb_helper.c | 326 ++++++++++++++++++++++++++++++++++
8 files changed, 439 insertions(+), 2 deletions(-)
create mode 100644 target/loongarch/tlb_helper.c
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 9a769b67e0..414d8fff46 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -13,6 +13,6 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 48
#define TARGET_PAGE_BITS 14
-#define NB_MMU_MODES 4
+#define NB_MMU_MODES 5
#endif
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 823951dddd..780eb96a3c 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -237,6 +237,7 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
LoongArchCPU *cpu = LOONGARCH_CPU(dev);
+ CPULoongArchState *env = &cpu->env;
#endif
cpu_exec_realizefn(cs, &local_err);
@@ -248,6 +249,7 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
&loongarch_constant_timer_cb, cpu);
+ loongarch_mmu_init(env);
#endif
cpu_reset(cs);
@@ -295,6 +297,23 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
+#ifndef CONFIG_USER_ONLY
+ qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
+ qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
+ qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
+ qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
+ qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
+ qemu_fprintf(f, "BadVAddr=%016" PRIx64 "\n", env->CSR_BADV);
+ qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
+ qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
+ qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
+ qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
+ qemu_fprintf(f, "BadInstr=%016" PRIx64 "\n", env->CSR_BADI);
+ qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
+ " PRCFG3=%016" PRIx64 "\n",
+ env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3);
+#endif
+
/* fpr */
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 32; i++) {
@@ -312,9 +331,21 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
static struct TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
+
+#if !defined(CONFIG_USER_ONLY)
+ .tlb_fill = loongarch_cpu_tlb_fill,
+#endif /* !CONFIG_USER_ONLY */
};
#endif /* CONFIG_TCG */
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps loongarch_sysemu_ops = {
+ .get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
+};
+#endif
+
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
{
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
@@ -331,6 +362,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = loongarch_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
dc->vmsd = &vmstate_loongarch_cpu;
+ cc->sysemu_ops = &loongarch_sysemu_ops;
#endif
cc->disas_set_info = loongarch_cpu_disas_set_info;
#ifdef CONFIG_TCG
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ef84584678..232d51e788 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -152,6 +152,29 @@ extern const char * const fregnames[32];
#define N_IRQS 14
#define IRQ_TIMER 11
+#define LOONGARCH_TLB_MAX (2048 + 64) /* 2048 STLB + 64 MTLB */
+#define LOONGARCH_STLB 2048 /* 2048 STLB */
+#define LOONGARCH_MTLB 64 /* 64 MTLB */
+
+/*
+ * define the ASID PS E VPPN field of TLB
+ *
+ * PS of stlb come from stlbps.ps
+ * PS of mtlb come from tlbidx.ps
+ */
+FIELD(TLB_MISC, E, 0, 1)
+FIELD(TLB_MISC, ASID, 1, 10)
+FIELD(TLB_MISC, VPPN, 13, 35)
+FIELD(TLB_MISC, PS, 48, 6)
+
+struct LoongArchTLB {
+ uint64_t tlb_misc;
+ /* Fields corresponding to CSR_TLBELO0/1 */
+ uint64_t tlb_entry0;
+ uint64_t tlb_entry1;
+};
+typedef struct LoongArchTLB LoongArchTLB;
+
typedef struct CPULoongArchState CPULoongArchState;
struct CPULoongArchState {
uint64_t gpr[32];
@@ -231,6 +254,10 @@ struct CPULoongArchState {
uint64_t CSR_DBG;
uint64_t CSR_DERA;
uint64_t CSR_DSAVE;
+
+#ifndef CONFIG_USER_ONLY
+ LoongArchTLB tlb[LOONGARCH_TLB_MAX];
+#endif
};
/**
@@ -270,11 +297,27 @@ struct LoongArchCPUClass {
DeviceReset parent_reset;
};
-#define MMU_USER_IDX 3
+/*
+ * LoongArch cpu has 4 priv level.
+ * 0 for kernel mode, 3 for user mode.
+ * Define a extra index for Direct mode.
+ */
+#define MMU_KERNEL_IDX 0 /* kernel mode idx */
+#define MMU_USER_IDX 3 /* user mode idx */
+#define MMU_DA_IDX 4 /* DA mode idx */
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
+#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
+#else
+ uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
+
+ if (!pg) {
+ return MMU_DA_IDX;
+ }
+ return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+#endif
}
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index c8e6f7012c..a5b81bdca3 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -13,6 +13,9 @@
#define FCMP_UN 0b0100 /* unordered */
#define FCMP_GT 0b1000 /* fp0 > fp1 */
+#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
+#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
+
void loongarch_translate_init(void);
void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
@@ -27,6 +30,13 @@ void restore_fp_status(CPULoongArchState *env);
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_loongarch_cpu;
+
+bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+
+void loongarch_mmu_init(CPULoongArchState *env);
+hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
#endif
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index b9effe6db2..bc10492708 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -8,6 +8,20 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/cpu.h"
+#include "internals.h"
+
+/* TLB state */
+const VMStateDescription vmstate_tlb = {
+ .name = "cpu/tlb",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(tlb_misc, LoongArchTLB),
+ VMSTATE_UINT64(tlb_entry0, LoongArchTLB),
+ VMSTATE_UINT64(tlb_entry1, LoongArchTLB),
+ VMSTATE_END_OF_LIST()
+ }
+};
/* LoongArch CPU state */
@@ -78,6 +92,9 @@ const VMStateDescription vmstate_loongarch_cpu = {
VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
+ /* TLB */
+ VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX,
+ 0, vmstate_tlb, LoongArchTLB),
VMSTATE_END_OF_LIST()
},
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 6168e910a0..6bf2d88104 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -18,6 +18,7 @@ loongarch_softmmu_ss = ss.source_set()
loongarch_softmmu_ss.add(files(
'machine.c',
'constant_timer.c',
+ 'tlb_helper.c',
))
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index 1083e39b7f..48c25e5a9b 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -47,16 +47,24 @@ target_ulong helper_bitswap(target_ulong v)
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj > rk) {
+#ifdef CONFIG_USER_ONLY
cpu_loop_exit_sigsegv(env_cpu(env), GETPC(),
MMU_DATA_LOAD, true, GETPC());
+#else
+ do_raise_exception(env, EXCCODE_ADEM, GETPC());
+#endif
}
}
void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj <= rk) {
+#ifdef CONFIG_USER_ONLY
cpu_loop_exit_sigsegv(env_cpu(env), GETPC(),
MMU_DATA_LOAD, true, GETPC());
+#else
+ do_raise_exception(env, EXCCODE_ADEM, GETPC());
+#endif
}
}
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
new file mode 100644
index 0000000000..ff72ac4eaf
--- /dev/null
+++ b/target/loongarch/tlb_helper.c
@@ -0,0 +1,326 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch TLB helpers for qemu
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ */
+
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "internals.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
+#include "exec/log.h"
+#include "cpu-csr.h"
+
+enum {
+ TLBRET_MATCH = 0,
+ TLBRET_BADADDR = 1,
+ TLBRET_NOMATCH = 2,
+ TLBRET_INVALID = 3,
+ TLBRET_DIRTY = 4,
+ TLBRET_RI = 5,
+ TLBRET_XI = 6,
+ TLBRET_PE = 7,
+};
+
+/* TLB address map */
+static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ int access_type, int index, int mmu_idx)
+{
+ LoongArchTLB *tlb = &env->tlb[index];
+ uint64_t plv = mmu_idx;
+ uint64_t tlb_entry, tlb_ppn;
+ uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
+
+ if (index >= LOONGARCH_STLB) {
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ } else {
+ tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ }
+ n = (address >> tlb_ps) & 0x1;/* Odd or even */
+
+ tlb_entry = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
+ tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
+ tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
+ tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
+ tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
+ tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
+ tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
+
+ /* Check access rights */
+ if (!tlb_v) {
+ return TLBRET_INVALID;
+ }
+
+ if (access_type == MMU_INST_FETCH && tlb_nx) {
+ return TLBRET_XI;
+ }
+
+ if (access_type == MMU_DATA_LOAD && tlb_nr) {
+ return TLBRET_RI;
+ }
+
+ if (((tlb_rplv == 0) && (plv > tlb_plv)) ||
+ ((tlb_rplv == 1) && (plv != tlb_plv))) {
+ return TLBRET_PE;
+ }
+
+ if ((access_type == MMU_DATA_STORE) && !tlb_d) {
+ return TLBRET_DIRTY;
+ }
+
+ /*
+ * tlb_entry contains ppn[47:12] while 16KB ppn is [47:15]
+ * need adjust.
+ */
+ *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
+ (address & MAKE_64BIT_MASK(0, tlb_ps));
+ *prot = PAGE_READ;
+ if (tlb_d) {
+ *prot |= PAGE_WRITE;
+ }
+ if (!tlb_nx) {
+ *prot |= PAGE_EXEC;
+ }
+ return TLBRET_MATCH;
+}
+
+/*
+ * One tlb entry holds a adjacent odd/even pair, the vpn is the
+ * content of the virtual page number divided by 2.So the
+ * compare vpn is bit[47:15] for 16KB page. while the vppn
+ * field in tlb entry contains bit[47:13], so need adjust.
+ * virt_vpn = vaddr[47:13]
+ */
+static bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
+ int *index)
+{
+ LoongArchTLB *tlb;
+ uint16_t csr_asid, tlb_asid, stlb_idx;
+ uint8_t tlb_e, tlb_ps, tlb_g, stlb_ps;
+ int i, compare_shift;
+ uint64_t vpn, tlb_vppn; /* Address to map */
+
+ csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
+ stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ vpn = (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1);
+ stlb_idx = vpn & 0xff; /* VA[25:15] <==> TLBIDX.index for 16KB Page */
+ compare_shift = stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
+
+ /* Search STLB */
+ for (i = 0; i < 8; ++i) {
+ tlb = &env->tlb[i * 256 + stlb_idx];
+ tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+ if (tlb_e) {
+ tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
+ tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+
+ if ((tlb_g == 1 || tlb_asid == csr_asid) &&
+ (vpn == (tlb_vppn >> compare_shift))) {
+ *index = i * 256 + stlb_idx;
+ return true;
+ }
+ }
+ }
+
+ /* Search MTLB */
+ for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; ++i) {
+ tlb = &env->tlb[i];
+ tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+ if (tlb_e) {
+ tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
+
+ if ((tlb_g == 1 || tlb_asid == csr_asid) &&
+ (vpn == (tlb_vppn >> compare_shift))) {
+ *index = i;
+ return true;
+ }
+ }
+ }
+ return false;
+}
+
+static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx)
+{
+ int index, match;
+
+ match = loongarch_tlb_search(env, address, &index);
+ if (match) {
+ return loongarch_map_tlb_entry(env, physical, prot,
+ address, access_type, index, mmu_idx);
+ }
+
+ return TLBRET_NOMATCH;
+}
+
+static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx)
+{
+ int user_mode = mmu_idx == MMU_USER_IDX;
+ int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
+ uint32_t plv, base_c, base_v;
+ int64_t addr_high;
+ uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
+ uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
+
+ /* Check PG and DA*/
+ if (da & !pg) {
+ /* DA mode */
+ *physical = address & TARGET_PHYS_MASK;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return TLBRET_MATCH;
+ }
+
+ plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
+ base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS;
+ /* Check direct map window */
+ for (int i = 0; i < 4; i++) {
+ base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS;
+ if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
+ *physical = dmw_va2pa(address);
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return TLBRET_MATCH;
+ }
+ }
+
+ /* Check valid extension */
+ addr_high = sextract64(address, TARGET_VIRT_ADDR_SPACE_BITS, 16);
+ if (!(addr_high == 0 || addr_high == -1)) {
+ return TLBRET_BADADDR;
+ }
+ /* Mapped address */
+ return loongarch_map_address(env, physical, prot, address,
+ access_type, mmu_idx);
+}
+
+hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ hwaddr phys_addr;
+ int prot;
+
+ if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
+ cpu_mmu_index(env, false)) != 0) {
+ return -1;
+ }
+ return phys_addr;
+}
+
+static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
+ MMUAccessType access_type, int tlb_error)
+{
+ CPUState *cs = env_cpu(env);
+
+ switch (tlb_error) {
+ default:
+ case TLBRET_BADADDR:
+ cs->exception_index = EXCCODE_ADEM;
+ break;
+ case TLBRET_NOMATCH:
+ /* No TLB match for a mapped address */
+ if (access_type == MMU_DATA_LOAD) {
+ cs->exception_index = EXCCODE_PIL;
+ } else if (access_type == MMU_DATA_STORE) {
+ cs->exception_index = EXCCODE_PIS;
+ } else if (access_type == MMU_INST_FETCH) {
+ cs->exception_index = EXCCODE_PIF;
+ }
+ env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 1);
+ break;
+ case TLBRET_INVALID:
+ /* TLB match with no valid bit */
+ if (access_type == MMU_DATA_LOAD) {
+ cs->exception_index = EXCCODE_PIL;
+ } else if (access_type == MMU_DATA_STORE) {
+ cs->exception_index = EXCCODE_PIS;
+ } else if (access_type == MMU_INST_FETCH) {
+ cs->exception_index = EXCCODE_PIF;
+ }
+ break;
+ case TLBRET_DIRTY:
+ /* TLB match but 'D' bit is cleared */
+ cs->exception_index = EXCCODE_PME;
+ break;
+ case TLBRET_XI:
+ /* Execute-Inhibit Exception */
+ cs->exception_index = EXCCODE_PNX;
+ break;
+ case TLBRET_RI:
+ /* Read-Inhibit Exception */
+ cs->exception_index = EXCCODE_PNR;
+ break;
+ case TLBRET_PE:
+ /* Privileged Exception */
+ cs->exception_index = EXCCODE_PPI;
+ break;
+ }
+
+ if (tlb_error == TLBRET_NOMATCH) {
+ env->CSR_TLBRBADV = address;
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
+ extract64(address, 13, 35));
+ } else {
+ if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
+ env->CSR_BADV = address;
+ }
+ env->CSR_TLBEHI = address & (TARGET_PAGE_MASK << 1);
+ }
+}
+
+void loongarch_mmu_init(CPULoongArchState *env)
+{
+ /* For 16KB, ps = 14, compare the bit [47:15] */
+ for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
+ env->tlb[i].tlb_misc = FIELD_DP64(env->tlb[i].tlb_misc, TLB_MISC, E, 0);
+ }
+}
+
+bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ hwaddr physical;
+ int prot;
+ int ret = TLBRET_BADADDR;
+
+ /* Data access */
+ /* XXX: put correct access by using cpu_restore_state() correctly */
+ ret = get_physical_address(env, &physical, &prot, address,
+ access_type, mmu_idx);
+
+ if (ret == TLBRET_MATCH) {
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot,
+ mmu_idx, TARGET_PAGE_SIZE);
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ " prot %d\n", __func__, address, physical, prot);
+ return true;
+ } else {
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
+ ret);
+ }
+ if (probe) {
+ return false;
+ } else {
+ raise_mmu_exception(env, address, access_type, ret);
+ do_raise_exception(env, cs->exception_index, retaddr);
+ }
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 06/30] target/loongarch: Add MMU support for LoongArch CPU.
2022-01-08 9:13 ` [RFC PATCH v4 06/30] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This patch introduces basic TLB interfaces.
Same comment regarding commit messages adding little information.
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/cpu-param.h | 2 +-
> target/loongarch/cpu.c | 32 ++++
> target/loongarch/cpu.h | 45 ++++-
> target/loongarch/internals.h | 10 ++
> target/loongarch/machine.c | 17 ++
> target/loongarch/meson.build | 1 +
> target/loongarch/op_helper.c | 8 +
> target/loongarch/tlb_helper.c | 326 ++++++++++++++++++++++++++++++++++
> 8 files changed, 439 insertions(+), 2 deletions(-)
> create mode 100644 target/loongarch/tlb_helper.c
>
> diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
> index 9a769b67e0..414d8fff46 100644
> --- a/target/loongarch/cpu-param.h
> +++ b/target/loongarch/cpu-param.h
> @@ -13,6 +13,6 @@
> #define TARGET_VIRT_ADDR_SPACE_BITS 48
>
> #define TARGET_PAGE_BITS 14
> -#define NB_MMU_MODES 4
> +#define NB_MMU_MODES 5
>
> #endif
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 823951dddd..780eb96a3c 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -237,6 +237,7 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
>
> #ifndef CONFIG_USER_ONLY
> LoongArchCPU *cpu = LOONGARCH_CPU(dev);
> + CPULoongArchState *env = &cpu->env;
> #endif
>
> cpu_exec_realizefn(cs, &local_err);
> @@ -248,6 +249,7 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
> #ifndef CONFIG_USER_ONLY
> timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
> &loongarch_constant_timer_cb, cpu);
> + loongarch_mmu_init(env);
> #endif
>
> cpu_reset(cs);
> @@ -295,6 +297,23 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> }
> }
>
> +#ifndef CONFIG_USER_ONLY
> + qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
Why EUEN first and generally not in the structure definition/manual order?
> + qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
> + qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
> + qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
> + qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
> + qemu_fprintf(f, "BadVAddr=%016" PRIx64 "\n", env->CSR_BADV);
The register is named just "BADV" in the manuals, "BadVAddr" seems like
MIPS leftover...
> + qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
> + qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
> + qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
> + qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
> + qemu_fprintf(f, "BadInstr=%016" PRIx64 "\n", env->CSR_BADI);
Also this; "BadInstr" also comes from MIPS IIRC.
> + qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
> + " PRCFG3=%016" PRIx64 "\n",
> + env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3);
> +#endif
> +
> /* fpr */
> if (flags & CPU_DUMP_FPU) {
> for (i = 0; i < 32; i++) {
> @@ -312,9 +331,21 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> static struct TCGCPUOps loongarch_tcg_ops = {
> .initialize = loongarch_translate_init,
> .synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
> +
> +#if !defined(CONFIG_USER_ONLY)
> + .tlb_fill = loongarch_cpu_tlb_fill,
> +#endif /* !CONFIG_USER_ONLY */
> };
> #endif /* CONFIG_TCG */
>
> +#ifndef CONFIG_USER_ONLY
> +#include "hw/core/sysemu-cpu-ops.h"
> +
> +static const struct SysemuCPUOps loongarch_sysemu_ops = {
> + .get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
> +};
> +#endif
> +
> static void loongarch_cpu_class_init(ObjectClass *c, void *data)
> {
> LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
> @@ -331,6 +362,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
> cc->set_pc = loongarch_cpu_set_pc;
> #ifndef CONFIG_USER_ONLY
> dc->vmsd = &vmstate_loongarch_cpu;
> + cc->sysemu_ops = &loongarch_sysemu_ops;
> #endif
> cc->disas_set_info = loongarch_cpu_disas_set_info;
> #ifdef CONFIG_TCG
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index ef84584678..232d51e788 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -152,6 +152,29 @@ extern const char * const fregnames[32];
> #define N_IRQS 14
> #define IRQ_TIMER 11
>
> +#define LOONGARCH_TLB_MAX (2048 + 64) /* 2048 STLB + 64 MTLB */
> +#define LOONGARCH_STLB 2048 /* 2048 STLB */
> +#define LOONGARCH_MTLB 64 /* 64 MTLB */
Why not define LOONGARCH_TLB_MAX after the two individual definitions,
and just say "#define LOONGARCH_TLB_MAX (LOONGARCH_STLB +
LOONGARCH_MTLB)" to really eliminate the duplication?
> +
> +/*
> + * define the ASID PS E VPPN field of TLB
> + *
> + * PS of stlb come from stlbps.ps
> + * PS of mtlb come from tlbidx.ps
> + */
I can't understand this comment, which seems like just describing what
the following code literally meant. Might remove as well...
> +FIELD(TLB_MISC, E, 0, 1)
> +FIELD(TLB_MISC, ASID, 1, 10)
> +FIELD(TLB_MISC, VPPN, 13, 35)
> +FIELD(TLB_MISC, PS, 48, 6)
> +
> +struct LoongArchTLB {
> + uint64_t tlb_misc;
> + /* Fields corresponding to CSR_TLBELO0/1 */
> + uint64_t tlb_entry0;
> + uint64_t tlb_entry1;
> +};
> +typedef struct LoongArchTLB LoongArchTLB;
> +
> typedef struct CPULoongArchState CPULoongArchState;
> struct CPULoongArchState {
> uint64_t gpr[32];
> @@ -231,6 +254,10 @@ struct CPULoongArchState {
> uint64_t CSR_DBG;
> uint64_t CSR_DERA;
> uint64_t CSR_DSAVE;
> +
> +#ifndef CONFIG_USER_ONLY
> + LoongArchTLB tlb[LOONGARCH_TLB_MAX];
> +#endif
> };
>
> /**
> @@ -270,11 +297,27 @@ struct LoongArchCPUClass {
> DeviceReset parent_reset;
> };
>
> -#define MMU_USER_IDX 3
> +/*
> + * LoongArch cpu has 4 priv level.
"LoongArch CPUs have 4 privilege levels"
> + * 0 for kernel mode, 3 for user mode.
> + * Define a extra index for Direct mode.
"an extra mode for DA (direct addressing) mode"
> + */
> +#define MMU_KERNEL_IDX 0 /* kernel mode idx */
> +#define MMU_USER_IDX 3 /* user mode idx */
> +#define MMU_DA_IDX 4 /* DA mode idx */
Remove the comments; they add no information.
>
> static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
> {
> +#ifdef CONFIG_USER_ONLY
> return MMU_USER_IDX;
> +#else
> + uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
> +
> + if (!pg) {
> + return MMU_DA_IDX;
> + }
> + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
> +#endif
> }
>
> static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
> index c8e6f7012c..a5b81bdca3 100644
> --- a/target/loongarch/internals.h
> +++ b/target/loongarch/internals.h
> @@ -13,6 +13,9 @@
> #define FCMP_UN 0b0100 /* unordered */
> #define FCMP_GT 0b1000 /* fp0 > fp1 */
>
> +#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
> +#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
> +
> void loongarch_translate_init(void);
>
> void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
> @@ -27,6 +30,13 @@ void restore_fp_status(CPULoongArchState *env);
>
> #ifndef CONFIG_USER_ONLY
> extern const VMStateDescription vmstate_loongarch_cpu;
> +
> +bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> + MMUAccessType access_type, int mmu_idx,
> + bool probe, uintptr_t retaddr);
> +
> +void loongarch_mmu_init(CPULoongArchState *env);
> +hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> #endif
>
> #endif
> diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
> index b9effe6db2..bc10492708 100644
> --- a/target/loongarch/machine.c
> +++ b/target/loongarch/machine.c
> @@ -8,6 +8,20 @@
> #include "qemu/osdep.h"
> #include "cpu.h"
> #include "migration/cpu.h"
> +#include "internals.h"
> +
> +/* TLB state */
> +const VMStateDescription vmstate_tlb = {
> + .name = "cpu/tlb",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64(tlb_misc, LoongArchTLB),
> + VMSTATE_UINT64(tlb_entry0, LoongArchTLB),
> + VMSTATE_UINT64(tlb_entry1, LoongArchTLB),
> + VMSTATE_END_OF_LIST()
> + }
> +};
>
> /* LoongArch CPU state */
>
> @@ -78,6 +92,9 @@ const VMStateDescription vmstate_loongarch_cpu = {
> VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
> VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
> VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
> + /* TLB */
> + VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX,
> + 0, vmstate_tlb, LoongArchTLB),
>
> VMSTATE_END_OF_LIST()
> },
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index 6168e910a0..6bf2d88104 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -18,6 +18,7 @@ loongarch_softmmu_ss = ss.source_set()
> loongarch_softmmu_ss.add(files(
> 'machine.c',
> 'constant_timer.c',
> + 'tlb_helper.c',
> ))
>
> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
> diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
> index 1083e39b7f..48c25e5a9b 100644
> --- a/target/loongarch/op_helper.c
> +++ b/target/loongarch/op_helper.c
> @@ -47,16 +47,24 @@ target_ulong helper_bitswap(target_ulong v)
> void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
> {
> if (rj > rk) {
> +#ifdef CONFIG_USER_ONLY
> cpu_loop_exit_sigsegv(env_cpu(env), GETPC(),
> MMU_DATA_LOAD, true, GETPC());
> +#else
> + do_raise_exception(env, EXCCODE_ADEM, GETPC());
> +#endif
> }
> }
>
> void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
> {
> if (rj <= rk) {
> +#ifdef CONFIG_USER_ONLY
> cpu_loop_exit_sigsegv(env_cpu(env), GETPC(),
> MMU_DATA_LOAD, true, GETPC());
> +#else
> + do_raise_exception(env, EXCCODE_ADEM, GETPC());
> +#endif
> }
> }
>
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> new file mode 100644
> index 0000000000..ff72ac4eaf
> --- /dev/null
> +++ b/target/loongarch/tlb_helper.c
> @@ -0,0 +1,326 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch TLB helpers for qemu
Remove the "for qemu" part...
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "cpu.h"
> +#include "internals.h"
> +#include "exec/exec-all.h"
> +#include "exec/cpu_ldst.h"
> +#include "exec/log.h"
> +#include "cpu-csr.h"
> +
> +enum {
> + TLBRET_MATCH = 0,
> + TLBRET_BADADDR = 1,
> + TLBRET_NOMATCH = 2,
> + TLBRET_INVALID = 3,
> + TLBRET_DIRTY = 4,
> + TLBRET_RI = 5,
> + TLBRET_XI = 6,
> + TLBRET_PE = 7,
> +};
> +
> +/* TLB address map */
Remove this comment, it says even less than the function name below...
> +static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
> + int *prot, target_ulong address,
> + int access_type, int index, int mmu_idx)
> +{
> + LoongArchTLB *tlb = &env->tlb[index];
> + uint64_t plv = mmu_idx;
> + uint64_t tlb_entry, tlb_ppn;
> + uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
> +
> + if (index >= LOONGARCH_STLB) {
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> + } else {
> + tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> + }
> + n = (address >> tlb_ps) & 0x1;/* Odd or even */
> +
> + tlb_entry = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
> + tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
> + tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
> + tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
> + tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
> + tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
> + tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
> + tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
> +
> + /* Check access rights */
> + if (!tlb_v) {
> + return TLBRET_INVALID;
> + }
> +
> + if (access_type == MMU_INST_FETCH && tlb_nx) {
> + return TLBRET_XI;
> + }
> +
> + if (access_type == MMU_DATA_LOAD && tlb_nr) {
> + return TLBRET_RI;
> + }
> +
> + if (((tlb_rplv == 0) && (plv > tlb_plv)) ||
> + ((tlb_rplv == 1) && (plv != tlb_plv))) {
> + return TLBRET_PE;
> + }
> +
> + if ((access_type == MMU_DATA_STORE) && !tlb_d) {
> + return TLBRET_DIRTY;
> + }
> +
> + /*
> + * tlb_entry contains ppn[47:12] while 16KB ppn is [47:15]
> + * need adjust.
"16KiB" to be exact; and please clarify what to "adjust"?
> + */
> + *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
> + (address & MAKE_64BIT_MASK(0, tlb_ps));
> + *prot = PAGE_READ;
> + if (tlb_d) {
> + *prot |= PAGE_WRITE;
> + }
> + if (!tlb_nx) {
> + *prot |= PAGE_EXEC;
> + }
> + return TLBRET_MATCH;
> +}
> +
> +/*
> + * One tlb entry holds a adjacent odd/even pair, the vpn is the
"an adjacent"
> + * content of the virtual page number divided by 2.So the
Space after the period.
> + * compare vpn is bit[47:15] for 16KB page. while the vppn
> + * field in tlb entry contains bit[47:13], so need adjust.
Chinglish for the whole sentence; I'm not too familiar with the TLB
details so you may have to write that sentence yourself.
> + * virt_vpn = vaddr[47:13]
> + */
> +static bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
> + int *index)
> +{
> + LoongArchTLB *tlb;
> + uint16_t csr_asid, tlb_asid, stlb_idx;
> + uint8_t tlb_e, tlb_ps, tlb_g, stlb_ps;
> + int i, compare_shift;
> + uint64_t vpn, tlb_vppn; /* Address to map */
> +
> + csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
> + stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> + vpn = (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1);
> + stlb_idx = vpn & 0xff; /* VA[25:15] <==> TLBIDX.index for 16KB Page */
"16KiB pages"
> + compare_shift = stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> +
> + /* Search STLB */
> + for (i = 0; i < 8; ++i) {
> + tlb = &env->tlb[i * 256 + stlb_idx];
> + tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
> + if (tlb_e) {
> + tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> + tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> + tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> +
> + if ((tlb_g == 1 || tlb_asid == csr_asid) &&
> + (vpn == (tlb_vppn >> compare_shift))) {
> + *index = i * 256 + stlb_idx;
> + return true;
> + }
> + }
> + }
> +
> + /* Search MTLB */
> + for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; ++i) {
> + tlb = &env->tlb[i];
> + tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
> + if (tlb_e) {
> + tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> + tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> + tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> + compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> +
> + if ((tlb_g == 1 || tlb_asid == csr_asid) &&
> + (vpn == (tlb_vppn >> compare_shift))) {
> + *index = i;
> + return true;
> + }
> + }
> + }
> + return false;
> +}
> +
> +static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
> + int *prot, target_ulong address,
> + MMUAccessType access_type, int mmu_idx)
> +{
> + int index, match;
> +
> + match = loongarch_tlb_search(env, address, &index);
> + if (match) {
> + return loongarch_map_tlb_entry(env, physical, prot,
> + address, access_type, index, mmu_idx);
> + }
> +
> + return TLBRET_NOMATCH;
> +}
> +
> +static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
> + int *prot, target_ulong address,
> + MMUAccessType access_type, int mmu_idx)
> +{
> + int user_mode = mmu_idx == MMU_USER_IDX;
> + int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
> + uint32_t plv, base_c, base_v;
> + int64_t addr_high;
> + uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
> + uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
> +
> + /* Check PG and DA*/
> + if (da & !pg) {
> + /* DA mode */
> + *physical = address & TARGET_PHYS_MASK;
> + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> + return TLBRET_MATCH;
> + }
> +
> + plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
> + base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS;
> + /* Check direct map window */
> + for (int i = 0; i < 4; i++) {
> + base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS;
> + if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
> + *physical = dmw_va2pa(address);
> + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> + return TLBRET_MATCH;
> + }
> + }
> +
> + /* Check valid extension */
What does "extension" mean here? Do you mean to "check for non-canonical
addresses", considering what follows looks like checking the high bits
to be sign-extension of the lower part?
> + addr_high = sextract64(address, TARGET_VIRT_ADDR_SPACE_BITS, 16);
> + if (!(addr_high == 0 || addr_high == -1)) {
> + return TLBRET_BADADDR;
> + }
Newline after this line.
> + /* Mapped address */
> + return loongarch_map_address(env, physical, prot, address,
> + access_type, mmu_idx);
> +}
> +
> +hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> + hwaddr phys_addr;
> + int prot;
> +
> + if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
> + cpu_mmu_index(env, false)) != 0) {
> + return -1;
> + }
> + return phys_addr;
> +}
> +
> +static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
> + MMUAccessType access_type, int tlb_error)
> +{
> + CPUState *cs = env_cpu(env);
> +
> + switch (tlb_error) {
> + default:
> + case TLBRET_BADADDR:
> + cs->exception_index = EXCCODE_ADEM;
> + break;
> + case TLBRET_NOMATCH:
> + /* No TLB match for a mapped address */
> + if (access_type == MMU_DATA_LOAD) {
> + cs->exception_index = EXCCODE_PIL;
> + } else if (access_type == MMU_DATA_STORE) {
> + cs->exception_index = EXCCODE_PIS;
> + } else if (access_type == MMU_INST_FETCH) {
> + cs->exception_index = EXCCODE_PIF;
> + }
> + env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 1);
> + break;
> + case TLBRET_INVALID:
> + /* TLB match with no valid bit */
> + if (access_type == MMU_DATA_LOAD) {
> + cs->exception_index = EXCCODE_PIL;
> + } else if (access_type == MMU_DATA_STORE) {
> + cs->exception_index = EXCCODE_PIS;
> + } else if (access_type == MMU_INST_FETCH) {
> + cs->exception_index = EXCCODE_PIF;
> + }
> + break;
> + case TLBRET_DIRTY:
> + /* TLB match but 'D' bit is cleared */
> + cs->exception_index = EXCCODE_PME;
> + break;
> + case TLBRET_XI:
> + /* Execute-Inhibit Exception */
> + cs->exception_index = EXCCODE_PNX;
> + break;
> + case TLBRET_RI:
> + /* Read-Inhibit Exception */
> + cs->exception_index = EXCCODE_PNR;
> + break;
> + case TLBRET_PE:
> + /* Privileged Exception */
> + cs->exception_index = EXCCODE_PPI;
> + break;
> + }
> +
> + if (tlb_error == TLBRET_NOMATCH) {
> + env->CSR_TLBRBADV = address;
> + env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
> + extract64(address, 13, 35));
> + } else {
> + if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
> + env->CSR_BADV = address;
> + }
> + env->CSR_TLBEHI = address & (TARGET_PAGE_MASK << 1);
> + }
> +}
> +
> +void loongarch_mmu_init(CPULoongArchState *env)
> +{
> + /* For 16KB, ps = 14, compare the bit [47:15] */
"KiB"; "compare the bits"
> + for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
> + env->tlb[i].tlb_misc = FIELD_DP64(env->tlb[i].tlb_misc, TLB_MISC, E, 0);
> + }
> +}
> +
> +bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> + MMUAccessType access_type, int mmu_idx,
> + bool probe, uintptr_t retaddr)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> + hwaddr physical;
> + int prot;
> + int ret = TLBRET_BADADDR;
> +
> + /* Data access */
> + /* XXX: put correct access by using cpu_restore_state() correctly */
Do you plan to fix this in a subsequent revision?
> + ret = get_physical_address(env, &physical, &prot, address,
> + access_type, mmu_idx);
> +
> + if (ret == TLBRET_MATCH) {
> + tlb_set_page(cs, address & TARGET_PAGE_MASK,
> + physical & TARGET_PAGE_MASK, prot,
> + mmu_idx, TARGET_PAGE_SIZE);
> + qemu_log_mask(CPU_LOG_MMU,
> + "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
> + " prot %d\n", __func__, address, physical, prot);
> + return true;
> + } else {
> + qemu_log_mask(CPU_LOG_MMU,
> + "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
> + ret);
> + }
> + if (probe) {
> + return false;
> + } else {
> + raise_mmu_exception(env, address, access_type, ret);
> + do_raise_exception(env, cs->exception_index, retaddr);
> + }
> +}
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 07/30] target/loongarch: Add LoongArch CSR instruction
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (5 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 06/30] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-08 9:13 ` [RFC PATCH v4 08/30] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
` (24 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.h | 88 +++++++++++++
target/loongarch/csr_helper.c | 112 +++++++++++++++++
target/loongarch/disas.c | 15 +++
target/loongarch/helper.h | 7 ++
target/loongarch/insn_trans/trans_core.c.inc | 123 +++++++++++++++++++
target/loongarch/insns.decode | 13 ++
target/loongarch/meson.build | 1 +
target/loongarch/translate.c | 5 +
8 files changed, 364 insertions(+)
create mode 100644 target/loongarch/csr_helper.c
create mode 100644 target/loongarch/insn_trans/trans_core.c.inc
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 232d51e788..2a1841a708 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -260,6 +260,94 @@ struct CPULoongArchState {
#endif
};
+#define CSR_OFF(X) \
+ [LOONGARCH_CSR_##X] = offsetof(CPULoongArchState, CSR_##X)
+#define CSR_OFF_ARRAY(X, N) \
+ [LOONGARCH_CSR_##X(N)] = offsetof(CPULoongArchState, CSR_##X[N])
+
+static const int csr_offsets[] = {
+ CSR_OFF(CRMD),
+ CSR_OFF(PRMD),
+ CSR_OFF(EUEN),
+ CSR_OFF(MISC),
+ CSR_OFF(ECFG),
+ CSR_OFF(ESTAT),
+ CSR_OFF(ERA),
+ CSR_OFF(BADV),
+ CSR_OFF(BADI),
+ CSR_OFF(EENTRY),
+ CSR_OFF(TLBIDX),
+ CSR_OFF(TLBEHI),
+ CSR_OFF(TLBELO0),
+ CSR_OFF(TLBELO1),
+ CSR_OFF(ASID),
+ CSR_OFF(PGDL),
+ CSR_OFF(PGDH),
+ CSR_OFF(PGD),
+ CSR_OFF(PWCL),
+ CSR_OFF(PWCH),
+ CSR_OFF(STLBPS),
+ CSR_OFF(RVACFG),
+ CSR_OFF(CPUID),
+ CSR_OFF(PRCFG1),
+ CSR_OFF(PRCFG2),
+ CSR_OFF(PRCFG3),
+ CSR_OFF_ARRAY(SAVE, 0),
+ CSR_OFF_ARRAY(SAVE, 1),
+ CSR_OFF_ARRAY(SAVE, 2),
+ CSR_OFF_ARRAY(SAVE, 3),
+ CSR_OFF_ARRAY(SAVE, 4),
+ CSR_OFF_ARRAY(SAVE, 5),
+ CSR_OFF_ARRAY(SAVE, 6),
+ CSR_OFF_ARRAY(SAVE, 7),
+ CSR_OFF_ARRAY(SAVE, 8),
+ CSR_OFF_ARRAY(SAVE, 9),
+ CSR_OFF_ARRAY(SAVE, 10),
+ CSR_OFF_ARRAY(SAVE, 11),
+ CSR_OFF_ARRAY(SAVE, 12),
+ CSR_OFF_ARRAY(SAVE, 13),
+ CSR_OFF_ARRAY(SAVE, 14),
+ CSR_OFF_ARRAY(SAVE, 15),
+ CSR_OFF(TID),
+ CSR_OFF(TCFG),
+ CSR_OFF(TVAL),
+ CSR_OFF(CNTC),
+ CSR_OFF(TICLR),
+ CSR_OFF(LLBCTL),
+ CSR_OFF(IMPCTL1),
+ CSR_OFF(IMPCTL2),
+ CSR_OFF(TLBRENTRY),
+ CSR_OFF(TLBRBADV),
+ CSR_OFF(TLBRERA),
+ CSR_OFF(TLBRSAVE),
+ CSR_OFF(TLBRELO0),
+ CSR_OFF(TLBRELO1),
+ CSR_OFF(TLBREHI),
+ CSR_OFF(TLBRPRMD),
+ CSR_OFF(MERRCTL),
+ CSR_OFF(MERRINFO1),
+ CSR_OFF(MERRINFO2),
+ CSR_OFF(MERRENTRY),
+ CSR_OFF(MERRERA),
+ CSR_OFF(MERRSAVE),
+ CSR_OFF(CTAG),
+ CSR_OFF_ARRAY(DMW, 0),
+ CSR_OFF_ARRAY(DMW, 1),
+ CSR_OFF_ARRAY(DMW, 2),
+ CSR_OFF_ARRAY(DMW, 3),
+ CSR_OFF(DBG),
+ CSR_OFF(DERA),
+ CSR_OFF(DSAVE),
+};
+
+static inline int cpu_csr_offset(unsigned csr_num)
+{
+ if (csr_num < ARRAY_SIZE(csr_offsets)) {
+ return csr_offsets[csr_num];
+ }
+ return 0;
+}
+
/**
* LoongArchCPU:
* @env: #CPULoongArchState
diff --git a/target/loongarch/csr_helper.c b/target/loongarch/csr_helper.c
new file mode 100644
index 0000000000..4d0619cec8
--- /dev/null
+++ b/target/loongarch/csr_helper.c
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch emulation helpers for csr registers
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "cpu.h"
+#include "internals.h"
+#include "qemu/host-utils.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
+#include "hw/irq.h"
+#include "cpu-csr.h"
+#include "hw/loongarch/loongarch.h"
+#include "tcg/tcg-ldst.h"
+
+target_ulong helper_csr_rdq(CPULoongArchState *env, uint64_t csr)
+{
+ LoongArchCPU *cpu;
+ int64_t v;
+
+ switch (csr) {
+ case LOONGARCH_CSR_PGD:
+ if (env->CSR_TLBRERA & 0x1) {
+ v = env->CSR_TLBRBADV;
+ } else {
+ v = env->CSR_BADV;
+ }
+
+ if ((v >> 63) & 0x1) {
+ v = env->CSR_PGDH;
+ } else {
+ v = env->CSR_PGDL;
+ }
+ break;
+ case LOONGARCH_CSR_CPUID:
+ v = (env_cpu(env))->cpu_index;
+ break;
+ case LOONGARCH_CSR_TVAL:
+ cpu = LOONGARCH_CPU(env_cpu(env));
+ v = cpu_loongarch_get_constant_timer_ticks(cpu);
+ break;
+ default:
+ break;
+ }
+
+ return v;
+}
+
+target_ulong helper_csr_wrq(CPULoongArchState *env, target_ulong val,
+ uint64_t csr)
+{
+ LoongArchCPU *cpu;
+ int64_t old_v = -1;
+
+ switch (csr) {
+ case LOONGARCH_CSR_ESTAT:
+ /* Only IS[1:0] can be write */
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, IS, val & 0x3);
+ break;
+ case LOONGARCH_CSR_ASID:
+ old_v = env->CSR_ASID;
+ /* Only ASID filed of CSR_ASID can be write. */
+ env->CSR_ASID = FIELD_DP64(env->CSR_ASID, CSR_ASID, ASID,
+ val & R_CSR_ASID_ASID_MASK);
+ if (old_v != val) {
+ tlb_flush(env_cpu(env));
+ }
+ break;
+ case LOONGARCH_CSR_TCFG:
+ cpu = LOONGARCH_CPU(env_cpu(env));
+ old_v = env->CSR_TCFG;
+ cpu_loongarch_store_constant_timer_config(cpu, val);
+ break;
+ case LOONGARCH_CSR_TICLR:
+ old_v = 0;
+ env->CSR_ESTAT &= ~(1 << IRQ_TIMER);
+ cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
+ break;
+ default:
+ break;
+ }
+
+ return old_v;
+}
+
+target_ulong helper_csr_xchgq(CPULoongArchState *env, target_ulong new_val,
+ target_ulong mask, uint64_t csr_num)
+{
+ unsigned csr_offset = cpu_csr_offset(csr_num);
+ if (csr_offset == 0) {
+ /* CSR is undefined: read as 0, write ignored. */
+ return 0;
+ }
+
+ uint64_t *csr = (void *)env + csr_offset;
+ uint64_t old_val = *csr;
+
+ new_val = (new_val & mask) | (old_val & ~mask);
+
+ if (csr_num == LOONGARCH_CSR_TCFG) {
+ LoongArchCPU *cpu = LOONGARCH_CPU(env_cpu(env));
+ cpu_loongarch_store_constant_timer_config(cpu, new_val);
+ } else {
+ *csr = new_val;
+ }
+ return old_val;
+}
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 45be34de27..de683bb88b 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -204,6 +204,18 @@ static void output_rr_offs(DisasContext *ctx, arg_rr_offs *a,
output(ctx, mnemonic, "r%d, r%d, %d", a->rj, a->rd, a->offs);
}
+static void output_r_csr(DisasContext *ctx, arg_r_csr *a,
+ const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, %d", a->rd, a->csr);
+}
+
+static void output_rr_csr(DisasContext *ctx, arg_rr_csr *a,
+ const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, r%d, %d", a->rd, a->rj, a->csr);
+}
+
#define INSN(insn, type) \
static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
{ \
@@ -516,6 +528,9 @@ INSN(blt, rr_offs)
INSN(bge, rr_offs)
INSN(bltu, rr_offs)
INSN(bgeu, rr_offs)
+INSN(csrrd, r_csr)
+INSN(csrwr, r_csr)
+INSN(csrxchg, rr_csr)
#define output_fcmp(C, PREFIX, SUFFIX) \
{ \
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index da1a2bced7..036dbf31f8 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -92,3 +92,10 @@ DEF_HELPER_2(frint_s, i64, env, i64)
DEF_HELPER_2(frint_d, i64, env, i64)
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32)
+
+/*Core functions */
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_2(csr_rdq, i64, env, i64)
+DEF_HELPER_3(csr_wrq, i64, env, tl, i64)
+DEF_HELPER_4(csr_xchgq, i64, env, tl, tl, i64)
+#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
new file mode 100644
index 0000000000..7d2cfe3534
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_core.c.inc
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch translate functions for system mode
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+/* Privileged instruction translation */
+
+#include "cpu-csr.h"
+
+#ifdef CONFIG_USER_ONLY
+
+#define GEN_FALSE_TRANS(name) \
+static bool trans_##name(DisasContext *ctx, arg_##name * a) \
+{ \
+ return false; \
+}
+
+GEN_FALSE_TRANS(csrrd)
+GEN_FALSE_TRANS(csrwr)
+GEN_FALSE_TRANS(csrxchg)
+
+#else
+
+static bool check_plv(DisasContext *ctx)
+{
+ if (ctx->base.tb->flags == MMU_USER_IDX) {
+ generate_exception(ctx, EXCCODE_IPE);
+ return true;
+ }
+ return false;
+}
+
+static bool ro_csr(int csr_num)
+{
+ /*
+ * For now qemu does not support any features of the MISC
+ * bits yet treat as a RO CSR.
+ */
+ if ((csr_num == LOONGARCH_CSR_BADI) || (csr_num == LOONGARCH_CSR_CPUID) ||
+ (csr_num == LOONGARCH_CSR_PRCFG1) || (csr_num == LOONGARCH_CSR_PRCFG2) ||
+ (csr_num == LOONGARCH_CSR_PRCFG3) || (csr_num == LOONGARCH_CSR_PGD) ||
+ (csr_num == LOONGARCH_CSR_TVAL) || (csr_num == LOONGARCH_CSR_MISC)) {
+ return true;
+ }
+
+ return false;
+}
+
+static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+
+ unsigned csr_offset = cpu_csr_offset(a->csr);
+ if (csr_offset == 0) {
+ /* CSR is undefined: read as 0 */
+ dest = tcg_constant_tl(0);
+ return true;
+ }
+
+ if ((a->csr == LOONGARCH_CSR_PGD) || (a->csr == LOONGARCH_CSR_CPUID) ||
+ (a->csr == LOONGARCH_CSR_TVAL)) {
+ gen_helper_csr_rdq(dest, cpu_env, tcg_constant_i64(a->csr));
+ } else {
+ tcg_gen_ld_tl(dest, cpu_env, csr_offset);
+ }
+ return true;
+}
+
+static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
+
+ if (check_plv(ctx) || ro_csr(a->csr)) {
+ return false;
+ }
+
+ unsigned csr_offset = cpu_csr_offset(a->csr);
+ if (csr_offset == 0) {
+ /* CSR is undefined: write ignored. */
+ return true;
+ }
+
+ if ((a->csr == LOONGARCH_CSR_ASID) || (a->csr == LOONGARCH_CSR_TCFG) ||
+ (a->csr == LOONGARCH_CSR_TICLR) || (a->csr == LOONGARCH_CSR_ESTAT)) {
+ gen_helper_csr_wrq(dest, cpu_env, src1, tcg_constant_i64(a->csr));
+ } else {
+ TCGv temp = tcg_temp_new();
+ tcg_gen_ld_tl(temp, cpu_env, csr_offset);
+ tcg_gen_st_tl(src1, cpu_env, csr_offset);
+ tcg_gen_mov_tl(dest, temp);
+ tcg_temp_free(temp);
+
+ /* Cpu state may be changed, need exit */
+ if ((a->csr == LOONGARCH_CSR_CRMD) || (a->csr == LOONGARCH_CSR_EUEN)) {
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXIT;
+ }
+ }
+
+ return true;
+}
+
+static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx) || ro_csr(a->csr)) {
+ return false;
+ }
+ gen_helper_csr_xchgq(dest, cpu_env, src1, src2, tcg_constant_i64(a->csr));
+ return true;
+}
+
+#endif
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 3379d22979..647fcb9def 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -45,6 +45,8 @@
&c_offs cj offs
&offs offs
&rr_offs rj rd offs
+&r_csr rd csr
+&rr_csr rd rj csr
#
# Formats
@@ -85,6 +87,8 @@
@c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21
@offs26 .... .. .......................... &offs offs=%offs26
@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
+@r_csr .... .... csr:14 ..... rd:5 &r_csr
+@rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
#
# Fixed point arithmetic operation instruction
@@ -440,3 +444,12 @@ blt 0110 00 ................ ..... ..... @rr_offs16
bge 0110 01 ................ ..... ..... @rr_offs16
bltu 0110 10 ................ ..... ..... @rr_offs16
bgeu 0110 11 ................ ..... ..... @rr_offs16
+
+#
+# Core instructions
+#
+{
+ csrrd 0000 0100 .............. 00000 ..... @r_csr
+ csrwr 0000 0100 .............. 00001 ..... @r_csr
+ csrxchg 0000 0100 .............. ..... ..... @rr_csr
+}
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 6bf2d88104..5fb7542e88 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -19,6 +19,7 @@ loongarch_softmmu_ss.add(files(
'machine.c',
'constant_timer.c',
'tlb_helper.c',
+ 'csr_helper.c',
))
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 2710764653..09771ee43f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -26,6 +26,7 @@ TCGv_i32 cpu_fcsr0;
TCGv_i64 cpu_fpr[32];
#define DISAS_STOP DISAS_TARGET_0
+#define DISAS_EXIT DISAS_TARGET_1
static inline int plus_1(DisasContext *ctx, int x)
{
@@ -172,6 +173,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_fmov.c.inc"
#include "insn_trans/trans_fmemory.c.inc"
#include "insn_trans/trans_branch.c.inc"
+#include "insn_trans/trans_core.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
@@ -209,6 +211,9 @@ static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
break;
case DISAS_NORETURN:
break;
+ case DISAS_EXIT:
+ tcg_gen_exit_tb(NULL, 0);
+ break;
default:
g_assert_not_reached();
}
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 07/30] target/loongarch: Add LoongArch CSR instruction
2022-01-08 9:13 ` [RFC PATCH v4 07/30] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This includes:
> - CSRRD
> - CSRWR
> - CSRXCHG
>
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/cpu.h | 88 +++++++++++++
> target/loongarch/csr_helper.c | 112 +++++++++++++++++
> target/loongarch/disas.c | 15 +++
> target/loongarch/helper.h | 7 ++
> target/loongarch/insn_trans/trans_core.c.inc | 123 +++++++++++++++++++
> target/loongarch/insns.decode | 13 ++
> target/loongarch/meson.build | 1 +
> target/loongarch/translate.c | 5 +
> 8 files changed, 364 insertions(+)
> create mode 100644 target/loongarch/csr_helper.c
> create mode 100644 target/loongarch/insn_trans/trans_core.c.inc
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 232d51e788..2a1841a708 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -260,6 +260,94 @@ struct CPULoongArchState {
> #endif
> };
>
> +#define CSR_OFF(X) \
> + [LOONGARCH_CSR_##X] = offsetof(CPULoongArchState, CSR_##X)
> +#define CSR_OFF_ARRAY(X, N) \
> + [LOONGARCH_CSR_##X(N)] = offsetof(CPULoongArchState, CSR_##X[N])
> +
> +static const int csr_offsets[] = {
> + CSR_OFF(CRMD),
> + CSR_OFF(PRMD),
> + CSR_OFF(EUEN),
> + CSR_OFF(MISC),
> + CSR_OFF(ECFG),
> + CSR_OFF(ESTAT),
> + CSR_OFF(ERA),
> + CSR_OFF(BADV),
> + CSR_OFF(BADI),
> + CSR_OFF(EENTRY),
> + CSR_OFF(TLBIDX),
> + CSR_OFF(TLBEHI),
> + CSR_OFF(TLBELO0),
> + CSR_OFF(TLBELO1),
> + CSR_OFF(ASID),
> + CSR_OFF(PGDL),
> + CSR_OFF(PGDH),
> + CSR_OFF(PGD),
> + CSR_OFF(PWCL),
> + CSR_OFF(PWCH),
> + CSR_OFF(STLBPS),
> + CSR_OFF(RVACFG),
> + CSR_OFF(CPUID),
> + CSR_OFF(PRCFG1),
> + CSR_OFF(PRCFG2),
> + CSR_OFF(PRCFG3),
> + CSR_OFF_ARRAY(SAVE, 0),
> + CSR_OFF_ARRAY(SAVE, 1),
> + CSR_OFF_ARRAY(SAVE, 2),
> + CSR_OFF_ARRAY(SAVE, 3),
> + CSR_OFF_ARRAY(SAVE, 4),
> + CSR_OFF_ARRAY(SAVE, 5),
> + CSR_OFF_ARRAY(SAVE, 6),
> + CSR_OFF_ARRAY(SAVE, 7),
> + CSR_OFF_ARRAY(SAVE, 8),
> + CSR_OFF_ARRAY(SAVE, 9),
> + CSR_OFF_ARRAY(SAVE, 10),
> + CSR_OFF_ARRAY(SAVE, 11),
> + CSR_OFF_ARRAY(SAVE, 12),
> + CSR_OFF_ARRAY(SAVE, 13),
> + CSR_OFF_ARRAY(SAVE, 14),
> + CSR_OFF_ARRAY(SAVE, 15),
> + CSR_OFF(TID),
> + CSR_OFF(TCFG),
> + CSR_OFF(TVAL),
> + CSR_OFF(CNTC),
> + CSR_OFF(TICLR),
> + CSR_OFF(LLBCTL),
> + CSR_OFF(IMPCTL1),
> + CSR_OFF(IMPCTL2),
> + CSR_OFF(TLBRENTRY),
> + CSR_OFF(TLBRBADV),
> + CSR_OFF(TLBRERA),
> + CSR_OFF(TLBRSAVE),
> + CSR_OFF(TLBRELO0),
> + CSR_OFF(TLBRELO1),
> + CSR_OFF(TLBREHI),
> + CSR_OFF(TLBRPRMD),
> + CSR_OFF(MERRCTL),
> + CSR_OFF(MERRINFO1),
> + CSR_OFF(MERRINFO2),
> + CSR_OFF(MERRENTRY),
> + CSR_OFF(MERRERA),
> + CSR_OFF(MERRSAVE),
> + CSR_OFF(CTAG),
> + CSR_OFF_ARRAY(DMW, 0),
> + CSR_OFF_ARRAY(DMW, 1),
> + CSR_OFF_ARRAY(DMW, 2),
> + CSR_OFF_ARRAY(DMW, 3),
> + CSR_OFF(DBG),
> + CSR_OFF(DERA),
> + CSR_OFF(DSAVE),
> +};
> +
> +static inline int cpu_csr_offset(unsigned csr_num)
> +{
> + if (csr_num < ARRAY_SIZE(csr_offsets)) {
> + return csr_offsets[csr_num];
> + }
> + return 0;
> +}
> +
> /**
> * LoongArchCPU:
> * @env: #CPULoongArchState
> diff --git a/target/loongarch/csr_helper.c b/target/loongarch/csr_helper.c
> new file mode 100644
> index 0000000000..4d0619cec8
> --- /dev/null
> +++ b/target/loongarch/csr_helper.c
> @@ -0,0 +1,112 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch emulation helpers for csr registers
"Emulation helpers for CSRs" is enough.
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/main-loop.h"
> +#include "cpu.h"
> +#include "internals.h"
> +#include "qemu/host-utils.h"
> +#include "exec/helper-proto.h"
> +#include "exec/exec-all.h"
> +#include "exec/cpu_ldst.h"
> +#include "hw/irq.h"
> +#include "cpu-csr.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "tcg/tcg-ldst.h"
> +
> +target_ulong helper_csr_rdq(CPULoongArchState *env, uint64_t csr)
> +{
> + LoongArchCPU *cpu;
> + int64_t v;
> +
> + switch (csr) {
> + case LOONGARCH_CSR_PGD:
> + if (env->CSR_TLBRERA & 0x1) {
> + v = env->CSR_TLBRBADV;
> + } else {
> + v = env->CSR_BADV;
> + }
> +
> + if ((v >> 63) & 0x1) {
> + v = env->CSR_PGDH;
> + } else {
> + v = env->CSR_PGDL;
> + }
> + break;
> + case LOONGARCH_CSR_CPUID:
> + v = (env_cpu(env))->cpu_index;
> + break;
> + case LOONGARCH_CSR_TVAL:
> + cpu = LOONGARCH_CPU(env_cpu(env));
> + v = cpu_loongarch_get_constant_timer_ticks(cpu);
> + break;
> + default:
> + break;
> + }
> +
> + return v;
> +}
> +
> +target_ulong helper_csr_wrq(CPULoongArchState *env, target_ulong val,
> + uint64_t csr)
> +{
> + LoongArchCPU *cpu;
> + int64_t old_v = -1;
> +
> + switch (csr) {
> + case LOONGARCH_CSR_ESTAT:
> + /* Only IS[1:0] can be write */
> + env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, IS, val & 0x3);
> + break;
> + case LOONGARCH_CSR_ASID:
> + old_v = env->CSR_ASID;
> + /* Only ASID filed of CSR_ASID can be write. */
> + env->CSR_ASID = FIELD_DP64(env->CSR_ASID, CSR_ASID, ASID,
> + val & R_CSR_ASID_ASID_MASK);
> + if (old_v != val) {
> + tlb_flush(env_cpu(env));
> + }
> + break;
> + case LOONGARCH_CSR_TCFG:
> + cpu = LOONGARCH_CPU(env_cpu(env));
> + old_v = env->CSR_TCFG;
> + cpu_loongarch_store_constant_timer_config(cpu, val);
> + break;
> + case LOONGARCH_CSR_TICLR:
> + old_v = 0;
> + env->CSR_ESTAT &= ~(1 << IRQ_TIMER);
> + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
> + break;
> + default:
> + break;
> + }
> +
> + return old_v;
> +}
> +
> +target_ulong helper_csr_xchgq(CPULoongArchState *env, target_ulong new_val,
> + target_ulong mask, uint64_t csr_num)
> +{
> + unsigned csr_offset = cpu_csr_offset(csr_num);
> + if (csr_offset == 0) {
> + /* CSR is undefined: read as 0, write ignored. */
"Undefined CSR; reads return 0, writes are ignored. */
> + return 0;
> + }
> +
> + uint64_t *csr = (void *)env + csr_offset;
> + uint64_t old_val = *csr;
> +
> + new_val = (new_val & mask) | (old_val & ~mask);
> +
> + if (csr_num == LOONGARCH_CSR_TCFG) {
> + LoongArchCPU *cpu = LOONGARCH_CPU(env_cpu(env));
> + cpu_loongarch_store_constant_timer_config(cpu, new_val);
> + } else {
> + *csr = new_val;
> + }
> + return old_val;
> +}
> diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
> index 45be34de27..de683bb88b 100644
> --- a/target/loongarch/disas.c
> +++ b/target/loongarch/disas.c
> @@ -204,6 +204,18 @@ static void output_rr_offs(DisasContext *ctx, arg_rr_offs *a,
> output(ctx, mnemonic, "r%d, r%d, %d", a->rj, a->rd, a->offs);
> }
>
> +static void output_r_csr(DisasContext *ctx, arg_r_csr *a,
> + const char *mnemonic)
> +{
> + output(ctx, mnemonic, "r%d, %d", a->rd, a->csr);
> +}
> +
> +static void output_rr_csr(DisasContext *ctx, arg_rr_csr *a,
> + const char *mnemonic)
> +{
> + output(ctx, mnemonic, "r%d, r%d, %d", a->rd, a->rj, a->csr);
> +}
> +
> #define INSN(insn, type) \
> static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
> { \
> @@ -516,6 +528,9 @@ INSN(blt, rr_offs)
> INSN(bge, rr_offs)
> INSN(bltu, rr_offs)
> INSN(bgeu, rr_offs)
> +INSN(csrrd, r_csr)
> +INSN(csrwr, r_csr)
> +INSN(csrxchg, rr_csr)
>
> #define output_fcmp(C, PREFIX, SUFFIX) \
> { \
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index da1a2bced7..036dbf31f8 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -92,3 +92,10 @@ DEF_HELPER_2(frint_s, i64, env, i64)
> DEF_HELPER_2(frint_d, i64, env, i64)
>
> DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32)
> +
> +/*Core functions */
> +#ifndef CONFIG_USER_ONLY
> +DEF_HELPER_2(csr_rdq, i64, env, i64)
> +DEF_HELPER_3(csr_wrq, i64, env, tl, i64)
> +DEF_HELPER_4(csr_xchgq, i64, env, tl, tl, i64)
> +#endif /* !CONFIG_USER_ONLY */
> diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
> new file mode 100644
> index 0000000000..7d2cfe3534
> --- /dev/null
> +++ b/target/loongarch/insn_trans/trans_core.c.inc
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch translate functions for system mode
"Translation functions for privileged mode"? And rename the file to
"trans_privileged.c.inc"?
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +/* Privileged instruction translation */
And this comment could be removed.
> +
> +#include "cpu-csr.h"
> +
> +#ifdef CONFIG_USER_ONLY
> +
> +#define GEN_FALSE_TRANS(name) \
GEN_TRANS_STUB? "false trans" sounds like something that's NOT a
"trans", but the generated functions are actually real "trans" helpers
that do nothing.
> +static bool trans_##name(DisasContext *ctx, arg_##name * a) \
> +{ \
> + return false; \
> +}
> +
> +GEN_FALSE_TRANS(csrrd)
> +GEN_FALSE_TRANS(csrwr)
> +GEN_FALSE_TRANS(csrxchg)
> +
> +#else
> +
> +static bool check_plv(DisasContext *ctx)
> +{
> + if (ctx->base.tb->flags == MMU_USER_IDX) {
> + generate_exception(ctx, EXCCODE_IPE);
Are the instructions accessible from PLV0 to PLV2 inclusive, as implied
by this "if" statement? Or do we only allow for PLV0?
> + return true;
> + }
> + return false;
> +}
> +
> +static bool ro_csr(int csr_num)
> +{
> + /*
> + * For now qemu does not support any features of the MISC
> + * bits yet treat as a RO CSR.
"Treat MISC as a read-only CSR because its features are not supported yet."
> + */
> + if ((csr_num == LOONGARCH_CSR_BADI) || (csr_num == LOONGARCH_CSR_CPUID) ||
> + (csr_num == LOONGARCH_CSR_PRCFG1) || (csr_num == LOONGARCH_CSR_PRCFG2) ||
> + (csr_num == LOONGARCH_CSR_PRCFG3) || (csr_num == LOONGARCH_CSR_PGD) ||
> + (csr_num == LOONGARCH_CSR_TVAL) || (csr_num == LOONGARCH_CSR_MISC)) {
Use a switch statement for match arms spanning many values like this;
doing so increases readability and reduces duplication.
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> +
> + unsigned csr_offset = cpu_csr_offset(a->csr);
> + if (csr_offset == 0) {
> + /* CSR is undefined: read as 0 */
"reads return 0"
> + dest = tcg_constant_tl(0);
> + return true;
> + }
> +
> + if ((a->csr == LOONGARCH_CSR_PGD) || (a->csr == LOONGARCH_CSR_CPUID) ||
> + (a->csr == LOONGARCH_CSR_TVAL)) {
Use a switch.
> + gen_helper_csr_rdq(dest, cpu_env, tcg_constant_i64(a->csr));
> + } else {
> + tcg_gen_ld_tl(dest, cpu_env, csr_offset);
> + }
> + return true;
> +}
> +
> +static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> + TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
> +
> + if (check_plv(ctx) || ro_csr(a->csr)) {
> + return false;
> + }
> +
> + unsigned csr_offset = cpu_csr_offset(a->csr);
> + if (csr_offset == 0) {
> + /* CSR is undefined: write ignored. */
"writes are ignored"
> + return true;
> + }
> +
> + if ((a->csr == LOONGARCH_CSR_ASID) || (a->csr == LOONGARCH_CSR_TCFG) ||
> + (a->csr == LOONGARCH_CSR_TICLR) || (a->csr == LOONGARCH_CSR_ESTAT)) {
Use a switch.
> + gen_helper_csr_wrq(dest, cpu_env, src1, tcg_constant_i64(a->csr));
> + } else {
> + TCGv temp = tcg_temp_new();
> + tcg_gen_ld_tl(temp, cpu_env, csr_offset);
> + tcg_gen_st_tl(src1, cpu_env, csr_offset);
> + tcg_gen_mov_tl(dest, temp);
> + tcg_temp_free(temp);
> +
> + /* Cpu state may be changed, need exit */
"CPU state may be changed, need to exit"
> + if ((a->csr == LOONGARCH_CSR_CRMD) || (a->csr == LOONGARCH_CSR_EUEN)) {
And here if you feel like doing that already. (It's only 2 codes so not
switch-ify-ing is okay too.)
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXIT;
> + }
> + }
> +
> + return true;
> +}
> +
> +static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> + TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
> + TCGv src2 = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx) || ro_csr(a->csr)) {
> + return false;
> + }
> + gen_helper_csr_xchgq(dest, cpu_env, src1, src2, tcg_constant_i64(a->csr));
> + return true;
> +}
> +
> +#endif
> diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
> index 3379d22979..647fcb9def 100644
> --- a/target/loongarch/insns.decode
> +++ b/target/loongarch/insns.decode
> @@ -45,6 +45,8 @@
> &c_offs cj offs
> &offs offs
> &rr_offs rj rd offs
> +&r_csr rd csr
> +&rr_csr rd rj csr
>
> #
> # Formats
> @@ -85,6 +87,8 @@
> @c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21
> @offs26 .... .. .......................... &offs offs=%offs26
> @rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
> +@r_csr .... .... csr:14 ..... rd:5 &r_csr
> +@rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
>
> #
> # Fixed point arithmetic operation instruction
> @@ -440,3 +444,12 @@ blt 0110 00 ................ ..... ..... @rr_offs16
> bge 0110 01 ................ ..... ..... @rr_offs16
> bltu 0110 10 ................ ..... ..... @rr_offs16
> bgeu 0110 11 ................ ..... ..... @rr_offs16
> +
> +#
> +# Core instructions
"Privileged instructions"?
> +#
> +{
> + csrrd 0000 0100 .............. 00000 ..... @r_csr
> + csrwr 0000 0100 .............. 00001 ..... @r_csr
> + csrxchg 0000 0100 .............. ..... ..... @rr_csr
> +}
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index 6bf2d88104..5fb7542e88 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -19,6 +19,7 @@ loongarch_softmmu_ss.add(files(
> 'machine.c',
> 'constant_timer.c',
> 'tlb_helper.c',
> + 'csr_helper.c',
> ))
>
> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
> diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
> index 2710764653..09771ee43f 100644
> --- a/target/loongarch/translate.c
> +++ b/target/loongarch/translate.c
> @@ -26,6 +26,7 @@ TCGv_i32 cpu_fcsr0;
> TCGv_i64 cpu_fpr[32];
>
> #define DISAS_STOP DISAS_TARGET_0
> +#define DISAS_EXIT DISAS_TARGET_1
>
> static inline int plus_1(DisasContext *ctx, int x)
> {
> @@ -172,6 +173,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
> #include "insn_trans/trans_fmov.c.inc"
> #include "insn_trans/trans_fmemory.c.inc"
> #include "insn_trans/trans_branch.c.inc"
> +#include "insn_trans/trans_core.c.inc"
>
> static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> {
> @@ -209,6 +211,9 @@ static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> break;
> case DISAS_NORETURN:
> break;
> + case DISAS_EXIT:
> + tcg_gen_exit_tb(NULL, 0);
> + break;
> default:
> g_assert_not_reached();
> }
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 08/30] target/loongarch: Add LoongArch IOCSR instruction
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (6 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 07/30] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:25 ` WANG Xuerui
2022-01-08 9:13 ` [RFC PATCH v4 09/30] target/loongarch: Add TLB instruction support Xiaojuan Yang
` (23 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This includes:
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 8 ++
target/loongarch/cpu.h | 4 +
target/loongarch/disas.c | 8 ++
target/loongarch/helper.h | 2 +
target/loongarch/insn_trans/trans_core.c.inc | 103 ++++++++++++++++
target/loongarch/insns.decode | 9 ++
target/loongarch/iocsr_helper.c | 120 +++++++++++++++++++
target/loongarch/meson.build | 1 +
8 files changed, 255 insertions(+)
create mode 100644 target/loongarch/iocsr_helper.c
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 780eb96a3c..571092ce53 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -158,6 +158,14 @@ static void loongarch_3a5000_initfn(Object *obj)
env->cpucfg[20] = data;
env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
+
+#ifndef CONFIG_USER_ONLY
+ env->address_space_iocsr = g_malloc(sizeof(*env->address_space_iocsr));
+ env->system_iocsr = g_malloc(sizeof(*env->system_iocsr));
+ memory_region_init_io(env->system_iocsr, obj, NULL,
+ env, "iocsr", UINT64_MAX);
+ address_space_init(env->address_space_iocsr, env->system_iocsr, "IOCSR");
+#endif
}
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 2a1841a708..ddb69ffecf 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -151,6 +151,7 @@ extern const char * const fregnames[32];
#define N_IRQS 14
#define IRQ_TIMER 11
+#define IRQ_IPI 12
#define LOONGARCH_TLB_MAX (2048 + 64) /* 2048 STLB + 64 MTLB */
#define LOONGARCH_STLB 2048 /* 2048 STLB */
@@ -257,6 +258,9 @@ struct CPULoongArchState {
#ifndef CONFIG_USER_ONLY
LoongArchTLB tlb[LOONGARCH_TLB_MAX];
+
+ AddressSpace *address_space_iocsr;
+ MemoryRegion *system_iocsr;
#endif
};
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index de683bb88b..cbb264a318 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -531,6 +531,14 @@ INSN(bgeu, rr_offs)
INSN(csrrd, r_csr)
INSN(csrwr, r_csr)
INSN(csrxchg, rr_csr)
+INSN(iocsrrd_b, rr)
+INSN(iocsrrd_h, rr)
+INSN(iocsrrd_w, rr)
+INSN(iocsrrd_d, rr)
+INSN(iocsrwr_b, rr)
+INSN(iocsrwr_h, rr)
+INSN(iocsrwr_w, rr)
+INSN(iocsrwr_d, rr)
#define output_fcmp(C, PREFIX, SUFFIX) \
{ \
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 036dbf31f8..1bcd082858 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -98,4 +98,6 @@ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_2(csr_rdq, i64, env, i64)
DEF_HELPER_3(csr_wrq, i64, env, tl, i64)
DEF_HELPER_4(csr_xchgq, i64, env, tl, tl, i64)
+DEF_HELPER_3(iocsr_read, i64, env, tl, i32)
+DEF_HELPER_4(iocsr_write, void, env, tl, tl, i32)
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
index 7d2cfe3534..592d2a339e 100644
--- a/target/loongarch/insn_trans/trans_core.c.inc
+++ b/target/loongarch/insn_trans/trans_core.c.inc
@@ -20,6 +20,14 @@ static bool trans_##name(DisasContext *ctx, arg_##name * a) \
GEN_FALSE_TRANS(csrrd)
GEN_FALSE_TRANS(csrwr)
GEN_FALSE_TRANS(csrxchg)
+GEN_FALSE_TRANS(iocsrrd_b)
+GEN_FALSE_TRANS(iocsrrd_h)
+GEN_FALSE_TRANS(iocsrrd_w)
+GEN_FALSE_TRANS(iocsrrd_d)
+GEN_FALSE_TRANS(iocsrwr_b)
+GEN_FALSE_TRANS(iocsrwr_h)
+GEN_FALSE_TRANS(iocsrwr_w)
+GEN_FALSE_TRANS(iocsrwr_d)
#else
@@ -120,4 +128,99 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
return true;
}
+static bool trans_iocsrrd_b(DisasContext *ctx, arg_iocsrrd_b *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(1));
+ return true;
+}
+
+static bool trans_iocsrrd_h(DisasContext *ctx, arg_iocsrrd_h *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(2));
+ return true;
+}
+
+static bool trans_iocsrrd_w(DisasContext *ctx, arg_iocsrrd_w *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(4));
+ return true;
+}
+
+static bool trans_iocsrrd_d(DisasContext *ctx, arg_iocsrrd_d *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(8));
+ return true;
+}
+
+static bool trans_iocsrwr_b(DisasContext *ctx, arg_iocsrwr_b *a)
+{
+ TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(1));
+ return true;
+}
+
+static bool trans_iocsrwr_h(DisasContext *ctx, arg_iocsrwr_h *a)
+{
+ TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(2));
+ return true;
+}
+
+static bool trans_iocsrwr_w(DisasContext *ctx, arg_iocsrwr_w *a)
+{
+ TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(4));
+ return true;
+}
+
+static bool trans_iocsrwr_d(DisasContext *ctx, arg_iocsrwr_d *a)
+{
+ TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(8));
+ return true;
+}
#endif
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 647fcb9def..9a43f288c3 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -453,3 +453,12 @@ bgeu 0110 11 ................ ..... ..... @rr_offs16
csrwr 0000 0100 .............. 00001 ..... @r_csr
csrxchg 0000 0100 .............. ..... ..... @rr_csr
}
+
+iocsrrd_b 0000 01100100 10000 00000 ..... ..... @rr
+iocsrrd_h 0000 01100100 10000 00001 ..... ..... @rr
+iocsrrd_w 0000 01100100 10000 00010 ..... ..... @rr
+iocsrrd_d 0000 01100100 10000 00011 ..... ..... @rr
+iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr
+iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr
+iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr
+iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
new file mode 100644
index 0000000000..f9efe2517f
--- /dev/null
+++ b/target/loongarch/iocsr_helper.c
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch emulation helpers for iocsr read/write
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "cpu.h"
+#include "internals.h"
+#include "qemu/host-utils.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
+#include "hw/irq.h"
+#include "cpu-csr.h"
+#include "hw/loongarch/loongarch.h"
+#include "tcg/tcg-ldst.h"
+
+/*
+ * For per core address 0x10xx(IPI) 0x18xx(EXTIOI)
+ * need extra adjust the iocsr addr.
+ */
+uint64_t helper_iocsr_read(CPULoongArchState *env, target_ulong r_addr,
+ uint32_t size)
+{
+ int cpuid = env_cpu(env)->cpu_index;
+ CPUState *cs = qemu_get_cpu(cpuid);
+ env = cs->env_ptr;
+
+ if (((r_addr & 0xff00) == 0x1000) || ((r_addr & 0xff00) == 0x1800)) {
+ r_addr = r_addr + ((target_ulong)(cpuid & 0x3) << 8);
+ }
+
+ if (size == 1) {
+ return address_space_ldub(env->address_space_iocsr, r_addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+ } else if (size == 2) {
+ return address_space_lduw(env->address_space_iocsr, r_addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+ } else if (size == 4) {
+ return address_space_ldl(env->address_space_iocsr, r_addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+ } else if (size == 8) {
+ return address_space_ldq(env->address_space_iocsr, r_addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+ }
+ return 0;
+}
+
+void helper_iocsr_write(CPULoongArchState *env, target_ulong w_addr,
+ target_ulong val, uint32_t size)
+{
+ int cpuid = env_cpu(env)->cpu_index;
+ CPUState *cs = qemu_get_cpu(cpuid);
+ int mask, i;
+
+ env = cs->env_ptr;
+ /*
+ * For IPI send, Mail send, ANY send adjust addr and val
+ * according to their real meaning. The iocsr write
+ * will finally lead to the corresponding mmio write
+ * all operations handled there.
+ */
+ if (w_addr == 0x1040) { /* IPI send */
+ cpuid = (val >> 16) & 0x3ff;
+ val = 1UL << (val & 0x1f);
+ if (val) {
+ qemu_mutex_lock_iothread();
+ cs = qemu_get_cpu(cpuid);
+ env = cs->env_ptr;
+ env->CSR_ESTAT |= 1 << IRQ_IPI;
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ qemu_mutex_unlock_iothread();
+ }
+ } else if (w_addr == 0x1048) { /* Mail Send */
+ cpuid = (val >> 16) & 0x3ff;
+ w_addr = 0x1020 + (val & 0x1c);
+ val = val >> 32;
+ mask = (val >> 27) & 0xf;
+ size = 4;
+ env = (qemu_get_cpu(cpuid))->env_ptr;
+ } else if (w_addr == 0x1158) { /* ANY send */
+ cpuid = (val >> 16) & 0x3ff;
+ w_addr = val & 0xffff;
+ val = val >> 32;
+ mask = (val >> 27) & 0xf;
+ size = 1;
+ env = (qemu_get_cpu(cpuid))->env_ptr;
+
+ for (i = 0; i < 4; i++) {
+ if (!((mask >> i) & 1)) {
+ address_space_stb(env->address_space_iocsr, w_addr,
+ val, MEMTXATTRS_UNSPECIFIED, NULL);
+ }
+ w_addr = w_addr + 1;
+ val = val >> 8;
+ }
+ return;
+ }
+
+ if (((w_addr & 0xff00) == 0x1000) || ((w_addr & 0xff00) == 0x1800)) {
+ w_addr = w_addr + ((target_ulong)(cpuid & 0x3) << 8);
+ }
+
+ if (size == 1) {
+ address_space_stb(env->address_space_iocsr, w_addr,
+ val, MEMTXATTRS_UNSPECIFIED, NULL);
+ } else if (size == 2) {
+ address_space_stw(env->address_space_iocsr, w_addr,
+ val, MEMTXATTRS_UNSPECIFIED, NULL);
+ } else if (size == 4) {
+ address_space_stl(env->address_space_iocsr, w_addr,
+ val, MEMTXATTRS_UNSPECIFIED, NULL);
+ } else if (size == 8) {
+ address_space_stq(env->address_space_iocsr, w_addr,
+ val, MEMTXATTRS_UNSPECIFIED, NULL);
+ }
+}
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 5fb7542e88..072684ca6d 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -20,6 +20,7 @@ loongarch_softmmu_ss.add(files(
'constant_timer.c',
'tlb_helper.c',
'csr_helper.c',
+ 'iocsr_helper.c',
))
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 08/30] target/loongarch: Add LoongArch IOCSR instruction
2022-01-08 9:13 ` [RFC PATCH v4 08/30] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
@ 2022-01-09 9:25 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:25 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This includes:
> - IOCSR{RD/WR}.{B/H/W/D}
>
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/cpu.c | 8 ++
> target/loongarch/cpu.h | 4 +
> target/loongarch/disas.c | 8 ++
> target/loongarch/helper.h | 2 +
> target/loongarch/insn_trans/trans_core.c.inc | 103 ++++++++++++++++
> target/loongarch/insns.decode | 9 ++
> target/loongarch/iocsr_helper.c | 120 +++++++++++++++++++
> target/loongarch/meson.build | 1 +
> 8 files changed, 255 insertions(+)
> create mode 100644 target/loongarch/iocsr_helper.c
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 780eb96a3c..571092ce53 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -158,6 +158,14 @@ static void loongarch_3a5000_initfn(Object *obj)
> env->cpucfg[20] = data;
>
> env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
> +
> +#ifndef CONFIG_USER_ONLY
> + env->address_space_iocsr = g_malloc(sizeof(*env->address_space_iocsr));
> + env->system_iocsr = g_malloc(sizeof(*env->system_iocsr));
> + memory_region_init_io(env->system_iocsr, obj, NULL,
> + env, "iocsr", UINT64_MAX);
> + address_space_init(env->address_space_iocsr, env->system_iocsr, "IOCSR");
> +#endif
> }
>
> static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 2a1841a708..ddb69ffecf 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -151,6 +151,7 @@ extern const char * const fregnames[32];
>
> #define N_IRQS 14
> #define IRQ_TIMER 11
> +#define IRQ_IPI 12
>
> #define LOONGARCH_TLB_MAX (2048 + 64) /* 2048 STLB + 64 MTLB */
> #define LOONGARCH_STLB 2048 /* 2048 STLB */
> @@ -257,6 +258,9 @@ struct CPULoongArchState {
>
> #ifndef CONFIG_USER_ONLY
> LoongArchTLB tlb[LOONGARCH_TLB_MAX];
> +
> + AddressSpace *address_space_iocsr;
> + MemoryRegion *system_iocsr;
> #endif
> };
>
> diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
> index de683bb88b..cbb264a318 100644
> --- a/target/loongarch/disas.c
> +++ b/target/loongarch/disas.c
> @@ -531,6 +531,14 @@ INSN(bgeu, rr_offs)
> INSN(csrrd, r_csr)
> INSN(csrwr, r_csr)
> INSN(csrxchg, rr_csr)
> +INSN(iocsrrd_b, rr)
> +INSN(iocsrrd_h, rr)
> +INSN(iocsrrd_w, rr)
> +INSN(iocsrrd_d, rr)
> +INSN(iocsrwr_b, rr)
> +INSN(iocsrwr_h, rr)
> +INSN(iocsrwr_w, rr)
> +INSN(iocsrwr_d, rr)
>
> #define output_fcmp(C, PREFIX, SUFFIX) \
> { \
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index 036dbf31f8..1bcd082858 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -98,4 +98,6 @@ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32)
> DEF_HELPER_2(csr_rdq, i64, env, i64)
> DEF_HELPER_3(csr_wrq, i64, env, tl, i64)
> DEF_HELPER_4(csr_xchgq, i64, env, tl, tl, i64)
> +DEF_HELPER_3(iocsr_read, i64, env, tl, i32)
> +DEF_HELPER_4(iocsr_write, void, env, tl, tl, i32)
> #endif /* !CONFIG_USER_ONLY */
> diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
> index 7d2cfe3534..592d2a339e 100644
> --- a/target/loongarch/insn_trans/trans_core.c.inc
> +++ b/target/loongarch/insn_trans/trans_core.c.inc
> @@ -20,6 +20,14 @@ static bool trans_##name(DisasContext *ctx, arg_##name * a) \
> GEN_FALSE_TRANS(csrrd)
> GEN_FALSE_TRANS(csrwr)
> GEN_FALSE_TRANS(csrxchg)
> +GEN_FALSE_TRANS(iocsrrd_b)
> +GEN_FALSE_TRANS(iocsrrd_h)
> +GEN_FALSE_TRANS(iocsrrd_w)
> +GEN_FALSE_TRANS(iocsrrd_d)
> +GEN_FALSE_TRANS(iocsrwr_b)
> +GEN_FALSE_TRANS(iocsrwr_h)
> +GEN_FALSE_TRANS(iocsrwr_w)
> +GEN_FALSE_TRANS(iocsrwr_d)
>
> #else
>
> @@ -120,4 +128,99 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
> return true;
> }
>
> +static bool trans_iocsrrd_b(DisasContext *ctx, arg_iocsrrd_b *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(1));
> + return true;
> +}
> +
> +static bool trans_iocsrrd_h(DisasContext *ctx, arg_iocsrrd_h *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(2));
> + return true;
> +}
> +
> +static bool trans_iocsrrd_w(DisasContext *ctx, arg_iocsrrd_w *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(4));
> + return true;
> +}
> +
> +static bool trans_iocsrrd_d(DisasContext *ctx, arg_iocsrrd_d *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_read(dest, cpu_env, src1, tcg_constant_i32(8));
> + return true;
> +}
> +
> +static bool trans_iocsrwr_b(DisasContext *ctx, arg_iocsrwr_b *a)
> +{
> + TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
> + TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(1));
> + return true;
> +}
> +
> +static bool trans_iocsrwr_h(DisasContext *ctx, arg_iocsrwr_h *a)
> +{
> + TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
> + TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(2));
> + return true;
> +}
> +
> +static bool trans_iocsrwr_w(DisasContext *ctx, arg_iocsrwr_w *a)
> +{
> + TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
> + TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(4));
> + return true;
> +}
> +
> +static bool trans_iocsrwr_d(DisasContext *ctx, arg_iocsrwr_d *a)
> +{
> + TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
> + TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(8));
> + return true;
> +}
> #endif
> diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
> index 647fcb9def..9a43f288c3 100644
> --- a/target/loongarch/insns.decode
> +++ b/target/loongarch/insns.decode
> @@ -453,3 +453,12 @@ bgeu 0110 11 ................ ..... ..... @rr_offs16
> csrwr 0000 0100 .............. 00001 ..... @r_csr
> csrxchg 0000 0100 .............. ..... ..... @rr_csr
> }
> +
> +iocsrrd_b 0000 01100100 10000 00000 ..... ..... @rr
> +iocsrrd_h 0000 01100100 10000 00001 ..... ..... @rr
> +iocsrrd_w 0000 01100100 10000 00010 ..... ..... @rr
> +iocsrrd_d 0000 01100100 10000 00011 ..... ..... @rr
> +iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr
> +iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr
> +iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr
> +iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr
> diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
> new file mode 100644
> index 0000000000..f9efe2517f
> --- /dev/null
> +++ b/target/loongarch/iocsr_helper.c
> @@ -0,0 +1,120 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch emulation helpers for iocsr read/write
"Helpers for IOCSR reads/writes"
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/main-loop.h"
> +#include "cpu.h"
> +#include "internals.h"
> +#include "qemu/host-utils.h"
> +#include "exec/helper-proto.h"
> +#include "exec/exec-all.h"
> +#include "exec/cpu_ldst.h"
> +#include "hw/irq.h"
> +#include "cpu-csr.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "tcg/tcg-ldst.h"
> +
> +/*
> + * For per core address 0x10xx(IPI) 0x18xx(EXTIOI)
> + * need extra adjust the iocsr addr.
> + */
Put this comment (after fixing broken English)...
> +uint64_t helper_iocsr_read(CPULoongArchState *env, target_ulong r_addr,
> + uint32_t size)
> +{
> + int cpuid = env_cpu(env)->cpu_index;
> + CPUState *cs = qemu_get_cpu(cpuid);
> + env = cs->env_ptr;
> +
...here directly before the "if" statement it's supposed to document.
> + if (((r_addr & 0xff00) == 0x1000) || ((r_addr & 0xff00) == 0x1800)) {
> + r_addr = r_addr + ((target_ulong)(cpuid & 0x3) << 8);
> + }
> +
> + if (size == 1) {
> + return address_space_ldub(env->address_space_iocsr, r_addr,
> + MEMTXATTRS_UNSPECIFIED, NULL);
> + } else if (size == 2) {
> + return address_space_lduw(env->address_space_iocsr, r_addr,
> + MEMTXATTRS_UNSPECIFIED, NULL);
> + } else if (size == 4) {
> + return address_space_ldl(env->address_space_iocsr, r_addr,
> + MEMTXATTRS_UNSPECIFIED, NULL);
> + } else if (size == 8) {
> + return address_space_ldq(env->address_space_iocsr, r_addr,
> + MEMTXATTRS_UNSPECIFIED, NULL);
> + }
Use a switch statement.
> + return 0;
> +}
> +
> +void helper_iocsr_write(CPULoongArchState *env, target_ulong w_addr,
> + target_ulong val, uint32_t size)
> +{
> + int cpuid = env_cpu(env)->cpu_index;
> + CPUState *cs = qemu_get_cpu(cpuid);
> + int mask, i;
> +
> + env = cs->env_ptr;
> + /*
> + * For IPI send, Mail send, ANY send adjust addr and val
> + * according to their real meaning. The iocsr write
> + * will finally lead to the corresponding mmio write
> + * all operations handled there.
> + */
"For IPI sends, mailbox sends and anysends, adjust addr and val
accordingly; the IOCSR writes are turned to MMIO writes respectively."
> + if (w_addr == 0x1040) { /* IPI send */
Use a switch for this w_addr as well...
> + cpuid = (val >> 16) & 0x3ff;
> + val = 1UL << (val & 0x1f);
> + if (val) {
> + qemu_mutex_lock_iothread();
> + cs = qemu_get_cpu(cpuid);
> + env = cs->env_ptr;
> + env->CSR_ESTAT |= 1 << IRQ_IPI;
> + cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> + qemu_mutex_unlock_iothread();
> + }
> + } else if (w_addr == 0x1048) { /* Mail Send */
> + cpuid = (val >> 16) & 0x3ff;
> + w_addr = 0x1020 + (val & 0x1c);
> + val = val >> 32;
> + mask = (val >> 27) & 0xf;
> + size = 4;
> + env = (qemu_get_cpu(cpuid))->env_ptr;
> + } else if (w_addr == 0x1158) { /* ANY send */
> + cpuid = (val >> 16) & 0x3ff;
> + w_addr = val & 0xffff;
> + val = val >> 32;
> + mask = (val >> 27) & 0xf;
> + size = 1;
> + env = (qemu_get_cpu(cpuid))->env_ptr;
> +
> + for (i = 0; i < 4; i++) {
> + if (!((mask >> i) & 1)) {
> + address_space_stb(env->address_space_iocsr, w_addr,
> + val, MEMTXATTRS_UNSPECIFIED, NULL);
> + }
> + w_addr = w_addr + 1;
> + val = val >> 8;
> + }
> + return;
> + }
> +
> + if (((w_addr & 0xff00) == 0x1000) || ((w_addr & 0xff00) == 0x1800)) {
> + w_addr = w_addr + ((target_ulong)(cpuid & 0x3) << 8);
> + }
> +
> + if (size == 1) {
> + address_space_stb(env->address_space_iocsr, w_addr,
> + val, MEMTXATTRS_UNSPECIFIED, NULL);
> + } else if (size == 2) {
> + address_space_stw(env->address_space_iocsr, w_addr,
> + val, MEMTXATTRS_UNSPECIFIED, NULL);
> + } else if (size == 4) {
> + address_space_stl(env->address_space_iocsr, w_addr,
> + val, MEMTXATTRS_UNSPECIFIED, NULL);
> + } else if (size == 8) {
> + address_space_stq(env->address_space_iocsr, w_addr,
> + val, MEMTXATTRS_UNSPECIFIED, NULL);
> + }
Use a switch for this too.
> +}
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index 5fb7542e88..072684ca6d 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -20,6 +20,7 @@ loongarch_softmmu_ss.add(files(
> 'constant_timer.c',
> 'tlb_helper.c',
> 'csr_helper.c',
> + 'iocsr_helper.c',
> ))
>
> loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 09/30] target/loongarch: Add TLB instruction support
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (7 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 08/30] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:26 ` WANG Xuerui
2022-01-08 9:13 ` [RFC PATCH v4 10/30] target/loongarch: Add other core instructions support Xiaojuan Yang
` (22 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 17 +
target/loongarch/helper.h | 12 +
target/loongarch/insn_trans/trans_core.c.inc | 112 ++++++
target/loongarch/insns.decode | 11 +
target/loongarch/tlb_helper.c | 364 +++++++++++++++++++
5 files changed, 516 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index cbb264a318..483270f331 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -216,6 +216,16 @@ static void output_rr_csr(DisasContext *ctx, arg_rr_csr *a,
output(ctx, mnemonic, "r%d, r%d, %d", a->rd, a->rj, a->csr);
}
+static void output_empty(DisasContext *ctx, arg_empty *a,
+ const char *mnemonic)
+{
+}
+
+static void output_i_rr(DisasContext *ctx, arg_i_rr *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "%d, r%d, r%d", a->imm, a->rj, a->rk);
+}
+
#define INSN(insn, type) \
static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
{ \
@@ -539,6 +549,13 @@ INSN(iocsrwr_b, rr)
INSN(iocsrwr_h, rr)
INSN(iocsrwr_w, rr)
INSN(iocsrwr_d, rr)
+INSN(tlbsrch, empty)
+INSN(tlbrd, empty)
+INSN(tlbwr, empty)
+INSN(tlbfill, empty)
+INSN(tlbclr, empty)
+INSN(tlbflush, empty)
+INSN(invtlb, i_rr)
#define output_fcmp(C, PREFIX, SUFFIX) \
{ \
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 1bcd082858..97af7ac8aa 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -100,4 +100,16 @@ DEF_HELPER_3(csr_wrq, i64, env, tl, i64)
DEF_HELPER_4(csr_xchgq, i64, env, tl, tl, i64)
DEF_HELPER_3(iocsr_read, i64, env, tl, i32)
DEF_HELPER_4(iocsr_write, void, env, tl, tl, i32)
+
+DEF_HELPER_1(tlbwr, void, env)
+DEF_HELPER_1(tlbfill, void, env)
+DEF_HELPER_1(tlbsrch, void, env)
+DEF_HELPER_1(tlbrd, void, env)
+DEF_HELPER_1(tlbclr, void, env)
+DEF_HELPER_1(tlbflush, void, env)
+DEF_HELPER_1(invtlb_all, void, env)
+DEF_HELPER_2(invtlb_all_g, void, env, i32)
+DEF_HELPER_2(invtlb_all_asid, void, env, tl)
+DEF_HELPER_3(invtlb_page_asid, void, env, tl, tl)
+DEF_HELPER_3(invtlb_page_asid_or_g, void, env, tl, tl)
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
index 592d2a339e..5a8e9e0643 100644
--- a/target/loongarch/insn_trans/trans_core.c.inc
+++ b/target/loongarch/insn_trans/trans_core.c.inc
@@ -28,6 +28,13 @@ GEN_FALSE_TRANS(iocsrwr_b)
GEN_FALSE_TRANS(iocsrwr_h)
GEN_FALSE_TRANS(iocsrwr_w)
GEN_FALSE_TRANS(iocsrwr_d)
+GEN_FALSE_TRANS(tlbsrch)
+GEN_FALSE_TRANS(tlbrd)
+GEN_FALSE_TRANS(tlbwr)
+GEN_FALSE_TRANS(tlbfill)
+GEN_FALSE_TRANS(tlbclr)
+GEN_FALSE_TRANS(tlbflush)
+GEN_FALSE_TRANS(invtlb)
#else
@@ -223,4 +230,109 @@ static bool trans_iocsrwr_d(DisasContext *ctx, arg_iocsrwr_d *a)
gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(8));
return true;
}
+
+static bool trans_tlbsrch(DisasContext *ctx, arg_tlbsrch *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_tlbsrch(cpu_env);
+ return true;
+}
+
+static bool trans_tlbrd(DisasContext *ctx, arg_tlbrd *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_tlbrd(cpu_env);
+ return true;
+}
+
+static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_tlbwr(cpu_env);
+
+ if (ctx->mem_idx != MMU_DA_IDX) {
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXIT;
+ }
+ return true;
+}
+
+static bool trans_tlbfill(DisasContext *ctx, arg_tlbfill *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_tlbfill(cpu_env);
+
+ if (ctx->mem_idx != MMU_DA_IDX) {
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXIT;
+ }
+ return true;
+}
+
+static bool trans_tlbclr(DisasContext *ctx, arg_tlbclr *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_tlbclr(cpu_env);
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXIT;
+ return true;
+}
+
+static bool trans_tlbflush(DisasContext *ctx, arg_tlbflush *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_tlbflush(cpu_env);
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXIT;
+ return true;
+}
+
+static bool trans_invtlb(DisasContext *ctx, arg_invtlb *a)
+{
+ TCGv rj = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv rk = gpr_src(ctx, a->rk, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+
+ switch (a->imm) {
+ case 0:
+ case 1:
+ gen_helper_invtlb_all(cpu_env);
+ break;
+ case 2:
+ gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(1));
+ break;
+ case 3:
+ gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(0));
+ break;
+ case 4:
+ gen_helper_invtlb_all_asid(cpu_env, rj);
+ break;
+ case 5:
+ gen_helper_invtlb_page_asid(cpu_env, rj, rk);
+ break;
+ case 6:
+ gen_helper_invtlb_page_asid_or_g(cpu_env, rj, rk);
+ break;
+ default:
+ return false;
+ }
+ ctx->base.is_jmp = DISAS_STOP;
+ return true;
+}
+
#endif
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 9a43f288c3..6f2a814195 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -47,6 +47,8 @@
&rr_offs rj rd offs
&r_csr rd csr
&rr_csr rd rj csr
+&empty
+&i_rr imm rj rk
#
# Formats
@@ -89,6 +91,8 @@
@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
@r_csr .... .... csr:14 ..... rd:5 &r_csr
@rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
+@empty .... ........ ..... ..... ..... ..... &empty
+@i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr
#
# Fixed point arithmetic operation instruction
@@ -462,3 +466,10 @@ iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr
iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr
iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr
iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr
+tlbsrch 0000 01100100 10000 01010 00000 00000 @empty
+tlbrd 0000 01100100 10000 01011 00000 00000 @empty
+tlbwr 0000 01100100 10000 01100 00000 00000 @empty
+tlbfill 0000 01100100 10000 01101 00000 00000 @empty
+tlbclr 0000 01100100 10000 01000 00000 00000 @empty
+tlbflush 0000 01100100 10000 01001 00000 00000 @empty
+invtlb 0000 01100100 10011 ..... ..... ..... @i_rr
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index ff72ac4eaf..53dd70de17 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -7,9 +7,11 @@
*/
#include "qemu/osdep.h"
+#include "qemu/guest-random.h"
#include "cpu.h"
#include "internals.h"
+#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
@@ -281,6 +283,368 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
}
}
+static void cpu_loongarch_tlb_flush(CPULoongArchState *env)
+{
+ /* Flush qemu's TLB and discard all shadowed entries. */
+ tlb_flush(env_cpu(env));
+}
+
+static void loongarch_invalidate_tlb_entry(CPULoongArchState *env,
+ int index)
+{
+ target_ulong addr, mask, pagesize;
+ uint8_t tlb_ps;
+ LoongArchTLB *tlb = &env->tlb[index];
+
+ int mmu_idx = cpu_mmu_index(env, false);
+ uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
+ uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
+ uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
+
+ if (index >= LOONGARCH_STLB) {
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ } else {
+ tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ }
+ pagesize = 1 << tlb_ps;
+ mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
+
+ if (tlb_v0) {
+ addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; /* even */
+ tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
+ mmu_idx, TARGET_LONG_BITS);
+ }
+
+ if (tlb_v1) {
+ addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & pagesize; /* odd */
+ tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
+ mmu_idx, TARGET_LONG_BITS);
+ }
+}
+
+static void loongarch_invalidate_tlb(CPULoongArchState *env, int index)
+{
+ LoongArchTLB *tlb;
+ uint16_t csr_asid, tlb_asid, tlb_g;
+
+ csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
+ tlb = &env->tlb[index];
+ tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ if (tlb_g == 0 && tlb_asid != csr_asid) {
+ return;
+ }
+ loongarch_invalidate_tlb_entry(env, index);
+}
+
+static void loongarch_fill_tlb_entry(CPULoongArchState *env, int index)
+{
+ LoongArchTLB *tlb = &env->tlb[index];
+ uint64_t lo0, lo1, csr_vppn;
+ uint16_t csr_asid;
+ uint8_t csr_ps;
+
+ if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
+ csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
+ csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
+ lo0 = env->CSR_TLBRELO0;
+ lo1 = env->CSR_TLBRELO1;
+ } else {
+ csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
+ csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
+ lo0 = env->CSR_TLBELO0;
+ lo1 = env->CSR_TLBELO1;
+ }
+
+ if (csr_ps == 0) {
+ qemu_log_mask(CPU_LOG_MMU, "page size is 0\n");
+ }
+
+ /* Only mtlb has the ps fields */
+ if (index >= LOONGARCH_STLB) {
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
+ }
+
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn);
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1);
+ csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid);
+
+ tlb->tlb_entry0 = lo0;
+ tlb->tlb_entry1 = lo1;
+}
+
+/* Return random value in [low, high] */
+static uint32_t cpu_loongarch_get_random_loongarch_tlb(uint32_t low,
+ uint32_t high)
+{
+ uint32_t val;
+
+ qemu_guest_getrandom_nofail(&val, sizeof(val));
+ return val % (high - low + 1) + low;
+}
+
+void helper_tlbsrch(CPULoongArchState *env)
+{
+ int index, match;
+
+ if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
+ match = loongarch_tlb_search(env, env->CSR_TLBREHI, &index);
+ } else {
+ match = loongarch_tlb_search(env, env->CSR_TLBEHI, &index);
+ }
+
+ if (match) {
+ env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX, index);
+ env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
+ return;
+ }
+
+ env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
+}
+
+void helper_tlbrd(CPULoongArchState *env)
+{
+ LoongArchTLB *tlb;
+ int index;
+ uint8_t tlb_ps, tlb_e;
+
+ index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+ tlb = &env->tlb[index];
+
+ if (index >= LOONGARCH_STLB) {
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ } else {
+ tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ }
+ tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+
+ if (!tlb_e) {
+ /* Invalid TLB entry */
+ env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
+ env->CSR_ASID = FIELD_DP64(env->CSR_ASID, CSR_ASID, ASID, 0);
+ env->CSR_TLBEHI = 0;
+ env->CSR_TLBELO0 = 0;
+ env->CSR_TLBELO1 = 0;
+ env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, PS, 0);
+ } else {
+ /* Valid TLB entry */
+ env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
+ env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX,
+ PS, (tlb_ps & 0x3f));
+ env->CSR_TLBEHI = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) <<
+ R_TLB_MISC_VPPN_SHIFT;
+ env->CSR_TLBELO0 = tlb->tlb_entry0;
+ env->CSR_TLBELO1 = tlb->tlb_entry1;
+ }
+}
+
+void helper_tlbwr(CPULoongArchState *env)
+{
+ int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+
+ loongarch_invalidate_tlb(env, index);
+
+ if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
+ env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
+ TLB_MISC, E, 0);
+ return;
+ }
+
+ loongarch_fill_tlb_entry(env, index);
+}
+
+void helper_tlbfill(CPULoongArchState *env)
+{
+ uint64_t address, entryhi;
+ int index, set, stlb_idx;
+ uint16_t pagesize, stlb_ps;
+
+ if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
+ entryhi = env->CSR_TLBREHI;
+ pagesize = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
+ } else {
+ entryhi = env->CSR_TLBEHI;
+ pagesize = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
+ }
+
+ stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+
+ if (pagesize == stlb_ps) {
+ /* Only write into STLB bit [47:13] */
+ address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
+
+ /* Choose one set ramdomly */
+ set = cpu_loongarch_get_random_loongarch_tlb(0, 7);
+
+ /* Index in one set */
+ stlb_idx = (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */
+
+ index = set * 256 + stlb_idx;
+ } else {
+ /* Only write into MTLB */
+ index = cpu_loongarch_get_random_loongarch_tlb(
+ LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
+ }
+
+ loongarch_invalidate_tlb(env, index);
+ loongarch_fill_tlb_entry(env, index);
+}
+
+void helper_tlbclr(CPULoongArchState *env)
+{
+ LoongArchTLB *tlb;
+ int i, index;
+ uint16_t csr_asid, tlb_asid, tlb_g;
+
+ csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
+ index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+
+ if (index < LOONGARCH_STLB) {
+ /* STLB. One line per operation */
+ for (i = 0; i < 8; i++) {
+ tlb = &env->tlb[i * 256 + (index % 256)];
+ tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ if (!tlb_g && tlb_asid == csr_asid) {
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
+ }
+ }
+ } else if (index < LOONGARCH_TLB_MAX) {
+ /* MTLB. All entries */
+ for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; i++) {
+ tlb = &env->tlb[i];
+ tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ if (!tlb_g && tlb_asid == csr_asid) {
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
+ }
+ }
+ }
+
+ cpu_loongarch_tlb_flush(env);
+}
+
+void helper_tlbflush(CPULoongArchState *env)
+{
+ int i, index;
+
+ index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+
+ if (index < LOONGARCH_STLB) {
+ /* STLB. One line per operation */
+ for (i = 0; i < 8; i++) {
+ int index = i * 256 + (index % 256);
+ env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
+ TLB_MISC, E, 0);
+ }
+ } else if (index < LOONGARCH_TLB_MAX) {
+ /* MTLB. All entries */
+ for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; i++) {
+ env->tlb[i].tlb_misc = FIELD_DP64(env->tlb[i].tlb_misc,
+ TLB_MISC, E, 0);
+ }
+ }
+
+ cpu_loongarch_tlb_flush(env);
+}
+
+void helper_invtlb_all(CPULoongArchState *env)
+{
+ for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
+ env->tlb[i].tlb_misc = FIELD_DP64(env->tlb[i].tlb_misc,
+ TLB_MISC, E, 0);
+ }
+ cpu_loongarch_tlb_flush(env);
+}
+
+void helper_invtlb_all_g(CPULoongArchState *env, uint32_t g)
+{
+ for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
+ LoongArchTLB *tlb = &env->tlb[i];
+ uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+
+ if (tlb_g == g) {
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
+ }
+ }
+ cpu_loongarch_tlb_flush(env);
+}
+
+void helper_invtlb_all_asid(CPULoongArchState *env, target_ulong info)
+{
+ uint16_t asid = info & 0x3ff;
+
+ for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
+ LoongArchTLB *tlb = &env->tlb[i];
+ uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+
+ if (!tlb_g && (tlb_asid == asid)) {
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
+ }
+ }
+ cpu_loongarch_tlb_flush(env);
+}
+
+void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
+ target_ulong addr)
+{
+ uint16_t asid = info & 0x3ff;
+
+ for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
+ LoongArchTLB *tlb = &env->tlb[i];
+ uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ uint64_t vpn, tlb_vppn;
+ uint8_t tlb_ps, compare_shift;
+
+ if (i >= LOONGARCH_STLB) {
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ } else {
+ tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ }
+ tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
+ vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
+ compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
+
+ if (!tlb_g && (tlb_asid == asid) &&
+ (vpn == (tlb_vppn >> compare_shift))) {
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
+ }
+ }
+ cpu_loongarch_tlb_flush(env);
+}
+
+void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
+ target_ulong info, target_ulong addr)
+{
+ uint16_t asid = info & 0x3ff;
+
+ for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
+ LoongArchTLB *tlb = &env->tlb[i];
+ uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ uint64_t vpn, tlb_vppn;
+ uint8_t tlb_ps, compare_shift;
+
+ if (i >= LOONGARCH_STLB) {
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ } else {
+ tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ }
+ tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
+ vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
+ compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
+
+ if ((tlb_g || (tlb_asid == asid)) &&
+ (vpn == (tlb_vppn >> compare_shift))) {
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
+ }
+ }
+ cpu_loongarch_tlb_flush(env);
+}
+
void loongarch_mmu_init(CPULoongArchState *env)
{
/* For 16KB, ps = 14, compare the bit [47:15] */
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 09/30] target/loongarch: Add TLB instruction support
2022-01-08 9:13 ` [RFC PATCH v4 09/30] target/loongarch: Add TLB instruction support Xiaojuan Yang
@ 2022-01-09 9:26 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:26 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This includes:
> - TLBSRCH
> - TLBRD
> - TLBWR
> - TLBFILL
> - TLBCLR
> - TLBFLUSH
> - INVTLB
>
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/disas.c | 17 +
> target/loongarch/helper.h | 12 +
> target/loongarch/insn_trans/trans_core.c.inc | 112 ++++++
> target/loongarch/insns.decode | 11 +
> target/loongarch/tlb_helper.c | 364 +++++++++++++++++++
> 5 files changed, 516 insertions(+)
>
> diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
> index cbb264a318..483270f331 100644
> --- a/target/loongarch/disas.c
> +++ b/target/loongarch/disas.c
> @@ -216,6 +216,16 @@ static void output_rr_csr(DisasContext *ctx, arg_rr_csr *a,
> output(ctx, mnemonic, "r%d, r%d, %d", a->rd, a->rj, a->csr);
> }
>
> +static void output_empty(DisasContext *ctx, arg_empty *a,
> + const char *mnemonic)
> +{
Isn't this missing an output altogether so you don't even have mnemonic
output?
> +}
> +
> +static void output_i_rr(DisasContext *ctx, arg_i_rr *a, const char *mnemonic)
> +{
> + output(ctx, mnemonic, "%d, r%d, r%d", a->imm, a->rj, a->rk);
> +}
> +
> #define INSN(insn, type) \
> static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
> { \
> @@ -539,6 +549,13 @@ INSN(iocsrwr_b, rr)
> INSN(iocsrwr_h, rr)
> INSN(iocsrwr_w, rr)
> INSN(iocsrwr_d, rr)
> +INSN(tlbsrch, empty)
> +INSN(tlbrd, empty)
> +INSN(tlbwr, empty)
> +INSN(tlbfill, empty)
> +INSN(tlbclr, empty)
> +INSN(tlbflush, empty)
> +INSN(invtlb, i_rr)
>
> #define output_fcmp(C, PREFIX, SUFFIX) \
> { \
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index 1bcd082858..97af7ac8aa 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -100,4 +100,16 @@ DEF_HELPER_3(csr_wrq, i64, env, tl, i64)
> DEF_HELPER_4(csr_xchgq, i64, env, tl, tl, i64)
> DEF_HELPER_3(iocsr_read, i64, env, tl, i32)
> DEF_HELPER_4(iocsr_write, void, env, tl, tl, i32)
> +
> +DEF_HELPER_1(tlbwr, void, env)
> +DEF_HELPER_1(tlbfill, void, env)
> +DEF_HELPER_1(tlbsrch, void, env)
> +DEF_HELPER_1(tlbrd, void, env)
> +DEF_HELPER_1(tlbclr, void, env)
> +DEF_HELPER_1(tlbflush, void, env)
> +DEF_HELPER_1(invtlb_all, void, env)
> +DEF_HELPER_2(invtlb_all_g, void, env, i32)
> +DEF_HELPER_2(invtlb_all_asid, void, env, tl)
> +DEF_HELPER_3(invtlb_page_asid, void, env, tl, tl)
> +DEF_HELPER_3(invtlb_page_asid_or_g, void, env, tl, tl)
> #endif /* !CONFIG_USER_ONLY */
> diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
> index 592d2a339e..5a8e9e0643 100644
> --- a/target/loongarch/insn_trans/trans_core.c.inc
> +++ b/target/loongarch/insn_trans/trans_core.c.inc
> @@ -28,6 +28,13 @@ GEN_FALSE_TRANS(iocsrwr_b)
> GEN_FALSE_TRANS(iocsrwr_h)
> GEN_FALSE_TRANS(iocsrwr_w)
> GEN_FALSE_TRANS(iocsrwr_d)
> +GEN_FALSE_TRANS(tlbsrch)
> +GEN_FALSE_TRANS(tlbrd)
> +GEN_FALSE_TRANS(tlbwr)
> +GEN_FALSE_TRANS(tlbfill)
> +GEN_FALSE_TRANS(tlbclr)
> +GEN_FALSE_TRANS(tlbflush)
> +GEN_FALSE_TRANS(invtlb)
>
> #else
>
> @@ -223,4 +230,109 @@ static bool trans_iocsrwr_d(DisasContext *ctx, arg_iocsrwr_d *a)
> gen_helper_iocsr_write(cpu_env, addr, val, tcg_constant_i32(8));
> return true;
> }
> +
> +static bool trans_tlbsrch(DisasContext *ctx, arg_tlbsrch *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_tlbsrch(cpu_env);
> + return true;
> +}
> +
> +static bool trans_tlbrd(DisasContext *ctx, arg_tlbrd *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_tlbrd(cpu_env);
> + return true;
> +}
> +
> +static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_tlbwr(cpu_env);
> +
> + if (ctx->mem_idx != MMU_DA_IDX) {
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXIT;
> + }
> + return true;
> +}
> +
> +static bool trans_tlbfill(DisasContext *ctx, arg_tlbfill *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_tlbfill(cpu_env);
> +
> + if (ctx->mem_idx != MMU_DA_IDX) {
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXIT;
> + }
> + return true;
> +}
> +
> +static bool trans_tlbclr(DisasContext *ctx, arg_tlbclr *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_tlbclr(cpu_env);
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXIT;
> + return true;
> +}
> +
> +static bool trans_tlbflush(DisasContext *ctx, arg_tlbflush *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_tlbflush(cpu_env);
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXIT;
> + return true;
> +}
> +
> +static bool trans_invtlb(DisasContext *ctx, arg_invtlb *a)
> +{
> + TCGv rj = gpr_src(ctx, a->rj, EXT_NONE);
> + TCGv rk = gpr_src(ctx, a->rk, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> +
> + switch (a->imm) {
> + case 0:
> + case 1:
> + gen_helper_invtlb_all(cpu_env);
> + break;
> + case 2:
> + gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(1));
> + break;
> + case 3:
> + gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(0));
> + break;
> + case 4:
> + gen_helper_invtlb_all_asid(cpu_env, rj);
> + break;
> + case 5:
> + gen_helper_invtlb_page_asid(cpu_env, rj, rk);
> + break;
> + case 6:
> + gen_helper_invtlb_page_asid_or_g(cpu_env, rj, rk);
> + break;
> + default:
> + return false;
> + }
> + ctx->base.is_jmp = DISAS_STOP;
> + return true;
> +}
> +
> #endif
> diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
> index 9a43f288c3..6f2a814195 100644
> --- a/target/loongarch/insns.decode
> +++ b/target/loongarch/insns.decode
> @@ -47,6 +47,8 @@
> &rr_offs rj rd offs
> &r_csr rd csr
> &rr_csr rd rj csr
> +&empty
> +&i_rr imm rj rk
>
> #
> # Formats
> @@ -89,6 +91,8 @@
> @rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
> @r_csr .... .... csr:14 ..... rd:5 &r_csr
> @rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
> +@empty .... ........ ..... ..... ..... ..... &empty
> +@i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr
>
> #
> # Fixed point arithmetic operation instruction
> @@ -462,3 +466,10 @@ iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr
> iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr
> iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr
> iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr
> +tlbsrch 0000 01100100 10000 01010 00000 00000 @empty
> +tlbrd 0000 01100100 10000 01011 00000 00000 @empty
> +tlbwr 0000 01100100 10000 01100 00000 00000 @empty
> +tlbfill 0000 01100100 10000 01101 00000 00000 @empty
> +tlbclr 0000 01100100 10000 01000 00000 00000 @empty
> +tlbflush 0000 01100100 10000 01001 00000 00000 @empty
> +invtlb 0000 01100100 10011 ..... ..... ..... @i_rr
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> index ff72ac4eaf..53dd70de17 100644
> --- a/target/loongarch/tlb_helper.c
> +++ b/target/loongarch/tlb_helper.c
> @@ -7,9 +7,11 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/guest-random.h"
>
> #include "cpu.h"
> #include "internals.h"
> +#include "exec/helper-proto.h"
> #include "exec/exec-all.h"
> #include "exec/cpu_ldst.h"
> #include "exec/log.h"
> @@ -281,6 +283,368 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
> }
> }
>
> +static void cpu_loongarch_tlb_flush(CPULoongArchState *env)
> +{
> + /* Flush qemu's TLB and discard all shadowed entries. */
> + tlb_flush(env_cpu(env));
> +}
Only MIPS defines a function like this (and you seem to have copied the
MIPS code, cpu_mips_tlb_flush, the comment is identical), other targets
just write "tlb_flush(env_cpu(env))" everywhere. Do we really need such
a thin wrapper for sake of similarity with MIPS?
> +
> +static void loongarch_invalidate_tlb_entry(CPULoongArchState *env,
> + int index)
> +{
> + target_ulong addr, mask, pagesize;
> + uint8_t tlb_ps;
> + LoongArchTLB *tlb = &env->tlb[index];
> +
> + int mmu_idx = cpu_mmu_index(env, false);
> + uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
> + uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
> + uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> +
> + if (index >= LOONGARCH_STLB) {
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> + } else {
> + tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> + }
> + pagesize = 1 << tlb_ps;
> + mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
> +
> + if (tlb_v0) {
> + addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; /* even */
> + tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
> + mmu_idx, TARGET_LONG_BITS);
> + }
> +
> + if (tlb_v1) {
> + addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & pagesize; /* odd */
> + tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
> + mmu_idx, TARGET_LONG_BITS);
> + }
> +}
> +
> +static void loongarch_invalidate_tlb(CPULoongArchState *env, int index)
> +{
> + LoongArchTLB *tlb;
> + uint16_t csr_asid, tlb_asid, tlb_g;
> +
> + csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
> + tlb = &env->tlb[index];
> + tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> + tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> + if (tlb_g == 0 && tlb_asid != csr_asid) {
> + return;
> + }
> + loongarch_invalidate_tlb_entry(env, index);
> +}
> +
> +static void loongarch_fill_tlb_entry(CPULoongArchState *env, int index)
> +{
> + LoongArchTLB *tlb = &env->tlb[index];
> + uint64_t lo0, lo1, csr_vppn;
> + uint16_t csr_asid;
> + uint8_t csr_ps;
> +
> + if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
> + csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
> + csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
> + lo0 = env->CSR_TLBRELO0;
> + lo1 = env->CSR_TLBRELO1;
> + } else {
> + csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
> + csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
> + lo0 = env->CSR_TLBELO0;
> + lo1 = env->CSR_TLBELO1;
> + }
> +
> + if (csr_ps == 0) {
> + qemu_log_mask(CPU_LOG_MMU, "page size is 0\n");
> + }
> +
> + /* Only mtlb has the ps fields */
"MTLB"
> + if (index >= LOONGARCH_STLB) {
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
> + }
> +
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn);
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1);
> + csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid);
> +
> + tlb->tlb_entry0 = lo0;
> + tlb->tlb_entry1 = lo1;
> +}
> +
> +/* Return random value in [low, high] */
"Return an random value"
> +static uint32_t cpu_loongarch_get_random_loongarch_tlb(uint32_t low,
> + uint32_t high)
> +{
> + uint32_t val;
> +
> + qemu_guest_getrandom_nofail(&val, sizeof(val));
> + return val % (high - low + 1) + low;
> +}
> +
> +void helper_tlbsrch(CPULoongArchState *env)
> +{
> + int index, match;
> +
> + if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
> + match = loongarch_tlb_search(env, env->CSR_TLBREHI, &index);
> + } else {
> + match = loongarch_tlb_search(env, env->CSR_TLBEHI, &index);
> + }
> +
> + if (match) {
> + env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX, index);
> + env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
> + return;
> + }
> +
> + env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
> +}
> +
> +void helper_tlbrd(CPULoongArchState *env)
> +{
> + LoongArchTLB *tlb;
> + int index;
> + uint8_t tlb_ps, tlb_e;
> +
> + index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> + tlb = &env->tlb[index];
> +
> + if (index >= LOONGARCH_STLB) {
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> + } else {
> + tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> + }
> + tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
> +
> + if (!tlb_e) {
> + /* Invalid TLB entry */
> + env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1);
> + env->CSR_ASID = FIELD_DP64(env->CSR_ASID, CSR_ASID, ASID, 0);
> + env->CSR_TLBEHI = 0;
> + env->CSR_TLBELO0 = 0;
> + env->CSR_TLBELO1 = 0;
> + env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, PS, 0);
> + } else {
> + /* Valid TLB entry */
> + env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0);
> + env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX,
> + PS, (tlb_ps & 0x3f));
> + env->CSR_TLBEHI = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) <<
> + R_TLB_MISC_VPPN_SHIFT;
> + env->CSR_TLBELO0 = tlb->tlb_entry0;
> + env->CSR_TLBELO1 = tlb->tlb_entry1;
> + }
> +}
> +
> +void helper_tlbwr(CPULoongArchState *env)
> +{
> + int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> +
> + loongarch_invalidate_tlb(env, index);
> +
> + if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
> + env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
> + TLB_MISC, E, 0);
> + return;
> + }
> +
> + loongarch_fill_tlb_entry(env, index);
> +}
> +
> +void helper_tlbfill(CPULoongArchState *env)
> +{
> + uint64_t address, entryhi;
> + int index, set, stlb_idx;
> + uint16_t pagesize, stlb_ps;
> +
> + if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
> + entryhi = env->CSR_TLBREHI;
> + pagesize = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
> + } else {
> + entryhi = env->CSR_TLBEHI;
> + pagesize = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
> + }
> +
> + stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> +
> + if (pagesize == stlb_ps) {
> + /* Only write into STLB bit [47:13] */
"bits"
> + address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
> +
> + /* Choose one set ramdomly */
> + set = cpu_loongarch_get_random_loongarch_tlb(0, 7);
> +
> + /* Index in one set */
> + stlb_idx = (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */
> +
> + index = set * 256 + stlb_idx;
> + } else {
> + /* Only write into MTLB */
> + index = cpu_loongarch_get_random_loongarch_tlb(
> + LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
> + }
> +
> + loongarch_invalidate_tlb(env, index);
> + loongarch_fill_tlb_entry(env, index);
> +}
> +
> +void helper_tlbclr(CPULoongArchState *env)
> +{
> + LoongArchTLB *tlb;
> + int i, index;
> + uint16_t csr_asid, tlb_asid, tlb_g;
> +
> + csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
> + index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> +
> + if (index < LOONGARCH_STLB) {
> + /* STLB. One line per operation */
> + for (i = 0; i < 8; i++) {
> + tlb = &env->tlb[i * 256 + (index % 256)];
> + tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> + tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> + if (!tlb_g && tlb_asid == csr_asid) {
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
> + }
> + }
> + } else if (index < LOONGARCH_TLB_MAX) {
> + /* MTLB. All entries */
"Operate on all entries"?
> + for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; i++) {
> + tlb = &env->tlb[i];
> + tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> + tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> + if (!tlb_g && tlb_asid == csr_asid) {
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
> + }
> + }
> + }
> +
> + cpu_loongarch_tlb_flush(env);
> +}
> +
> +void helper_tlbflush(CPULoongArchState *env)
> +{
> + int i, index;
> +
> + index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> +
> + if (index < LOONGARCH_STLB) {
> + /* STLB. One line per operation */
> + for (i = 0; i < 8; i++) {
> + int index = i * 256 + (index % 256);
> + env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
> + TLB_MISC, E, 0);
> + }
> + } else if (index < LOONGARCH_TLB_MAX) {
> + /* MTLB. All entries */
Ditto.
> + for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; i++) {
> + env->tlb[i].tlb_misc = FIELD_DP64(env->tlb[i].tlb_misc,
> + TLB_MISC, E, 0);
> + }
> + }
> +
> + cpu_loongarch_tlb_flush(env);
> +}
> +
> +void helper_invtlb_all(CPULoongArchState *env)
> +{
> + for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
> + env->tlb[i].tlb_misc = FIELD_DP64(env->tlb[i].tlb_misc,
> + TLB_MISC, E, 0);
> + }
> + cpu_loongarch_tlb_flush(env);
> +}
> +
> +void helper_invtlb_all_g(CPULoongArchState *env, uint32_t g)
> +{
> + for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
> + LoongArchTLB *tlb = &env->tlb[i];
> + uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> +
> + if (tlb_g == g) {
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
> + }
> + }
> + cpu_loongarch_tlb_flush(env);
> +}
> +
> +void helper_invtlb_all_asid(CPULoongArchState *env, target_ulong info)
> +{
> + uint16_t asid = info & 0x3ff;
> +
> + for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
> + LoongArchTLB *tlb = &env->tlb[i];
> + uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> + uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> +
> + if (!tlb_g && (tlb_asid == asid)) {
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
> + }
> + }
> + cpu_loongarch_tlb_flush(env);
> +}
> +
> +void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
> + target_ulong addr)
> +{
> + uint16_t asid = info & 0x3ff;
> +
> + for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
> + LoongArchTLB *tlb = &env->tlb[i];
> + uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> + uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> + uint64_t vpn, tlb_vppn;
> + uint8_t tlb_ps, compare_shift;
> +
> + if (i >= LOONGARCH_STLB) {
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> + } else {
> + tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> + }
> + tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> + vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
> + compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> +
> + if (!tlb_g && (tlb_asid == asid) &&
> + (vpn == (tlb_vppn >> compare_shift))) {
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
> + }
> + }
> + cpu_loongarch_tlb_flush(env);
> +}
> +
> +void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
> + target_ulong info, target_ulong addr)
> +{
> + uint16_t asid = info & 0x3ff;
This is hardcoded to be 10-bits-wide, but according to the manuals we
have plenty of reserved bits above the ASID field, so do we want to
define the mask in a header file for easier maintenance afterwards?
> +
> + for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
> + LoongArchTLB *tlb = &env->tlb[i];
> + uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> + uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> + uint64_t vpn, tlb_vppn;
> + uint8_t tlb_ps, compare_shift;
> +
> + if (i >= LOONGARCH_STLB) {
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> + } else {
> + tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> + }
> + tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> + vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
> + compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> +
> + if ((tlb_g || (tlb_asid == asid)) &&
> + (vpn == (tlb_vppn >> compare_shift))) {
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
> + }
> + }
> + cpu_loongarch_tlb_flush(env);
> +}
> +
> void loongarch_mmu_init(CPULoongArchState *env)
> {
> /* For 16KB, ps = 14, compare the bit [47:15] */
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 10/30] target/loongarch: Add other core instructions support
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (8 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 09/30] target/loongarch: Add TLB instruction support Xiaojuan Yang
@ 2022-01-08 9:13 ` Xiaojuan Yang
2022-01-09 9:26 ` WANG Xuerui
2022-01-08 9:14 ` [RFC PATCH v4 11/30] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
` (21 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:13 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.h | 2 +
target/loongarch/disas.c | 17 ++++
target/loongarch/helper.h | 4 +
target/loongarch/insn_trans/trans_core.c.inc | 74 +++++++++++++++++
target/loongarch/insns.decode | 11 +++
target/loongarch/internals.h | 5 ++
target/loongarch/op_helper.c | 43 ++++++++++
target/loongarch/tlb_helper.c | 87 ++++++++++++++++++++
8 files changed, 243 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ddb69ffecf..2d5bae1af4 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -442,6 +442,8 @@ enum {
EXCP_LAST = EXCP_FPE,
};
+#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
+
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 483270f331..516866c2d3 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -226,6 +226,17 @@ static void output_i_rr(DisasContext *ctx, arg_i_rr *a, const char *mnemonic)
output(ctx, mnemonic, "%d, r%d, r%d", a->imm, a->rj, a->rk);
}
+static void output_cop_r_i(DisasContext *ctx, arg_cop_r_i *a,
+ const char *mnemonic)
+{
+ output(ctx, mnemonic, "%d, r%d, %d", a->cop, a->rj, a->imm);
+}
+
+static void output_j_i(DisasContext *ctx, arg_j_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, %d", a->rj, a->imm);
+}
+
#define INSN(insn, type) \
static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
{ \
@@ -556,6 +567,12 @@ INSN(tlbfill, empty)
INSN(tlbclr, empty)
INSN(tlbflush, empty)
INSN(invtlb, i_rr)
+INSN(cacop, cop_r_i)
+INSN(lddir, rr_i)
+INSN(ldpte, j_i)
+INSN(ertn, empty)
+INSN(idle, i)
+INSN(dbcl, i)
#define output_fcmp(C, PREFIX, SUFFIX) \
{ \
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 97af7ac8aa..c916f2650b 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -112,4 +112,8 @@ DEF_HELPER_2(invtlb_all_g, void, env, i32)
DEF_HELPER_2(invtlb_all_asid, void, env, tl)
DEF_HELPER_3(invtlb_page_asid, void, env, tl, tl)
DEF_HELPER_3(invtlb_page_asid_or_g, void, env, tl, tl)
+DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
+DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
+DEF_HELPER_1(ertn, void, env)
+DEF_HELPER_1(idle, void, env)
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
index 5a8e9e0643..834ffc03d5 100644
--- a/target/loongarch/insn_trans/trans_core.c.inc
+++ b/target/loongarch/insn_trans/trans_core.c.inc
@@ -35,6 +35,12 @@ GEN_FALSE_TRANS(tlbfill)
GEN_FALSE_TRANS(tlbclr)
GEN_FALSE_TRANS(tlbflush)
GEN_FALSE_TRANS(invtlb)
+GEN_FALSE_TRANS(cacop)
+GEN_FALSE_TRANS(ldpte)
+GEN_FALSE_TRANS(lddir)
+GEN_FALSE_TRANS(ertn)
+GEN_FALSE_TRANS(dbcl)
+GEN_FALSE_TRANS(idle)
#else
@@ -335,4 +341,72 @@ static bool trans_invtlb(DisasContext *ctx, arg_invtlb *a)
return true;
}
+static bool trans_cacop(DisasContext *ctx, arg_cacop *a)
+{
+ /* Treat the cacop as a nop */
+ if (check_plv(ctx)) {
+ return false;
+ }
+ return true;
+}
+
+static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a)
+{
+ TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_ldpte(cpu_env, src1, tcg_constant_tl(a->imm), mem_idx);
+ return true;
+}
+
+static bool trans_lddir(DisasContext *ctx, arg_lddir *a)
+{
+ TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx);
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_lddir(dest, cpu_env, src, tcg_constant_tl(a->imm), mem_idx);
+ return true;
+}
+
+static bool trans_ertn(DisasContext *ctx, arg_ertn *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+ gen_helper_ertn(cpu_env);
+ ctx->base.is_jmp = DISAS_EXIT;
+ return true;
+}
+
+static bool trans_dbcl(DisasContext *ctx, arg_dbcl *a)
+{
+ /*
+ * XXX: not clear which exception should be raised
+ * when in debug mode...
+ */
+ if (check_plv(ctx)) {
+ return false;
+ }
+ generate_exception(ctx, EXCCODE_DBP);
+ return true;
+}
+
+static bool trans_idle(DisasContext *ctx, arg_idle *a)
+{
+ if (check_plv(ctx)) {
+ return false;
+ }
+
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
+ gen_helper_idle(cpu_env);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
#endif
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 6f2a814195..3fdc6e148c 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -49,6 +49,8 @@
&rr_csr rd rj csr
&empty
&i_rr imm rj rk
+&cop_r_i cop rj imm
+&j_i rj imm
#
# Formats
@@ -60,6 +62,7 @@
@r_i20 .... ... imm:s20 rd:5 &r_i
@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
+@rr_ui8 .. ........ .... imm:8 rj:5 rd:5 &rr_i
@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
@rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
@@ -93,6 +96,8 @@
@rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
@empty .... ........ ..... ..... ..... ..... &empty
@i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr
+@cop_r_i .... ...... imm:s12 rj:5 cop:5 &cop_r_i
+@j_i .... ........ .. imm:8 rj:5 ..... &j_i
#
# Fixed point arithmetic operation instruction
@@ -473,3 +478,9 @@ tlbfill 0000 01100100 10000 01101 00000 00000 @empty
tlbclr 0000 01100100 10000 01000 00000 00000 @empty
tlbflush 0000 01100100 10000 01001 00000 00000 @empty
invtlb 0000 01100100 10011 ..... ..... ..... @i_rr
+cacop 0000 011000 ............ ..... ..... @cop_r_i
+lddir 0000 01100100 00 ........ ..... ..... @rr_ui8
+ldpte 0000 01100100 01 ........ ..... 00000 @j_i
+ertn 0000 01100100 10000 01110 00000 00000 @empty
+idle 0000 01100100 10001 ............... @i15
+dbcl 0000 00000010 10101 ............... @i15
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index a5b81bdca3..7035cbd7d5 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -16,6 +16,11 @@
#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
+/* Global bit used for lddir/ldpte */
+#define LOONGARCH_PAGE_HUGE_SHIFT 6
+/* Global bit for huge page */
+#define LOONGARCH_HGLOBAL_SHIFT 12
+
void loongarch_translate_init(void);
void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index 48c25e5a9b..6f9742054a 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -91,3 +91,46 @@ target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
{
return rj > 21 ? 0 : env->cpucfg[rj];
}
+
+#ifndef CONFIG_USER_ONLY
+void helper_ertn(CPULoongArchState *env)
+{
+ uint64_t csr_pplv, csr_pie;
+ if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
+ csr_pplv = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV);
+ csr_pie = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE);
+
+ /* Clear Refill flag DA flag and set pc */
+ env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
+ env->pc = env->CSR_TLBRERA;
+ qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA 0x%lx\n",
+ __func__, env->CSR_TLBRERA);
+ } else {
+ csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
+ csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
+
+ /* set pc*/
+ env->pc = env->CSR_ERA;
+ qemu_log_mask(CPU_LOG_INT, "%s: ERA 0x%lx\n", __func__, env->CSR_ERA);
+ }
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, csr_pplv);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, csr_pie);
+
+ env->lladdr = 1;
+}
+
+void helper_idle(CPULoongArchState *env)
+{
+ CPUState *cs = env_cpu(env);
+
+ cs->halted = 1;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
+ /*
+ * Last instruction in the block, PC was updated before
+ * - no need to recover PC and icount
+ */
+ do_raise_exception(env, EXCP_HLT, 0);
+}
+#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 53dd70de17..a778ae8a66 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -688,3 +688,90 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
do_raise_exception(env, cs->exception_index, retaddr);
}
}
+
+target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
+ target_ulong level, uint32_t mem_idx)
+{
+ CPUState *cs = env_cpu(env);
+ target_ulong badvaddr, index, phys, ret;
+ int shift;
+ uint64_t dir1_base, dir1_width;
+ uint64_t dir3_base, dir3_width;
+ bool huge = (base >> LOONGARCH_PAGE_HUGE_SHIFT) & 0x1;
+
+ badvaddr = env->CSR_TLBRBADV;
+ base = base & TARGET_PHYS_MASK;
+
+ /* 0:8B, 1:16B, 2:32B, 3:64B */
+ shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH);
+ shift = (shift + 1) * 3;
+
+ if (huge) {
+ return base;
+ }
+ switch (level) {
+ case 1:
+ dir1_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_BASE);
+ dir1_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_WIDTH);
+ index = (badvaddr >> dir1_base) & ((1 << dir1_width) - 1);
+ break;
+ case 3:
+ dir3_base = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_BASE);
+ dir3_width = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_WIDTH);
+ index = (badvaddr >> dir3_base) & ((1 << dir3_width) - 1);
+ break;
+ default:
+ do_raise_exception(env, EXCCODE_INE, GETPC());
+ return 0;
+ }
+
+ phys = base | index << shift;
+ ret = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+ return ret;
+}
+
+void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
+ uint32_t mem_idx)
+{
+ CPUState *cs = env_cpu(env);
+ target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, ps, badv;
+ int shift;
+ bool huge = (base >> LOONGARCH_PAGE_HUGE_SHIFT) & 0x1;
+ uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
+ uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
+
+ base = base & TARGET_PHYS_MASK;
+
+ if (huge) {
+ /* Huge Page. base is paddr */
+ tmp0 = base ^ LOONGARCH_PAGE_HUGE_SHIFT;
+ /* Move Global bit */
+ tmp0 = (tmp0 >> LOONGARCH_HGLOBAL_SHIFT) << R_TLBENTRY_G_SHIFT |
+ (tmp0 & (~(1 << R_TLBENTRY_G_SHIFT)));
+ ps = ptbase + ptwidth - 1;
+ if (odd) {
+ tmp0 += (1 << ps);
+ }
+ } else {
+ /* 0:8B, 1:16B, 2:32B, 3:64B */
+ shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH);
+ shift = (shift + 1) * 3;
+ badv = env->CSR_TLBRBADV;
+
+ ptindex = (badv >> ptbase) & ((1 << ptwidth) - 1);
+ ptindex = ptindex & ~0x1; /* clear bit 0 */
+ ptoffset0 = ptindex << shift;
+ ptoffset1 = (ptindex + 1) << shift;
+
+ phys = base | (odd ? ptoffset1 : ptoffset0);
+ tmp0 = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+ ps = ptbase;
+ }
+
+ if (odd) {
+ env->CSR_TLBRELO1 = tmp0;
+ } else {
+ env->CSR_TLBRELO0 = tmp0;
+ }
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 10/30] target/loongarch: Add other core instructions support
2022-01-08 9:13 ` [RFC PATCH v4 10/30] target/loongarch: Add other core instructions support Xiaojuan Yang
@ 2022-01-09 9:26 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:26 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This includes:
> -CACOP
> -LDDIR
> -LDPTE
> -ERTN
> -DBCL
> -IDLE
Okay, now I got that the word "core" actually meant "privileged"... so
please adjust all occurrences of that word.
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/cpu.h | 2 +
> target/loongarch/disas.c | 17 ++++
> target/loongarch/helper.h | 4 +
> target/loongarch/insn_trans/trans_core.c.inc | 74 +++++++++++++++++
> target/loongarch/insns.decode | 11 +++
> target/loongarch/internals.h | 5 ++
> target/loongarch/op_helper.c | 43 ++++++++++
> target/loongarch/tlb_helper.c | 87 ++++++++++++++++++++
> 8 files changed, 243 insertions(+)
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index ddb69ffecf..2d5bae1af4 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -442,6 +442,8 @@ enum {
> EXCP_LAST = EXCP_FPE,
> };
>
> +#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
> +
> #define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
> #define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
> #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
> diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
> index 483270f331..516866c2d3 100644
> --- a/target/loongarch/disas.c
> +++ b/target/loongarch/disas.c
> @@ -226,6 +226,17 @@ static void output_i_rr(DisasContext *ctx, arg_i_rr *a, const char *mnemonic)
> output(ctx, mnemonic, "%d, r%d, r%d", a->imm, a->rj, a->rk);
> }
>
> +static void output_cop_r_i(DisasContext *ctx, arg_cop_r_i *a,
> + const char *mnemonic)
> +{
> + output(ctx, mnemonic, "%d, r%d, %d", a->cop, a->rj, a->imm);
> +}
> +
> +static void output_j_i(DisasContext *ctx, arg_j_i *a, const char *mnemonic)
> +{
> + output(ctx, mnemonic, "r%d, %d", a->rj, a->imm);
> +}
> +
> #define INSN(insn, type) \
> static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
> { \
> @@ -556,6 +567,12 @@ INSN(tlbfill, empty)
> INSN(tlbclr, empty)
> INSN(tlbflush, empty)
> INSN(invtlb, i_rr)
> +INSN(cacop, cop_r_i)
"cop" reads like "co-processor" while you may just mean "cache op"... as
the format is for this particular instruction only, you may as well just
name the format "cacop" and be done with it. (AFAIK it's called "cache"
before being renamed, allegedly for avoiding the MIPS name, but the new
name is miserable and unpronounceable, coming up with names is hard but
people should really try harder...)
> +INSN(lddir, rr_i)
> +INSN(ldpte, j_i)
> +INSN(ertn, empty)
> +INSN(idle, i)
> +INSN(dbcl, i)
>
> #define output_fcmp(C, PREFIX, SUFFIX) \
> { \
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index 97af7ac8aa..c916f2650b 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -112,4 +112,8 @@ DEF_HELPER_2(invtlb_all_g, void, env, i32)
> DEF_HELPER_2(invtlb_all_asid, void, env, tl)
> DEF_HELPER_3(invtlb_page_asid, void, env, tl, tl)
> DEF_HELPER_3(invtlb_page_asid_or_g, void, env, tl, tl)
> +DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
> +DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
> +DEF_HELPER_1(ertn, void, env)
> +DEF_HELPER_1(idle, void, env)
> #endif /* !CONFIG_USER_ONLY */
> diff --git a/target/loongarch/insn_trans/trans_core.c.inc b/target/loongarch/insn_trans/trans_core.c.inc
> index 5a8e9e0643..834ffc03d5 100644
> --- a/target/loongarch/insn_trans/trans_core.c.inc
> +++ b/target/loongarch/insn_trans/trans_core.c.inc
> @@ -35,6 +35,12 @@ GEN_FALSE_TRANS(tlbfill)
> GEN_FALSE_TRANS(tlbclr)
> GEN_FALSE_TRANS(tlbflush)
> GEN_FALSE_TRANS(invtlb)
> +GEN_FALSE_TRANS(cacop)
> +GEN_FALSE_TRANS(ldpte)
> +GEN_FALSE_TRANS(lddir)
> +GEN_FALSE_TRANS(ertn)
> +GEN_FALSE_TRANS(dbcl)
> +GEN_FALSE_TRANS(idle)
>
> #else
>
> @@ -335,4 +341,72 @@ static bool trans_invtlb(DisasContext *ctx, arg_invtlb *a)
> return true;
> }
>
> +static bool trans_cacop(DisasContext *ctx, arg_cacop *a)
> +{
> + /* Treat the cacop as a nop */
> + if (check_plv(ctx)) {
> + return false;
> + }
> + return true;
> +}
> +
> +static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a)
> +{
> + TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx);
> + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_ldpte(cpu_env, src1, tcg_constant_tl(a->imm), mem_idx);
> + return true;
> +}
> +
> +static bool trans_lddir(DisasContext *ctx, arg_lddir *a)
> +{
> + TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx);
> + TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> +
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_lddir(dest, cpu_env, src, tcg_constant_tl(a->imm), mem_idx);
> + return true;
> +}
> +
> +static bool trans_ertn(DisasContext *ctx, arg_ertn *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> + gen_helper_ertn(cpu_env);
> + ctx->base.is_jmp = DISAS_EXIT;
> + return true;
> +}
> +
> +static bool trans_dbcl(DisasContext *ctx, arg_dbcl *a)
> +{
> + /*
> + * XXX: not clear which exception should be raised
> + * when in debug mode...
> + */
Then confirm this with other people?
> + if (check_plv(ctx)) {
> + return false;
> + }
> + generate_exception(ctx, EXCCODE_DBP);
> + return true;
> +}
> +
> +static bool trans_idle(DisasContext *ctx, arg_idle *a)
> +{
> + if (check_plv(ctx)) {
> + return false;
> + }
> +
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
> + gen_helper_idle(cpu_env);
> + ctx->base.is_jmp = DISAS_NORETURN;
> + return true;
> +}
> #endif
> diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
> index 6f2a814195..3fdc6e148c 100644
> --- a/target/loongarch/insns.decode
> +++ b/target/loongarch/insns.decode
> @@ -49,6 +49,8 @@
> &rr_csr rd rj csr
> &empty
> &i_rr imm rj rk
> +&cop_r_i cop rj imm
> +&j_i rj imm
>
> #
> # Formats
> @@ -60,6 +62,7 @@
> @r_i20 .... ... imm:s20 rd:5 &r_i
> @rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
> @rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
> +@rr_ui8 .. ........ .... imm:8 rj:5 rd:5 &rr_i
> @rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
> @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
> @rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
> @@ -93,6 +96,8 @@
> @rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
> @empty .... ........ ..... ..... ..... ..... &empty
> @i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr
> +@cop_r_i .... ...... imm:s12 rj:5 cop:5 &cop_r_i
> +@j_i .... ........ .. imm:8 rj:5 ..... &j_i
>
> #
> # Fixed point arithmetic operation instruction
> @@ -473,3 +478,9 @@ tlbfill 0000 01100100 10000 01101 00000 00000 @empty
> tlbclr 0000 01100100 10000 01000 00000 00000 @empty
> tlbflush 0000 01100100 10000 01001 00000 00000 @empty
> invtlb 0000 01100100 10011 ..... ..... ..... @i_rr
> +cacop 0000 011000 ............ ..... ..... @cop_r_i
> +lddir 0000 01100100 00 ........ ..... ..... @rr_ui8
> +ldpte 0000 01100100 01 ........ ..... 00000 @j_i
> +ertn 0000 01100100 10000 01110 00000 00000 @empty
> +idle 0000 01100100 10001 ............... @i15
> +dbcl 0000 00000010 10101 ............... @i15
> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
> index a5b81bdca3..7035cbd7d5 100644
> --- a/target/loongarch/internals.h
> +++ b/target/loongarch/internals.h
> @@ -16,6 +16,11 @@
> #define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
> #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
>
> +/* Global bit used for lddir/ldpte */
> +#define LOONGARCH_PAGE_HUGE_SHIFT 6
> +/* Global bit for huge page */
> +#define LOONGARCH_HGLOBAL_SHIFT 12
> +
> void loongarch_translate_init(void);
>
> void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
> diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
> index 48c25e5a9b..6f9742054a 100644
> --- a/target/loongarch/op_helper.c
> +++ b/target/loongarch/op_helper.c
> @@ -91,3 +91,46 @@ target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
> {
> return rj > 21 ? 0 : env->cpucfg[rj];
> }
> +
> +#ifndef CONFIG_USER_ONLY
> +void helper_ertn(CPULoongArchState *env)
> +{
> + uint64_t csr_pplv, csr_pie;
> + if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
> + csr_pplv = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV);
> + csr_pie = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE);
> +
> + /* Clear Refill flag DA flag and set pc */
"clear the IsTLBR flag and the DA flag, and set PC", but as the code is
obvious enough it's better to just drop this comment...
> + env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
> + env->pc = env->CSR_TLBRERA;
> + qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA 0x%lx\n",
> + __func__, env->CSR_TLBRERA);
> + } else {
> + csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
> + csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
> +
> + /* set pc*/
This comment serves no purpose, remove it.
> + env->pc = env->CSR_ERA;
> + qemu_log_mask(CPU_LOG_INT, "%s: ERA 0x%lx\n", __func__, env->CSR_ERA);
> + }
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, csr_pplv);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, csr_pie);
> +
> + env->lladdr = 1;
> +}
> +
> +void helper_idle(CPULoongArchState *env)
> +{
> + CPUState *cs = env_cpu(env);
> +
> + cs->halted = 1;
> + cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
> + /*
> + * Last instruction in the block, PC was updated before
> + * - no need to recover PC and icount
> + */
It seems no other targets need this explanation, as the behavior should
be the same across targets -- this block of comment could be removed as
well.
> + do_raise_exception(env, EXCP_HLT, 0);
> +}
> +#endif /* !CONFIG_USER_ONLY */
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> index 53dd70de17..a778ae8a66 100644
> --- a/target/loongarch/tlb_helper.c
> +++ b/target/loongarch/tlb_helper.c
> @@ -688,3 +688,90 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> do_raise_exception(env, cs->exception_index, retaddr);
> }
> }
> +
> +target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
> + target_ulong level, uint32_t mem_idx)
> +{
> + CPUState *cs = env_cpu(env);
> + target_ulong badvaddr, index, phys, ret;
> + int shift;
> + uint64_t dir1_base, dir1_width;
> + uint64_t dir3_base, dir3_width;
> + bool huge = (base >> LOONGARCH_PAGE_HUGE_SHIFT) & 0x1;
> +
> + badvaddr = env->CSR_TLBRBADV;
> + base = base & TARGET_PHYS_MASK;
> +
> + /* 0:8B, 1:16B, 2:32B, 3:64B */
> + shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH);
> + shift = (shift + 1) * 3;
This seems wrong, according to the manual on CSR.PWCL.PTEWidth:
- 0 for 64-bit,
- 1 for 128-bit,
- 2 for 192-bit,
- 3 for 256-bit;
so the comment is incorrect, and the PTEWidth=2 case cannot be
represented with shifts.
> +
> + if (huge) {
> + return base;
> + }
> + switch (level) {
> + case 1:
> + dir1_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_BASE);
> + dir1_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_WIDTH);
> + index = (badvaddr >> dir1_base) & ((1 << dir1_width) - 1);
> + break;
> + case 3:
> + dir3_base = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_BASE);
> + dir3_width = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_WIDTH);
> + index = (badvaddr >> dir3_base) & ((1 << dir3_width) - 1);
> + break;
> + default:
> + do_raise_exception(env, EXCCODE_INE, GETPC());
> + return 0;
> + }
> +
> + phys = base | index << shift;
> + ret = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
> + return ret;
> +}
> +
> +void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
> + uint32_t mem_idx)
> +{
> + CPUState *cs = env_cpu(env);
> + target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, ps, badv;
> + int shift;
> + bool huge = (base >> LOONGARCH_PAGE_HUGE_SHIFT) & 0x1;
> + uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
> + uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
> +
> + base = base & TARGET_PHYS_MASK;
> +
> + if (huge) {
> + /* Huge Page. base is paddr */
> + tmp0 = base ^ LOONGARCH_PAGE_HUGE_SHIFT;
> + /* Move Global bit */
> + tmp0 = (tmp0 >> LOONGARCH_HGLOBAL_SHIFT) << R_TLBENTRY_G_SHIFT |
> + (tmp0 & (~(1 << R_TLBENTRY_G_SHIFT)));
> + ps = ptbase + ptwidth - 1;
> + if (odd) {
> + tmp0 += (1 << ps);
> + }
> + } else {
> + /* 0:8B, 1:16B, 2:32B, 3:64B */
> + shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH);
> + shift = (shift + 1) * 3;
Same problem here.
> + badv = env->CSR_TLBRBADV;
> +
> + ptindex = (badv >> ptbase) & ((1 << ptwidth) - 1);
> + ptindex = ptindex & ~0x1; /* clear bit 0 */
> + ptoffset0 = ptindex << shift;
> + ptoffset1 = (ptindex + 1) << shift;
> +
> + phys = base | (odd ? ptoffset1 : ptoffset0);
> + tmp0 = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
> + ps = ptbase;
> + }
> +
> + if (odd) {
> + env->CSR_TLBRELO1 = tmp0;
> + } else {
> + env->CSR_TLBRELO0 = tmp0;
> + }
> + env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
> +}
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 11/30] target/loongarch: Add LoongArch interrupt and exception handle
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (9 preceding siblings ...)
2022-01-08 9:13 ` [RFC PATCH v4 10/30] target/loongarch: Add other core instructions support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-09 9:26 ` WANG Xuerui
2022-01-08 9:14 ` [RFC PATCH v4 12/30] target/loongarch: Add timer related instructions support Xiaojuan Yang
` (20 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
1.This patch Add loongarch interrupt and exception handle.
2.Rename the user excp to the exccode from the csr defintions.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
linux-user/loongarch64/cpu_loop.c | 8 +-
target/loongarch/cpu.c | 252 +++++++++++++++++-
target/loongarch/cpu.h | 11 -
target/loongarch/fpu_helper.c | 2 +-
| 4 +-
target/loongarch/translate.c | 2 +-
6 files changed, 254 insertions(+), 25 deletions(-)
diff --git a/linux-user/loongarch64/cpu_loop.c b/linux-user/loongarch64/cpu_loop.c
index 6628d215ca..dd58eb048f 100644
--- a/linux-user/loongarch64/cpu_loop.c
+++ b/linux-user/loongarch64/cpu_loop.c
@@ -28,7 +28,7 @@ void cpu_loop(CPULoongArchState *env)
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
- case EXCP_SYSCALL:
+ case EXCCODE_SYS:
env->pc += 4;
ret = do_syscall(env, env->gpr[11],
env->gpr[4], env->gpr[5],
@@ -48,10 +48,10 @@ void cpu_loop(CPULoongArchState *env)
}
env->gpr[4] = ret;
break;
- case EXCP_INE:
+ case EXCCODE_INE:
force_sig_fault(TARGET_SIGILL, 0, env->pc);
break;
- case EXCP_FPE:
+ case EXCCODE_FPE:
si_code = TARGET_FPE_FLTUNK;
if (GET_FP_CAUSE(env->fcsr0) & FP_INVALID) {
si_code = TARGET_FPE_FLTINV;
@@ -67,7 +67,7 @@ void cpu_loop(CPULoongArchState *env)
force_sig_fault(TARGET_SIGFPE, si_code, env->pc);
break;
case EXCP_DEBUG:
- case EXCP_BREAK:
+ case EXCCODE_BRK:
force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
break;
case EXCP_ATOMIC:
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 571092ce53..caab59b83a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -30,11 +30,23 @@ const char * const fregnames[32] = {
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
};
-static const char * const excp_names[EXCP_LAST + 1] = {
- [EXCP_SYSCALL] = "Syscall",
- [EXCP_BREAK] = "Break",
- [EXCP_INE] = "Instruction Non-existent",
- [EXCP_FPE] = "Floating Point Exception",
+static const char * const excp_names[] = {
+ [EXCCODE_INT] = "Interrupt",
+ [EXCCODE_PIL] = "TLB load page invalid",
+ [EXCCODE_PIS] = "TLB store page invalid",
+ [EXCCODE_PIF] = "TLB Fetch page invalid",
+ [EXCCODE_PME] = "TLB Page modify",
+ [EXCCODE_PNR] = "TLB read-inhibit",
+ [EXCCODE_PNX] = "TLB execute-inhibit",
+ [EXCCODE_PPI] = "TLB priviledged error",
+ [EXCCODE_ADEF] = "Fetch instruction error",
+ [EXCCODE_ADEM] = "Memory access error",
+ [EXCCODE_SYS] = "Syscall",
+ [EXCCODE_BRK] = "Break",
+ [EXCCODE_INE] = "Instruction Non-existent",
+ [EXCCODE_IPE] = "Instruction priveiledged error",
+ [EXCCODE_FPE] = "Floating Point Exception",
+ [EXCCODE_DBP] = "Debug breakpoint",
};
const char *loongarch_exception_name(int32_t exception)
@@ -66,6 +78,215 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
env->pc = value;
}
+#if !defined(CONFIG_USER_ONLY)
+static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
+{
+ bool ret = 0;
+
+ ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
+ !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
+
+ return ret;
+}
+
+/* Check if there is pending and not masked out interrupt */
+static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
+{
+ uint32_t pending;
+ uint32_t status;
+ bool r;
+
+ pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
+ status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
+
+ r = (pending & status) != 0;
+ return r;
+}
+
+static inline unsigned int get_vint_size(CPULoongArchState *env)
+{
+ uint64_t vs = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
+ uint64_t size = 0;
+
+ if (vs == 0) {
+ return 0;
+ }
+
+ if (vs < 8) {
+ size = 1 << (vs + 2);
+ }
+
+ if (vs > 8) {
+ qemu_log("%s: unexpected value", __func__);
+ assert(0);
+ }
+
+ return size;
+}
+
+static void loongarch_cpu_do_interrupt(CPUState *cs)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ bool update_badinstr = 1;
+ int cause = -1;
+ const char *name;
+ bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
+
+ if (cs->exception_index != EXCCODE_INT) {
+ if (cs->exception_index < 0 ||
+ cs->exception_index > ARRAY_SIZE(excp_names)) {
+ name = "unknown";
+ } else {
+ name = excp_names[cs->exception_index];
+ }
+
+ qemu_log_mask(CPU_LOG_INT,
+ "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
+ " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
+ env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
+ }
+
+ switch (cs->exception_index) {
+ case EXCCODE_DBP:
+ env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
+ env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
+ env->CSR_DERA = env->pc;
+ env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
+ env->pc = env->CSR_EENTRY + 0x480;
+ break;
+ case EXCCODE_INT:
+ case EXCCODE_PIF:
+ cause = cs->exception_index;
+ update_badinstr = 0;
+ break;
+ case EXCCODE_ADEM:
+ case EXCCODE_SYS:
+ case EXCCODE_BRK:
+ case EXCCODE_PIL:
+ case EXCCODE_PIS:
+ case EXCCODE_PME:
+ case EXCCODE_PNR:
+ case EXCCODE_PNX:
+ case EXCCODE_PPI:
+ case EXCCODE_INE:
+ case EXCCODE_IPE:
+ case EXCCODE_FPE:
+ cause = cs->exception_index;
+ break;
+ default:
+ qemu_log("Error: exception(%d) '%s' has not been supported\n",
+ cs->exception_index, excp_names[cs->exception_index]);
+ abort();
+ }
+
+ if (update_badinstr) {
+ env->CSR_BADI = cpu_ldl_code(env, env->pc);
+ }
+
+ /* Save PLV and IE */
+ if (tlbfill) {
+ env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
+ FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
+ env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
+ FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
+ /* set the DA mode */
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
+ env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
+ PC, (env->pc >> 2));
+ } else {
+ env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
+ FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
+ env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
+ FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
+ env->CSR_ERA = env->pc;
+ }
+
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
+ env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
+
+ uint32_t vec_size = get_vint_size(env);
+ env->pc = env->CSR_EENTRY;
+ env->pc += cause * vec_size;
+ if (tlbfill) {
+ /* TLB Refill */
+ env->pc = env->CSR_TLBRENTRY;
+ }
+ if (cs->exception_index == EXCCODE_INT) {
+ /* Interrupt */
+ uint32_t vector = 0;
+ uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
+ pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
+
+ /* Find the highest-priority interrupt. */
+ while (pending >>= 1) {
+ vector++;
+ }
+ env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
+ qemu_log_mask(CPU_LOG_INT,
+ "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
+ " cause %d\n" " A " TARGET_FMT_lx " D "
+ TARGET_FMT_lx " vector = %d ExC %08lx ExS %08lx\n",
+ __func__, env->pc, env->CSR_ERA,
+ cause, env->CSR_BADV, env->CSR_DERA, vector,
+ env->CSR_ECFG, env->CSR_ESTAT);
+ }
+
+ /* Excode */
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
+
+ if (cs->exception_index != EXCCODE_INT) {
+ qemu_log_mask(CPU_LOG_INT,
+ "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
+ " cause %d%s\n, ESTAT " TARGET_FMT_lx
+ " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
+ "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
+ " cpu %d asid 0x%lx" "\n", __func__, env->pc,
+ tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
+ cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
+ env->CSR_ECFG,
+ tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
+ env->CSR_BADI, env->gpr[11], cs->cpu_index,
+ env->CSR_ASID);
+ }
+ cs->exception_index = -1;
+}
+
+static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ if (access_type == MMU_INST_FETCH) {
+ do_raise_exception(env, EXCCODE_ADEF, retaddr);
+ } else {
+ do_raise_exception(env, EXCCODE_ADEM, retaddr);
+ }
+}
+
+static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ if (cpu_loongarch_hw_interrupts_enabled(env) &&
+ cpu_loongarch_hw_interrupts_pending(env)) {
+ /* Raise it */
+ cs->exception_index = EXCCODE_INT;
+ loongarch_cpu_do_interrupt(cs);
+ return true;
+ }
+ }
+ return false;
+}
+#endif
+
#ifdef CONFIG_TCG
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
@@ -79,7 +300,20 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
static bool loongarch_cpu_has_work(CPUState *cs)
{
+#ifdef CONFIG_USER_ONLY
return true;
+#else
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ bool has_work = false;
+
+ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+ cpu_loongarch_hw_interrupts_pending(env)) {
+ has_work = true;
+ }
+
+ return has_work;
+#endif
}
static void loongarch_3a5000_initfn(Object *obj)
@@ -228,8 +462,11 @@ static void loongarch_cpu_reset(DeviceState *dev)
env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
}
+#ifndef CONFIG_USER_ONLY
+ env->pc = 0x1c000000;
+#endif
restore_fp_status(env);
- cs->exception_index = EXCP_NONE;
+ cs->exception_index = -1;
}
static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
@@ -342,6 +579,9 @@ static struct TCGCPUOps loongarch_tcg_ops = {
#if !defined(CONFIG_USER_ONLY)
.tlb_fill = loongarch_cpu_tlb_fill,
+ .cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
+ .do_interrupt = loongarch_cpu_do_interrupt,
+ .do_transaction_failed = loongarch_cpu_do_transaction_failed,
#endif /* !CONFIG_USER_ONLY */
};
#endif /* CONFIG_TCG */
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 2d5bae1af4..e623e358ec 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -431,17 +431,6 @@ typedef LoongArchCPU ArchCPU;
#include "exec/cpu-all.h"
-/* Exceptions */
-enum {
- EXCP_NONE = -1,
- EXCP_SYSCALL = 0,
- EXCP_BREAK,
- EXCP_INE,
- EXCP_FPE,
-
- EXCP_LAST = EXCP_FPE,
-};
-
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
index 9f5235c4f8..1baf012ef7 100644
--- a/target/loongarch/fpu_helper.c
+++ b/target/loongarch/fpu_helper.c
@@ -74,7 +74,7 @@ static void update_fcsr0_mask(CPULoongArchState *env, uintptr_t pc, int mask)
}
if (GET_FP_ENABLES(env->fcsr0) & flags) {
- do_raise_exception(env, EXCP_FPE, pc);
+ do_raise_exception(env, EXCCODE_FPE, pc);
} else {
UPDATE_FP_FLAGS(env->fcsr0, flags);
}
--git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
index bc622ced23..2ce95d3382 100644
--- a/target/loongarch/insn_trans/trans_extra.c.inc
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
@@ -5,13 +5,13 @@
static bool trans_break(DisasContext *ctx, arg_break *a)
{
- generate_exception(ctx, EXCP_BREAK);
+ generate_exception(ctx, EXCCODE_BRK);
return true;
}
static bool trans_syscall(DisasContext *ctx, arg_syscall *a)
{
- generate_exception(ctx, EXCP_SYSCALL);
+ generate_exception(ctx, EXCCODE_SYS);
return true;
}
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 09771ee43f..ddb97661fa 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -185,7 +185,7 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
if (!decode(ctx, ctx->opcode)) {
qemu_log_mask(LOG_UNIMP, "Error: unkown opcode. 0x%lx: 0x%x\n",
ctx->base.pc_next, ctx->opcode);
- generate_exception(ctx, EXCP_INE);
+ generate_exception(ctx, EXCCODE_INE);
}
for (int i = ctx->ntemp - 1; i >= 0; --i) {
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 11/30] target/loongarch: Add LoongArch interrupt and exception handle
2022-01-08 9:14 ` [RFC PATCH v4 11/30] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
@ 2022-01-09 9:26 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:26 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:14, Xiaojuan Yang wrote:
> 1.This patch Add loongarch interrupt and exception handle.
> 2.Rename the user excp to the exccode from the csr defintions.
>
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> linux-user/loongarch64/cpu_loop.c | 8 +-
> target/loongarch/cpu.c | 252 +++++++++++++++++-
> target/loongarch/cpu.h | 11 -
> target/loongarch/fpu_helper.c | 2 +-
> target/loongarch/insn_trans/trans_extra.c.inc | 4 +-
> target/loongarch/translate.c | 2 +-
> 6 files changed, 254 insertions(+), 25 deletions(-)
>
> diff --git a/linux-user/loongarch64/cpu_loop.c b/linux-user/loongarch64/cpu_loop.c
> index 6628d215ca..dd58eb048f 100644
> --- a/linux-user/loongarch64/cpu_loop.c
> +++ b/linux-user/loongarch64/cpu_loop.c
> @@ -28,7 +28,7 @@ void cpu_loop(CPULoongArchState *env)
> case EXCP_INTERRUPT:
> /* just indicate that signals should be handled asap */
> break;
> - case EXCP_SYSCALL:
> + case EXCCODE_SYS:
> env->pc += 4;
> ret = do_syscall(env, env->gpr[11],
> env->gpr[4], env->gpr[5],
> @@ -48,10 +48,10 @@ void cpu_loop(CPULoongArchState *env)
> }
> env->gpr[4] = ret;
> break;
> - case EXCP_INE:
> + case EXCCODE_INE:
> force_sig_fault(TARGET_SIGILL, 0, env->pc);
> break;
> - case EXCP_FPE:
> + case EXCCODE_FPE:
> si_code = TARGET_FPE_FLTUNK;
> if (GET_FP_CAUSE(env->fcsr0) & FP_INVALID) {
> si_code = TARGET_FPE_FLTINV;
> @@ -67,7 +67,7 @@ void cpu_loop(CPULoongArchState *env)
> force_sig_fault(TARGET_SIGFPE, si_code, env->pc);
> break;
> case EXCP_DEBUG:
> - case EXCP_BREAK:
> + case EXCCODE_BRK:
> force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
> break;
> case EXCP_ATOMIC:
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 571092ce53..caab59b83a 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -30,11 +30,23 @@ const char * const fregnames[32] = {
> "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
> };
>
> -static const char * const excp_names[EXCP_LAST + 1] = {
> - [EXCP_SYSCALL] = "Syscall",
> - [EXCP_BREAK] = "Break",
> - [EXCP_INE] = "Instruction Non-existent",
> - [EXCP_FPE] = "Floating Point Exception",
> +static const char * const excp_names[] = {
> + [EXCCODE_INT] = "Interrupt",
> + [EXCCODE_PIL] = "TLB load page invalid",
> + [EXCCODE_PIS] = "TLB store page invalid",
> + [EXCCODE_PIF] = "TLB Fetch page invalid",
Where do the translations come from? According to the Chinese original,
we should have "Page Invalid for {Load,Store,instruction Fetch}" here
for correct acronyms.
> + [EXCCODE_PME] = "TLB Page modify",
> + [EXCCODE_PNR] = "TLB read-inhibit",
> + [EXCCODE_PNX] = "TLB execute-inhibit",
> + [EXCCODE_PPI] = "TLB priviledged error",
And "Page Modified Exception", "Page Not Readable", "Page Not
Executable", and "Page Privilege Error" accordingly.
> + [EXCCODE_ADEF] = "Fetch instruction error",
> + [EXCCODE_ADEM] = "Memory access error",
And "Address Error for instruction Fetch", and "Address Error for Memory
access".
> + [EXCCODE_SYS] = "Syscall",
> + [EXCCODE_BRK] = "Break",
> + [EXCCODE_INE] = "Instruction Non-existent",
> + [EXCCODE_IPE] = "Instruction priveiledged error",
"Instruction Privilege Error"
> + [EXCCODE_FPE] = "Floating Point Exception",
> + [EXCCODE_DBP] = "Debug breakpoint",
If you re-organize the series so that basic CPU emulation and system
emulation come first, you may want to squash part of this commit into
the former commit defining this array.
> };
>
> const char *loongarch_exception_name(int32_t exception)
> @@ -66,6 +78,215 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
> env->pc = value;
> }
>
> +#if !defined(CONFIG_USER_ONLY)
> +static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
> +{
> + bool ret = 0;
> +
> + ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
> + !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
> +
> + return ret;
> +}
> +
> +/* Check if there is pending and not masked out interrupt */
> +static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
> +{
> + uint32_t pending;
> + uint32_t status;
> + bool r;
> +
> + pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
> + status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
> +
> + r = (pending & status) != 0;
> + return r;
> +}
> +
> +static inline unsigned int get_vint_size(CPULoongArchState *env)
> +{
> + uint64_t vs = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
> + uint64_t size = 0;
> +
> + if (vs == 0) {
> + return 0;
> + }
> +
> + if (vs < 8) {
> + size = 1 << (vs + 2);
> + }
> +
> + if (vs > 8) {
> + qemu_log("%s: unexpected value", __func__);
> + assert(0);
> + }
> +
> + return size;
> +}
> +
> +static void loongarch_cpu_do_interrupt(CPUState *cs)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> + bool update_badinstr = 1;
> + int cause = -1;
> + const char *name;
> + bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
> +
> + if (cs->exception_index != EXCCODE_INT) {
> + if (cs->exception_index < 0 ||
> + cs->exception_index > ARRAY_SIZE(excp_names)) {
> + name = "unknown";
> + } else {
> + name = excp_names[cs->exception_index];
> + }
> +
> + qemu_log_mask(CPU_LOG_INT,
> + "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
> + " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
> + env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
> + }
> +
> + switch (cs->exception_index) {
> + case EXCCODE_DBP:
> + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
> + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
> + env->CSR_DERA = env->pc;
> + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
> + env->pc = env->CSR_EENTRY + 0x480;
> + break;
> + case EXCCODE_INT:
> + case EXCCODE_PIF:
> + cause = cs->exception_index;
> + update_badinstr = 0;
> + break;
> + case EXCCODE_ADEM:
> + case EXCCODE_SYS:
> + case EXCCODE_BRK:
> + case EXCCODE_PIL:
> + case EXCCODE_PIS:
> + case EXCCODE_PME:
> + case EXCCODE_PNR:
> + case EXCCODE_PNX:
> + case EXCCODE_PPI:
> + case EXCCODE_INE:
> + case EXCCODE_IPE:
> + case EXCCODE_FPE:
> + cause = cs->exception_index;
> + break;
> + default:
> + qemu_log("Error: exception(%d) '%s' has not been supported\n",
> + cs->exception_index, excp_names[cs->exception_index]);
> + abort();
> + }
> +
> + if (update_badinstr) {
> + env->CSR_BADI = cpu_ldl_code(env, env->pc);
> + }
> +
> + /* Save PLV and IE */
> + if (tlbfill) {
> + env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
> + FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
> + env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
> + FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
> + /* set the DA mode */
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
> + env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
> + PC, (env->pc >> 2));
> + } else {
> + env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
> + FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
> + env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
> + FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
> + env->CSR_ERA = env->pc;
> + }
> +
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
> + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
> +
> + uint32_t vec_size = get_vint_size(env);
> + env->pc = env->CSR_EENTRY;
> + env->pc += cause * vec_size;
> + if (tlbfill) {
> + /* TLB Refill */
> + env->pc = env->CSR_TLBRENTRY;
> + }
> + if (cs->exception_index == EXCCODE_INT) {
> + /* Interrupt */
> + uint32_t vector = 0;
> + uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
> + pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
> +
> + /* Find the highest-priority interrupt. */
> + while (pending >>= 1) {
> + vector++;
> + }
> + env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
> + qemu_log_mask(CPU_LOG_INT,
> + "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
> + " cause %d\n" " A " TARGET_FMT_lx " D "
> + TARGET_FMT_lx " vector = %d ExC %08lx ExS %08lx\n",
> + __func__, env->pc, env->CSR_ERA,
> + cause, env->CSR_BADV, env->CSR_DERA, vector,
> + env->CSR_ECFG, env->CSR_ESTAT);
> + }
> +
> + /* Excode */
"exccode"?
> + env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
> +
> + if (cs->exception_index != EXCCODE_INT) {
> + qemu_log_mask(CPU_LOG_INT,
> + "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
> + " cause %d%s\n, ESTAT " TARGET_FMT_lx
> + " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
> + "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
> + " cpu %d asid 0x%lx" "\n", __func__, env->pc,
> + tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
> + cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
> + env->CSR_ECFG,
> + tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
> + env->CSR_BADI, env->gpr[11], cs->cpu_index,
> + env->CSR_ASID);
> + }
> + cs->exception_index = -1;
> +}
> +
> +static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> + vaddr addr, unsigned size,
> + MMUAccessType access_type,
> + int mmu_idx, MemTxAttrs attrs,
> + MemTxResult response, uintptr_t retaddr)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> +
> + if (access_type == MMU_INST_FETCH) {
> + do_raise_exception(env, EXCCODE_ADEF, retaddr);
> + } else {
> + do_raise_exception(env, EXCCODE_ADEM, retaddr);
> + }
> +}
> +
> +static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> +{
> + if (interrupt_request & CPU_INTERRUPT_HARD) {
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> +
> + if (cpu_loongarch_hw_interrupts_enabled(env) &&
> + cpu_loongarch_hw_interrupts_pending(env)) {
> + /* Raise it */
> + cs->exception_index = EXCCODE_INT;
> + loongarch_cpu_do_interrupt(cs);
> + return true;
> + }
> + }
> + return false;
> +}
> +#endif
> +
> #ifdef CONFIG_TCG
> static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> @@ -79,7 +300,20 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
>
> static bool loongarch_cpu_has_work(CPUState *cs)
> {
> +#ifdef CONFIG_USER_ONLY
> return true;
> +#else
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> + bool has_work = false;
> +
> + if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
> + cpu_loongarch_hw_interrupts_pending(env)) {
> + has_work = true;
> + }
> +
> + return has_work;
> +#endif
> }
>
> static void loongarch_3a5000_initfn(Object *obj)
> @@ -228,8 +462,11 @@ static void loongarch_cpu_reset(DeviceState *dev)
> env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
> }
>
> +#ifndef CONFIG_USER_ONLY
> + env->pc = 0x1c000000;
> +#endif
> restore_fp_status(env);
> - cs->exception_index = EXCP_NONE;
> + cs->exception_index = -1;
> }
>
> static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> @@ -342,6 +579,9 @@ static struct TCGCPUOps loongarch_tcg_ops = {
>
> #if !defined(CONFIG_USER_ONLY)
> .tlb_fill = loongarch_cpu_tlb_fill,
> + .cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
> + .do_interrupt = loongarch_cpu_do_interrupt,
> + .do_transaction_failed = loongarch_cpu_do_transaction_failed,
> #endif /* !CONFIG_USER_ONLY */
> };
> #endif /* CONFIG_TCG */
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 2d5bae1af4..e623e358ec 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -431,17 +431,6 @@ typedef LoongArchCPU ArchCPU;
>
> #include "exec/cpu-all.h"
>
> -/* Exceptions */
> -enum {
> - EXCP_NONE = -1,
> - EXCP_SYSCALL = 0,
> - EXCP_BREAK,
> - EXCP_INE,
> - EXCP_FPE,
> -
> - EXCP_LAST = EXCP_FPE,
> -};
> -
> #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
>
> #define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
> diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
> index 9f5235c4f8..1baf012ef7 100644
> --- a/target/loongarch/fpu_helper.c
> +++ b/target/loongarch/fpu_helper.c
> @@ -74,7 +74,7 @@ static void update_fcsr0_mask(CPULoongArchState *env, uintptr_t pc, int mask)
> }
>
> if (GET_FP_ENABLES(env->fcsr0) & flags) {
> - do_raise_exception(env, EXCP_FPE, pc);
> + do_raise_exception(env, EXCCODE_FPE, pc);
> } else {
> UPDATE_FP_FLAGS(env->fcsr0, flags);
> }
> diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
> index bc622ced23..2ce95d3382 100644
> --- a/target/loongarch/insn_trans/trans_extra.c.inc
> +++ b/target/loongarch/insn_trans/trans_extra.c.inc
> @@ -5,13 +5,13 @@
>
> static bool trans_break(DisasContext *ctx, arg_break *a)
> {
> - generate_exception(ctx, EXCP_BREAK);
> + generate_exception(ctx, EXCCODE_BRK);
> return true;
> }
>
> static bool trans_syscall(DisasContext *ctx, arg_syscall *a)
> {
> - generate_exception(ctx, EXCP_SYSCALL);
> + generate_exception(ctx, EXCCODE_SYS);
> return true;
> }
>
> diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
> index 09771ee43f..ddb97661fa 100644
> --- a/target/loongarch/translate.c
> +++ b/target/loongarch/translate.c
> @@ -185,7 +185,7 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> if (!decode(ctx, ctx->opcode)) {
> qemu_log_mask(LOG_UNIMP, "Error: unkown opcode. 0x%lx: 0x%x\n",
> ctx->base.pc_next, ctx->opcode);
> - generate_exception(ctx, EXCP_INE);
> + generate_exception(ctx, EXCCODE_INE);
> }
>
> for (int i = ctx->ntemp - 1; i >= 0; --i) {
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 12/30] target/loongarch: Add timer related instructions support.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (10 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 11/30] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-09 9:26 ` WANG Xuerui
2022-01-08 9:14 ` [RFC PATCH v4 13/30] target/loongarch: Add gdb support Xiaojuan Yang
` (19 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/helper.h | 1 +
| 32 +++++++++++++++++++
target/loongarch/op_helper.c | 6 ++++
target/loongarch/translate.c | 2 ++
4 files changed, 41 insertions(+)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index c916f2650b..035bd141ed 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -116,4 +116,5 @@ DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
DEF_HELPER_1(ertn, void, env)
DEF_HELPER_1(idle, void, env)
+DEF_HELPER_1(rdtime_d, i64, env)
#endif /* !CONFIG_USER_ONLY */
--git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
index 2ce95d3382..8d3425ba61 100644
--- a/target/loongarch/insn_trans/trans_extra.c.inc
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
@@ -33,22 +33,54 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
return true;
}
+#ifndef CONFIG_USER_ONLY
+static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
+ bool word, bool high)
+{
+ TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_rdtime_d(dst1, cpu_env);
+ if (word) {
+ tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
+ }
+ tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID));
+
+ return true;
+}
+#endif
+
static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 1, 0);
+#endif
}
static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 1, 1);
+#endif
}
static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 0, 0);
+#endif
}
static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index 6f9742054a..1d8b501ab9 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -133,4 +133,10 @@ void helper_idle(CPULoongArchState *env)
*/
do_raise_exception(env, EXCP_HLT, 0);
}
+
+uint64_t helper_rdtime_d(CPULoongArchState *env)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(env_cpu(env));
+ return cpu_loongarch_get_constant_timer_counter(cpu);
+}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index ddb97661fa..53a5ef3aa9 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval;
TCGv_i32 cpu_fcsr0;
TCGv_i64 cpu_fpr[32];
+#include "exec/gen-icount.h"
+
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 12/30] target/loongarch: Add timer related instructions support.
2022-01-08 9:14 ` [RFC PATCH v4 12/30] target/loongarch: Add timer related instructions support Xiaojuan Yang
@ 2022-01-09 9:26 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:26 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:14, Xiaojuan Yang wrote:
> This includes:
> -RDTIME{L/H}.W
> -RDTIME.D
>
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> target/loongarch/helper.h | 1 +
> target/loongarch/insn_trans/trans_extra.c.inc | 32 +++++++++++++++++++
> target/loongarch/op_helper.c | 6 ++++
> target/loongarch/translate.c | 2 ++
> 4 files changed, 41 insertions(+)
>
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index c916f2650b..035bd141ed 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -116,4 +116,5 @@ DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
> DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
> DEF_HELPER_1(ertn, void, env)
> DEF_HELPER_1(idle, void, env)
> +DEF_HELPER_1(rdtime_d, i64, env)
Are we missing rdtimel_w and rdtimeh_w here?
> #endif /* !CONFIG_USER_ONLY */
> diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
> index 2ce95d3382..8d3425ba61 100644
> --- a/target/loongarch/insn_trans/trans_extra.c.inc
> +++ b/target/loongarch/insn_trans/trans_extra.c.inc
> @@ -33,22 +33,54 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
> return true;
> }
>
> +#ifndef CONFIG_USER_ONLY
> +static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
> + bool word, bool high)
> +{
> + TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
> + TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
> +
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_rdtime_d(dst1, cpu_env);
> + if (word) {
> + tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
> + }
> + tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID));
> +
> + return true;
> +}
> +#endif
> +
> static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a)
> {
> +#ifdef CONFIG_USER_ONLY
> tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
> return true;
> +#else
> + return gen_rdtime(ctx, a, 1, 0);
> +#endif
> }
>
> static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a)
> {
> +#ifdef CONFIG_USER_ONLY
> tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
> return true;
> +#else
> + return gen_rdtime(ctx, a, 1, 1);
> +#endif
> }
>
> static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
> {
> +#ifdef CONFIG_USER_ONLY
> tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
> return true;
> +#else
> + return gen_rdtime(ctx, a, 0, 0);
> +#endif
> }
>
> static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
> diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
> index 6f9742054a..1d8b501ab9 100644
> --- a/target/loongarch/op_helper.c
> +++ b/target/loongarch/op_helper.c
> @@ -133,4 +133,10 @@ void helper_idle(CPULoongArchState *env)
> */
> do_raise_exception(env, EXCP_HLT, 0);
> }
> +
> +uint64_t helper_rdtime_d(CPULoongArchState *env)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(env_cpu(env));
> + return cpu_loongarch_get_constant_timer_counter(cpu);
> +}
> #endif /* !CONFIG_USER_ONLY */
> diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
> index ddb97661fa..53a5ef3aa9 100644
> --- a/target/loongarch/translate.c
> +++ b/target/loongarch/translate.c
> @@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval;
> TCGv_i32 cpu_fcsr0;
> TCGv_i64 cpu_fpr[32];
>
> +#include "exec/gen-icount.h"
> +
> #define DISAS_STOP DISAS_TARGET_0
> #define DISAS_EXIT DISAS_TARGET_1
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 13/30] target/loongarch: Add gdb support.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (11 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 12/30] target/loongarch: Add timer related instructions support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-09 9:26 ` WANG Xuerui
2022-01-08 9:14 ` [RFC PATCH v4 14/30] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3 Platform Xiaojuan Yang
` (18 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml | 43 +++++++++++
gdb-xml/loongarch-fpu64.xml | 57 +++++++++++++++
target/loongarch/cpu.c | 7 ++
target/loongarch/gdbstub.c | 97 +++++++++++++++++++++++++
target/loongarch/internals.h | 10 +++
target/loongarch/meson.build | 1 +
7 files changed, 216 insertions(+)
create mode 100644 configs/targets/loongarch64-softmmu.mak
create mode 100644 gdb-xml/loongarch-base64.xml
create mode 100644 gdb-xml/loongarch-fpu64.xml
create mode 100644 target/loongarch/gdbstub.c
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
new file mode 100644
index 0000000000..f33fa1590b
--- /dev/null
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -0,0 +1 @@
+TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
diff --git a/gdb-xml/loongarch-base64.xml b/gdb-xml/loongarch-base64.xml
new file mode 100644
index 0000000000..f2af2a4b6e
--- /dev/null
+++ b/gdb-xml/loongarch-base64.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2021 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.base">
+ <reg name="r0" bitsize="64" type="uint64" group="general"/>
+ <reg name="r1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r3" bitsize="64" type="uint64" group="general"/>
+ <reg name="r4" bitsize="64" type="uint64" group="general"/>
+ <reg name="r5" bitsize="64" type="uint64" group="general"/>
+ <reg name="r6" bitsize="64" type="uint64" group="general"/>
+ <reg name="r7" bitsize="64" type="uint64" group="general"/>
+ <reg name="r8" bitsize="64" type="uint64" group="general"/>
+ <reg name="r9" bitsize="64" type="uint64" group="general"/>
+ <reg name="r10" bitsize="64" type="uint64" group="general"/>
+ <reg name="r11" bitsize="64" type="uint64" group="general"/>
+ <reg name="r12" bitsize="64" type="uint64" group="general"/>
+ <reg name="r13" bitsize="64" type="uint64" group="general"/>
+ <reg name="r14" bitsize="64" type="uint64" group="general"/>
+ <reg name="r15" bitsize="64" type="uint64" group="general"/>
+ <reg name="r16" bitsize="64" type="uint64" group="general"/>
+ <reg name="r17" bitsize="64" type="uint64" group="general"/>
+ <reg name="r18" bitsize="64" type="uint64" group="general"/>
+ <reg name="r19" bitsize="64" type="uint64" group="general"/>
+ <reg name="r20" bitsize="64" type="uint64" group="general"/>
+ <reg name="r21" bitsize="64" type="uint64" group="general"/>
+ <reg name="r22" bitsize="64" type="uint64" group="general"/>
+ <reg name="r23" bitsize="64" type="uint64" group="general"/>
+ <reg name="r24" bitsize="64" type="uint64" group="general"/>
+ <reg name="r25" bitsize="64" type="uint64" group="general"/>
+ <reg name="r26" bitsize="64" type="uint64" group="general"/>
+ <reg name="r27" bitsize="64" type="uint64" group="general"/>
+ <reg name="r28" bitsize="64" type="uint64" group="general"/>
+ <reg name="r29" bitsize="64" type="uint64" group="general"/>
+ <reg name="r30" bitsize="64" type="uint64" group="general"/>
+ <reg name="r31" bitsize="64" type="uint64" group="general"/>
+ <reg name="pc" bitsize="64" type="code_ptr" group="general"/>
+</feature>
diff --git a/gdb-xml/loongarch-fpu64.xml b/gdb-xml/loongarch-fpu64.xml
new file mode 100644
index 0000000000..e52cf89fbc
--- /dev/null
+++ b/gdb-xml/loongarch-fpu64.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2021 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.fpu">
+
+ <union id="fpu64type">
+ <field name="f" type="ieee_single"/>
+ <field name="d" type="ieee_double"/>
+ </union>
+
+ <reg name="f0" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f1" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f2" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f3" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f4" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f5" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f6" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f7" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f8" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f9" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f10" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f11" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f12" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f13" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f14" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f15" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f16" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f17" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f18" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f19" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f20" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f21" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f22" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f23" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f24" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f25" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f26" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f27" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f28" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f29" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f30" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="f31" bitsize="64" type="fpu64type" group="float"/>
+ <reg name="fcc0" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc1" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc2" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc3" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc4" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc5" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc6" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcc7" bitsize="8" type="uint8" group="float"/>
+ <reg name="fcsr" bitsize="32" type="uint32" group="float"/>
+</feature>
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index caab59b83a..8d0be47d4b 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -146,11 +146,18 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
" TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
}
+ if (cs->exception_index == EXCCODE_INT &&
+ (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))) {
+ env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
+ goto set_DERA;
+ }
switch (cs->exception_index) {
case EXCCODE_DBP:
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
+ goto set_DERA;
+ set_DERA:
env->CSR_DERA = env->pc;
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
env->pc = env->CSR_EENTRY + 0x480;
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
new file mode 100644
index 0000000000..2fec9364de
--- /dev/null
+++ b/target/loongarch/gdbstub.c
@@ -0,0 +1,97 @@
+/*
+ * LOONGARCH gdb server stub
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "internals.h"
+#include "exec/gdbstub.h"
+#include "exec/helper-proto.h"
+
+int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ if (0 <= n && n < 32) {
+ return gdb_get_regl(mem_buf, env->gpr[n]);
+ } else if (n == 32) {
+ return gdb_get_regl(mem_buf, env->pc);
+ }
+ return 0;
+}
+
+int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ target_ulong tmp = ldtul_p(mem_buf);
+
+ if (0 <= n && n < 32) {
+ return env->gpr[n] = tmp, sizeof(target_ulong);
+ } else if (n == 32) {
+ return env->pc = tmp, sizeof(target_ulong);
+ }
+ return 0;
+}
+
+static int loongarch_gdb_get_fpu(CPULoongArchState *env,
+ GByteArray *mem_buf, int n)
+{
+ if (0 <= n && n < 32) {
+ return gdb_get_reg64(mem_buf, env->fpr[n]);
+ } else if (32 <= n && n < 40) {
+ return gdb_get_reg8(mem_buf, env->cf[n - 32]);
+ } else if (n == 40) {
+ return gdb_get_reg32(mem_buf, env->fcsr0);
+ }
+ return 0;
+}
+
+static int loongarch_gdb_set_fpu(CPULoongArchState *env,
+ uint8_t *mem_buf, int n)
+{
+ if (0 <= n && n < 32) {
+ return env->fpr[n] = ldq_p(mem_buf), 8;
+ } else if (32 <= n && n < 40) {
+ return env->cf[n - 32] = ldub_p(mem_buf), 1;
+ } else if (n == 40) {
+ return env->fcsr0 = ldl_p(mem_buf), 4;
+ }
+ return 0;
+}
+
+void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
+{
+ gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
+ 41, "loongarch-fpu64.xml", 0);
+}
+
+int loongarch_read_qxfer(CPUState *cs, const char *annex, uint8_t *read_buf,
+ unsigned long offset, unsigned long len)
+{
+ if (strncmp(annex, "cpucfg", sizeof("cpucfg") - 1) == 0) {
+ if (offset % 4 != 0 || len % 4 != 0) {
+ return 0;
+ }
+
+ size_t i;
+ for (i = offset; i < offset + len; i += 4)
+ ((uint32_t *)read_buf)[(i - offset) / 4] =
+ helper_cpucfg(&(LOONGARCH_CPU(cs)->env), i / 4);
+ return 32 * 4;
+ }
+ return 0;
+}
+
+int loongarch_write_qxfer(CPUState *cs, const char *annex,
+ const uint8_t *write_buf, unsigned long offset,
+ unsigned long len)
+{
+ return 0;
+}
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 7035cbd7d5..dbeac6900d 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -43,5 +43,15 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
void loongarch_mmu_init(CPULoongArchState *env);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
+int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
+int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
+int loongarch_read_qxfer(CPUState *cs, const char *annex,
+ uint8_t *read_buf,
+ unsigned long offset, unsigned long len);
+int loongarch_write_qxfer(CPUState *cs, const char *annex,
+ const uint8_t *write_buf,
+ unsigned long offset, unsigned long len);
+
+void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
#endif
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 072684ca6d..4fb0c96e52 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files(
'fpu_helper.c',
'op_helper.c',
'translate.c',
+ 'gdbstub.c',
))
loongarch_tcg_ss.add(zlib)
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 13/30] target/loongarch: Add gdb support.
2022-01-08 9:14 ` [RFC PATCH v4 13/30] target/loongarch: Add gdb support Xiaojuan Yang
@ 2022-01-09 9:26 ` WANG Xuerui
0 siblings, 0 replies; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:26 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: mark.cave-ayland, richard.henderson, philmd, Song Gao
On 1/8/22 17:14, Xiaojuan Yang wrote:
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
> configs/targets/loongarch64-softmmu.mak | 1 +
> gdb-xml/loongarch-base64.xml | 43 +++++++++++
> gdb-xml/loongarch-fpu64.xml | 57 +++++++++++++++
> target/loongarch/cpu.c | 7 ++
> target/loongarch/gdbstub.c | 97 +++++++++++++++++++++++++
> target/loongarch/internals.h | 10 +++
> target/loongarch/meson.build | 1 +
> 7 files changed, 216 insertions(+)
> create mode 100644 configs/targets/loongarch64-softmmu.mak
> create mode 100644 gdb-xml/loongarch-base64.xml
> create mode 100644 gdb-xml/loongarch-fpu64.xml
> create mode 100644 target/loongarch/gdbstub.c
>
> diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
> new file mode 100644
> index 0000000000..f33fa1590b
> --- /dev/null
> +++ b/configs/targets/loongarch64-softmmu.mak
> @@ -0,0 +1 @@
> +TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
> diff --git a/gdb-xml/loongarch-base64.xml b/gdb-xml/loongarch-base64.xml
> new file mode 100644
> index 0000000000..f2af2a4b6e
> --- /dev/null
> +++ b/gdb-xml/loongarch-base64.xml
> @@ -0,0 +1,43 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2021 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.loongarch.base">
> + <reg name="r0" bitsize="64" type="uint64" group="general"/>
> + <reg name="r1" bitsize="64" type="uint64" group="general"/>
> + <reg name="r2" bitsize="64" type="uint64" group="general"/>
> + <reg name="r3" bitsize="64" type="uint64" group="general"/>
> + <reg name="r4" bitsize="64" type="uint64" group="general"/>
> + <reg name="r5" bitsize="64" type="uint64" group="general"/>
> + <reg name="r6" bitsize="64" type="uint64" group="general"/>
> + <reg name="r7" bitsize="64" type="uint64" group="general"/>
> + <reg name="r8" bitsize="64" type="uint64" group="general"/>
> + <reg name="r9" bitsize="64" type="uint64" group="general"/>
> + <reg name="r10" bitsize="64" type="uint64" group="general"/>
> + <reg name="r11" bitsize="64" type="uint64" group="general"/>
> + <reg name="r12" bitsize="64" type="uint64" group="general"/>
> + <reg name="r13" bitsize="64" type="uint64" group="general"/>
> + <reg name="r14" bitsize="64" type="uint64" group="general"/>
> + <reg name="r15" bitsize="64" type="uint64" group="general"/>
> + <reg name="r16" bitsize="64" type="uint64" group="general"/>
> + <reg name="r17" bitsize="64" type="uint64" group="general"/>
> + <reg name="r18" bitsize="64" type="uint64" group="general"/>
> + <reg name="r19" bitsize="64" type="uint64" group="general"/>
> + <reg name="r20" bitsize="64" type="uint64" group="general"/>
> + <reg name="r21" bitsize="64" type="uint64" group="general"/>
> + <reg name="r22" bitsize="64" type="uint64" group="general"/>
> + <reg name="r23" bitsize="64" type="uint64" group="general"/>
> + <reg name="r24" bitsize="64" type="uint64" group="general"/>
> + <reg name="r25" bitsize="64" type="uint64" group="general"/>
> + <reg name="r26" bitsize="64" type="uint64" group="general"/>
> + <reg name="r27" bitsize="64" type="uint64" group="general"/>
> + <reg name="r28" bitsize="64" type="uint64" group="general"/>
> + <reg name="r29" bitsize="64" type="uint64" group="general"/>
> + <reg name="r30" bitsize="64" type="uint64" group="general"/>
> + <reg name="r31" bitsize="64" type="uint64" group="general"/>
> + <reg name="pc" bitsize="64" type="code_ptr" group="general"/>
> +</feature>
> diff --git a/gdb-xml/loongarch-fpu64.xml b/gdb-xml/loongarch-fpu64.xml
> new file mode 100644
> index 0000000000..e52cf89fbc
> --- /dev/null
> +++ b/gdb-xml/loongarch-fpu64.xml
> @@ -0,0 +1,57 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2021 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.loongarch.fpu">
> +
> + <union id="fpu64type">
> + <field name="f" type="ieee_single"/>
> + <field name="d" type="ieee_double"/>
> + </union>
> +
> + <reg name="f0" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f1" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f2" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f3" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f4" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f5" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f6" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f7" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f8" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f9" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f10" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f11" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f12" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f13" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f14" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f15" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f16" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f17" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f18" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f19" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f20" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f21" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f22" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f23" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f24" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f25" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f26" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f27" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f28" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f29" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f30" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="f31" bitsize="64" type="fpu64type" group="float"/>
> + <reg name="fcc0" bitsize="8" type="uint8" group="float"/>
> + <reg name="fcc1" bitsize="8" type="uint8" group="float"/>
> + <reg name="fcc2" bitsize="8" type="uint8" group="float"/>
> + <reg name="fcc3" bitsize="8" type="uint8" group="float"/>
> + <reg name="fcc4" bitsize="8" type="uint8" group="float"/>
> + <reg name="fcc5" bitsize="8" type="uint8" group="float"/>
> + <reg name="fcc6" bitsize="8" type="uint8" group="float"/>
> + <reg name="fcc7" bitsize="8" type="uint8" group="float"/>
I know this file is copied from binutils, but aren't FCC registers 1-bit
each? They are just predicates after all... Clarification from Loongson
toolchain people would be appreciated.
> + <reg name="fcsr" bitsize="32" type="uint32" group="float"/>
> +</feature>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index caab59b83a..8d0be47d4b 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -146,11 +146,18 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
> " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
> env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
> }
> + if (cs->exception_index == EXCCODE_INT &&
> + (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))) {
> + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
> + goto set_DERA;
> + }
>
> switch (cs->exception_index) {
> case EXCCODE_DBP:
> env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
> env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
> + goto set_DERA;
> + set_DERA:
> env->CSR_DERA = env->pc;
> env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
> env->pc = env->CSR_EENTRY + 0x480;
> diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
> new file mode 100644
> index 0000000000..2fec9364de
> --- /dev/null
> +++ b/target/loongarch/gdbstub.c
> @@ -0,0 +1,97 @@
> +/*
> + * LOONGARCH gdb server stub
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + *
> + * SPDX-License-Identifier: LGPL-2.1+
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "cpu.h"
> +#include "internals.h"
> +#include "exec/gdbstub.h"
> +#include "exec/helper-proto.h"
> +
> +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> +
> + if (0 <= n && n < 32) {
> + return gdb_get_regl(mem_buf, env->gpr[n]);
> + } else if (n == 32) {
> + return gdb_get_regl(mem_buf, env->pc);
> + }
> + return 0;
> +}
> +
> +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> + target_ulong tmp = ldtul_p(mem_buf);
> +
> + if (0 <= n && n < 32) {
> + return env->gpr[n] = tmp, sizeof(target_ulong);
> + } else if (n == 32) {
> + return env->pc = tmp, sizeof(target_ulong);
> + }
> + return 0;
> +}
> +
> +static int loongarch_gdb_get_fpu(CPULoongArchState *env,
> + GByteArray *mem_buf, int n)
> +{
> + if (0 <= n && n < 32) {
> + return gdb_get_reg64(mem_buf, env->fpr[n]);
> + } else if (32 <= n && n < 40) {
> + return gdb_get_reg8(mem_buf, env->cf[n - 32]);
> + } else if (n == 40) {
> + return gdb_get_reg32(mem_buf, env->fcsr0);
> + }
> + return 0;
> +}
> +
> +static int loongarch_gdb_set_fpu(CPULoongArchState *env,
> + uint8_t *mem_buf, int n)
> +{
> + if (0 <= n && n < 32) {
> + return env->fpr[n] = ldq_p(mem_buf), 8;
> + } else if (32 <= n && n < 40) {
> + return env->cf[n - 32] = ldub_p(mem_buf), 1;
> + } else if (n == 40) {
> + return env->fcsr0 = ldl_p(mem_buf), 4;
> + }
> + return 0;
> +}
> +
> +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
> +{
> + gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
> + 41, "loongarch-fpu64.xml", 0);
> +}
> +
> +int loongarch_read_qxfer(CPUState *cs, const char *annex, uint8_t *read_buf,
> + unsigned long offset, unsigned long len)
> +{
> + if (strncmp(annex, "cpucfg", sizeof("cpucfg") - 1) == 0) {
> + if (offset % 4 != 0 || len % 4 != 0) {
> + return 0;
> + }
> +
> + size_t i;
> + for (i = offset; i < offset + len; i += 4)
> + ((uint32_t *)read_buf)[(i - offset) / 4] =
> + helper_cpucfg(&(LOONGARCH_CPU(cs)->env), i / 4);
> + return 32 * 4;
> + }
> + return 0;
> +}
> +
> +int loongarch_write_qxfer(CPUState *cs, const char *annex,
> + const uint8_t *write_buf, unsigned long offset,
> + unsigned long len)
> +{
> + return 0;
> +}
> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
> index 7035cbd7d5..dbeac6900d 100644
> --- a/target/loongarch/internals.h
> +++ b/target/loongarch/internals.h
> @@ -43,5 +43,15 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> void loongarch_mmu_init(CPULoongArchState *env);
> hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> #endif
> +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
> +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
> +int loongarch_read_qxfer(CPUState *cs, const char *annex,
> + uint8_t *read_buf,
> + unsigned long offset, unsigned long len);
> +int loongarch_write_qxfer(CPUState *cs, const char *annex,
> + const uint8_t *write_buf,
> + unsigned long offset, unsigned long len);
> +
> +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
>
> #endif
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index 072684ca6d..4fb0c96e52 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files(
> 'fpu_helper.c',
> 'op_helper.c',
> 'translate.c',
> + 'gdbstub.c',
> ))
> loongarch_tcg_ss.add(zlib)
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 14/30] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3 Platform
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (12 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 13/30] target/loongarch: Add gdb support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 15/30] hw/loongarch: Add support loongson3-ls7a machine type Xiaojuan Yang
` (17 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This is a model of the PCIe Host Bridge found on a Loongson-5000
processor. It includes a interrupt controller, some interface for
pci and nonpci devices. Mainly emulate part of it that is not
exactly the same as the host and only use part devices for
tcg mode. It support for MSI and MSIX interrupt sources.
For more detailed info about ls7a1000 you can see the doc at
https://github.com/loongson/LoongArch-Documentation/releases/latest/
download/Loongson-7A1000-usermanual-2.00-EN.pdf
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/pci-host/Kconfig | 4 +
hw/pci-host/ls7a.c | 178 +++++++++++++++++++++++++++++++++++++
hw/pci-host/meson.build | 1 +
include/hw/pci-host/ls7a.h | 52 +++++++++++
include/hw/pci/pci_ids.h | 3 +
5 files changed, 238 insertions(+)
create mode 100644 hw/pci-host/ls7a.c
create mode 100644 include/hw/pci-host/ls7a.h
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 2b5f7d58cc..b02a9d1454 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -77,3 +77,7 @@ config MV64361
bool
select PCI
select I8259
+
+config PCI_EXPRESS_7A
+ bool
+ select PCI_EXPRESS
diff --git a/hw/pci-host/ls7a.c b/hw/pci-host/ls7a.c
new file mode 100644
index 0000000000..eb16b669bb
--- /dev/null
+++ b/hw/pci-host/ls7a.c
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU Loongson 7A1000 North Bridge Emulation
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/pci/pci.h"
+#include "hw/pci/pcie_host.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "hw/irq.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pci_bus.h"
+#include "sysemu/reset.h"
+#include "hw/pci-host/ls7a.h"
+#include "migration/vmstate.h"
+
+static const VMStateDescription vmstate_ls7a_pcie = {
+ .name = "LS7A_PCI_DEVICE",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(parent_obj, LS7APCIState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void pci_ls7a_config_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ pci_data_write(opaque, addr, val, size);
+}
+
+static uint64_t pci_ls7a_config_read(void *opaque,
+ hwaddr addr, unsigned size)
+{
+ uint64_t val;
+
+ val = pci_data_read(opaque, addr, size);
+
+ return val;
+}
+
+static const MemoryRegionOps pci_ls7a_config_ops = {
+ .read = pci_ls7a_config_read,
+ .write = pci_ls7a_config_write,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ls7a_pciehost_realize(DeviceState *dev, Error **errp)
+{
+ PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+ LS7APCIEHost *s = LS7A_HOST_DEVICE(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
+
+ pcie_host_mmcfg_init(pex, LS_PCIECFG_SIZE);
+ sysbus_init_mmio(sbd, &pex->mmio);
+
+ /* Add ls7a pci-io/pci-mmio */
+ memory_region_init(&s->pci_io, OBJECT(s), "io", LS7A_PCI_IO_SIZE);
+ memory_region_init(&s->pci_mmio, OBJECT(s), "ls7a_mmio", UINT64_MAX);
+ sysbus_init_mmio(sbd, &s->pci_io);
+ sysbus_init_mmio(sbd, &s->pci_mmio);
+
+ pci->bus = pci_register_root_bus(dev, "pcie.0", NULL, NULL, s,
+ &s->pci_mmio, &s->pci_io,
+ PCI_DEVFN(1, 0), 128, TYPE_PCIE_BUS);
+
+ memory_region_init_io(&s->pci_conf, OBJECT(dev),
+ &pci_ls7a_config_ops, pci->bus,
+ "ls7a_pci_conf", HT1LO_PCICFG_SIZE);
+ sysbus_init_mmio(sbd, &s->pci_conf);
+
+ qdev_realize(DEVICE(&s->pci_dev), BUS(pci->bus), &error_fatal);
+}
+
+static void ls7a_reset(DeviceState *qdev)
+{
+ PCIDevice *d = PCI_DEVICE(qdev);
+
+ /* pci status */
+ d->config[0x6] = 0x01;
+ /* base class code */
+ d->config[0xb] = 0x06;
+ /* header type */
+ d->config[0xe] = 0x80;
+ /* capabilities pointer */
+ d->config[0x34] = 0x40;
+ /* link status and control register 0 */
+ d->config[0x44] = 0x20;
+}
+
+static void ls7a_pcie_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->desc = "LS7A1000 PCIE Host bridge";
+ dc->vmsd = &vmstate_ls7a_pcie;
+ k->vendor_id = PCI_VENDOR_ID_LOONGSON;
+ k->device_id = PCI_DEVICE_ID_LOONGSON_HOST;
+ k->revision = 0x0;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+ dc->reset = ls7a_reset;
+ /*
+ * PCI-facing part of the host bridge, not usable without the
+ * host-facing part, which can't be device_add'ed, yet.
+ */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo ls7a_pcie_device_info = {
+ .name = TYPE_LS7A_PCI_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(LS7APCIState),
+ .class_init = ls7a_pcie_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
+static void ls7a_pciehost_initfn(Object *obj)
+{
+ LS7APCIEHost *s = LS7A_HOST_DEVICE(obj);
+ LS7APCIState *ls7a_pci = &s->pci_dev;
+
+ object_initialize_child(obj, "ls7a_pci", ls7a_pci, TYPE_LS7A_PCI_DEVICE);
+ qdev_prop_set_int32(DEVICE(ls7a_pci), "addr", PCI_DEVFN(0, 0));
+ qdev_prop_set_bit(DEVICE(ls7a_pci), "multifunction", false);
+}
+
+static const char *ls7a_pciehost_root_bus_path(PCIHostState *host_bridge,
+ PCIBus *rootbus)
+{
+ return "0000:00";
+}
+
+static void ls7a_pciehost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
+
+ hc->root_bus_path = ls7a_pciehost_root_bus_path;
+ dc->realize = ls7a_pciehost_realize;
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->fw_name = "pci";
+ dc->user_creatable = false;
+}
+
+static const TypeInfo ls7a_pciehost_info = {
+ .name = TYPE_LS7A_HOST_DEVICE,
+ .parent = TYPE_PCIE_HOST_BRIDGE,
+ .instance_size = sizeof(LS7APCIEHost),
+ .instance_init = ls7a_pciehost_initfn,
+ .class_init = ls7a_pciehost_class_init,
+};
+
+static void ls7a_register_types(void)
+{
+ type_register_static(&ls7a_pciehost_info);
+ type_register_static(&ls7a_pcie_device_info);
+}
+
+type_init(ls7a_register_types)
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index 4c4f39c15c..c4955455fd 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -11,6 +11,7 @@ pci_ss.add(when: 'CONFIG_PCI_SABRE', if_true: files('sabre.c'))
pci_ss.add(when: 'CONFIG_XEN_IGD_PASSTHROUGH', if_true: files('xen_igd_pt.c'))
pci_ss.add(when: 'CONFIG_REMOTE_PCIHOST', if_true: files('remote.c'))
pci_ss.add(when: 'CONFIG_SH_PCI', if_true: files('sh_pci.c'))
+pci_ss.add(when: 'CONFIG_PCI_EXPRESS_7A', if_true: files('ls7a.c'))
# PPC devices
pci_ss.add(when: 'CONFIG_RAVEN_PCI', if_true: files('raven.c'))
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
new file mode 100644
index 0000000000..6adbfbe443
--- /dev/null
+++ b/include/hw/pci-host/ls7a.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch CPU
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LS7A_H
+#define HW_LS7A_H
+
+#include "hw/pci/pci.h"
+#include "hw/pci/pcie_host.h"
+#include "hw/pci-host/pam.h"
+#include "qemu/units.h"
+#include "qemu/range.h"
+#include "qom/object.h"
+
+#define HT1LO_PCICFG_BASE 0x1a000000
+#define HT1LO_PCICFG_SIZE 0x02000000
+
+#define LS_PCIECFG_BASE 0x20000000
+#define LS_PCIECFG_SIZE 0x08000000
+
+#define LS7A_PCI_IO_BASE 0x18004000UL
+#define LS7A_PCI_IO_SIZE 0xC000
+
+struct LS7APCIState {
+ /*< private >*/
+ PCIDevice parent_obj;
+ /*< public >*/
+};
+
+typedef struct LS7APCIState LS7APCIState;
+typedef struct LS7APCIEHost {
+ /*< private >*/
+ PCIExpressHost parent_obj;
+ /*< public >*/
+
+ LS7APCIState pci_dev;
+
+ MemoryRegion pci_conf;
+ MemoryRegion pci_mmio;
+ MemoryRegion pci_io;
+} LS7APCIEHost;
+
+#define TYPE_LS7A_HOST_DEVICE "ls7a1000-pciehost"
+OBJECT_DECLARE_SIMPLE_TYPE(LS7APCIEHost, LS7A_HOST_DEVICE)
+
+#define TYPE_LS7A_PCI_DEVICE "ls7a1000_pci"
+OBJECT_DECLARE_SIMPLE_TYPE(LS7APCIState, LS7A_PCI_DEVICE)
+
+#endif /* HW_LS7A_H */
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index 11abe22d46..f3cdf7a912 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -283,4 +283,7 @@
#define PCI_VENDOR_ID_NVIDIA 0x10de
+#define PCI_VENDOR_ID_LOONGSON 0x0014
+#define PCI_DEVICE_ID_LOONGSON_HOST 0x7a00
+
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 15/30] hw/loongarch: Add support loongson3-ls7a machine type.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (13 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 14/30] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3 Platform Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-15 13:35 ` Mark Cave-Ayland
2022-01-08 9:14 ` [RFC PATCH v4 16/30] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC) Xiaojuan Yang
` (16 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the 7A1000
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are emulated.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
.../devices/loongarch64-softmmu/default.mak | 3 +
configs/targets/loongarch64-softmmu.mak | 3 +
hw/Kconfig | 1 +
hw/loongarch/Kconfig | 3 +
hw/loongarch/loongson3.c | 152 ++++++++++++++++++
hw/loongarch/meson.build | 4 +
hw/meson.build | 1 +
include/exec/poison.h | 2 +
include/hw/loongarch/loongarch.h | 50 ++++++
include/sysemu/arch_init.h | 1 +
qapi/machine.json | 2 +-
target/Kconfig | 1 +
target/loongarch/Kconfig | 2 +
target/loongarch/cpu.c | 3 +
target/loongarch/cpu.h | 2 +
15 files changed, 229 insertions(+), 1 deletion(-)
create mode 100644 configs/devices/loongarch64-softmmu/default.mak
create mode 100644 hw/loongarch/Kconfig
create mode 100644 hw/loongarch/loongson3.c
create mode 100644 hw/loongarch/meson.build
create mode 100644 include/hw/loongarch/loongarch.h
create mode 100644 target/loongarch/Kconfig
diff --git a/configs/devices/loongarch64-softmmu/default.mak b/configs/devices/loongarch64-softmmu/default.mak
new file mode 100644
index 0000000000..973ce4c30a
--- /dev/null
+++ b/configs/devices/loongarch64-softmmu/default.mak
@@ -0,0 +1,3 @@
+# Default configuration for loongarch64-softmmu
+
+CONFIG_LOONGSON3_LS7A=y
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
index f33fa1590b..7bc06c850c 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1 +1,4 @@
+TARGET_ARCH=loongarch64
+TARGET_BASE_ARCH=loongarch
+TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
diff --git a/hw/Kconfig b/hw/Kconfig
index ad20cce0a9..f71b2155ed 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -49,6 +49,7 @@ source avr/Kconfig
source cris/Kconfig
source hppa/Kconfig
source i386/Kconfig
+source loongarch/Kconfig
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
new file mode 100644
index 0000000000..ae8498de6a
--- /dev/null
+++ b/hw/loongarch/Kconfig
@@ -0,0 +1,3 @@
+config LOONGSON3_LS7A
+ bool
+ select PCI_EXPRESS_7A
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
new file mode 100644
index 0000000000..3e72c1666c
--- /dev/null
+++ b/hw/loongarch/loongson3.c
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU loongson 3a5000 develop board emulation
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qemu/datadir.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/runstate.h"
+#include "sysemu/reset.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/pci-host/ls7a.h"
+
+static void loongarch_cpu_reset(void *opaque)
+{
+ LoongArchCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+}
+
+#define LOONGARCH_SIMPLE_MMIO_OPS(ADDR, NAME, SIZE, INDEX) \
+({\
+ memory_region_init_io(env->iocsr_mem[INDEX], NULL, &loongarch_qemu_ops,\
+ (void *)ADDR, NAME, SIZE);\
+ memory_region_add_subregion(env->system_iocsr, ADDR, env->iocsr_mem[INDEX]);\
+})
+
+static void loongarch_qemu_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+}
+
+static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
+{
+ uint64_t feature = 0UL;
+ addr = ((hwaddr)(long)opaque) + addr;
+
+ switch (addr) {
+ case FEATURE_REG:
+ feature |= 1UL << IOCSRF_MSI | 1UL << IOCSRF_EXTIOI |
+ 1UL << IOCSRF_CSRIPI;
+ return feature ;
+ case VENDOR_REG:
+ return *(uint64_t *)"Loongson";
+ case CPUNAME_REG:
+ return *(uint64_t *)"3A5000";
+ case MISC_FUNC_REG:
+ return 1UL << IOCSRM_EXTIOI_EN;
+ }
+ return 0;
+}
+
+static const MemoryRegionOps loongarch_qemu_ops = {
+ .read = loongarch_qemu_read,
+ .write = loongarch_qemu_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+};
+
+static void loongarch_init(MachineState *machine)
+{
+ const char *cpu_model = machine->cpu_type;
+ LoongArchCPU *la_cpu;
+ CPULoongArchState *env;
+ ram_addr_t offset = 0;
+ ram_addr_t ram_size = machine->ram_size;
+ uint64_t highram_size = 0;
+ MemoryRegion *address_space_mem = get_system_memory();
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
+ int i;
+
+ if (!cpu_model) {
+ cpu_model = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
+ }
+
+ if (!strstr(cpu_model, "Loongson-3A5000")) {
+ error_report("LoongArch/TCG needs cpu type Loongson-3A5000");
+ exit(1);
+ }
+
+ /* Init CPUs */
+ for (i = 0; i < machine->smp.cpus; i++) {
+ la_cpu = LOONGARCH_CPU(cpu_create(machine->cpu_type));
+
+ qemu_register_reset(loongarch_cpu_reset, la_cpu);
+
+ env = &la_cpu->env;
+ LOONGARCH_SIMPLE_MMIO_OPS(FEATURE_REG, "loongarch_feature", 0x8, 0);
+ LOONGARCH_SIMPLE_MMIO_OPS(VENDOR_REG, "loongarch_vendor", 0x8, 1);
+ LOONGARCH_SIMPLE_MMIO_OPS(CPUNAME_REG, "loongarch_cpuname", 0x8, 2);
+ LOONGARCH_SIMPLE_MMIO_OPS(MISC_FUNC_REG, "loongarch_misc_func", 0x8, 3);
+ }
+
+ /* Add memory region */
+ memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
+ machine->ram, 0, 256 * MiB);
+ memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
+ offset += 256 * MiB;
+
+ highram_size = ram_size - 256 * MiB;
+ memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
+ machine->ram, offset, highram_size);
+ memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
+ offset += highram_size;
+
+ /* Add isa io region */
+ memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
+ get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
+ memory_region_add_subregion(get_system_memory(), LOONGARCH_ISA_IO_BASE,
+ &lams->isa_io);
+}
+
+static void loongarch_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Loongson-3A5000 LS7A1000 machine";
+ mc->init = loongarch_init;
+ mc->default_ram_size = 1 * GiB;
+ mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
+ mc->default_ram_id = "loongarch.ram";
+ mc->max_cpus = LOONGARCH_MAX_VCPUS;
+ mc->is_default = 1;
+ mc->default_kernel_irqchip_split = false;
+ mc->block_default_type = IF_VIRTIO;
+ mc->default_boot_order = "c";
+ mc->no_cdrom = 1;
+}
+
+static const TypeInfo loongarch_machine_types[] = {
+ {
+ .name = TYPE_LOONGARCH_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(LoongArchMachineState),
+ .class_init = loongarch_class_init,
+ }
+};
+
+DEFINE_TYPES(loongarch_machine_types)
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
new file mode 100644
index 0000000000..1db3529cbc
--- /dev/null
+++ b/hw/loongarch/meson.build
@@ -0,0 +1,4 @@
+loongarch_ss = ss.source_set()
+loongarch_ss.add(when: 'CONFIG_LOONGSON3_LS7A', if_true: files('loongson3.c'))
+
+hw_arch += {'loongarch': loongarch_ss}
diff --git a/hw/meson.build b/hw/meson.build
index b3366c888e..95202649b7 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -49,6 +49,7 @@ subdir('avr')
subdir('cris')
subdir('hppa')
subdir('i386')
+subdir('loongarch')
subdir('m68k')
subdir('microblaze')
subdir('mips')
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 7ad4ad18e8..590bc305c7 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -14,6 +14,7 @@
#pragma GCC poison TARGET_CRIS
#pragma GCC poison TARGET_HEXAGON
#pragma GCC poison TARGET_HPPA
+#pragma GCC poison TARGET_LOONGARCH64
#pragma GCC poison TARGET_M68K
#pragma GCC poison TARGET_MICROBLAZE
#pragma GCC poison TARGET_MIPS
@@ -73,6 +74,7 @@
#pragma GCC poison CONFIG_HPPA_DIS
#pragma GCC poison CONFIG_I386_DIS
#pragma GCC poison CONFIG_HEXAGON_DIS
+#pragma GCC poison CONFIG_LOONGARCH_DIS
#pragma GCC poison CONFIG_M68K_DIS
#pragma GCC poison CONFIG_MICROBLAZE_DIS
#pragma GCC poison CONFIG_MIPS_DIS
diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
new file mode 100644
index 0000000000..fd95fbce91
--- /dev/null
+++ b/include/hw/loongarch/loongarch.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Definitions for loongarch board emulation.
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_H
+#define HW_LOONGARCH_H
+
+#include "target/loongarch/cpu.h"
+#include "qemu-common.h"
+#include "hw/boards.h"
+#include "qemu/queue.h"
+
+#define LOONGARCH_MAX_VCPUS 4
+
+#define FEATURE_REG 0x8
+#define IOCSRF_TEMP 0
+#define IOCSRF_NODECNT 1
+#define IOCSRF_MSI 2
+#define IOCSRF_EXTIOI 3
+#define IOCSRF_CSRIPI 4
+#define IOCSRF_FREQCSR 5
+#define IOCSRF_FREQSCALE 6
+#define IOCSRF_DVFSV1 7
+#define IOCSRF_GMOD 9
+#define IOCSRF_VM 11
+
+#define VENDOR_REG 0x10
+#define CPUNAME_REG 0x20
+#define MISC_FUNC_REG 0x420
+#define IOCSRM_EXTIOI_EN 48
+
+#define LOONGARCH_ISA_IO_BASE 0x18000000UL
+#define LOONGARCH_ISA_IO_SIZE 0x0004000
+
+typedef struct LoongArchMachineState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ MemoryRegion lowmem;
+ MemoryRegion highmem;
+ MemoryRegion isa_io;
+} LoongArchMachineState;
+
+#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson3-ls7a")
+DECLARE_INSTANCE_CHECKER(LoongArchMachineState, LOONGARCH_MACHINE,
+ TYPE_LOONGARCH_MACHINE)
+#endif
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 70c579560a..3ac3634bbb 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -24,6 +24,7 @@ enum {
QEMU_ARCH_RX = (1 << 20),
QEMU_ARCH_AVR = (1 << 21),
QEMU_ARCH_HEXAGON = (1 << 22),
+ QEMU_ARCH_LOONGARCH = (1 << 23),
};
extern const uint32_t arch_type;
diff --git a/qapi/machine.json b/qapi/machine.json
index b6a37e17c4..b261017e90 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -30,7 +30,7 @@
##
{ 'enum' : 'SysEmuTarget',
'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386',
- 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
+ 'loongarch64', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
'mips64el', 'mipsel', 'nios2', 'or1k', 'ppc',
'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4',
'sh4eb', 'sparc', 'sparc64', 'tricore',
diff --git a/target/Kconfig b/target/Kconfig
index ae7f24fc66..83da0bd293 100644
--- a/target/Kconfig
+++ b/target/Kconfig
@@ -4,6 +4,7 @@ source avr/Kconfig
source cris/Kconfig
source hppa/Kconfig
source i386/Kconfig
+source loongarch/Kconfig
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig
diff --git a/target/loongarch/Kconfig b/target/loongarch/Kconfig
new file mode 100644
index 0000000000..46b26b1a85
--- /dev/null
+++ b/target/loongarch/Kconfig
@@ -0,0 +1,2 @@
+config LOONGARCH64
+ bool
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 8d0be47d4b..f97206ac67 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -403,6 +403,9 @@ static void loongarch_3a5000_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
env->address_space_iocsr = g_malloc(sizeof(*env->address_space_iocsr));
env->system_iocsr = g_malloc(sizeof(*env->system_iocsr));
+ for (i = 0; i < IOCSR_NUM; i++) {
+ env->iocsr_mem[i] = g_malloc(sizeof(*env->system_iocsr));
+ }
memory_region_init_io(env->system_iocsr, obj, NULL,
env, "iocsr", UINT64_MAX);
address_space_init(env->address_space_iocsr, env->system_iocsr, "IOCSR");
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index e623e358ec..5d6ad4a5a4 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -152,6 +152,7 @@ extern const char * const fregnames[32];
#define N_IRQS 14
#define IRQ_TIMER 11
#define IRQ_IPI 12
+#define IOCSR_NUM 4
#define LOONGARCH_TLB_MAX (2048 + 64) /* 2048 STLB + 64 MTLB */
#define LOONGARCH_STLB 2048 /* 2048 STLB */
@@ -261,6 +262,7 @@ struct CPULoongArchState {
AddressSpace *address_space_iocsr;
MemoryRegion *system_iocsr;
+ MemoryRegion *iocsr_mem[IOCSR_NUM];
#endif
};
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 15/30] hw/loongarch: Add support loongson3-ls7a machine type.
2022-01-08 9:14 ` [RFC PATCH v4 15/30] hw/loongarch: Add support loongson3-ls7a machine type Xiaojuan Yang
@ 2022-01-15 13:35 ` Mark Cave-Ayland
0 siblings, 0 replies; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 13:35 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: richard.henderson, philmd, Song Gao
On 08/01/2022 09:14, Xiaojuan Yang wrote:
> Emulate a 3A5000 board use the new loongarch instruction.
> 3A5000 belongs to the Loongson3 series processors.
> The board consists of a 3A5000 cpu model and the 7A1000
> bridge. The host 3A5000 board is really complicated and
> contains many functions.Now for the tcg softmmu mode
> only part functions are emulated.
>
> More detailed info you can see
> https://github.com/loongson/LoongArch-Documentation
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> .../devices/loongarch64-softmmu/default.mak | 3 +
> configs/targets/loongarch64-softmmu.mak | 3 +
> hw/Kconfig | 1 +
> hw/loongarch/Kconfig | 3 +
> hw/loongarch/loongson3.c | 152 ++++++++++++++++++
> hw/loongarch/meson.build | 4 +
> hw/meson.build | 1 +
> include/exec/poison.h | 2 +
> include/hw/loongarch/loongarch.h | 50 ++++++
> include/sysemu/arch_init.h | 1 +
> qapi/machine.json | 2 +-
> target/Kconfig | 1 +
> target/loongarch/Kconfig | 2 +
> target/loongarch/cpu.c | 3 +
> target/loongarch/cpu.h | 2 +
> 15 files changed, 229 insertions(+), 1 deletion(-)
> create mode 100644 configs/devices/loongarch64-softmmu/default.mak
> create mode 100644 hw/loongarch/Kconfig
> create mode 100644 hw/loongarch/loongson3.c
> create mode 100644 hw/loongarch/meson.build
> create mode 100644 include/hw/loongarch/loongarch.h
> create mode 100644 target/loongarch/Kconfig
>
> diff --git a/configs/devices/loongarch64-softmmu/default.mak b/configs/devices/loongarch64-softmmu/default.mak
> new file mode 100644
> index 0000000000..973ce4c30a
> --- /dev/null
> +++ b/configs/devices/loongarch64-softmmu/default.mak
> @@ -0,0 +1,3 @@
> +# Default configuration for loongarch64-softmmu
> +
> +CONFIG_LOONGSON3_LS7A=y
> diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
> index f33fa1590b..7bc06c850c 100644
> --- a/configs/targets/loongarch64-softmmu.mak
> +++ b/configs/targets/loongarch64-softmmu.mak
> @@ -1 +1,4 @@
> +TARGET_ARCH=loongarch64
> +TARGET_BASE_ARCH=loongarch
> +TARGET_SUPPORTS_MTTCG=y
> TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
> diff --git a/hw/Kconfig b/hw/Kconfig
> index ad20cce0a9..f71b2155ed 100644
> --- a/hw/Kconfig
> +++ b/hw/Kconfig
> @@ -49,6 +49,7 @@ source avr/Kconfig
> source cris/Kconfig
> source hppa/Kconfig
> source i386/Kconfig
> +source loongarch/Kconfig
> source m68k/Kconfig
> source microblaze/Kconfig
> source mips/Kconfig
> diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
> new file mode 100644
> index 0000000000..ae8498de6a
> --- /dev/null
> +++ b/hw/loongarch/Kconfig
> @@ -0,0 +1,3 @@
> +config LOONGSON3_LS7A
> + bool
> + select PCI_EXPRESS_7A
> diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
> new file mode 100644
> index 0000000000..3e72c1666c
> --- /dev/null
> +++ b/hw/loongarch/loongson3.c
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU loongson 3a5000 develop board emulation
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "qemu/units.h"
> +#include "qemu/datadir.h"
> +#include "qapi/error.h"
> +#include "hw/boards.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/qtest.h"
> +#include "sysemu/runstate.h"
> +#include "sysemu/reset.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "hw/pci-host/ls7a.h"
> +
> +static void loongarch_cpu_reset(void *opaque)
> +{
> + LoongArchCPU *cpu = opaque;
> +
> + cpu_reset(CPU(cpu));
> +}
> +
> +#define LOONGARCH_SIMPLE_MMIO_OPS(ADDR, NAME, SIZE, INDEX) \
> +({\
> + memory_region_init_io(env->iocsr_mem[INDEX], NULL, &loongarch_qemu_ops,\
> + (void *)ADDR, NAME, SIZE);\
The second parameter to memory_region_init_io() should be the name of the owning
device if possible, which I believe here is the CPU (LoongArchCPU).
> + memory_region_add_subregion(env->system_iocsr, ADDR, env->iocsr_mem[INDEX]);\
> +})
> +
> +static void loongarch_qemu_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> +}
> +
> +static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + uint64_t feature = 0UL;
> + addr = ((hwaddr)(long)opaque) + addr;
This looks odd...
> + switch (addr) {
> + case FEATURE_REG:
> + feature |= 1UL << IOCSRF_MSI | 1UL << IOCSRF_EXTIOI |
> + 1UL << IOCSRF_CSRIPI;
> + return feature ;
> + case VENDOR_REG:
> + return *(uint64_t *)"Loongson";
> + case CPUNAME_REG:
> + return *(uint64_t *)"3A5000";
> + case MISC_FUNC_REG:
> + return 1UL << IOCSRM_EXTIOI_EN;
> + }
> + return 0;
> +}
> +
> +static const MemoryRegionOps loongarch_qemu_ops = {
> + .read = loongarch_qemu_read,
> + .write = loongarch_qemu_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 8,
> + },
> + .impl = {
> + .min_access_size = 4,
> + .max_access_size = 8,
> + },
> +};
> +
> +static void loongarch_init(MachineState *machine)
> +{
> + const char *cpu_model = machine->cpu_type;
> + LoongArchCPU *la_cpu;
> + CPULoongArchState *env;
> + ram_addr_t offset = 0;
> + ram_addr_t ram_size = machine->ram_size;
> + uint64_t highram_size = 0;
> + MemoryRegion *address_space_mem = get_system_memory();
> + LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
> + int i;
> +
> + if (!cpu_model) {
> + cpu_model = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
> + }
> +
> + if (!strstr(cpu_model, "Loongson-3A5000")) {
> + error_report("LoongArch/TCG needs cpu type Loongson-3A5000");
> + exit(1);
> + }
> +
> + /* Init CPUs */
> + for (i = 0; i < machine->smp.cpus; i++) {
> + la_cpu = LOONGARCH_CPU(cpu_create(machine->cpu_type));
> +
> + qemu_register_reset(loongarch_cpu_reset, la_cpu);
> +
> + env = &la_cpu->env;
> + LOONGARCH_SIMPLE_MMIO_OPS(FEATURE_REG, "loongarch_feature", 0x8, 0);
> + LOONGARCH_SIMPLE_MMIO_OPS(VENDOR_REG, "loongarch_vendor", 0x8, 1);
> + LOONGARCH_SIMPLE_MMIO_OPS(CPUNAME_REG, "loongarch_cpuname", 0x8, 2);
> + LOONGARCH_SIMPLE_MMIO_OPS(MISC_FUNC_REG, "loongarch_misc_func", 0x8, 3);
How come these are separate memory regions? Could this not just be done with a single
memory region or do the registers need to be sparse to return a fault for a unknown
register.
This should enable you to remove the opaque cast to hwaddr if possible.
> + }
> +
> + /* Add memory region */
> + memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
> + machine->ram, 0, 256 * MiB);
> + memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
> + offset += 256 * MiB;
> +
> + highram_size = ram_size - 256 * MiB;
> + memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
> + machine->ram, offset, highram_size);
> + memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
> + offset += highram_size;
> +
> + /* Add isa io region */
> + memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
> + get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
> + memory_region_add_subregion(get_system_memory(), LOONGARCH_ISA_IO_BASE,
> + &lams->isa_io);
This looks like the odd one out: should it also be address_space_mem, or should the
others use get_system_memory() directory and then drop address_space_mem entirely?
> +}
> +
> +static void loongarch_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> + mc->desc = "Loongson-3A5000 LS7A1000 machine";
> + mc->init = loongarch_init;
> + mc->default_ram_size = 1 * GiB;
> + mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
> + mc->default_ram_id = "loongarch.ram";
> + mc->max_cpus = LOONGARCH_MAX_VCPUS;
> + mc->is_default = 1;
> + mc->default_kernel_irqchip_split = false;
> + mc->block_default_type = IF_VIRTIO;
> + mc->default_boot_order = "c";
> + mc->no_cdrom = 1;
> +}
> +
> +static const TypeInfo loongarch_machine_types[] = {
> + {
> + .name = TYPE_LOONGARCH_MACHINE,
> + .parent = TYPE_MACHINE,
> + .instance_size = sizeof(LoongArchMachineState),
> + .class_init = loongarch_class_init,
> + }
> +};
> +
> +DEFINE_TYPES(loongarch_machine_types)
> diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
> new file mode 100644
> index 0000000000..1db3529cbc
> --- /dev/null
> +++ b/hw/loongarch/meson.build
> @@ -0,0 +1,4 @@
> +loongarch_ss = ss.source_set()
> +loongarch_ss.add(when: 'CONFIG_LOONGSON3_LS7A', if_true: files('loongson3.c'))
> +
> +hw_arch += {'loongarch': loongarch_ss}
> diff --git a/hw/meson.build b/hw/meson.build
> index b3366c888e..95202649b7 100644
> --- a/hw/meson.build
> +++ b/hw/meson.build
> @@ -49,6 +49,7 @@ subdir('avr')
> subdir('cris')
> subdir('hppa')
> subdir('i386')
> +subdir('loongarch')
> subdir('m68k')
> subdir('microblaze')
> subdir('mips')
> diff --git a/include/exec/poison.h b/include/exec/poison.h
> index 7ad4ad18e8..590bc305c7 100644
> --- a/include/exec/poison.h
> +++ b/include/exec/poison.h
> @@ -14,6 +14,7 @@
> #pragma GCC poison TARGET_CRIS
> #pragma GCC poison TARGET_HEXAGON
> #pragma GCC poison TARGET_HPPA
> +#pragma GCC poison TARGET_LOONGARCH64
> #pragma GCC poison TARGET_M68K
> #pragma GCC poison TARGET_MICROBLAZE
> #pragma GCC poison TARGET_MIPS
> @@ -73,6 +74,7 @@
> #pragma GCC poison CONFIG_HPPA_DIS
> #pragma GCC poison CONFIG_I386_DIS
> #pragma GCC poison CONFIG_HEXAGON_DIS
> +#pragma GCC poison CONFIG_LOONGARCH_DIS
> #pragma GCC poison CONFIG_M68K_DIS
> #pragma GCC poison CONFIG_MICROBLAZE_DIS
> #pragma GCC poison CONFIG_MIPS_DIS
> diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
> new file mode 100644
> index 0000000000..fd95fbce91
> --- /dev/null
> +++ b/include/hw/loongarch/loongarch.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Definitions for loongarch board emulation.
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef HW_LOONGARCH_H
> +#define HW_LOONGARCH_H
> +
> +#include "target/loongarch/cpu.h"
> +#include "qemu-common.h"
> +#include "hw/boards.h"
> +#include "qemu/queue.h"
> +
> +#define LOONGARCH_MAX_VCPUS 4
> +
> +#define FEATURE_REG 0x8
> +#define IOCSRF_TEMP 0
> +#define IOCSRF_NODECNT 1
> +#define IOCSRF_MSI 2
> +#define IOCSRF_EXTIOI 3
> +#define IOCSRF_CSRIPI 4
> +#define IOCSRF_FREQCSR 5
> +#define IOCSRF_FREQSCALE 6
> +#define IOCSRF_DVFSV1 7
> +#define IOCSRF_GMOD 9
> +#define IOCSRF_VM 11
> +
> +#define VENDOR_REG 0x10
> +#define CPUNAME_REG 0x20
> +#define MISC_FUNC_REG 0x420
> +#define IOCSRM_EXTIOI_EN 48
> +
> +#define LOONGARCH_ISA_IO_BASE 0x18000000UL
> +#define LOONGARCH_ISA_IO_SIZE 0x0004000
> +
> +typedef struct LoongArchMachineState {
> + /*< private >*/
> + MachineState parent_obj;
> +
> + MemoryRegion lowmem;
> + MemoryRegion highmem;
> + MemoryRegion isa_io;
> +} LoongArchMachineState;
> +
> +#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson3-ls7a")
> +DECLARE_INSTANCE_CHECKER(LoongArchMachineState, LOONGARCH_MACHINE,
> + TYPE_LOONGARCH_MACHINE)
> +#endif
> diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
> index 70c579560a..3ac3634bbb 100644
> --- a/include/sysemu/arch_init.h
> +++ b/include/sysemu/arch_init.h
> @@ -24,6 +24,7 @@ enum {
> QEMU_ARCH_RX = (1 << 20),
> QEMU_ARCH_AVR = (1 << 21),
> QEMU_ARCH_HEXAGON = (1 << 22),
> + QEMU_ARCH_LOONGARCH = (1 << 23),
> };
>
> extern const uint32_t arch_type;
> diff --git a/qapi/machine.json b/qapi/machine.json
> index b6a37e17c4..b261017e90 100644
> --- a/qapi/machine.json
> +++ b/qapi/machine.json
> @@ -30,7 +30,7 @@
> ##
> { 'enum' : 'SysEmuTarget',
> 'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386',
> - 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
> + 'loongarch64', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
> 'mips64el', 'mipsel', 'nios2', 'or1k', 'ppc',
> 'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4',
> 'sh4eb', 'sparc', 'sparc64', 'tricore',
> diff --git a/target/Kconfig b/target/Kconfig
> index ae7f24fc66..83da0bd293 100644
> --- a/target/Kconfig
> +++ b/target/Kconfig
> @@ -4,6 +4,7 @@ source avr/Kconfig
> source cris/Kconfig
> source hppa/Kconfig
> source i386/Kconfig
> +source loongarch/Kconfig
> source m68k/Kconfig
> source microblaze/Kconfig
> source mips/Kconfig
> diff --git a/target/loongarch/Kconfig b/target/loongarch/Kconfig
> new file mode 100644
> index 0000000000..46b26b1a85
> --- /dev/null
> +++ b/target/loongarch/Kconfig
> @@ -0,0 +1,2 @@
> +config LOONGARCH64
> + bool
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 8d0be47d4b..f97206ac67 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -403,6 +403,9 @@ static void loongarch_3a5000_initfn(Object *obj)
> #ifndef CONFIG_USER_ONLY
> env->address_space_iocsr = g_malloc(sizeof(*env->address_space_iocsr));
> env->system_iocsr = g_malloc(sizeof(*env->system_iocsr));
> + for (i = 0; i < IOCSR_NUM; i++) {
> + env->iocsr_mem[i] = g_malloc(sizeof(*env->system_iocsr));
> + }
These g_malloc() allocations look odd: since they are all constant size could they
not be declared inline in env?
> memory_region_init_io(env->system_iocsr, obj, NULL,
> env, "iocsr", UINT64_MAX);
> address_space_init(env->address_space_iocsr, env->system_iocsr, "IOCSR");
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index e623e358ec..5d6ad4a5a4 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -152,6 +152,7 @@ extern const char * const fregnames[32];
> #define N_IRQS 14
> #define IRQ_TIMER 11
> #define IRQ_IPI 12
> +#define IOCSR_NUM 4
>
> #define LOONGARCH_TLB_MAX (2048 + 64) /* 2048 STLB + 64 MTLB */
> #define LOONGARCH_STLB 2048 /* 2048 STLB */
> @@ -261,6 +262,7 @@ struct CPULoongArchState {
>
> AddressSpace *address_space_iocsr;
> MemoryRegion *system_iocsr;
> + MemoryRegion *iocsr_mem[IOCSR_NUM];
As above I'd expect these fields to be inline in CPULoongArchState since they are
constant.
> #endif
> };
>
ATB,
Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 16/30] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (14 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 15/30] hw/loongarch: Add support loongson3-ls7a machine type Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 17/30] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
` (15 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76)
Loongson-3A5000 and ls7a form a legacy model and extended model irq
hierarchy.Tcg mode emulate a simplified extended model which
has no Legacy I/O Interrupt Controller(LIOINTC) and LPC.
e.g:
| +-----+ +---------+ +-------+ |
| | IPI |--> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ |
| | |
| +---------+
| | EIOINTC |
| +---------+
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | UARTs | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
The following series patch will realize the interrupt
controller in this model.
More detailed info can be found at the kernel doc or manual
1.https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/
linux-loongson.git/tree/Documentation/loongarch?h=loongarch-next
2.https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/loongson3.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 3e72c1666c..6e796c2c08 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -70,6 +70,29 @@ static const MemoryRegionOps loongarch_qemu_ops = {
},
};
+static void loongarch_cpu_set_irq(void *opaque, int irq, int level)
+{
+ LoongArchCPU *cpu = opaque;
+ CPULoongArchState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+
+ if (irq < 0 || irq > N_IRQS) {
+ return;
+ }
+
+ if (level) {
+ env->CSR_ESTAT |= 1 << irq;
+ } else {
+ env->CSR_ESTAT &= ~(1 << irq);
+ }
+
+ if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
static void loongarch_init(MachineState *machine)
{
const char *cpu_model = machine->cpu_type;
@@ -94,6 +117,7 @@ static void loongarch_init(MachineState *machine)
/* Init CPUs */
for (i = 0; i < machine->smp.cpus; i++) {
la_cpu = LOONGARCH_CPU(cpu_create(machine->cpu_type));
+ qdev_init_gpio_in(DEVICE(la_cpu), loongarch_cpu_set_irq, N_IRQS);
qemu_register_reset(loongarch_cpu_reset, la_cpu);
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 17/30] hw/loongarch: Add LoongArch ipi interrupt support(IPI)
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (15 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 16/30] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC) Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 18/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
` (14 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_ipi.c | 164 ++++++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/intc/trace-events | 4 +
hw/loongarch/Kconfig | 1 +
include/hw/intc/loongarch_ipi.h | 48 ++++++++++
6 files changed, 221 insertions(+)
create mode 100644 hw/intc/loongarch_ipi.c
create mode 100644 include/hw/intc/loongarch_ipi.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 010ded7eae..9f5aaffb6f 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -78,3 +78,6 @@ config GOLDFISH_PIC
config M68K_IRQC
bool
+
+config LOONGARCH_IPI
+ bool
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
new file mode 100644
index 0000000000..b358ac68e5
--- /dev/null
+++ b/hw/intc/loongarch_ipi.c
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch ipi interrupt support
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/intc/loongarch_ipi.h"
+#include "hw/irq.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "exec/address-spaces.h"
+#include "hw/loongarch/loongarch.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
+{
+ IPICore *s = opaque;
+ uint64_t ret = 0;
+ int index = 0;
+
+ addr &= 0xff;
+ switch (addr) {
+ case CORE_STATUS_OFF:
+ ret = s->status;
+ break;
+ case CORE_EN_OFF:
+ ret = s->en;
+ break;
+ case CORE_SET_OFF:
+ ret = 0;
+ break;
+ case CORE_CLEAR_OFF:
+ ret = 0;
+ break;
+ case CORE_BUF_20 ... CORE_BUF_38 + 4:
+ index = (addr - CORE_BUF_20) >> 2;
+ ret = s->buf[index];
+ break;
+ case IOCSR_IPI_SEND:
+ ret = s->status;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
+ break;
+ }
+
+ trace_loongarch_ipi_read(size, (uint64_t)addr, ret);
+ return ret;
+}
+
+static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ IPICore *s = opaque;
+ int index = 0;
+
+ addr &= 0xff;
+ trace_loongarch_ipi_write(size, (uint64_t)addr, val);
+ switch (addr) {
+ case CORE_STATUS_OFF:
+ qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
+ break;
+ case CORE_EN_OFF:
+ s->en = val;
+ break;
+ case CORE_SET_OFF:
+ s->status |= val;
+ if (s->status != 0) {
+ qemu_irq_raise(s->irq);
+ }
+ break;
+ case CORE_CLEAR_OFF:
+ s->status ^= val;
+ if (s->status == 0) {
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ case CORE_BUF_20 ... CORE_BUF_38 + 4:
+ index = (addr - CORE_BUF_20) >> 2;
+ s->buf[index] = val;
+ break;
+ case IOCSR_IPI_SEND:
+ s->status |= val;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
+ break;
+ }
+}
+
+static const MemoryRegionOps loongarch_ipi_ops = {
+ .read = loongarch_ipi_readl,
+ .write = loongarch_ipi_writel,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void loongarch_ipi_init(Object *obj)
+{
+ LoongArchIPI *s = LOONGARCH_IPI(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ int cpu;
+
+ for (cpu = 0; cpu < MACHINE(qdev_get_machine())->smp.cpus; cpu++) {
+ memory_region_init_io(&s->ipi_mmio[cpu], obj, &loongarch_ipi_ops,
+ &s->core[cpu], "loongarch_ipi", 0x100);
+ sysbus_init_mmio(sbd, &s->ipi_mmio[cpu]);
+ qdev_init_gpio_out(DEVICE(obj), &s->core[cpu].irq, 1);
+ }
+}
+
+static const VMStateDescription vmstate_ipi_core = {
+ .name = "ipi-single",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(status, IPICore),
+ VMSTATE_UINT32(en, IPICore),
+ VMSTATE_UINT32(set, IPICore),
+ VMSTATE_UINT32(clear, IPICore),
+ VMSTATE_UINT32_ARRAY(buf, IPICore, MAX_IPI_MBX_NUM * 2),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_loongarch_ipi = {
+ .name = TYPE_LOONGARCH_IPI,
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(core, LoongArchIPI, MAX_IPI_CORE_NUM, 0,
+ vmstate_ipi_core, IPICore),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_loongarch_ipi;
+}
+
+static const TypeInfo loongarch_ipi_info = {
+ .name = TYPE_LOONGARCH_IPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LoongArchIPI),
+ .instance_init = loongarch_ipi_init,
+ .class_init = loongarch_ipi_class_init,
+};
+
+static void loongarch_ipi_register_types(void)
+{
+ type_register_static(&loongarch_ipi_info);
+}
+
+type_init(loongarch_ipi_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 70080bc161..14c0834c67 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -60,3 +60,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 9aba7e3a7a..55f2f3a8b6 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -246,3 +246,7 @@ sh_intc_register(const char *s, int id, unsigned short v, int c, int m) "%s %u -
sh_intc_read(unsigned size, uint64_t offset, unsigned long val) "size %u 0x%" PRIx64 " -> 0x%lx"
sh_intc_write(unsigned size, uint64_t offset, unsigned long val) "size %u 0x%" PRIx64 " <- 0x%lx"
sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
+
+# loongarch_ipi.c
+loongarch_ipi_read(unsigned size, uint64_t addr, unsigned long val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
+loongarch_ipi_write(unsigned size, uint64_t addr, unsigned long val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index ae8498de6a..1591574397 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -1,3 +1,4 @@
config LOONGSON3_LS7A
bool
select PCI_EXPRESS_7A
+ select LOONGARCH_IPI
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
new file mode 100644
index 0000000000..78e676db2c
--- /dev/null
+++ b/include/hw/intc/loongarch_ipi.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch ipi interrupt header files
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_IPI_H
+#define HW_LOONGARCH_IPI_H
+
+#include "hw/sysbus.h"
+
+/* Mainy used by iocsr read and write */
+#define SMP_IPI_MAILBOX 0x1000ULL
+#define CORE_STATUS_OFF 0x0
+#define CORE_EN_OFF 0x4
+#define CORE_SET_OFF 0x8
+#define CORE_CLEAR_OFF 0xc
+#define CORE_BUF_20 0x20
+#define CORE_BUF_28 0x28
+#define CORE_BUF_30 0x30
+#define CORE_BUF_38 0x38
+#define IOCSR_IPI_SEND 0x40
+
+#define MAX_IPI_CORE_NUM 16
+#define MAX_IPI_MBX_NUM 4
+
+#define TYPE_LOONGARCH_IPI "loongarch_ipi"
+DECLARE_INSTANCE_CHECKER(struct LoongArchIPI, LOONGARCH_IPI,
+ TYPE_LOONGARCH_IPI)
+
+typedef struct IPICore {
+ uint32_t status;
+ uint32_t en;
+ uint32_t set;
+ uint32_t clear;
+ /* 64bit buf divide into 2 32bit buf */
+ uint32_t buf[MAX_IPI_MBX_NUM * 2];
+ qemu_irq irq;
+} IPICore;
+
+typedef struct LoongArchIPI {
+ SysBusDevice parent_obj;
+ IPICore core[MAX_IPI_CORE_NUM];
+ MemoryRegion ipi_mmio[MAX_IPI_CORE_NUM];
+} LoongArchIPI;
+
+#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 18/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (16 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 17/30] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-15 13:41 ` Mark Cave-Ayland
2022-01-08 9:14 ` [RFC PATCH v4 19/30] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
` (13 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 428 ++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/intc/trace-events | 7 +
hw/loongarch/Kconfig | 1 +
include/hw/intc/loongarch_pch_pic.h | 74 +++++
6 files changed, 515 insertions(+)
create mode 100644 hw/intc/loongarch_pch_pic.c
create mode 100644 include/hw/intc/loongarch_pch_pic.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 9f5aaffb6f..928db92bb4 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -81,3 +81,7 @@ config M68K_IRQC
config LOONGARCH_IPI
bool
+
+config LOONGARCH_PCH_PIC
+ bool
+ select UNIMP
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
new file mode 100644
index 0000000000..4da78b5bc8
--- /dev/null
+++ b/hw/intc/loongarch_pch_pic.c
@@ -0,0 +1,428 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU Loongson 7A1000 I/O interrupt controller.
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/irq.h"
+#include "hw/intc/loongarch_pch_pic.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+static void pch_pic_update_irq(LoongArchPCHPIC *s, uint32_t mask,
+ int level, int hi)
+{
+ uint32_t val, irq;
+
+ if (level == 1) {
+ if (hi) {
+ val = mask & s->intirr_hi & (~s->int_mask_hi);
+ irq = find_first_bit((void *)&val, 32);
+ if (irq != 32) {
+ s->intisr_hi |= 1ULL << irq;
+ qemu_set_irq(s->parent_irq[s->htmsi_vector[irq + 32]], 1);
+ }
+ } else {
+ val = mask & s->intirr_lo & (~s->int_mask_lo);
+ irq = find_first_bit((void *)&val, 32);
+ if (irq != 32) {
+ s->intisr_lo |= 1ULL << irq;
+ qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1);
+ }
+ }
+ } else {
+ if (hi) {
+ val = mask & s->intisr_hi;
+ irq = find_first_bit((void *)&val, 32);
+ if (irq != 32) {
+ s->intisr_hi &= ~(0x1ULL << irq);
+ qemu_set_irq(s->parent_irq[s->htmsi_vector[irq + 32]], 0);
+ }
+ } else {
+ val = mask & s->intisr_lo;
+ irq = find_first_bit((void *)&val, 32);
+ if (irq != 32) {
+ s->intisr_lo &= ~(0x1ULL << irq);
+ qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 0);
+ }
+ }
+ }
+}
+
+static void pch_pic_irq_handler(void *opaque, int irq, int level)
+{
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ int hi = 0;
+ uint32_t mask;
+
+ assert(irq < PCH_PIC_IRQ_NUM);
+ trace_pch_pic_irq_handler(irq, level);
+
+ hi = (irq >= 32) ? 1 : 0;
+ if (hi) {
+ irq = irq - 32;
+ }
+
+ mask = 1ULL << irq;
+
+ if (hi) {
+ if (s->intedge_hi & mask) {
+ /* Edge triggered */
+ if (level) {
+ if ((s->last_intirr_hi & mask) == 0) {
+ s->intirr_hi |= mask;
+ }
+ s->last_intirr_hi |= mask;
+ } else {
+ s->last_intirr_hi &= ~mask;
+ }
+ } else {
+ /* Level triggered */
+ if (level) {
+ s->intirr_hi |= mask;
+ s->last_intirr_hi |= mask;
+ } else {
+ s->intirr_hi &= ~mask;
+ s->last_intirr_hi &= ~mask;
+ }
+ }
+ } else {
+ if (s->intedge_lo & mask) {
+ /* Edge triggered */
+ if (level) {
+ if ((s->last_intirr_lo & mask) == 0) {
+ s->intirr_lo |= mask;
+ }
+ s->last_intirr_lo |= mask;
+ } else {
+ s->last_intirr_lo &= ~mask;
+ }
+ } else {
+ /* Level triggered */
+ if (level) {
+ s->intirr_lo |= mask;
+ s->last_intirr_lo |= mask;
+ } else {
+ s->intirr_lo &= ~mask;
+ s->last_intirr_lo &= ~mask;
+ }
+
+ }
+ }
+ pch_pic_update_irq(s, mask, level, hi);
+}
+
+static uint64_t loongarch_pch_pic_readw(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ uint64_t val = 0;
+ uint32_t offset = addr & 0xfff;
+
+ switch (offset) {
+ case PCH_PIC_INT_ID_LO:
+ val = PCH_PIC_INT_ID_VAL;
+ break;
+ case PCH_PIC_INT_ID_HI:
+ val = PCH_PIC_INT_ID_NUM;
+ break;
+ case PCH_PIC_INT_MASK_LO:
+ val = s->int_mask_lo;
+ break;
+ case PCH_PIC_INT_MASK_HI:
+ val = s->int_mask_hi;
+ break;
+ case PCH_PIC_INT_STATUS_LO:
+ val = s->intisr_lo & (~s->int_mask_lo);
+ break;
+ case PCH_PIC_INT_STATUS_HI:
+ val = s->intisr_hi & (~s->int_mask_hi);
+ break;
+ case PCH_PIC_INT_EDGE_LO:
+ val = s->intedge_lo;
+ break;
+ case PCH_PIC_INT_EDGE_HI:
+ val = s->intedge_hi;
+ break;
+ case PCH_PIC_INT_POL_LO:
+ val = s->int_polarity_lo;
+ break;
+ case PCH_PIC_INT_POL_HI:
+ val = s->int_polarity_hi;
+ break;
+ case PCH_PIC_HTMSI_EN_LO:
+ val = s->htmsi_en_lo;
+ break;
+ case PCH_PIC_HTMSI_EN_HI:
+ val = s->htmsi_en_hi;
+ break;
+ case PCH_PIC_AUTO_CTRL0_LO:
+ case PCH_PIC_AUTO_CTRL0_HI:
+ case PCH_PIC_AUTO_CTRL1_LO:
+ case PCH_PIC_AUTO_CTRL1_HI:
+ break;
+ default:
+ break;
+ }
+
+ trace_loongarch_pch_pic_readw(size, (uint32_t)addr, val);
+ return val;
+}
+
+static void loongarch_pch_pic_writew(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ uint32_t offset, old;
+ offset = addr & 0xfff;
+
+ trace_loongarch_pch_pic_writew(size, (uint32_t)addr, data);
+
+ switch (offset) {
+ case PCH_PIC_INT_MASK_LO:
+ old = s->int_mask_lo;
+ s->int_mask_lo = data;
+ if (old & ~data) {
+ pch_pic_update_irq(s, (old & ~data), 1, 0);
+ } else if (~old & data) {
+ pch_pic_update_irq(s, (~old & data), 0, 0);
+ }
+ break;
+ case PCH_PIC_INT_MASK_HI:
+ old = s->int_mask_hi;
+ s->int_mask_hi = data;
+ if (old & ~data) {
+ pch_pic_update_irq(s, (old & ~data), 1, 1);
+ } else if (~old & data) {
+ pch_pic_update_irq(s, (~old & data), 0, 1);
+ }
+ break;
+ case PCH_PIC_INT_STATUS_LO:
+ s->intisr_lo = data;
+ break;
+ case PCH_PIC_INT_STATUS_HI:
+ s->intisr_hi = data;
+ break;
+ case PCH_PIC_INT_EDGE_LO:
+ s->intedge_lo = data;
+ break;
+ case PCH_PIC_INT_EDGE_HI:
+ s->intedge_hi = data;
+ break;
+ case PCH_PIC_INT_CLEAR_LO:
+ if (s->intedge_lo & data) {
+ s->intirr_lo &= (~data);
+ pch_pic_update_irq(s, data, 0, 0);
+ s->intisr_lo &= (~data);
+ }
+ break;
+ case PCH_PIC_INT_CLEAR_HI:
+ if (s->intedge_hi & data) {
+ s->intirr_hi &= (~data);
+ pch_pic_update_irq(s, data, 0, 1);
+ s->intisr_hi &= (~data);
+ }
+ break;
+ case PCH_PIC_INT_POL_LO:
+ s->int_polarity_lo = data;
+ break;
+ case PCH_PIC_INT_POL_HI:
+ s->int_polarity_hi = data;
+ break;
+ case PCH_PIC_HTMSI_EN_LO:
+ s->htmsi_en_lo = data;
+ break;
+ case PCH_PIC_HTMSI_EN_HI:
+ s->htmsi_en_hi = data;
+ break;
+ case PCH_PIC_AUTO_CTRL0_LO:
+ case PCH_PIC_AUTO_CTRL0_HI:
+ case PCH_PIC_AUTO_CTRL1_LO:
+ case PCH_PIC_AUTO_CTRL1_HI:
+ break;
+ default:
+ break;
+ }
+}
+
+static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ uint64_t val = 0;
+ uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
+ int64_t offset_tmp;
+
+ if (offset >= PCH_PIC_HTMSI_VEC_OFFSET) {
+ offset_tmp = offset - PCH_PIC_HTMSI_VEC_OFFSET;
+ if (offset_tmp >= 0 && offset_tmp < 64) {
+ val = s->htmsi_vector[offset_tmp];
+ }
+ } else if (offset >= PCH_PIC_ROUTE_ENTRY_OFFSET) {
+ offset_tmp = offset - PCH_PIC_ROUTE_ENTRY_OFFSET;
+ if (offset_tmp >= 0 && offset_tmp < 64) {
+ val = s->route_entry[offset_tmp];
+ }
+ }
+
+ trace_loongarch_pch_pic_readb(size, (uint32_t)addr, val);
+ return val;
+}
+
+static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ int32_t offset_tmp;
+ uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
+
+ trace_loongarch_pch_pic_writeb(size, (uint32_t)addr, data);
+
+ if (offset >= PCH_PIC_HTMSI_VEC_OFFSET) {
+ offset_tmp = offset - PCH_PIC_HTMSI_VEC_OFFSET;
+ if (offset_tmp >= 0 && offset_tmp < 64) {
+ s->htmsi_vector[offset_tmp] = (uint8_t)(data & 0xff);
+ }
+ } else if (offset >= PCH_PIC_ROUTE_ENTRY_OFFSET) {
+ offset_tmp = offset - PCH_PIC_ROUTE_ENTRY_OFFSET;
+ if (offset_tmp >= 0 && offset_tmp < 64) {
+ s->route_entry[offset_tmp] = (uint8_t)(data & 0xff);
+ }
+ }
+}
+
+static const MemoryRegionOps loongarch_pch_pic_reg32_ops = {
+ .read = loongarch_pch_pic_readw,
+ .write = loongarch_pch_pic_writew,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
+ .read = loongarch_pch_pic_readb,
+ .write = loongarch_pch_pic_writeb,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void loongarch_pch_pic_reset(DeviceState *d)
+{
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
+ int i;
+
+ s->int_mask_lo = -1;
+ s->int_mask_hi = -1;
+ s->htmsi_en_lo = 0x0;
+ s->htmsi_en_hi = 0x0;
+ s->intedge_lo = 0x0;
+ s->intedge_hi = 0x0;
+ s->intclr_lo = 0x0;
+ s->intclr_hi = 0x0;
+ s->auto_crtl0_lo = 0x0;
+ s->auto_crtl0_hi = 0x0;
+ s->auto_crtl1_lo = 0x0;
+ s->auto_crtl1_hi = 0x0;
+ for (i = 0; i < 64; i++) {
+ s->route_entry[i] = 0x1;
+ s->htmsi_vector[i] = 0x0;
+ }
+ s->intirr_lo = 0x0;
+ s->intirr_hi = 0x0;
+ s->intisr_lo = 0x0;
+ s->intisr_hi = 0x0;
+ s->last_intirr_lo = 0x0;
+ s->last_intirr_hi = 0x0;
+ s->int_polarity_lo = 0x0;
+ s->int_polarity_hi = 0x0;
+}
+
+static void loongarch_pch_pic_init(Object *obj)
+{
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ int i;
+
+ memory_region_init_io(&s->iomem32, obj, &loongarch_pch_pic_reg32_ops,
+ s, TYPE_LOONGARCH_PCH_PIC, 0x1000);
+ memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
+ s, TYPE_LOONGARCH_PCH_PIC, 0x140);
+ sysbus_init_mmio(sbd, &s->iomem32);
+ sysbus_init_mmio(sbd, &s->iomem8);
+
+ for (i = 0; i < PCH_PIC_IRQ_NUM; i++) {
+ sysbus_init_irq(sbd, &s->parent_irq[i]);
+ }
+ qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
+}
+
+static const VMStateDescription vmstate_loongarch_pch_pic = {
+ .name = TYPE_LOONGARCH_PCH_PIC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(int_mask_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(int_mask_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(htmsi_en_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(htmsi_en_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(intedge_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(intedge_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(intclr_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(intclr_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(auto_crtl0_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(auto_crtl0_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(auto_crtl1_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(auto_crtl1_hi, LoongArchPCHPIC),
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
+ VMSTATE_UINT32(last_intirr_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(last_intirr_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(intirr_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(intirr_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(intisr_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(intisr_hi, LoongArchPCHPIC),
+ VMSTATE_UINT32(int_polarity_lo, LoongArchPCHPIC),
+ VMSTATE_UINT32(int_polarity_hi, LoongArchPCHPIC),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = loongarch_pch_pic_reset;
+ dc->vmsd = &vmstate_loongarch_pch_pic;
+}
+
+static const TypeInfo loongarch_pch_pic_info = {
+ .name = TYPE_LOONGARCH_PCH_PIC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LoongArchPCHPIC),
+ .instance_init = loongarch_pch_pic_init,
+ .class_init = loongarch_pch_pic_class_init,
+};
+
+static void loongarch_pch_pic_register_types(void)
+{
+ type_register_static(&loongarch_pch_pic_info);
+}
+
+type_init(loongarch_pch_pic_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 14c0834c67..cf08816547 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -61,3 +61,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 55f2f3a8b6..ec42cfd3d5 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -250,3 +250,10 @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
# loongarch_ipi.c
loongarch_ipi_read(unsigned size, uint64_t addr, unsigned long val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
loongarch_ipi_write(unsigned size, uint64_t addr, unsigned long val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
+
+# loongarch_pch_pic.c
+pch_pic_irq_handler(int irq, int level) "irq %d level %d"
+loongarch_pch_pic_readw(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
+loongarch_pch_pic_writew(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
+loongarch_pch_pic_readb(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
+loongarch_pch_pic_writeb(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 1591574397..c2b8046b94 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -2,3 +2,4 @@ config LOONGSON3_LS7A
bool
select PCI_EXPRESS_7A
select LOONGARCH_IPI
+ select LOONGARCH_PCH_PIC
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
new file mode 100644
index 0000000000..3c2a5ed3eb
--- /dev/null
+++ b/include/hw/intc/loongarch_pch_pic.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch 7A1000 I/O interrupt controller definitions
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
+DECLARE_INSTANCE_CHECKER(struct LoongArchPCHPIC, LOONGARCH_PCH_PIC,
+ TYPE_LOONGARCH_PCH_PIC)
+
+#define PCH_PIC_IRQ_START 0
+#define PCH_PIC_IRQ_END 63
+#define PCH_PIC_IRQ_NUM 64
+#define PCH_PIC_INT_ID_VAL 0x7000000UL
+#define PCH_PIC_INT_ID_NUM 0x3f0001UL
+
+#define PCH_PIC_INT_ID_LO 0x00
+#define PCH_PIC_INT_ID_HI 0x04
+#define PCH_PIC_INT_MASK_LO 0x20
+#define PCH_PIC_INT_MASK_HI 0x24
+#define PCH_PIC_HTMSI_EN_LO 0x40
+#define PCH_PIC_HTMSI_EN_HI 0x44
+#define PCH_PIC_INT_EDGE_LO 0x60
+#define PCH_PIC_INT_EDGE_HI 0x64
+#define PCH_PIC_INT_CLEAR_LO 0x80
+#define PCH_PIC_INT_CLEAR_HI 0x84
+#define PCH_PIC_AUTO_CTRL0_LO 0xc0
+#define PCH_PIC_AUTO_CTRL0_HI 0xc4
+#define PCH_PIC_AUTO_CTRL1_LO 0xe0
+#define PCH_PIC_AUTO_CTRL1_HI 0xe4
+#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
+#define PCH_PIC_ROUTE_ENTRY_END 0x13f
+#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
+#define PCH_PIC_HTMSI_VEC_END 0x23f
+#define PCH_PIC_INT_STATUS_LO 0x3a0
+#define PCH_PIC_INT_STATUS_HI 0x3a4
+#define PCH_PIC_INT_POL_LO 0x3e0
+#define PCH_PIC_INT_POL_HI 0x3e4
+
+typedef struct LoongArchPCHPIC {
+ SysBusDevice parent_obj;
+ qemu_irq parent_irq[64];
+ uint32_t int_mask_lo; /*0x020 interrupt mask register*/
+ uint32_t int_mask_hi;
+ uint32_t htmsi_en_lo; /*0x040 1=msi*/
+ uint32_t htmsi_en_hi;
+ uint32_t intedge_lo; /*0x060 edge=1 level =0*/
+ uint32_t intedge_hi; /*0x060 edge=1 level =0*/
+ uint32_t intclr_lo; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
+ uint32_t intclr_hi; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
+ uint32_t auto_crtl0_lo; /*0x0c0*/
+ uint32_t auto_crtl0_hi; /*0x0c0*/
+ uint32_t auto_crtl1_lo; /*0x0e0*/
+ uint32_t auto_crtl1_hi; /*0x0e0*/
+ uint32_t last_intirr_lo; /* edge detection */
+ uint32_t last_intirr_hi; /* edge detection */
+ uint32_t intirr_lo; /* 0x380 interrupt request register */
+ uint32_t intirr_hi; /* 0x380 interrupt request register */
+ uint32_t intisr_lo; /* 0x3a0 interrupt service register */
+ uint32_t intisr_hi; /* 0x3a0 interrupt service register */
+ /*
+ * 0x3e0 interrupt level polarity selection
+ * register 0 for high level trigger
+ */
+ uint32_t int_polarity_lo;
+ uint32_t int_polarity_hi;
+
+ uint8_t route_entry[64]; /*0x100 - 0x138*/
+ uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
+
+ MemoryRegion iomem32;
+ MemoryRegion iomem8;
+} LoongArchPCHPIC;
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 18/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
2022-01-08 9:14 ` [RFC PATCH v4 18/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
@ 2022-01-15 13:41 ` Mark Cave-Ayland
0 siblings, 0 replies; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 13:41 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: philmd, richard.henderson, Song Gao
On 08/01/2022 09:14, Xiaojuan Yang wrote:
> This patch realize the PCH-PIC interrupt controller.
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> hw/intc/Kconfig | 4 +
> hw/intc/loongarch_pch_pic.c | 428 ++++++++++++++++++++++++++++
> hw/intc/meson.build | 1 +
> hw/intc/trace-events | 7 +
> hw/loongarch/Kconfig | 1 +
> include/hw/intc/loongarch_pch_pic.h | 74 +++++
> 6 files changed, 515 insertions(+)
> create mode 100644 hw/intc/loongarch_pch_pic.c
> create mode 100644 include/hw/intc/loongarch_pch_pic.h
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 9f5aaffb6f..928db92bb4 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -81,3 +81,7 @@ config M68K_IRQC
>
> config LOONGARCH_IPI
> bool
> +
> +config LOONGARCH_PCH_PIC
> + bool
> + select UNIMP
> diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
> new file mode 100644
> index 0000000000..4da78b5bc8
> --- /dev/null
> +++ b/hw/intc/loongarch_pch_pic.c
> @@ -0,0 +1,428 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU Loongson 7A1000 I/O interrupt controller.
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "hw/irq.h"
> +#include "hw/intc/loongarch_pch_pic.h"
> +#include "migration/vmstate.h"
> +#include "trace.h"
> +
> +static void pch_pic_update_irq(LoongArchPCHPIC *s, uint32_t mask,
> + int level, int hi)
> +{
> + uint32_t val, irq;
> +
> + if (level == 1) {
> + if (hi) {
> + val = mask & s->intirr_hi & (~s->int_mask_hi);
> + irq = find_first_bit((void *)&val, 32);
> + if (irq != 32) {
> + s->intisr_hi |= 1ULL << irq;
> + qemu_set_irq(s->parent_irq[s->htmsi_vector[irq + 32]], 1);
> + }
> + } else {
> + val = mask & s->intirr_lo & (~s->int_mask_lo);
> + irq = find_first_bit((void *)&val, 32);
> + if (irq != 32) {
> + s->intisr_lo |= 1ULL << irq;
> + qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1);
> + }
> + }
> + } else {
> + if (hi) {
> + val = mask & s->intisr_hi;
> + irq = find_first_bit((void *)&val, 32);
> + if (irq != 32) {
> + s->intisr_hi &= ~(0x1ULL << irq);
> + qemu_set_irq(s->parent_irq[s->htmsi_vector[irq + 32]], 0);
> + }
> + } else {
> + val = mask & s->intisr_lo;
> + irq = find_first_bit((void *)&val, 32);
> + if (irq != 32) {
> + s->intisr_lo &= ~(0x1ULL << irq);
> + qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 0);
> + }
> + }
> + }
> +}
> +
> +static void pch_pic_irq_handler(void *opaque, int irq, int level)
> +{
> + LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
> + int hi = 0;
> + uint32_t mask;
> +
> + assert(irq < PCH_PIC_IRQ_NUM);
> + trace_pch_pic_irq_handler(irq, level);
> +
> + hi = (irq >= 32) ? 1 : 0;
> + if (hi) {
> + irq = irq - 32;
> + }
> +
> + mask = 1ULL << irq;
> +
> + if (hi) {
> + if (s->intedge_hi & mask) {
> + /* Edge triggered */
> + if (level) {
> + if ((s->last_intirr_hi & mask) == 0) {
> + s->intirr_hi |= mask;
> + }
> + s->last_intirr_hi |= mask;
> + } else {
> + s->last_intirr_hi &= ~mask;
> + }
> + } else {
> + /* Level triggered */
> + if (level) {
> + s->intirr_hi |= mask;
> + s->last_intirr_hi |= mask;
> + } else {
> + s->intirr_hi &= ~mask;
> + s->last_intirr_hi &= ~mask;
> + }
> + }
> + } else {
> + if (s->intedge_lo & mask) {
> + /* Edge triggered */
> + if (level) {
> + if ((s->last_intirr_lo & mask) == 0) {
> + s->intirr_lo |= mask;
> + }
> + s->last_intirr_lo |= mask;
> + } else {
> + s->last_intirr_lo &= ~mask;
> + }
> + } else {
> + /* Level triggered */
> + if (level) {
> + s->intirr_lo |= mask;
> + s->last_intirr_lo |= mask;
> + } else {
> + s->intirr_lo &= ~mask;
> + s->last_intirr_lo &= ~mask;
> + }
> +
> + }
> + }
> + pch_pic_update_irq(s, mask, level, hi);
> +}
> +
> +static uint64_t loongarch_pch_pic_readw(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
> + uint64_t val = 0;
> + uint32_t offset = addr & 0xfff;
> +
> + switch (offset) {
> + case PCH_PIC_INT_ID_LO:
> + val = PCH_PIC_INT_ID_VAL;
> + break;
> + case PCH_PIC_INT_ID_HI:
> + val = PCH_PIC_INT_ID_NUM;
> + break;
> + case PCH_PIC_INT_MASK_LO:
> + val = s->int_mask_lo;
> + break;
> + case PCH_PIC_INT_MASK_HI:
> + val = s->int_mask_hi;
> + break;
> + case PCH_PIC_INT_STATUS_LO:
> + val = s->intisr_lo & (~s->int_mask_lo);
> + break;
> + case PCH_PIC_INT_STATUS_HI:
> + val = s->intisr_hi & (~s->int_mask_hi);
> + break;
> + case PCH_PIC_INT_EDGE_LO:
> + val = s->intedge_lo;
> + break;
> + case PCH_PIC_INT_EDGE_HI:
> + val = s->intedge_hi;
> + break;
> + case PCH_PIC_INT_POL_LO:
> + val = s->int_polarity_lo;
> + break;
> + case PCH_PIC_INT_POL_HI:
> + val = s->int_polarity_hi;
> + break;
> + case PCH_PIC_HTMSI_EN_LO:
> + val = s->htmsi_en_lo;
> + break;
> + case PCH_PIC_HTMSI_EN_HI:
> + val = s->htmsi_en_hi;
> + break;
> + case PCH_PIC_AUTO_CTRL0_LO:
> + case PCH_PIC_AUTO_CTRL0_HI:
> + case PCH_PIC_AUTO_CTRL1_LO:
> + case PCH_PIC_AUTO_CTRL1_HI:
> + break;
> + default:
> + break;
> + }
> +
> + trace_loongarch_pch_pic_readw(size, (uint32_t)addr, val);
> + return val;
> +}
> +
> +static void loongarch_pch_pic_writew(void *opaque, hwaddr addr,
> + uint64_t data, unsigned size)
> +{
> + LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
> + uint32_t offset, old;
> + offset = addr & 0xfff;
> +
> + trace_loongarch_pch_pic_writew(size, (uint32_t)addr, data);
> +
> + switch (offset) {
> + case PCH_PIC_INT_MASK_LO:
> + old = s->int_mask_lo;
> + s->int_mask_lo = data;
> + if (old & ~data) {
> + pch_pic_update_irq(s, (old & ~data), 1, 0);
> + } else if (~old & data) {
> + pch_pic_update_irq(s, (~old & data), 0, 0);
> + }
> + break;
> + case PCH_PIC_INT_MASK_HI:
> + old = s->int_mask_hi;
> + s->int_mask_hi = data;
> + if (old & ~data) {
> + pch_pic_update_irq(s, (old & ~data), 1, 1);
> + } else if (~old & data) {
> + pch_pic_update_irq(s, (~old & data), 0, 1);
> + }
> + break;
> + case PCH_PIC_INT_STATUS_LO:
> + s->intisr_lo = data;
> + break;
> + case PCH_PIC_INT_STATUS_HI:
> + s->intisr_hi = data;
> + break;
> + case PCH_PIC_INT_EDGE_LO:
> + s->intedge_lo = data;
> + break;
> + case PCH_PIC_INT_EDGE_HI:
> + s->intedge_hi = data;
> + break;
> + case PCH_PIC_INT_CLEAR_LO:
> + if (s->intedge_lo & data) {
> + s->intirr_lo &= (~data);
> + pch_pic_update_irq(s, data, 0, 0);
> + s->intisr_lo &= (~data);
> + }
> + break;
> + case PCH_PIC_INT_CLEAR_HI:
> + if (s->intedge_hi & data) {
> + s->intirr_hi &= (~data);
> + pch_pic_update_irq(s, data, 0, 1);
> + s->intisr_hi &= (~data);
> + }
> + break;
> + case PCH_PIC_INT_POL_LO:
> + s->int_polarity_lo = data;
> + break;
> + case PCH_PIC_INT_POL_HI:
> + s->int_polarity_hi = data;
> + break;
> + case PCH_PIC_HTMSI_EN_LO:
> + s->htmsi_en_lo = data;
> + break;
> + case PCH_PIC_HTMSI_EN_HI:
> + s->htmsi_en_hi = data;
> + break;
> + case PCH_PIC_AUTO_CTRL0_LO:
> + case PCH_PIC_AUTO_CTRL0_HI:
> + case PCH_PIC_AUTO_CTRL1_LO:
> + case PCH_PIC_AUTO_CTRL1_HI:
> + break;
> + default:
> + break;
> + }
> +}
> +
> +static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
> + uint64_t val = 0;
> + uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
> + int64_t offset_tmp;
> +
> + if (offset >= PCH_PIC_HTMSI_VEC_OFFSET) {
> + offset_tmp = offset - PCH_PIC_HTMSI_VEC_OFFSET;
> + if (offset_tmp >= 0 && offset_tmp < 64) {
> + val = s->htmsi_vector[offset_tmp];
> + }
> + } else if (offset >= PCH_PIC_ROUTE_ENTRY_OFFSET) {
> + offset_tmp = offset - PCH_PIC_ROUTE_ENTRY_OFFSET;
> + if (offset_tmp >= 0 && offset_tmp < 64) {
> + val = s->route_entry[offset_tmp];
> + }
> + }
Can you convert this into a switch() so it is like the others (plus it makes it
easier to read):
switch (offset) {
case PCH_PIC_HTMSI_VEC_OFFSET ... PCH_PIC_HTMSI_VEC_END:
....
break;
case PCH_PIC_ROUTE_ENTRY_OFFSET ... PCH_PIC_ROUTE_ENTRY_END:
....
break;
}
> + trace_loongarch_pch_pic_readb(size, (uint32_t)addr, val);
> + return val;
> +}
> +
> +static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
> + uint64_t data, unsigned size)
> +{
> + LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
> + int32_t offset_tmp;
> + uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
> +
> + trace_loongarch_pch_pic_writeb(size, (uint32_t)addr, data);
> +
> + if (offset >= PCH_PIC_HTMSI_VEC_OFFSET) {
> + offset_tmp = offset - PCH_PIC_HTMSI_VEC_OFFSET;
> + if (offset_tmp >= 0 && offset_tmp < 64) {
> + s->htmsi_vector[offset_tmp] = (uint8_t)(data & 0xff);
> + }
> + } else if (offset >= PCH_PIC_ROUTE_ENTRY_OFFSET) {
> + offset_tmp = offset - PCH_PIC_ROUTE_ENTRY_OFFSET;
> + if (offset_tmp >= 0 && offset_tmp < 64) {
> + s->route_entry[offset_tmp] = (uint8_t)(data & 0xff);
> + }
> + }
> +}
> +
> +static const MemoryRegionOps loongarch_pch_pic_reg32_ops = {
> + .read = loongarch_pch_pic_readw,
> + .write = loongarch_pch_pic_writew,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 8,
> + },
> + .impl = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
> + .read = loongarch_pch_pic_readb,
> + .write = loongarch_pch_pic_writeb,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static void loongarch_pch_pic_reset(DeviceState *d)
> +{
> + LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
> + int i;
> +
> + s->int_mask_lo = -1;
> + s->int_mask_hi = -1;
> + s->htmsi_en_lo = 0x0;
> + s->htmsi_en_hi = 0x0;
> + s->intedge_lo = 0x0;
> + s->intedge_hi = 0x0;
> + s->intclr_lo = 0x0;
> + s->intclr_hi = 0x0;
> + s->auto_crtl0_lo = 0x0;
> + s->auto_crtl0_hi = 0x0;
> + s->auto_crtl1_lo = 0x0;
> + s->auto_crtl1_hi = 0x0;
> + for (i = 0; i < 64; i++) {
> + s->route_entry[i] = 0x1;
> + s->htmsi_vector[i] = 0x0;
> + }
> + s->intirr_lo = 0x0;
> + s->intirr_hi = 0x0;
> + s->intisr_lo = 0x0;
> + s->intisr_hi = 0x0;
> + s->last_intirr_lo = 0x0;
> + s->last_intirr_hi = 0x0;
> + s->int_polarity_lo = 0x0;
> + s->int_polarity_hi = 0x0;
> +}
> +
> +static void loongarch_pch_pic_init(Object *obj)
> +{
> + LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + int i;
> +
> + memory_region_init_io(&s->iomem32, obj, &loongarch_pch_pic_reg32_ops,
> + s, TYPE_LOONGARCH_PCH_PIC, 0x1000);
> + memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
> + s, TYPE_LOONGARCH_PCH_PIC, 0x140);
> + sysbus_init_mmio(sbd, &s->iomem32);
> + sysbus_init_mmio(sbd, &s->iomem8);
> +
> + for (i = 0; i < PCH_PIC_IRQ_NUM; i++) {
> + sysbus_init_irq(sbd, &s->parent_irq[i]);
> + }
> + qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
> +}
> +
> +static const VMStateDescription vmstate_loongarch_pch_pic = {
> + .name = TYPE_LOONGARCH_PCH_PIC,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(int_mask_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(int_mask_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(htmsi_en_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(htmsi_en_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(intedge_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(intedge_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(intclr_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(intclr_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(auto_crtl0_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(auto_crtl0_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(auto_crtl1_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(auto_crtl1_hi, LoongArchPCHPIC),
> + VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
> + VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
> + VMSTATE_UINT32(last_intirr_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(last_intirr_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(intirr_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(intirr_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(intisr_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(intisr_hi, LoongArchPCHPIC),
> + VMSTATE_UINT32(int_polarity_lo, LoongArchPCHPIC),
> + VMSTATE_UINT32(int_polarity_hi, LoongArchPCHPIC),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->reset = loongarch_pch_pic_reset;
> + dc->vmsd = &vmstate_loongarch_pch_pic;
> +}
> +
> +static const TypeInfo loongarch_pch_pic_info = {
> + .name = TYPE_LOONGARCH_PCH_PIC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(LoongArchPCHPIC),
> + .instance_init = loongarch_pch_pic_init,
> + .class_init = loongarch_pch_pic_class_init,
> +};
> +
> +static void loongarch_pch_pic_register_types(void)
> +{
> + type_register_static(&loongarch_pch_pic_info);
> +}
> +
> +type_init(loongarch_pch_pic_register_types)
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 14c0834c67..cf08816547 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -61,3 +61,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
> specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
> specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
> specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
> +specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
> index 55f2f3a8b6..ec42cfd3d5 100644
> --- a/hw/intc/trace-events
> +++ b/hw/intc/trace-events
> @@ -250,3 +250,10 @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
> # loongarch_ipi.c
> loongarch_ipi_read(unsigned size, uint64_t addr, unsigned long val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
> loongarch_ipi_write(unsigned size, uint64_t addr, unsigned long val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
> +
> +# loongarch_pch_pic.c
> +pch_pic_irq_handler(int irq, int level) "irq %d level %d"
> +loongarch_pch_pic_readw(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
> +loongarch_pch_pic_writew(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
> +loongarch_pch_pic_readb(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
> +loongarch_pch_pic_writeb(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
> diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
> index 1591574397..c2b8046b94 100644
> --- a/hw/loongarch/Kconfig
> +++ b/hw/loongarch/Kconfig
> @@ -2,3 +2,4 @@ config LOONGSON3_LS7A
> bool
> select PCI_EXPRESS_7A
> select LOONGARCH_IPI
> + select LOONGARCH_PCH_PIC
> diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
> new file mode 100644
> index 0000000000..3c2a5ed3eb
> --- /dev/null
> +++ b/include/hw/intc/loongarch_pch_pic.h
> @@ -0,0 +1,74 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch 7A1000 I/O interrupt controller definitions
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
> +DECLARE_INSTANCE_CHECKER(struct LoongArchPCHPIC, LOONGARCH_PCH_PIC,
> + TYPE_LOONGARCH_PCH_PIC)
> +
> +#define PCH_PIC_IRQ_START 0
> +#define PCH_PIC_IRQ_END 63
> +#define PCH_PIC_IRQ_NUM 64
> +#define PCH_PIC_INT_ID_VAL 0x7000000UL
> +#define PCH_PIC_INT_ID_NUM 0x3f0001UL
> +
> +#define PCH_PIC_INT_ID_LO 0x00
> +#define PCH_PIC_INT_ID_HI 0x04
> +#define PCH_PIC_INT_MASK_LO 0x20
> +#define PCH_PIC_INT_MASK_HI 0x24
> +#define PCH_PIC_HTMSI_EN_LO 0x40
> +#define PCH_PIC_HTMSI_EN_HI 0x44
> +#define PCH_PIC_INT_EDGE_LO 0x60
> +#define PCH_PIC_INT_EDGE_HI 0x64
> +#define PCH_PIC_INT_CLEAR_LO 0x80
> +#define PCH_PIC_INT_CLEAR_HI 0x84
> +#define PCH_PIC_AUTO_CTRL0_LO 0xc0
> +#define PCH_PIC_AUTO_CTRL0_HI 0xc4
> +#define PCH_PIC_AUTO_CTRL1_LO 0xe0
> +#define PCH_PIC_AUTO_CTRL1_HI 0xe4
> +#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
> +#define PCH_PIC_ROUTE_ENTRY_END 0x13f
> +#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
> +#define PCH_PIC_HTMSI_VEC_END 0x23f
> +#define PCH_PIC_INT_STATUS_LO 0x3a0
> +#define PCH_PIC_INT_STATUS_HI 0x3a4
> +#define PCH_PIC_INT_POL_LO 0x3e0
> +#define PCH_PIC_INT_POL_HI 0x3e4
> +
> +typedef struct LoongArchPCHPIC {
> + SysBusDevice parent_obj;
> + qemu_irq parent_irq[64];
> + uint32_t int_mask_lo; /*0x020 interrupt mask register*/
> + uint32_t int_mask_hi;
> + uint32_t htmsi_en_lo; /*0x040 1=msi*/
> + uint32_t htmsi_en_hi;
> + uint32_t intedge_lo; /*0x060 edge=1 level =0*/
> + uint32_t intedge_hi; /*0x060 edge=1 level =0*/
> + uint32_t intclr_lo; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
> + uint32_t intclr_hi; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
> + uint32_t auto_crtl0_lo; /*0x0c0*/
> + uint32_t auto_crtl0_hi; /*0x0c0*/
> + uint32_t auto_crtl1_lo; /*0x0e0*/
> + uint32_t auto_crtl1_hi; /*0x0e0*/
> + uint32_t last_intirr_lo; /* edge detection */
> + uint32_t last_intirr_hi; /* edge detection */
> + uint32_t intirr_lo; /* 0x380 interrupt request register */
> + uint32_t intirr_hi; /* 0x380 interrupt request register */
> + uint32_t intisr_lo; /* 0x3a0 interrupt service register */
> + uint32_t intisr_hi; /* 0x3a0 interrupt service register */
> + /*
> + * 0x3e0 interrupt level polarity selection
> + * register 0 for high level trigger
> + */
> + uint32_t int_polarity_lo;
> + uint32_t int_polarity_hi;
> +
> + uint8_t route_entry[64]; /*0x100 - 0x138*/
> + uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
> +
> + MemoryRegion iomem32;
> + MemoryRegion iomem8;
> +} LoongArchPCHPIC;
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 19/30] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (17 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 18/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 20/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
` (12 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 75 +++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/intc/trace-events | 3 ++
hw/loongarch/Kconfig | 1 +
include/hw/intc/loongarch_pch_msi.h | 21 ++++++++
6 files changed, 106 insertions(+)
create mode 100644 hw/intc/loongarch_pch_msi.c
create mode 100644 include/hw/intc/loongarch_pch_msi.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 928db92bb4..727a3bb3e6 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -85,3 +85,8 @@ config LOONGARCH_IPI
config LOONGARCH_PCH_PIC
bool
select UNIMP
+
+config LOONGARCH_PCH_MSI
+ select MSI_NONBROKEN
+ bool
+ select UNIMP
diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
new file mode 100644
index 0000000000..57a894f3e5
--- /dev/null
+++ b/hw/intc/loongarch_pch_msi.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU Loongson 7A1000 msi interrupt controller.
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/intc/loongarch_pch_msi.h"
+#include "hw/intc/loongarch_pch_pic.h"
+#include "hw/pci/msi.h"
+#include "hw/misc/unimp.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return 0;
+}
+
+static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
+ int irq_num = val & 0xff;
+
+ trace_loongarch_msi_set_irq(irq_num);
+ qemu_set_irq(s->pch_msi_irq[irq_num - PCH_PIC_IRQ_NUM], 1);
+}
+
+static const MemoryRegionOps loongarch_pch_msi_ops = {
+ .read = loongarch_msi_mem_read,
+ .write = loongarch_msi_mem_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void pch_msi_irq_handler(void *opaque, int irq, int level)
+{
+ LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
+
+ qemu_set_irq(s->pch_msi_irq[irq], level);
+}
+
+static void loongarch_pch_msi_init(Object *obj)
+{
+ LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ int i;
+
+ memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
+ s, TYPE_LOONGARCH_PCH_MSI, 0x8);
+ sysbus_init_mmio(sbd, &s->msi_mmio);
+ msi_nonbroken = true;
+
+ for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
+ sysbus_init_irq(sbd, &s->pch_msi_irq[i]);
+ }
+ qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
+}
+
+static const TypeInfo loongarch_pch_msi_info = {
+ .name = TYPE_LOONGARCH_PCH_MSI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LoongArchPCHMSI),
+ .instance_init = loongarch_pch_msi_init,
+};
+
+static void loongarch_pch_msi_register_types(void)
+{
+ type_register_static(&loongarch_pch_msi_info);
+}
+
+type_init(loongarch_pch_msi_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index cf08816547..c679223420 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -62,3 +62,4 @@ specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index ec42cfd3d5..6d2d041766 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -257,3 +257,6 @@ loongarch_pch_pic_readw(unsigned size, uint32_t addr, unsigned long val) "size:
loongarch_pch_pic_writew(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
loongarch_pch_pic_readb(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
loongarch_pch_pic_writeb(unsigned size, uint32_t addr, unsigned long val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx64
+
+# loongarch_pch_msi.c
+loongarch_msi_set_irq(int irq_num) "set msi irq %d"
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index c2b8046b94..cd38d03a19 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -3,3 +3,4 @@ config LOONGSON3_LS7A
select PCI_EXPRESS_7A
select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
+ select LOONGARCH_PCH_MSI
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h
new file mode 100644
index 0000000000..68009d4b4a
--- /dev/null
+++ b/include/hw/intc/loongarch_pch_msi.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch 7A1000 I/O interrupt controller definitions
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
+DECLARE_INSTANCE_CHECKER(struct LoongArchPCHMSI, LOONGARCH_PCH_MSI,
+ TYPE_LOONGARCH_PCH_MSI)
+
+/* Msi irq start start from 64 to 255 */
+#define PCH_MSI_IRQ_START 64
+#define PCH_MSI_IRQ_END 255
+#define PCH_MSI_IRQ_NUM 192
+
+typedef struct LoongArchPCHMSI {
+ SysBusDevice parent_obj;
+ qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
+ MemoryRegion msi_mmio;
+} LoongArchPCHMSI;
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 20/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (18 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 19/30] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-15 13:49 ` Mark Cave-Ayland
2022-01-08 9:14 ` [RFC PATCH v4 21/30] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
` (11 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_extioi.c | 376 +++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/intc/trace-events | 11 +
hw/loongarch/Kconfig | 1 +
include/hw/intc/loongarch_extioi.h | 69 ++++++
6 files changed, 461 insertions(+)
create mode 100644 hw/intc/loongarch_extioi.c
create mode 100644 include/hw/intc/loongarch_extioi.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 727a3bb3e6..ecdf821205 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -90,3 +90,6 @@ config LOONGARCH_PCH_MSI
select MSI_NONBROKEN
bool
select UNIMP
+
+config LOONGARCH_EXTIOI
+ bool
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
new file mode 100644
index 0000000000..b9a91f77b3
--- /dev/null
+++ b/hw/intc/loongarch_extioi.c
@@ -0,0 +1,376 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson 3A5000 ext interrupt controller emulation
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/module.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "hw/intc/loongarch_extioi.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+static void extioi_update_irq(void *opaque, int irq_num, int level)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ uint8_t ipnum, cpu;
+ unsigned long found1, found2;
+
+ ipnum = s->sw_ipmap[irq_num];
+ cpu = s->sw_coremap[irq_num];
+ if (level == 1) {
+ if (test_bit(irq_num, (void *)s->enable) == false) {
+ return;
+ }
+ bitmap_set((void *)s->coreisr[cpu], irq_num, 1);
+ found1 = find_next_bit((void *)&(s->sw_ipisr[cpu][ipnum]),
+ EXTIOI_IRQS, 0);
+ bitmap_set((void *)&(s->sw_ipisr[cpu][ipnum]), irq_num, 1);
+
+ if (found1 >= EXTIOI_IRQS) {
+ qemu_set_irq(s->parent_irq[cpu][ipnum], level);
+ }
+ } else {
+ bitmap_clear((void *)s->coreisr[cpu], irq_num, 1);
+ found1 = find_next_bit((void *)&(s->sw_ipisr[cpu][ipnum]),
+ EXTIOI_IRQS, 0);
+ bitmap_clear((void *)&(s->sw_ipisr[cpu][ipnum]), irq_num, 1);
+ found2 = find_next_bit((void *)&(s->sw_ipisr[cpu][ipnum]),
+ EXTIOI_IRQS, 0);
+
+ if ((found1 < EXTIOI_IRQS) && (found2 >= EXTIOI_IRQS)) {
+ qemu_set_irq(s->parent_irq[cpu][ipnum], level);
+ }
+ }
+}
+
+static void extioi_setirq(void *opaque, int irq, int level)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ trace_extioi_setirq(irq, level);
+ extioi_update_irq(s, irq, level);
+}
+
+static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ unsigned long offset = addr & 0xffff;
+ uint32_t ret, index;
+ int cpu;
+
+ if ((offset >= EXTIOI_NODETYPE_START) && (offset < EXTIOI_NODETYPE_END)) {
+ index = (offset - EXTIOI_NODETYPE_START) >> 2;
+ ret = s->nodetype[index];
+ } else if ((offset >= EXTIOI_BOUNCE_START) &&
+ (offset < EXTIOI_BOUNCE_END)) {
+ index = (offset - EXTIOI_BOUNCE_START) >> 2;
+ ret = s->bounce[index];
+ } else if ((offset >= EXTIOI_COREISR_START) &&
+ (offset < EXTIOI_COREISR_END)) {
+ index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
+ cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+ ret = s->coreisr[cpu][index];
+ }
+
+ trace_loongarch_extioi_readw((uint32_t)addr, ret);
+ return ret;
+}
+
+static void extioi_writew(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ int cpu, index;
+ uint32_t offset, old_data, i, j, bits;
+
+ offset = addr & 0xffff;
+ trace_loongarch_extioi_writew(size, (uint32_t)addr, val);
+
+ if ((offset >= EXTIOI_NODETYPE_START) && (offset < EXTIOI_NODETYPE_END)) {
+ index = (offset - EXTIOI_NODETYPE_START) >> 2;
+ s->nodetype[index] = val;
+ } else if ((offset >= EXTIOI_BOUNCE_START) &&
+ (offset < EXTIOI_BOUNCE_END)) {
+ index = (offset - EXTIOI_BOUNCE_START) >> 2;
+ s->bounce[index] = val;
+ } else if ((offset >= EXTIOI_COREISR_START) &&
+ (offset < EXTIOI_COREISR_END)) {
+ index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
+ cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+
+ /* Ext_core_ioisr */
+ old_data = s->coreisr[cpu][index];
+ s->coreisr[cpu][index] = old_data & ~val;
+
+ if (old_data != s->coreisr[cpu][index]) {
+ bits = size * 8;
+ while ((i = find_first_bit((void *)&val, bits)) != bits) {
+ j = test_bit(i, (unsigned long *)&old_data);
+ if (j) {
+ extioi_update_irq(s, i + index * 32, 0);
+ }
+ clear_bit(i, (void *)&val);
+ }
+ }
+ }
+}
+
+static uint64_t extioi_enable_read(void *opaque, hwaddr addr, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ uint8_t ret;
+
+ if (addr < EXTIOI_ENABLE_END) {
+ ret = s->enable[addr];
+ }
+
+ trace_loongarch_extioi_enable_read((uint8_t)addr, ret);
+ return ret;
+}
+
+static void extioi_enable_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ uint8_t old_data, val = value & 0xff;
+ int i, level;
+
+ trace_loongarch_extioi_enable_write(size, (uint8_t)addr, val);
+ if (addr < EXTIOI_ENABLE_END) {
+ old_data = s->enable[addr];
+
+ if (old_data != val) {
+ s->enable[addr] = val;
+ old_data = old_data ^ val;
+
+ while ((i = find_first_bit((void *)&old_data, 8)) != 8) {
+ level = test_bit(i, (unsigned long *)&val);
+ extioi_update_irq(s, i + addr * 8, level);
+ clear_bit(i, (void *)&old_data);
+ }
+ }
+ }
+}
+
+static uint64_t extioi_ipmap_read(void *opaque, hwaddr addr, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ uint8_t ret;
+
+ if (addr < EXTIOI_IPMAP_END) {
+ ret = s->ipmap[addr];
+ }
+
+ trace_loongarch_extioi_ipmap_read((uint8_t)addr, ret);
+ return ret;
+}
+
+static void extioi_ipmap_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ uint8_t val = value & 0xff;
+ int i, ipnum, irqnum;
+
+ trace_loongarch_extioi_ipmap_write(size, (uint8_t)addr, val);
+ if (addr < EXTIOI_IPMAP_END) {
+ s->ipmap[addr] = val;
+
+ /* Routing in groups of 32 interrupt */
+ ipnum = find_first_bit((void *)&val, 4);
+ for (i = 0; i < 32; i++) {
+ irqnum = addr * 32 + i;
+ if (ipnum != 4) {
+ s->sw_ipmap[irqnum] = ipnum;
+ } else {
+ s->sw_ipmap[irqnum] = 0;
+ }
+ }
+ }
+}
+
+static uint64_t extioi_coremap_read(void *opaque, hwaddr addr, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ uint8_t ret;
+
+ if (addr < EXTIOI_COREMAP_END) {
+ ret = s->coremap[addr];
+ }
+
+ trace_loongarch_extioi_coremap_read((uint8_t)addr, ret);
+ return ret;
+}
+
+static void extioi_coremap_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ uint8_t val = value & 0xff;
+ int cpu;
+
+ trace_loongarch_extioi_coremap_write(size, (uint8_t)addr, val);
+ if (addr < EXTIOI_COREMAP_END) {
+ s->coremap[addr] = val;
+
+ /* Only support 1 node now only handle the core map*/
+ if (val) {
+ cpu = find_first_bit((void *)&val, 4);
+ if (cpu != 4) {
+ s->sw_coremap[addr] = cpu;
+ }
+ }
+ }
+}
+
+static const MemoryRegionOps extioi_reg32_ops = {
+ .read = extioi_readw,
+ .write = extioi_writew,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static const MemoryRegionOps extioi_enable_ops = {
+ .read = extioi_enable_read,
+ .write = extioi_enable_write,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 1,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static const MemoryRegionOps extioi_ipmap_ops = {
+ .read = extioi_ipmap_read,
+ .write = extioi_ipmap_write,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 1,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static const MemoryRegionOps extioi_coremap_ops = {
+ .read = extioi_coremap_read,
+ .write = extioi_coremap_write,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 1,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void loongarch_extioi_realize(DeviceState *dev, Error **errp)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev);
+ MachineState *ms = MACHINE(qdev_get_machine());
+ int cpu;
+
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+ memory_region_init_io(&s->mmio_reg32[cpu], OBJECT(s),
+ &extioi_reg32_ops, s, TYPE_LOONGARCH_EXTIOI,
+ 0x900);
+ /*
+ * kernel use anysend to handle enable reg.
+ * need support different size handle.
+ */
+ memory_region_init_io(&s->mmio_enable[cpu], OBJECT(s),
+ &extioi_enable_ops, s, TYPE_LOONGARCH_EXTIOI,
+ 0x18);
+ memory_region_init_io(&s->mmio_ipmap[cpu], OBJECT(s),
+ &extioi_ipmap_ops, s, TYPE_LOONGARCH_EXTIOI,
+ 0x8);
+ memory_region_init_io(&s->mmio_coremap[cpu], OBJECT(s),
+ &extioi_coremap_ops, s, TYPE_LOONGARCH_EXTIOI,
+ 0x100);
+ }
+}
+
+static const VMStateDescription vmstate_ext_sw_ipisr = {
+ .name = "ext_sw_ipisr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(irq, ext_sw_ipisr, EXTIOI_IRQS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_loongarch_extioi = {
+ .name = TYPE_LOONGARCH_EXTIOI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
+ VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, MAX_CORES,
+ EXTIOI_IRQS_GROUP_COUNT),
+ VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
+ EXTIOI_IRQS_NODETYPE_COUNT / 2),
+ VMSTATE_UINT8_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 8),
+ VMSTATE_UINT8_ARRAY(ipmap, LoongArchExtIOI, 8),
+ VMSTATE_UINT8_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS),
+ VMSTATE_UINT8_ARRAY(sw_ipmap, LoongArchExtIOI, EXTIOI_IRQS),
+ VMSTATE_UINT8_ARRAY(sw_coremap, LoongArchExtIOI, EXTIOI_IRQS),
+ VMSTATE_STRUCT_2DARRAY(sw_ipisr, LoongArchExtIOI, MAX_CORES,
+ LS3A_INTC_IP, 1, vmstate_ext_sw_ipisr,
+ ext_sw_ipisr),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void loongarch_extioi_instance_init(Object *obj)
+{
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj);
+ MachineState *ms = MACHINE(qdev_get_machine());
+ int i, cpu, pin;
+
+ for (i = 0; i < EXTIOI_IRQS; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
+ }
+
+ qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
+
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+ sysbus_init_mmio(dev, &s->mmio_reg32[cpu]);
+ sysbus_init_mmio(dev, &s->mmio_enable[cpu]);
+ sysbus_init_mmio(dev, &s->mmio_ipmap[cpu]);
+ sysbus_init_mmio(dev, &s->mmio_coremap[cpu]);
+ for (pin = 0; pin < LS3A_INTC_IP; pin++) {
+ qdev_init_gpio_out(DEVICE(obj), &s->parent_irq[cpu][pin], 1);
+ }
+ }
+}
+
+static void loongarch_extioi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_loongarch_extioi;
+ dc->realize = loongarch_extioi_realize;
+}
+
+static const TypeInfo loongarch_extioi_info = {
+ .name = TYPE_LOONGARCH_EXTIOI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = loongarch_extioi_instance_init,
+ .instance_size = sizeof(struct LoongArchExtIOI),
+ .class_init = loongarch_extioi_class_init,
+};
+
+static void loongarch_extioi_register_types(void)
+{
+ type_register_static(&loongarch_extioi_info);
+}
+
+type_init(loongarch_extioi_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index c679223420..d09eb6b81d 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -63,3 +63,4 @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 6d2d041766..8f7854196b 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -260,3 +260,14 @@ loongarch_pch_pic_writeb(unsigned size, uint32_t addr, unsigned long val) "size:
# loongarch_pch_msi.c
loongarch_msi_set_irq(int irq_num) "set msi irq %d"
+
+# loongarch_extioi.c
+extioi_setirq(int irq, int level) "set extirq irq %d level %d"
+loongarch_extioi_readw(uint32_t addr, uint32_t val) "addr: 0x%"PRIx32 "val: 0x%" PRIx32
+loongarch_extioi_writew(unsigned size, uint32_t addr, uint32_t val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx32
+loongarch_extioi_enable_read(uint8_t addr, uint8_t val) "addr: 0x%"PRIu8 "val: 0x%" PRIu8
+loongarch_extioi_enable_write(unsigned size, uint8_t addr, uint8_t val) "size: %u addr: 0x%"PRIu8 "val: 0x%" PRIu8
+loongarch_extioi_ipmap_read(uint8_t addr, uint8_t val) "addr: 0x%"PRIu8 "val: 0x%" PRIu8
+loongarch_extioi_ipmap_write(unsigned size, uint8_t addr, uint8_t val) "size: %u addr: 0x%"PRIu8 "val: 0x%" PRIu8
+loongarch_extioi_coremap_read(uint8_t addr, uint8_t val) "addr: 0x%"PRIu8 "val: 0x%" PRIu8
+loongarch_extioi_coremap_write(unsigned size, uint8_t addr, uint8_t val) "size: %u addr: 0x%"PRIu8 "val: 0x%" PRIu8
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index cd38d03a19..468e3acc74 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -4,3 +4,4 @@ config LOONGSON3_LS7A
select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI
+ select LOONGARCH_EXTIOI
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
new file mode 100644
index 0000000000..12f3175183
--- /dev/null
+++ b/include/hw/intc/loongarch_extioi.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch 3A5000 ext interrupt controller definitions
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "hw/sysbus.h"
+#include "hw/loongarch/loongarch.h"
+
+#ifndef LOONGARCH_EXTIOI_H
+#define LOONGARCH_EXTIOI_H
+
+#define LS3A_INTC_IP 8
+#define MAX_CORES LOONGARCH_MAX_VCPUS
+#define EXTIOI_IRQS (256)
+/* 32 irqs belong to a group */
+#define EXTIOI_IRQS_GROUP_COUNT (256 / 32)
+/* map to ipnum per 32 irqs */
+#define EXTIOI_IRQS_NODETYPE_COUNT 16
+
+#define APIC_BASE 0x1400
+#define ENABLE_OFFSET 0x1600
+#define IPMAP_OFFSET 0x14c0
+#define COREMAP_OFFSET 0x1c00
+
+#define EXTIOI_NODETYPE_START (0x14a0 - APIC_BASE)
+#define EXTIOI_NODETYPE_END (0x14c0 - APIC_BASE)
+#define EXTIOI_BOUNCE_START (0x1680 - APIC_BASE)
+#define EXTIOI_BOUNCE_END (0x16a0 - APIC_BASE)
+#define EXTIOI_COREISR_START (0x1800 - APIC_BASE)
+#define EXTIOI_COREISR_END (0x1B20 - APIC_BASE)
+
+#define EXTIOI_ENABLE_END (0x1618 - ENABLE_OFFSET)
+#define EXTIOI_IPMAP_END (0x14c8 - IPMAP_OFFSET)
+#define EXTIOI_COREMAP_END (0x1d00 - COREMAP_OFFSET)
+
+#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
+DECLARE_INSTANCE_CHECKER(struct LoongArchExtIOI, LOONGARCH_EXTIOI,
+ TYPE_LOONGARCH_EXTIOI)
+
+typedef struct ext_sw_ipisr {
+ uint8_t irq[EXTIOI_IRQS];
+} ext_sw_ipisr;
+
+typedef struct LoongArchExtIOI {
+ SysBusDevice parent_obj;
+ /* hardware state */
+ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
+ uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
+ uint32_t coreisr[MAX_CORES][EXTIOI_IRQS_GROUP_COUNT];
+
+ uint8_t enable[EXTIOI_IRQS / 8];
+ uint8_t ipmap[8];
+ uint8_t coremap[EXTIOI_IRQS];
+ /*software state */
+ uint8_t sw_ipmap[EXTIOI_IRQS];
+ uint8_t sw_coremap[EXTIOI_IRQS];
+ ext_sw_ipisr sw_ipisr[MAX_CORES][LS3A_INTC_IP];
+
+ qemu_irq parent_irq[MAX_CORES][LS3A_INTC_IP];
+ qemu_irq irq[EXTIOI_IRQS];
+ MemoryRegion mmio_reg32[MAX_CORES];
+ MemoryRegion mmio_enable[MAX_CORES];
+ MemoryRegion mmio_ipmap[MAX_CORES];
+ MemoryRegion mmio_coremap[MAX_CORES];
+} LoongArchExtIOI;
+
+#endif /* LOONGARCH_EXTIOI_H */
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 20/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
2022-01-08 9:14 ` [RFC PATCH v4 20/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
@ 2022-01-15 13:49 ` Mark Cave-Ayland
0 siblings, 0 replies; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 13:49 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: richard.henderson, philmd, Song Gao
On 08/01/2022 09:14, Xiaojuan Yang wrote:
> This patch realize the EIOINTC interrupt controller.
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> hw/intc/Kconfig | 3 +
> hw/intc/loongarch_extioi.c | 376 +++++++++++++++++++++++++++++
> hw/intc/meson.build | 1 +
> hw/intc/trace-events | 11 +
> hw/loongarch/Kconfig | 1 +
> include/hw/intc/loongarch_extioi.h | 69 ++++++
> 6 files changed, 461 insertions(+)
> create mode 100644 hw/intc/loongarch_extioi.c
> create mode 100644 include/hw/intc/loongarch_extioi.h
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 727a3bb3e6..ecdf821205 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -90,3 +90,6 @@ config LOONGARCH_PCH_MSI
> select MSI_NONBROKEN
> bool
> select UNIMP
> +
> +config LOONGARCH_EXTIOI
> + bool
> diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
> new file mode 100644
> index 0000000000..b9a91f77b3
> --- /dev/null
> +++ b/hw/intc/loongarch_extioi.c
> @@ -0,0 +1,376 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Loongson 3A5000 ext interrupt controller emulation
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/module.h"
> +#include "qemu/log.h"
> +#include "hw/irq.h"
> +#include "hw/sysbus.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "hw/qdev-properties.h"
> +#include "exec/address-spaces.h"
> +#include "hw/intc/loongarch_extioi.h"
> +#include "migration/vmstate.h"
> +#include "trace.h"
> +
> +static void extioi_update_irq(void *opaque, int irq_num, int level)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + uint8_t ipnum, cpu;
> + unsigned long found1, found2;
> +
> + ipnum = s->sw_ipmap[irq_num];
> + cpu = s->sw_coremap[irq_num];
> + if (level == 1) {
> + if (test_bit(irq_num, (void *)s->enable) == false) {
> + return;
> + }
> + bitmap_set((void *)s->coreisr[cpu], irq_num, 1);
> + found1 = find_next_bit((void *)&(s->sw_ipisr[cpu][ipnum]),
> + EXTIOI_IRQS, 0);
> + bitmap_set((void *)&(s->sw_ipisr[cpu][ipnum]), irq_num, 1);
> +
> + if (found1 >= EXTIOI_IRQS) {
> + qemu_set_irq(s->parent_irq[cpu][ipnum], level);
> + }
> + } else {
> + bitmap_clear((void *)s->coreisr[cpu], irq_num, 1);
> + found1 = find_next_bit((void *)&(s->sw_ipisr[cpu][ipnum]),
> + EXTIOI_IRQS, 0);
> + bitmap_clear((void *)&(s->sw_ipisr[cpu][ipnum]), irq_num, 1);
> + found2 = find_next_bit((void *)&(s->sw_ipisr[cpu][ipnum]),
> + EXTIOI_IRQS, 0);
> +
> + if ((found1 < EXTIOI_IRQS) && (found2 >= EXTIOI_IRQS)) {
> + qemu_set_irq(s->parent_irq[cpu][ipnum], level);
> + }
> + }
> +}
> +
> +static void extioi_setirq(void *opaque, int irq, int level)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + trace_extioi_setirq(irq, level);
> + extioi_update_irq(s, irq, level);
> +}
> +
> +static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + unsigned long offset = addr & 0xffff;
> + uint32_t ret, index;
> + int cpu;
> +
> + if ((offset >= EXTIOI_NODETYPE_START) && (offset < EXTIOI_NODETYPE_END)) {
> + index = (offset - EXTIOI_NODETYPE_START) >> 2;
> + ret = s->nodetype[index];
> + } else if ((offset >= EXTIOI_BOUNCE_START) &&
> + (offset < EXTIOI_BOUNCE_END)) {
> + index = (offset - EXTIOI_BOUNCE_START) >> 2;
> + ret = s->bounce[index];
> + } else if ((offset >= EXTIOI_COREISR_START) &&
> + (offset < EXTIOI_COREISR_END)) {
> + index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
> + cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
> + ret = s->coreisr[cpu][index];
> + }
Please can you use a switch() statement here?
> + trace_loongarch_extioi_readw((uint32_t)addr, ret);
> + return ret;
> +}
> +
> +static void extioi_writew(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + int cpu, index;
> + uint32_t offset, old_data, i, j, bits;
> +
> + offset = addr & 0xffff;
> + trace_loongarch_extioi_writew(size, (uint32_t)addr, val);
> +
> + if ((offset >= EXTIOI_NODETYPE_START) && (offset < EXTIOI_NODETYPE_END)) {
> + index = (offset - EXTIOI_NODETYPE_START) >> 2;
> + s->nodetype[index] = val;
> + } else if ((offset >= EXTIOI_BOUNCE_START) &&
> + (offset < EXTIOI_BOUNCE_END)) {
> + index = (offset - EXTIOI_BOUNCE_START) >> 2;
> + s->bounce[index] = val;
> + } else if ((offset >= EXTIOI_COREISR_START) &&
> + (offset < EXTIOI_COREISR_END)) {
> + index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
> + cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
> +
> + /* Ext_core_ioisr */
> + old_data = s->coreisr[cpu][index];
> + s->coreisr[cpu][index] = old_data & ~val;
> +
> + if (old_data != s->coreisr[cpu][index]) {
> + bits = size * 8;
> + while ((i = find_first_bit((void *)&val, bits)) != bits) {
> + j = test_bit(i, (unsigned long *)&old_data);
> + if (j) {
> + extioi_update_irq(s, i + index * 32, 0);
> + }
> + clear_bit(i, (void *)&val);
> + }
> + }
> + }
And here too.
> +}
> +
> +static uint64_t extioi_enable_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + uint8_t ret;
> +
> + if (addr < EXTIOI_ENABLE_END) {
This hard limit shouldn't be required...
> + ret = s->enable[addr];
> + }
> +
> + trace_loongarch_extioi_enable_read((uint8_t)addr, ret);
> + return ret;
> +}
> +
> +static void extioi_enable_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + uint8_t old_data, val = value & 0xff;
> + int i, level;
> +
> + trace_loongarch_extioi_enable_write(size, (uint8_t)addr, val);
> + if (addr < EXTIOI_ENABLE_END) {
> + old_data = s->enable[addr];
or here.
> + if (old_data != val) {
> + s->enable[addr] = val;
> + old_data = old_data ^ val;
> +
> + while ((i = find_first_bit((void *)&old_data, 8)) != 8) {
> + level = test_bit(i, (unsigned long *)&val);
> + extioi_update_irq(s, i + addr * 8, level);
> + clear_bit(i, (void *)&old_data);
> + }
> + }
> + }
> +}
> +
> +static uint64_t extioi_ipmap_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + uint8_t ret;
> +
> + if (addr < EXTIOI_IPMAP_END) {
> + ret = s->ipmap[addr];
> + }
Or here.
> + trace_loongarch_extioi_ipmap_read((uint8_t)addr, ret);
> + return ret;
> +}
> +
> +static void extioi_ipmap_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + uint8_t val = value & 0xff;
> + int i, ipnum, irqnum;
> +
> + trace_loongarch_extioi_ipmap_write(size, (uint8_t)addr, val);
> + if (addr < EXTIOI_IPMAP_END) {
> + s->ipmap[addr] = val;
Or here.
> + /* Routing in groups of 32 interrupt */
> + ipnum = find_first_bit((void *)&val, 4);
> + for (i = 0; i < 32; i++) {
> + irqnum = addr * 32 + i;
> + if (ipnum != 4) {
> + s->sw_ipmap[irqnum] = ipnum;
> + } else {
> + s->sw_ipmap[irqnum] = 0;
> + }
> + }
> + }
> +}
> +
> +static uint64_t extioi_coremap_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + uint8_t ret;
> +
> + if (addr < EXTIOI_COREMAP_END) {
> + ret = s->coremap[addr];
> + }
Or here.
> + trace_loongarch_extioi_coremap_read((uint8_t)addr, ret);
> + return ret;
> +}
> +
> +static void extioi_coremap_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + uint8_t val = value & 0xff;
> + int cpu;
> +
> + trace_loongarch_extioi_coremap_write(size, (uint8_t)addr, val);
> + if (addr < EXTIOI_COREMAP_END) {
> + s->coremap[addr] = val;
Or here...
> + /* Only support 1 node now only handle the core map*/
> + if (val) {
> + cpu = find_first_bit((void *)&val, 4);
> + if (cpu != 4) {
> + s->sw_coremap[addr] = cpu;
> + }
> + }
> + }
> +}
> +
> +static const MemoryRegionOps extioi_reg32_ops = {
> + .read = extioi_readw,
> + .write = extioi_writew,
> + .impl.min_access_size = 4,
> + .impl.max_access_size = 4,
> + .valid.min_access_size = 4,
> + .valid.max_access_size = 8,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static const MemoryRegionOps extioi_enable_ops = {
> + .read = extioi_enable_read,
> + .write = extioi_enable_write,
> + .impl.min_access_size = 1,
> + .impl.max_access_size = 1,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 8,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static const MemoryRegionOps extioi_ipmap_ops = {
> + .read = extioi_ipmap_read,
> + .write = extioi_ipmap_write,
> + .impl.min_access_size = 1,
> + .impl.max_access_size = 1,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 8,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static const MemoryRegionOps extioi_coremap_ops = {
> + .read = extioi_coremap_read,
> + .write = extioi_coremap_write,
> + .impl.min_access_size = 1,
> + .impl.max_access_size = 1,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 8,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static void loongarch_extioi_realize(DeviceState *dev, Error **errp)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev);
> + MachineState *ms = MACHINE(qdev_get_machine());
> + int cpu;
> +
> + for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + memory_region_init_io(&s->mmio_reg32[cpu], OBJECT(s),
> + &extioi_reg32_ops, s, TYPE_LOONGARCH_EXTIOI,
> + 0x900);
> + /*
> + * kernel use anysend to handle enable reg.
> + * need support different size handle.
> + */
> + memory_region_init_io(&s->mmio_enable[cpu], OBJECT(s),
> + &extioi_enable_ops, s, TYPE_LOONGARCH_EXTIOI,
> + 0x18);
> + memory_region_init_io(&s->mmio_ipmap[cpu], OBJECT(s),
> + &extioi_ipmap_ops, s, TYPE_LOONGARCH_EXTIOI,
(side note: you could make the output of "info mtree" more helpful by extending the
description based upon TYPE_LOONGARCH_EXTIOI with its purpose i.e.
TYPE_LOONGARCH_EXTIOI ".enable" and TYPE_LOONGARCH_EXTIOI ".ipmap")
> + 0x8);
> + memory_region_init_io(&s->mmio_coremap[cpu], OBJECT(s),
> + &extioi_coremap_ops, s, TYPE_LOONGARCH_EXTIOI,
> + 0x100);
... since the sizes are already restricted by the memory regions here. Could you
reuse the constants below rather than hardcoding them?
> + }
> +}
> +
> +static const VMStateDescription vmstate_ext_sw_ipisr = {
> + .name = "ext_sw_ipisr",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8_ARRAY(irq, ext_sw_ipisr, EXTIOI_IRQS),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static const VMStateDescription vmstate_loongarch_extioi = {
> + .name = TYPE_LOONGARCH_EXTIOI,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
> + VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, MAX_CORES,
> + EXTIOI_IRQS_GROUP_COUNT),
> + VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
> + EXTIOI_IRQS_NODETYPE_COUNT / 2),
> + VMSTATE_UINT8_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 8),
> + VMSTATE_UINT8_ARRAY(ipmap, LoongArchExtIOI, 8),
> + VMSTATE_UINT8_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS),
> + VMSTATE_UINT8_ARRAY(sw_ipmap, LoongArchExtIOI, EXTIOI_IRQS),
> + VMSTATE_UINT8_ARRAY(sw_coremap, LoongArchExtIOI, EXTIOI_IRQS),
> + VMSTATE_STRUCT_2DARRAY(sw_ipisr, LoongArchExtIOI, MAX_CORES,
> + LS3A_INTC_IP, 1, vmstate_ext_sw_ipisr,
> + ext_sw_ipisr),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void loongarch_extioi_instance_init(Object *obj)
> +{
> + SysBusDevice *dev = SYS_BUS_DEVICE(obj);
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj);
> + MachineState *ms = MACHINE(qdev_get_machine());
> + int i, cpu, pin;
> +
> + for (i = 0; i < EXTIOI_IRQS; i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
> + }
> +
> + qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
> +
> + for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + sysbus_init_mmio(dev, &s->mmio_reg32[cpu]);
> + sysbus_init_mmio(dev, &s->mmio_enable[cpu]);
> + sysbus_init_mmio(dev, &s->mmio_ipmap[cpu]);
> + sysbus_init_mmio(dev, &s->mmio_coremap[cpu]);
> + for (pin = 0; pin < LS3A_INTC_IP; pin++) {
> + qdev_init_gpio_out(DEVICE(obj), &s->parent_irq[cpu][pin], 1);
> + }
> + }
> +}
> +
> +static void loongarch_extioi_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->vmsd = &vmstate_loongarch_extioi;
> + dc->realize = loongarch_extioi_realize;
> +}
> +
> +static const TypeInfo loongarch_extioi_info = {
> + .name = TYPE_LOONGARCH_EXTIOI,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_init = loongarch_extioi_instance_init,
> + .instance_size = sizeof(struct LoongArchExtIOI),
> + .class_init = loongarch_extioi_class_init,
> +};
> +
> +static void loongarch_extioi_register_types(void)
> +{
> + type_register_static(&loongarch_extioi_info);
> +}
> +
> +type_init(loongarch_extioi_register_types)
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index c679223420..d09eb6b81d 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -63,3 +63,4 @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
> specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
> specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
> specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
> +specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
> index 6d2d041766..8f7854196b 100644
> --- a/hw/intc/trace-events
> +++ b/hw/intc/trace-events
> @@ -260,3 +260,14 @@ loongarch_pch_pic_writeb(unsigned size, uint32_t addr, unsigned long val) "size:
>
> # loongarch_pch_msi.c
> loongarch_msi_set_irq(int irq_num) "set msi irq %d"
> +
> +# loongarch_extioi.c
> +extioi_setirq(int irq, int level) "set extirq irq %d level %d"
> +loongarch_extioi_readw(uint32_t addr, uint32_t val) "addr: 0x%"PRIx32 "val: 0x%" PRIx32
> +loongarch_extioi_writew(unsigned size, uint32_t addr, uint32_t val) "size: %u addr: 0x%"PRIx32 "val: 0x%" PRIx32
> +loongarch_extioi_enable_read(uint8_t addr, uint8_t val) "addr: 0x%"PRIu8 "val: 0x%" PRIu8
> +loongarch_extioi_enable_write(unsigned size, uint8_t addr, uint8_t val) "size: %u addr: 0x%"PRIu8 "val: 0x%" PRIu8
> +loongarch_extioi_ipmap_read(uint8_t addr, uint8_t val) "addr: 0x%"PRIu8 "val: 0x%" PRIu8
> +loongarch_extioi_ipmap_write(unsigned size, uint8_t addr, uint8_t val) "size: %u addr: 0x%"PRIu8 "val: 0x%" PRIu8
> +loongarch_extioi_coremap_read(uint8_t addr, uint8_t val) "addr: 0x%"PRIu8 "val: 0x%" PRIu8
> +loongarch_extioi_coremap_write(unsigned size, uint8_t addr, uint8_t val) "size: %u addr: 0x%"PRIu8 "val: 0x%" PRIu8
> diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
> index cd38d03a19..468e3acc74 100644
> --- a/hw/loongarch/Kconfig
> +++ b/hw/loongarch/Kconfig
> @@ -4,3 +4,4 @@ config LOONGSON3_LS7A
> select LOONGARCH_IPI
> select LOONGARCH_PCH_PIC
> select LOONGARCH_PCH_MSI
> + select LOONGARCH_EXTIOI
> diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
> new file mode 100644
> index 0000000000..12f3175183
> --- /dev/null
> +++ b/include/hw/intc/loongarch_extioi.h
> @@ -0,0 +1,69 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch 3A5000 ext interrupt controller definitions
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "hw/sysbus.h"
> +#include "hw/loongarch/loongarch.h"
> +
> +#ifndef LOONGARCH_EXTIOI_H
> +#define LOONGARCH_EXTIOI_H
> +
> +#define LS3A_INTC_IP 8
> +#define MAX_CORES LOONGARCH_MAX_VCPUS
> +#define EXTIOI_IRQS (256)
> +/* 32 irqs belong to a group */
> +#define EXTIOI_IRQS_GROUP_COUNT (256 / 32)
> +/* map to ipnum per 32 irqs */
> +#define EXTIOI_IRQS_NODETYPE_COUNT 16
> +
> +#define APIC_BASE 0x1400
> +#define ENABLE_OFFSET 0x1600
> +#define IPMAP_OFFSET 0x14c0
> +#define COREMAP_OFFSET 0x1c00
> +
> +#define EXTIOI_NODETYPE_START (0x14a0 - APIC_BASE)
> +#define EXTIOI_NODETYPE_END (0x14c0 - APIC_BASE)
> +#define EXTIOI_BOUNCE_START (0x1680 - APIC_BASE)
> +#define EXTIOI_BOUNCE_END (0x16a0 - APIC_BASE)
> +#define EXTIOI_COREISR_START (0x1800 - APIC_BASE)
> +#define EXTIOI_COREISR_END (0x1B20 - APIC_BASE)
> +
> +#define EXTIOI_ENABLE_END (0x1618 - ENABLE_OFFSET)
> +#define EXTIOI_IPMAP_END (0x14c8 - IPMAP_OFFSET)
> +#define EXTIOI_COREMAP_END (0x1d00 - COREMAP_OFFSET)
> +
> +#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
> +DECLARE_INSTANCE_CHECKER(struct LoongArchExtIOI, LOONGARCH_EXTIOI,
> + TYPE_LOONGARCH_EXTIOI)
> +
> +typedef struct ext_sw_ipisr {
> + uint8_t irq[EXTIOI_IRQS];
> +} ext_sw_ipisr;
> +
> +typedef struct LoongArchExtIOI {
> + SysBusDevice parent_obj;
> + /* hardware state */
> + uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
> + uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
> + uint32_t coreisr[MAX_CORES][EXTIOI_IRQS_GROUP_COUNT];
> +
> + uint8_t enable[EXTIOI_IRQS / 8];
> + uint8_t ipmap[8];
> + uint8_t coremap[EXTIOI_IRQS];
> + /*software state */
> + uint8_t sw_ipmap[EXTIOI_IRQS];
> + uint8_t sw_coremap[EXTIOI_IRQS];
> + ext_sw_ipisr sw_ipisr[MAX_CORES][LS3A_INTC_IP];
> +
> + qemu_irq parent_irq[MAX_CORES][LS3A_INTC_IP];
> + qemu_irq irq[EXTIOI_IRQS];
> + MemoryRegion mmio_reg32[MAX_CORES];
> + MemoryRegion mmio_enable[MAX_CORES];
> + MemoryRegion mmio_ipmap[MAX_CORES];
> + MemoryRegion mmio_coremap[MAX_CORES];
> +} LoongArchExtIOI;
> +
> +#endif /* LOONGARCH_EXTIOI_H */
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 21/30] hw/loongarch: Add irq hierarchy for the system
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (19 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 20/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-15 14:00 ` Mark Cave-Ayland
2022-01-08 9:14 ` [RFC PATCH v4 22/30] Enable common virtio pci support for LoongArch Xiaojuan Yang
` (10 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/loongson3.c | 85 ++++++++++++++++++++++++++++++++++++++
include/hw/pci-host/ls7a.h | 13 ++++++
2 files changed, 98 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 6e796c2c08..cc7ee02003 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -15,6 +15,10 @@
#include "sysemu/runstate.h"
#include "sysemu/reset.h"
#include "hw/loongarch/loongarch.h"
+#include "hw/intc/loongarch_ipi.h"
+#include "hw/intc/loongarch_extioi.h"
+#include "hw/intc/loongarch_pch_pic.h"
+#include "hw/intc/loongarch_pch_msi.h"
#include "hw/pci-host/ls7a.h"
static void loongarch_cpu_reset(void *opaque)
@@ -93,6 +97,84 @@ static void loongarch_cpu_set_irq(void *opaque, int irq, int level)
}
}
+static void loongarch_irq_init(LoongArchMachineState *lams)
+{
+ MachineState *ms = MACHINE(lams);
+ DeviceState *ipi, *extioi, *pch_pic, *pch_msi, *cpudev;
+ SysBusDevice *d;
+ int cpu, pin, i;
+ unsigned long ipi_addr;
+ CPULoongArchState *env;
+
+ ipi = qdev_new(TYPE_LOONGARCH_IPI);
+ d = SYS_BUS_DEVICE(ipi);
+ sysbus_realize_and_unref(d, &error_fatal);
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+ cpudev = DEVICE(qemu_get_cpu(cpu));
+ env = (qemu_get_cpu(cpu))->env_ptr;
+ ipi_addr = SMP_IPI_MAILBOX + cpu * 0x100;
+ memory_region_add_subregion(env->system_iocsr, ipi_addr,
+ sysbus_mmio_get_region(d, cpu));
+ /* connect ipi irq to cpu irq */
+ qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
+ }
+
+ extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
+ d = SYS_BUS_DEVICE(extioi);
+ sysbus_realize_and_unref(d, &error_fatal);
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+ env = (qemu_get_cpu(cpu))->env_ptr;
+ memory_region_add_subregion(env->system_iocsr, APIC_BASE,
+ sysbus_mmio_get_region(d, cpu * 4));
+ memory_region_add_subregion_overlap(env->system_iocsr, ENABLE_OFFSET,
+ sysbus_mmio_get_region(d, cpu * 4 + 1), 1);
+ memory_region_add_subregion_overlap(env->system_iocsr, IPMAP_OFFSET,
+ sysbus_mmio_get_region(d, cpu * 4 + 2), 1);
+ memory_region_add_subregion_overlap(env->system_iocsr, COREMAP_OFFSET,
+ sysbus_mmio_get_region(d, cpu * 4 + 3), 1);
+ }
+
+ for (i = 0; i < EXTIOI_IRQS; i++) {
+ sysbus_connect_irq(d, i, qdev_get_gpio_in(extioi, i));
+ }
+
+ /*
+ * connect ext irq to the cpu irq
+ * cpu_pin[9:2] <= intc_pin[7:0]
+ */
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+ cpudev = DEVICE(qemu_get_cpu(cpu));
+ for (pin = 0; pin < LS3A_INTC_IP; pin++) {
+ qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
+ qdev_get_gpio_in(cpudev, pin + 2));
+ }
+ }
+
+ pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
+ d = SYS_BUS_DEVICE(pch_pic);
+ sysbus_realize_and_unref(d, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), LS7A_IOAPIC_REG_BASE,
+ sysbus_mmio_get_region(d, 0));
+ memory_region_add_subregion_overlap(get_system_memory(),
+ LS7A_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
+ sysbus_mmio_get_region(d, 1), 1);
+
+ /* Connect 64 pch_pic irqs to extioi */
+ for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
+ sysbus_connect_irq(d, i, qdev_get_gpio_in(extioi, i));
+ }
+
+ pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
+ d = SYS_BUS_DEVICE(pch_msi);
+ sysbus_realize_and_unref(d, &error_fatal);
+ sysbus_mmio_map(d, 0, LS7A_PCH_MSI_ADDR_LOW);
+ for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
+ /* Connect 192 pch_msi irqs to extioi */
+ sysbus_connect_irq(d, i,
+ qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
+ }
+}
+
static void loongarch_init(MachineState *machine)
{
const char *cpu_model = machine->cpu_type;
@@ -145,6 +227,9 @@ static void loongarch_init(MachineState *machine)
get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
memory_region_add_subregion(get_system_memory(), LOONGARCH_ISA_IO_BASE,
&lams->isa_io);
+
+ /* Initialize the IO interrupt subsystem */
+ loongarch_irq_init(lams);
}
static void loongarch_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index 6adbfbe443..447450828e 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -24,6 +24,19 @@
#define LS7A_PCI_IO_BASE 0x18004000UL
#define LS7A_PCI_IO_SIZE 0xC000
+#define LS7A_PCH_REG_BASE 0x10000000UL
+#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
+#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL
+
+/*
+ * According to the kernel pch irq start from 64 offset
+ * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
+ * used for pci device.
+ */
+#define PCH_PIC_IRQ_OFFSET 64
+#define LS7A_DEVICE_IRQS 16
+#define LS7A_PCI_IRQS 48
+
struct LS7APCIState {
/*< private >*/
PCIDevice parent_obj;
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 21/30] hw/loongarch: Add irq hierarchy for the system
2022-01-08 9:14 ` [RFC PATCH v4 21/30] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
@ 2022-01-15 14:00 ` Mark Cave-Ayland
0 siblings, 0 replies; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 14:00 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: philmd, richard.henderson, Song Gao
On 08/01/2022 09:14, Xiaojuan Yang wrote:
> This patch add the irq hierarchy for the virt board.
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> hw/loongarch/loongson3.c | 85 ++++++++++++++++++++++++++++++++++++++
> include/hw/pci-host/ls7a.h | 13 ++++++
> 2 files changed, 98 insertions(+)
>
> diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
> index 6e796c2c08..cc7ee02003 100644
> --- a/hw/loongarch/loongson3.c
> +++ b/hw/loongarch/loongson3.c
> @@ -15,6 +15,10 @@
> #include "sysemu/runstate.h"
> #include "sysemu/reset.h"
> #include "hw/loongarch/loongarch.h"
> +#include "hw/intc/loongarch_ipi.h"
> +#include "hw/intc/loongarch_extioi.h"
> +#include "hw/intc/loongarch_pch_pic.h"
> +#include "hw/intc/loongarch_pch_msi.h"
> #include "hw/pci-host/ls7a.h"
>
> static void loongarch_cpu_reset(void *opaque)
> @@ -93,6 +97,84 @@ static void loongarch_cpu_set_irq(void *opaque, int irq, int level)
> }
> }
>
> +static void loongarch_irq_init(LoongArchMachineState *lams)
> +{
> + MachineState *ms = MACHINE(lams);
> + DeviceState *ipi, *extioi, *pch_pic, *pch_msi, *cpudev;
> + SysBusDevice *d;
> + int cpu, pin, i;
> + unsigned long ipi_addr;
> + CPULoongArchState *env;
> +
> + ipi = qdev_new(TYPE_LOONGARCH_IPI);
> + d = SYS_BUS_DEVICE(ipi);
> + sysbus_realize_and_unref(d, &error_fatal);
> + for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + cpudev = DEVICE(qemu_get_cpu(cpu));
> + env = (qemu_get_cpu(cpu))->env_ptr;
> + ipi_addr = SMP_IPI_MAILBOX + cpu * 0x100;
> + memory_region_add_subregion(env->system_iocsr, ipi_addr,
> + sysbus_mmio_get_region(d, cpu));
> + /* connect ipi irq to cpu irq */
> + qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
> + }
> +
> + extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
> + d = SYS_BUS_DEVICE(extioi);
> + sysbus_realize_and_unref(d, &error_fatal);
> + for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + env = (qemu_get_cpu(cpu))->env_ptr;
> + memory_region_add_subregion(env->system_iocsr, APIC_BASE,
> + sysbus_mmio_get_region(d, cpu * 4));
> + memory_region_add_subregion_overlap(env->system_iocsr, ENABLE_OFFSET,
> + sysbus_mmio_get_region(d, cpu * 4 + 1), 1);
> + memory_region_add_subregion_overlap(env->system_iocsr, IPMAP_OFFSET,
> + sysbus_mmio_get_region(d, cpu * 4 + 2), 1);
> + memory_region_add_subregion_overlap(env->system_iocsr, COREMAP_OFFSET,
> + sysbus_mmio_get_region(d, cpu * 4 + 3), 1);
This _overlap() doesn't look right: since all of these regions are contained within
env->system_iocsr then I'd expect to see just the top memory_region_add_subregion()
map env->system_iocsr into the CPU space.
Possibly I've misunderstood something about how these registers appear since I had a
similar question earlier.
> + }
> +
> + for (i = 0; i < EXTIOI_IRQS; i++) {
> + sysbus_connect_irq(d, i, qdev_get_gpio_in(extioi, i));
> + }
> +
> + /*
> + * connect ext irq to the cpu irq
> + * cpu_pin[9:2] <= intc_pin[7:0]
> + */
> + for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + cpudev = DEVICE(qemu_get_cpu(cpu));
> + for (pin = 0; pin < LS3A_INTC_IP; pin++) {
> + qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
> + qdev_get_gpio_in(cpudev, pin + 2));
> + }
> + }
> +
> + pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
> + d = SYS_BUS_DEVICE(pch_pic);
> + sysbus_realize_and_unref(d, &error_fatal);
> + memory_region_add_subregion(get_system_memory(), LS7A_IOAPIC_REG_BASE,
> + sysbus_mmio_get_region(d, 0));
> + memory_region_add_subregion_overlap(get_system_memory(),
> + LS7A_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
> + sysbus_mmio_get_region(d, 1), 1);
And also here - I can't quite understand what is happening here. Perhaps you could
supply the output of "info mtree" highlighting the relevant entries here and above?
> + /* Connect 64 pch_pic irqs to extioi */
> + for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
> + sysbus_connect_irq(d, i, qdev_get_gpio_in(extioi, i));
> + }
> +
> + pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
> + d = SYS_BUS_DEVICE(pch_msi);
> + sysbus_realize_and_unref(d, &error_fatal);
> + sysbus_mmio_map(d, 0, LS7A_PCH_MSI_ADDR_LOW);
> + for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
> + /* Connect 192 pch_msi irqs to extioi */
> + sysbus_connect_irq(d, i,
> + qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
> + }
> +}
> +
> static void loongarch_init(MachineState *machine)
> {
> const char *cpu_model = machine->cpu_type;
> @@ -145,6 +227,9 @@ static void loongarch_init(MachineState *machine)
> get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
> memory_region_add_subregion(get_system_memory(), LOONGARCH_ISA_IO_BASE,
> &lams->isa_io);
> +
> + /* Initialize the IO interrupt subsystem */
> + loongarch_irq_init(lams);
> }
>
> static void loongarch_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
> index 6adbfbe443..447450828e 100644
> --- a/include/hw/pci-host/ls7a.h
> +++ b/include/hw/pci-host/ls7a.h
> @@ -24,6 +24,19 @@
> #define LS7A_PCI_IO_BASE 0x18004000UL
> #define LS7A_PCI_IO_SIZE 0xC000
>
> +#define LS7A_PCH_REG_BASE 0x10000000UL
> +#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
> +#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL
> +
> +/*
> + * According to the kernel pch irq start from 64 offset
> + * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
> + * used for pci device.
> + */
> +#define PCH_PIC_IRQ_OFFSET 64
> +#define LS7A_DEVICE_IRQS 16
> +#define LS7A_PCI_IRQS 48
> +
> struct LS7APCIState {
> /*< private >*/
> PCIDevice parent_obj;
ATB,
Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH v4 22/30] Enable common virtio pci support for LoongArch
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (20 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 21/30] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 23/30] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
` (9 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
softmmu/qdev-monitor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c
index 01f3834db5..49491d74a1 100644
--- a/softmmu/qdev-monitor.c
+++ b/softmmu/qdev-monitor.c
@@ -60,7 +60,8 @@ typedef struct QDevAlias
QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \
QEMU_ARCH_MIPS | QEMU_ARCH_PPC | \
QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \
- QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA)
+ QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA | \
+ QEMU_ARCH_LOONGARCH)
#define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)
#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 23/30] hw/loongarch: Add some devices support for 3A5000.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (21 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 22/30] Enable common virtio pci support for LoongArch Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 24/30] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
` (8 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/Kconfig | 7 ++++
hw/loongarch/loongson3.c | 70 ++++++++++++++++++++++++++++++++++++++
hw/pci-host/ls7a.c | 42 ++++++++++++++++++++++-
include/hw/pci-host/ls7a.h | 5 +++
4 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 468e3acc74..e607c84d21 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -1,5 +1,12 @@
config LOONGSON3_LS7A
bool
+ imply VGA_PCI
+ imply VIRTIO_VGA
+ imply PCI_DEVICES
+ select ISA_BUS
+ select SERIAL
+ select SERIAL_ISA
+ select VIRTIO_PCI
select PCI_EXPRESS_7A
select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index cc7ee02003..85a4be0c7b 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -10,16 +10,20 @@
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "hw/boards.h"
+#include "hw/char/serial.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/runstate.h"
#include "sysemu/reset.h"
+#include "hw/irq.h"
+#include "net/net.h"
#include "hw/loongarch/loongarch.h"
#include "hw/intc/loongarch_ipi.h"
#include "hw/intc/loongarch_extioi.h"
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/pci-host/ls7a.h"
+#include "hw/misc/unimp.h"
static void loongarch_cpu_reset(void *opaque)
{
@@ -97,6 +101,70 @@ static void loongarch_cpu_set_irq(void *opaque, int irq, int level)
}
}
+static void loongarch_devices_init(DeviceState *pch_pic)
+{
+ DeviceState *pciehost;
+ SysBusDevice *d;
+ PCIBus *pci_bus;
+ MemoryRegion *pio_alias;
+ int i;
+
+ pciehost = qdev_new(TYPE_LS7A_HOST_DEVICE);
+ d = SYS_BUS_DEVICE(pciehost);
+ sysbus_realize_and_unref(d, &error_fatal);
+ pci_bus = PCI_HOST_BRIDGE(pciehost)->bus;
+
+ /* Map pcie ecam space */
+ memory_region_add_subregion(get_system_memory(), LS_PCIECFG_BASE,
+ sysbus_mmio_get_region(d, 0));
+
+ /* Map PCI IO port space. */
+ pio_alias = g_new0(MemoryRegion, 1);
+ memory_region_init_alias(pio_alias, OBJECT(pciehost), "ls7a-pci-io",
+ sysbus_mmio_get_region(d, 1),
+ LS7A_PCI_IO_OFFSET, LS7A_PCI_IO_SIZE);
+ memory_region_add_subregion(get_system_memory(), LS7A_PCI_IO_BASE,
+ pio_alias);
+
+ /* Map PCI mem space */
+ memory_region_add_subregion(get_system_memory(), 0,
+ sysbus_mmio_get_region(d, 2));
+
+ /* Map PCI conf space */
+ memory_region_add_subregion(get_system_memory(), HT1LO_PCICFG_BASE,
+ sysbus_mmio_get_region(d, 3));
+
+ /* Connect 48 pci irqs to pch_pic */
+ for (i = 0; i < LS7A_PCI_IRQS; i++) {
+ qdev_connect_gpio_out(pciehost, i,
+ qdev_get_gpio_in(pch_pic, i + LS7A_DEVICE_IRQS));
+ }
+
+ serial_mm_init(get_system_memory(), LS7A_UART_BASE, 0,
+ qdev_get_gpio_in(pch_pic, LS7A_UART_IRQ - PCH_PIC_IRQ_OFFSET),
+ 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+
+ /* Network init */
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
+
+ /* VGA setup */
+ pci_vga_init(pci_bus);
+
+ /*
+ * There are some invalid guest memory access.
+ * Create some unimplemented devices to emulate this.
+ */
+ create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
+}
+
static void loongarch_irq_init(LoongArchMachineState *lams)
{
MachineState *ms = MACHINE(lams);
@@ -173,6 +241,8 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
sysbus_connect_irq(d, i,
qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
}
+
+ loongarch_devices_init(pch_pic);
}
static void loongarch_init(MachineState *machine)
diff --git a/hw/pci-host/ls7a.c b/hw/pci-host/ls7a.c
index eb16b669bb..c1e08e2356 100644
--- a/hw/pci-host/ls7a.c
+++ b/hw/pci-host/ls7a.c
@@ -28,6 +28,41 @@ static const VMStateDescription vmstate_ls7a_pcie = {
}
};
+static PCIINTxRoute ls7a_route_intx_pin_to_irq(void *opaque, int pin)
+{
+ PCIINTxRoute route;
+
+ route.irq = pin;
+ route.mode = PCI_INTX_ENABLED;
+ return route;
+}
+
+static int pci_ls7a_map_irq(PCIDevice *d, int irq_num)
+{
+ PCIBus *bus;
+ int offset, irq;
+
+ bus = pci_get_bus(d);
+ if (bus->parent_dev) {
+ irq = pci_swizzle_map_irq_fn(d, irq_num);
+ return irq;
+ }
+
+ /* pci device start from irq 80 */
+ offset = PCH_PIC_IRQ_OFFSET + LS7A_DEVICE_IRQS;
+ irq = offset + ((PCI_SLOT(d->devfn) * 4 + irq_num)) % LS7A_PCI_IRQS;
+
+ return irq;
+}
+
+static void pci_ls7a_set_irq(void *opaque, int irq_num, int level)
+{
+ LS7APCIEHost *pciehost = opaque;
+ int offset = PCH_PIC_IRQ_OFFSET + LS7A_DEVICE_IRQS;
+
+ qemu_set_irq(pciehost->irqs[irq_num - offset], level);
+}
+
static void pci_ls7a_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
@@ -74,10 +109,13 @@ static void ls7a_pciehost_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->pci_io);
sysbus_init_mmio(sbd, &s->pci_mmio);
- pci->bus = pci_register_root_bus(dev, "pcie.0", NULL, NULL, s,
+ pci->bus = pci_register_root_bus(dev, "pcie.0", pci_ls7a_set_irq,
+ pci_ls7a_map_irq, s,
&s->pci_mmio, &s->pci_io,
PCI_DEVFN(1, 0), 128, TYPE_PCIE_BUS);
+ pci_bus_set_route_irq_fn(pci->bus, ls7a_route_intx_pin_to_irq);
+
memory_region_init_io(&s->pci_conf, OBJECT(dev),
&pci_ls7a_config_ops, pci->bus,
"ls7a_pci_conf", HT1LO_PCICFG_SIZE);
@@ -141,6 +179,8 @@ static void ls7a_pciehost_initfn(Object *obj)
object_initialize_child(obj, "ls7a_pci", ls7a_pci, TYPE_LS7A_PCI_DEVICE);
qdev_prop_set_int32(DEVICE(ls7a_pci), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(ls7a_pci), "multifunction", false);
+
+ qdev_init_gpio_out(DEVICE(obj), s->irqs, LS7A_PCI_IRQS);
}
static const char *ls7a_pciehost_root_bus_path(PCIHostState *host_bridge,
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index 447450828e..cfa990ff8a 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -23,6 +23,7 @@
#define LS7A_PCI_IO_BASE 0x18004000UL
#define LS7A_PCI_IO_SIZE 0xC000
+#define LS7A_PCI_IO_OFFSET 0x4000
#define LS7A_PCH_REG_BASE 0x10000000UL
#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
@@ -37,6 +38,9 @@
#define LS7A_DEVICE_IRQS 16
#define LS7A_PCI_IRQS 48
+#define LS7A_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
+#define LS7A_UART_BASE 0x1fe001e0
+
struct LS7APCIState {
/*< private >*/
PCIDevice parent_obj;
@@ -51,6 +55,7 @@ typedef struct LS7APCIEHost {
LS7APCIState pci_dev;
+ qemu_irq irqs[LS7A_PCI_IRQS];
MemoryRegion pci_conf;
MemoryRegion pci_mmio;
MemoryRegion pci_io;
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 24/30] hw/loongarch: Add LoongArch ls7a rtc device support
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (22 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 23/30] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 25/30] hw/loongarch: Add default bios startup support Xiaojuan Yang
` (7 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 4 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c | 322 +++++++++++++++++++++++++++++++++++++
hw/rtc/meson.build | 1 +
include/hw/pci-host/ls7a.h | 4 +
6 files changed, 335 insertions(+)
create mode 100644 hw/rtc/ls7a_rtc.c
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index e607c84d21..0f759eaa37 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -12,3 +12,4 @@ config LOONGSON3_LS7A
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI
select LOONGARCH_EXTIOI
+ select LS7A_RTC
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 85a4be0c7b..ff0ef71e7b 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -163,6 +163,10 @@ static void loongarch_devices_init(DeviceState *pch_pic)
* Create some unimplemented devices to emulate this.
*/
create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
+
+ sysbus_create_simple("ls7a_rtc", LS7A_RTC_REG_BASE,
+ qdev_get_gpio_in(pch_pic,
+ LS7A_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
}
static void loongarch_irq_init(LoongArchMachineState *lams)
diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig
index f06e133b8a..ba8f7bc202 100644
--- a/hw/rtc/Kconfig
+++ b/hw/rtc/Kconfig
@@ -25,3 +25,6 @@ config SUN4V_RTC
config GOLDFISH_RTC
bool
+
+config LS7A_RTC
+ bool
diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
new file mode 100644
index 0000000000..292acb3500
--- /dev/null
+++ b/hw/rtc/ls7a_rtc.c
@@ -0,0 +1,322 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongarch LS7A Real Time Clock emulation
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "include/hw/register.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+#include "qemu/cutils.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/misc/unimp.h"
+
+#define SYS_TOYTRIM 0x20
+#define SYS_TOYWRITE0 0x24
+#define SYS_TOYWRITE1 0x28
+#define SYS_TOYREAD0 0x2C
+#define SYS_TOYREAD1 0x30
+#define SYS_TOYMATCH0 0x34
+#define SYS_TOYMATCH1 0x38
+#define SYS_TOYMATCH2 0x3C
+#define SYS_RTCCTRL 0x40
+#define SYS_RTCTRIM 0x60
+#define SYS_RTCWRTIE0 0x64
+#define SYS_RTCREAD0 0x68
+#define SYS_RTCMATCH0 0x6C
+#define SYS_RTCMATCH1 0x70
+#define SYS_RTCMATCH2 0x74
+
+/*
+ * Shift bits and filed mask
+ */
+#define TOY_MON_MASK 0x3f
+#define TOY_DAY_MASK 0x1f
+#define TOY_HOUR_MASK 0x1f
+#define TOY_MIN_MASK 0x3f
+#define TOY_SEC_MASK 0x3f
+#define TOY_MSEC_MASK 0xf
+
+#define TOY_MON_SHIFT 26
+#define TOY_DAY_SHIFT 21
+#define TOY_HOUR_SHIFT 16
+#define TOY_MIN_SHIFT 10
+#define TOY_SEC_SHIFT 4
+#define TOY_MSEC_SHIFT 0
+
+#define TOY_MATCH_YEAR_MASK 0x3f
+#define TOY_MATCH_MON_MASK 0xf
+#define TOY_MATCH_DAY_MASK 0x1f
+#define TOY_MATCH_HOUR_MASK 0x1f
+#define TOY_MATCH_MIN_MASK 0x3f
+#define TOY_MATCH_SEC_MASK 0x3f
+
+#define TOY_MATCH_YEAR_SHIFT 26
+#define TOY_MATCH_MON_SHIFT 22
+#define TOY_MATCH_DAY_SHIFT 17
+#define TOY_MATCH_HOUR_SHIFT 12
+#define TOY_MATCH_MIN_SHIFT 6
+#define TOY_MATCH_SEC_SHIFT 0
+
+#define TOY_ENABLE_BIT (1U << 11)
+
+#define TYPE_LS7A_RTC "ls7a_rtc"
+OBJECT_DECLARE_SIMPLE_TYPE(LS7ARtcState, LS7A_RTC)
+
+typedef struct LS7ARtcState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ QEMUTimer *timer;
+ /*
+ * Needed to preserve the tick_count across migration, even if the
+ * absolute value of the rtc_clock is different on the source and
+ * destination.
+ */
+ int64_t offset;
+ int64_t data;
+ int64_t save_alarm_offset;
+ int tidx;
+ uint32_t toymatch[3];
+ uint32_t toytrim;
+ uint32_t cntrctl;
+ uint32_t rtctrim;
+ uint32_t rtccount;
+ uint32_t rtcmatch[3];
+ qemu_irq toy_irq;
+} LS7ARtcState;
+
+enum {
+ TOYEN = 1UL << 11,
+ RTCEN = 1UL << 13,
+};
+
+static uint64_t ls7a_rtc_read(void *opaque, hwaddr addr, unsigned size)
+{
+ LS7ARtcState *s = LS7A_RTC(opaque);
+ struct tm tm;
+ unsigned int val;
+
+ val = 0;
+
+ switch (addr) {
+ case SYS_TOYREAD0:
+ qemu_get_timedate(&tm, s->offset);
+ val = (((tm.tm_mon + 1) & TOY_MON_MASK) << TOY_MON_SHIFT)
+ | (((tm.tm_mday) & TOY_DAY_MASK) << TOY_DAY_SHIFT)
+ | (((tm.tm_hour) & TOY_HOUR_MASK) << TOY_HOUR_SHIFT)
+ | (((tm.tm_min) & TOY_MIN_MASK) << TOY_MIN_SHIFT)
+ | (((tm.tm_sec) & TOY_SEC_MASK) << TOY_SEC_SHIFT) | 0x0;
+ break;
+ case SYS_TOYREAD1:
+ qemu_get_timedate(&tm, s->offset);
+ val = tm.tm_year;
+ break;
+ case SYS_TOYMATCH0:
+ val = s->toymatch[0];
+ break;
+ case SYS_TOYMATCH1:
+ val = s->toymatch[1];
+ break;
+ case SYS_TOYMATCH2:
+ val = s->toymatch[2];
+ break;
+ case SYS_RTCCTRL:
+ val = s->cntrctl;
+ break;
+ case SYS_RTCREAD0:
+ val = s->rtccount;
+ break;
+ case SYS_RTCMATCH0:
+ val = s->rtcmatch[0];
+ break;
+ case SYS_RTCMATCH1:
+ val = s->rtcmatch[1];
+ break;
+ case SYS_RTCMATCH2:
+ val = s->rtcmatch[2];
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ return val;
+}
+
+static void ls7a_rtc_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ LS7ARtcState *s = LS7A_RTC(opaque);
+ struct tm tm;
+ int64_t alarm_offset, year_diff, expire_time;
+
+ switch (addr) {
+ case SYS_TOYWRITE0:
+ qemu_get_timedate(&tm, s->offset);
+ tm.tm_sec = (val >> TOY_SEC_SHIFT) & TOY_SEC_MASK;
+ tm.tm_min = (val >> TOY_MIN_SHIFT) & TOY_MIN_MASK;
+ tm.tm_hour = (val >> TOY_HOUR_SHIFT) & TOY_HOUR_MASK;
+ tm.tm_mday = ((val >> TOY_DAY_SHIFT) & TOY_DAY_MASK);
+ tm.tm_mon = ((val >> TOY_MON_SHIFT) & TOY_MON_MASK) - 1;
+ s->offset = qemu_timedate_diff(&tm);
+ break;
+ case SYS_TOYWRITE1:
+ qemu_get_timedate(&tm, s->offset);
+ tm.tm_year = val;
+ s->offset = qemu_timedate_diff(&tm);
+ break;
+ case SYS_TOYMATCH0:
+ s->toymatch[0] = val;
+ qemu_get_timedate(&tm, s->offset);
+ tm.tm_sec = (val >> TOY_MATCH_SEC_SHIFT) & TOY_MATCH_SEC_MASK;
+ tm.tm_min = (val >> TOY_MATCH_MIN_SHIFT) & TOY_MATCH_MIN_MASK;
+ tm.tm_hour = ((val >> TOY_MATCH_HOUR_SHIFT) & TOY_MATCH_HOUR_MASK);
+ tm.tm_mday = ((val >> TOY_MATCH_DAY_SHIFT) & TOY_MATCH_DAY_MASK);
+ tm.tm_mon = ((val >> TOY_MATCH_MON_SHIFT) & TOY_MATCH_MON_MASK) - 1;
+ year_diff = ((val >> TOY_MATCH_YEAR_SHIFT) & TOY_MATCH_YEAR_MASK);
+ year_diff = year_diff - (tm.tm_year & TOY_MATCH_YEAR_MASK);
+ tm.tm_year = tm.tm_year + year_diff;
+ alarm_offset = qemu_timedate_diff(&tm) - s->offset;
+ if ((alarm_offset < 0) && (alarm_offset > -5)) {
+ alarm_offset = 0;
+ }
+ expire_time = qemu_clock_get_ms(rtc_clock);
+ expire_time += ((alarm_offset * 1000) + 100);
+ timer_mod(s->timer, expire_time);
+ break;
+ case SYS_TOYMATCH1:
+ s->toymatch[1] = val;
+ break;
+ case SYS_TOYMATCH2:
+ s->toymatch[2] = val;
+ break;
+ case SYS_RTCCTRL:
+ s->cntrctl = val;
+ break;
+ case SYS_RTCWRTIE0:
+ s->rtccount = val;
+ break;
+ case SYS_RTCMATCH0:
+ s->rtcmatch[0] = val;
+ break;
+ case SYS_RTCMATCH1:
+ val = s->rtcmatch[1];
+ break;
+ case SYS_RTCMATCH2:
+ val = s->rtcmatch[2];
+ break;
+ default:
+ break;
+ }
+}
+
+static const MemoryRegionOps ls7a_rtc_ops = {
+ .read = ls7a_rtc_read,
+ .write = ls7a_rtc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void toy_timer(void *opaque)
+{
+ LS7ARtcState *s = LS7A_RTC(opaque);
+
+ if (s->cntrctl & TOY_ENABLE_BIT) {
+ qemu_irq_pulse(s->toy_irq);
+ }
+}
+
+static void ls7a_rtc_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ LS7ARtcState *d = LS7A_RTC(sbd);
+ memory_region_init_io(&d->iomem, NULL, &ls7a_rtc_ops,
+ (void *)d, "ls7a_rtc", 0x100);
+
+ sysbus_init_irq(sbd, &d->toy_irq);
+
+ sysbus_init_mmio(sbd, &d->iomem);
+ d->timer = timer_new_ms(rtc_clock, toy_timer, d);
+ timer_mod(d->timer, qemu_clock_get_ms(rtc_clock) + 100);
+ d->offset = 0;
+
+ create_unimplemented_device("mmio fallback 1", 0x10013ffc, 0x4);
+}
+
+static int ls7a_rtc_pre_save(void *opaque)
+{
+ LS7ARtcState *s = LS7A_RTC(opaque);
+ struct tm tm;
+ int64_t year_diff, value;
+
+ value = s->toymatch[0];
+ qemu_get_timedate(&tm, s->offset);
+ tm.tm_sec = (value >> TOY_MATCH_SEC_SHIFT) & TOY_MATCH_SEC_MASK;
+ tm.tm_min = (value >> TOY_MATCH_MIN_SHIFT) & TOY_MATCH_MIN_MASK;
+ tm.tm_hour = ((value >> TOY_MATCH_HOUR_SHIFT) & TOY_MATCH_HOUR_MASK);
+ tm.tm_mday = ((value >> TOY_MATCH_DAY_SHIFT) & TOY_MATCH_DAY_MASK);
+ tm.tm_mon = ((value >> TOY_MATCH_MON_SHIFT) & TOY_MATCH_MON_MASK) - 1;
+ year_diff = ((value >> TOY_MATCH_YEAR_SHIFT) & TOY_MATCH_YEAR_MASK);
+ year_diff = year_diff - (tm.tm_year & TOY_MATCH_YEAR_MASK);
+ tm.tm_year = tm.tm_year + year_diff;
+ s->save_alarm_offset = qemu_timedate_diff(&tm) - s->offset;
+
+ return 0;
+}
+
+static int ls7a_rtc_post_load(void *opaque, int version_id)
+{
+ LS7ARtcState *s = LS7A_RTC(opaque);
+ int64_t expire_time;
+
+ expire_time = qemu_clock_get_ms(rtc_clock) + (s->save_alarm_offset * 1000);
+ timer_mod(s->timer, expire_time);
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_ls7a_rtc = {
+ .name = "ls7a_rtc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .pre_save = ls7a_rtc_pre_save,
+ .post_load = ls7a_rtc_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_INT64(offset, LS7ARtcState),
+ VMSTATE_INT64(save_alarm_offset, LS7ARtcState),
+ VMSTATE_UINT32(toymatch[0], LS7ARtcState),
+ VMSTATE_UINT32(cntrctl, LS7ARtcState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void ls7a_rtc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->vmsd = &vmstate_ls7a_rtc;
+ dc->realize = ls7a_rtc_realize;
+ dc->desc = "ls7a rtc";
+}
+
+static const TypeInfo ls7a_rtc_info = {
+ .name = TYPE_LS7A_RTC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LS7ARtcState),
+ .class_init = ls7a_rtc_class_init,
+};
+
+static void ls7a_rtc_register_types(void)
+{
+ type_register_static(&ls7a_rtc_info);
+}
+
+type_init(ls7a_rtc_register_types)
diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build
index 8fd8d8f9a7..1d4870d8c4 100644
--- a/hw/rtc/meson.build
+++ b/hw/rtc/meson.build
@@ -11,6 +11,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_rtc.c'))
softmmu_ss.add(when: 'CONFIG_SUN4V_RTC', if_true: files('sun4v-rtc.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_rtc.c'))
softmmu_ss.add(when: 'CONFIG_GOLDFISH_RTC', if_true: files('goldfish_rtc.c'))
+softmmu_ss.add(when: 'CONFIG_LS7A_RTC', if_true: files('ls7a_rtc.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-rtc.c'))
specific_ss.add(when: 'CONFIG_MC146818RTC', if_true: files('mc146818rtc.c'))
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index cfa990ff8a..d7d0cac049 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -40,6 +40,10 @@
#define LS7A_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
#define LS7A_UART_BASE 0x1fe001e0
+#define LS7A_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)
+#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000)
+#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100)
+#define LS7A_RTC_LEN 0x100
struct LS7APCIState {
/*< private >*/
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 25/30] hw/loongarch: Add default bios startup support.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (23 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 24/30] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 26/30] hw/loongarch: Add -kernel and -initrd options support Xiaojuan Yang
` (6 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/Kconfig | 4 ++++
hw/loongarch/fw_cfg.c | 33 ++++++++++++++++++++++++++++++
hw/loongarch/fw_cfg.h | 15 ++++++++++++++
hw/loongarch/loongson3.c | 35 ++++++++++++++++++++++++++++++++
hw/loongarch/meson.build | 1 +
include/hw/loongarch/loongarch.h | 8 ++++++++
6 files changed, 96 insertions(+)
create mode 100644 hw/loongarch/fw_cfg.c
create mode 100644 hw/loongarch/fw_cfg.h
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 0f759eaa37..06bfb82b1d 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -13,3 +13,7 @@ config LOONGSON3_LS7A
select LOONGARCH_PCH_MSI
select LOONGARCH_EXTIOI
select LS7A_RTC
+ select FW_CFG_LOONGARCH
+
+config FW_CFG_LOONGARCH
+ bool
diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c
new file mode 100644
index 0000000000..4cefffc896
--- /dev/null
+++ b/hw/loongarch/fw_cfg.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU fw_cfg helpers (LoongArch specific)
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/loongarch/fw_cfg.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/nvram/fw_cfg.h"
+#include "sysemu/sysemu.h"
+
+static void fw_cfg_boot_set(void *opaque, const char *boot_device,
+ Error **errp)
+{
+ fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
+}
+
+FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms)
+{
+ FWCfgState *fw_cfg;
+ int max_cpus = ms->smp.max_cpus;
+ int smp_cpus = ms->smp.cpus;
+
+ fw_cfg = fw_cfg_init_mem_wide(FW_CFG_ADDR + 8, FW_CFG_ADDR, 8, 0, NULL);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
+
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
+ return fw_cfg;
+}
diff --git a/hw/loongarch/fw_cfg.h b/hw/loongarch/fw_cfg.h
new file mode 100644
index 0000000000..7c0de4db4a
--- /dev/null
+++ b/hw/loongarch/fw_cfg.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU fw_cfg helpers (LoongArch specific)
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_FW_CFG_H
+#define HW_LOONGARCH_FW_CFG_H
+
+#include "hw/boards.h"
+#include "hw/nvram/fw_cfg.h"
+
+FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms);
+#endif
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index ff0ef71e7b..31c285a74d 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -17,6 +17,8 @@
#include "sysemu/reset.h"
#include "hw/irq.h"
#include "net/net.h"
+#include "hw/loader.h"
+#include "elf.h"
#include "hw/loongarch/loongarch.h"
#include "hw/intc/loongarch_ipi.h"
#include "hw/intc/loongarch_extioi.h"
@@ -24,6 +26,9 @@
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/pci-host/ls7a.h"
#include "hw/misc/unimp.h"
+#include "hw/loongarch/fw_cfg.h"
+
+#define LOONGSON3_BIOSNAME "loongarch_bios.bin"
static void loongarch_cpu_reset(void *opaque)
{
@@ -260,6 +265,8 @@ static void loongarch_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
int i;
+ int bios_size;
+ char *filename;
if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
@@ -284,6 +291,11 @@ static void loongarch_init(MachineState *machine)
LOONGARCH_SIMPLE_MMIO_OPS(MISC_FUNC_REG, "loongarch_misc_func", 0x8, 3);
}
+ if (ram_size < 1 * GiB) {
+ error_report("ram_size must be greater than 1G due to the bios memory layout");
+ exit(1);
+ }
+
/* Add memory region */
memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
machine->ram, 0, 256 * MiB);
@@ -302,6 +314,28 @@ static void loongarch_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), LOONGARCH_ISA_IO_BASE,
&lams->isa_io);
+ /* load the BIOS image. */
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
+ machine->firmware ?: LOONGSON3_BIOSNAME);
+ if (filename) {
+ bios_size = load_image_targphys(filename, LA_BIOS_BASE, LA_BIOS_SIZE);
+ lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine);
+ rom_set_fw(lams->fw_cfg);
+ g_free(filename);
+ } else {
+ bios_size = -1;
+ }
+
+ if ((bios_size < 0 || bios_size > LA_BIOS_SIZE) && !qtest_enabled()) {
+ error_report("Could not load LOONGARCH bios '%s'", machine->firmware);
+ exit(1);
+ }
+
+ memory_region_init_ram(&lams->bios, NULL, "loongarch.bios",
+ LA_BIOS_SIZE, &error_fatal);
+ memory_region_set_readonly(&lams->bios, true);
+ memory_region_add_subregion(get_system_memory(), LA_BIOS_BASE, &lams->bios);
+
/* Initialize the IO interrupt subsystem */
loongarch_irq_init(lams);
}
@@ -317,6 +351,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data)
mc->default_ram_id = "loongarch.ram";
mc->max_cpus = LOONGARCH_MAX_VCPUS;
mc->is_default = 1;
+ mc->default_machine_opts = "firmware=loongarch_bios.bin";
mc->default_kernel_irqchip_split = false;
mc->block_default_type = IF_VIRTIO;
mc->default_boot_order = "c";
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
index 1db3529cbc..fed69dfb62 100644
--- a/hw/loongarch/meson.build
+++ b/hw/loongarch/meson.build
@@ -1,4 +1,5 @@
loongarch_ss = ss.source_set()
loongarch_ss.add(when: 'CONFIG_LOONGSON3_LS7A', if_true: files('loongson3.c'))
+loongarch_ss.add(when: 'CONFIG_FW_CFG_LOONGARCH', if_true: files('fw_cfg.c'))
hw_arch += {'loongarch': loongarch_ss}
diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
index fd95fbce91..59bbea86fe 100644
--- a/include/hw/loongarch/loongarch.h
+++ b/include/hw/loongarch/loongarch.h
@@ -35,6 +35,10 @@
#define LOONGARCH_ISA_IO_BASE 0x18000000UL
#define LOONGARCH_ISA_IO_SIZE 0x0004000
+#define FW_CFG_ADDR 0x1e020000
+#define LA_BIOS_BASE 0x1c000000
+#define LA_BIOS_SIZE (4 * 1024 * 1024)
+
typedef struct LoongArchMachineState {
/*< private >*/
MachineState parent_obj;
@@ -42,6 +46,10 @@ typedef struct LoongArchMachineState {
MemoryRegion lowmem;
MemoryRegion highmem;
MemoryRegion isa_io;
+ MemoryRegion bios;
+
+ /* State for other subsystems/APIs: */
+ FWCfgState *fw_cfg;
} LoongArchMachineState;
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson3-ls7a")
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 26/30] hw/loongarch: Add -kernel and -initrd options support
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (24 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 25/30] hw/loongarch: Add default bios startup support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 27/30] hw/loongarch: Add LoongArch smbios support Xiaojuan Yang
` (5 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/loongson3.c | 81 ++++++++++++++++++++++++++++++++
include/hw/loongarch/loongarch.h | 5 ++
2 files changed, 86 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 31c285a74d..546ef6f4f1 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -30,6 +30,76 @@
#define LOONGSON3_BIOSNAME "loongarch_bios.bin"
+static struct _loaderparams {
+ unsigned long ram_size;
+ const char *kernel_filename;
+ const char *kernel_cmdline;
+ const char *initrd_filename;
+} loaderparams;
+
+static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
+{
+ return addr & 0x1fffffffll;
+}
+
+static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg)
+{
+ int64_t kernel_entry, kernel_low, kernel_high, initrd_size = 0;
+ long kernel_size;
+ ram_addr_t initrd_offset = 0;
+ void *cmdline_buf;
+ int ret = 0;
+
+ kernel_size = load_elf(loaderparams.kernel_filename, NULL,
+ cpu_loongarch_virt_to_phys, NULL,
+ (uint64_t *)&kernel_entry, (uint64_t *)&kernel_low,
+ (uint64_t *)&kernel_high, NULL, 0,
+ EM_LOONGARCH, 1, 0);
+
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s': %s",
+ loaderparams.kernel_filename,
+ load_elf_strerror(kernel_size));
+ exit(1);
+ }
+
+ fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ENTRY, kernel_entry);
+
+ if (loaderparams.initrd_filename) {
+ initrd_size = get_image_size(loaderparams.initrd_filename);
+
+ if (initrd_size > 0) {
+ initrd_offset = MAX(INITRD_BASE,
+ ROUND_UP(kernel_high, INITRD_PAGE_SIZE));
+ if (initrd_offset + initrd_size > 0x10000000) {
+ error_report("ramdisk '%s' is too big",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+ initrd_size = load_image_targphys(loaderparams.initrd_filename,
+ initrd_offset,
+ loaderparams.ram_size - initrd_offset);
+ }
+ if (initrd_size == (target_ulong) -1) {
+ error_report("could not load initial ram disk '%s'",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+ }
+
+ cmdline_buf = g_malloc0(COMMAND_LINE_SIZE);
+ if (initrd_size > 0)
+ ret = (1 + snprintf(cmdline_buf, COMMAND_LINE_SIZE,
+ "initrd=0x%lx,%li %s", initrd_offset,
+ initrd_size, loaderparams.kernel_cmdline));
+ else
+ ret = (1 + snprintf(cmdline_buf, COMMAND_LINE_SIZE, "%s",
+ loaderparams.kernel_cmdline));
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, ret);
+ fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, (const char *)cmdline_buf);
+}
+
static void loongarch_cpu_reset(void *opaque)
{
LoongArchCPU *cpu = opaque;
@@ -257,6 +327,9 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
static void loongarch_init(MachineState *machine)
{
const char *cpu_model = machine->cpu_type;
+ const char *kernel_filename = machine->kernel_filename;
+ const char *kernel_cmdline = machine->kernel_cmdline;
+ const char *initrd_filename = machine->initrd_filename;
LoongArchCPU *la_cpu;
CPULoongArchState *env;
ram_addr_t offset = 0;
@@ -331,6 +404,14 @@ static void loongarch_init(MachineState *machine)
exit(1);
}
+ if (kernel_filename) {
+ loaderparams.ram_size = ram_size;
+ loaderparams.kernel_filename = kernel_filename;
+ loaderparams.kernel_cmdline = kernel_cmdline;
+ loaderparams.initrd_filename = initrd_filename;
+ fw_cfg_add_kernel_info(lams->fw_cfg);
+ }
+
memory_region_init_ram(&lams->bios, NULL, "loongarch.bios",
LA_BIOS_SIZE, &error_fatal);
memory_region_set_readonly(&lams->bios, true);
diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
index 59bbea86fe..9ffcf8429f 100644
--- a/include/hw/loongarch/loongarch.h
+++ b/include/hw/loongarch/loongarch.h
@@ -39,6 +39,11 @@
#define LA_BIOS_BASE 0x1c000000
#define LA_BIOS_SIZE (4 * 1024 * 1024)
+/* Kernels can be configured with 64KB pages */
+#define INITRD_PAGE_SIZE (64 * KiB)
+#define INITRD_BASE 0x04000000
+#define COMMAND_LINE_SIZE 4096
+
typedef struct LoongArchMachineState {
/*< private >*/
MachineState parent_obj;
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 27/30] hw/loongarch: Add LoongArch smbios support
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (25 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 26/30] hw/loongarch: Add -kernel and -initrd options support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 28/30] hw/loongarch: Add LoongArch acpi support Xiaojuan Yang
` (4 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 40 ++++++++++++++++++++++++++++++++
include/hw/loongarch/loongarch.h | 1 +
3 files changed, 42 insertions(+)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 06bfb82b1d..6e24e112b3 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -14,6 +14,7 @@ config LOONGSON3_LS7A
select LOONGARCH_EXTIOI
select LS7A_RTC
select FW_CFG_LOONGARCH
+ select SMBIOS
config FW_CFG_LOONGARCH
bool
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 546ef6f4f1..8856225a99 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -27,6 +27,7 @@
#include "hw/pci-host/ls7a.h"
#include "hw/misc/unimp.h"
#include "hw/loongarch/fw_cfg.h"
+#include "hw/firmware/smbios.h"
#define LOONGSON3_BIOSNAME "loongarch_bios.bin"
@@ -100,6 +101,42 @@ static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg)
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, (const char *)cmdline_buf);
}
+static void loongarch_build_smbios(LoongArchMachineState *lams)
+{
+ MachineState *ms = MACHINE(lams);
+ MachineClass *mc = MACHINE_GET_CLASS(lams);
+ uint8_t *smbios_tables, *smbios_anchor;
+ size_t smbios_tables_len, smbios_anchor_len;
+ const char *product = "QEMU Virtual Machine";
+
+ if (!lams->fw_cfg) {
+ return;
+ }
+
+ product = "Loongson-3A5000-7A1000-TCG";
+
+ smbios_set_defaults("QEMU", product, mc->name, false,
+ true, SMBIOS_ENTRY_POINT_TYPE_64);
+
+ smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len,
+ &smbios_anchor, &smbios_anchor_len, &error_fatal);
+
+ if (smbios_anchor) {
+ fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables",
+ smbios_tables, smbios_tables_len);
+ fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor",
+ smbios_anchor, smbios_anchor_len);
+ }
+}
+
+static
+void loongarch_machine_done(Notifier *notifier, void *data)
+{
+ LoongArchMachineState *lams = container_of(notifier,
+ LoongArchMachineState, machine_done);
+ loongarch_build_smbios(lams);
+}
+
static void loongarch_cpu_reset(void *opaque)
{
LoongArchCPU *cpu = opaque;
@@ -417,6 +454,9 @@ static void loongarch_init(MachineState *machine)
memory_region_set_readonly(&lams->bios, true);
memory_region_add_subregion(get_system_memory(), LA_BIOS_BASE, &lams->bios);
+ lams->machine_done.notify = loongarch_machine_done;
+ qemu_add_machine_init_done_notifier(&lams->machine_done);
+
/* Initialize the IO interrupt subsystem */
loongarch_irq_init(lams);
}
diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
index 9ffcf8429f..9080864804 100644
--- a/include/hw/loongarch/loongarch.h
+++ b/include/hw/loongarch/loongarch.h
@@ -54,6 +54,7 @@ typedef struct LoongArchMachineState {
MemoryRegion bios;
/* State for other subsystems/APIs: */
+ Notifier machine_done;
FWCfgState *fw_cfg;
} LoongArchMachineState;
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 28/30] hw/loongarch: Add LoongArch acpi support
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (26 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 27/30] hw/loongarch: Add LoongArch smbios support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 29/30] hw/loongarch: Add fdt support Xiaojuan Yang
` (3 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Add a simple acpi model for LoongArch cpu
More complex functions will be added later
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 374 ++++++++++++++++++
hw/acpi/meson.build | 1 +
hw/loongarch/Kconfig | 2 +
hw/loongarch/acpi-build.c | 636 +++++++++++++++++++++++++++++++
hw/loongarch/loongson3.c | 62 ++-
hw/loongarch/meson.build | 1 +
include/hw/acpi/ls7a.h | 53 +++
include/hw/loongarch/loongarch.h | 6 +
include/hw/pci-host/ls7a.h | 5 +
10 files changed, 1142 insertions(+), 2 deletions(-)
create mode 100644 hw/acpi/ls7a.c
create mode 100644 hw/loongarch/acpi-build.c
create mode 100644 include/hw/acpi/ls7a.h
diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
index 622b0b50b7..30f887d479 100644
--- a/hw/acpi/Kconfig
+++ b/hw/acpi/Kconfig
@@ -11,6 +11,10 @@ config ACPI_X86
select ACPI_PIIX4
select ACPI_PCIHP
+config ACPI_LOONGARCH
+ bool
+ select ACPI
+
config ACPI_X86_ICH
bool
select ACPI_X86
diff --git a/hw/acpi/ls7a.c b/hw/acpi/ls7a.c
new file mode 100644
index 0000000000..cc658422dd
--- /dev/null
+++ b/hw/acpi/ls7a.c
@@ -0,0 +1,374 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch ACPI implementation
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "sysemu/sysemu.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/ls7a.h"
+#include "hw/nvram/fw_cfg.h"
+#include "qemu/config-file.h"
+#include "qapi/opts-visitor.h"
+#include "qapi/qapi-events-run-state.h"
+#include "qapi/error.h"
+#include "hw/pci-host/ls7a.h"
+#include "hw/mem/pc-dimm.h"
+#include "hw/mem/nvdimm.h"
+#include "migration/vmstate.h"
+
+static void ls7a_pm_update_sci_fn(ACPIREGS *regs)
+{
+ LS7APMState *pm = container_of(regs, LS7APMState, acpi_regs);
+ acpi_update_sci(&pm->acpi_regs, pm->irq);
+}
+
+static uint64_t ls7a_gpe_readb(void *opaque, hwaddr addr, unsigned width)
+{
+ LS7APMState *pm = opaque;
+ return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
+}
+
+static void ls7a_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+ LS7APMState *pm = opaque;
+ acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
+ acpi_update_sci(&pm->acpi_regs, pm->irq);
+}
+
+static const MemoryRegionOps ls7a_gpe_ops = {
+ .read = ls7a_gpe_readb,
+ .write = ls7a_gpe_writeb,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 1,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+#define VMSTATE_GPE_ARRAY(_field, _state) \
+ { \
+ .name = (stringify(_field)), \
+ .version_id = 0, \
+ .num = ACPI_GPE0_LEN, \
+ .info = &vmstate_info_uint8, \
+ .size = sizeof(uint8_t), \
+ .flags = VMS_ARRAY | VMS_POINTER, \
+ .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
+ }
+
+static uint64_t ls7a_reset_readw(void *opaque, hwaddr addr, unsigned width)
+{
+ return 0;
+}
+
+static void ls7a_reset_writew(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+ if (val & 1) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
+ }
+}
+
+static const MemoryRegionOps ls7a_reset_ops = {
+ .read = ls7a_reset_readw,
+ .write = ls7a_reset_writew,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+const VMStateDescription vmstate_ls7a_pm = {
+ .name = "ls7a_pm",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(acpi_regs.pm1.evt.sts, LS7APMState),
+ VMSTATE_UINT16(acpi_regs.pm1.evt.en, LS7APMState),
+ VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, LS7APMState),
+ VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, LS7APMState),
+ VMSTATE_INT64(acpi_regs.tmr.overflow_time, LS7APMState),
+ VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, LS7APMState),
+ VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, LS7APMState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static inline int64_t acpi_pm_tmr_get_clock(void)
+{
+ return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), PM_TIMER_FREQUENCY,
+ NANOSECONDS_PER_SECOND);
+}
+
+static uint32_t acpi_pm_tmr_get(ACPIREGS *ar)
+{
+ uint32_t d = acpi_pm_tmr_get_clock();
+ return d & 0xffffff;
+}
+
+static void acpi_pm_tmr_timer(void *opaque)
+{
+ ACPIREGS *ar = opaque;
+ qemu_system_wakeup_request(QEMU_WAKEUP_REASON_PMTIMER, NULL);
+ ar->tmr.update_sci(ar);
+}
+
+static uint64_t acpi_pm_tmr_read(void *opaque, hwaddr addr, unsigned width)
+{
+ return acpi_pm_tmr_get(opaque);
+}
+
+static void acpi_pm_tmr_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+}
+
+static const MemoryRegionOps acpi_pm_tmr_ops = {
+ .read = acpi_pm_tmr_read,
+ .write = acpi_pm_tmr_write,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ls7a_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
+ MemoryRegion *parent, uint64_t offset)
+{
+ ar->tmr.update_sci = update_sci;
+ ar->tmr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, acpi_pm_tmr_timer, ar);
+ memory_region_init_io(&ar->tmr.io, memory_region_owner(parent),
+ &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
+ memory_region_add_subregion(parent, offset, &ar->tmr.io);
+}
+
+static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val)
+{
+ uint16_t pm1_sts = acpi_pm1_evt_get_sts(ar);
+ if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) {
+ /* if TMRSTS is reset, then compute the new overflow time */
+ acpi_pm_tmr_calc_overflow_time(ar);
+ }
+ ar->pm1.evt.sts &= ~val;
+}
+
+static uint64_t acpi_pm_evt_read(void *opaque, hwaddr addr, unsigned width)
+{
+ ACPIREGS *ar = opaque;
+ switch (addr) {
+ case 0:
+ return acpi_pm1_evt_get_sts(ar);
+ case 4:
+ return ar->pm1.evt.en;
+ default:
+ return 0;
+ }
+}
+
+static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val)
+{
+ ar->pm1.evt.en = val;
+ qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC,
+ val & ACPI_BITMASK_RT_CLOCK_ENABLE);
+ qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER,
+ val & ACPI_BITMASK_TIMER_ENABLE);
+}
+
+static void acpi_pm_evt_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+ ACPIREGS *ar = opaque;
+ switch (addr) {
+ case 0:
+ acpi_pm1_evt_write_sts(ar, val);
+ ar->pm1.evt.update_sci(ar);
+ break;
+ case 4:
+ acpi_pm1_evt_write_en(ar, val);
+ ar->pm1.evt.update_sci(ar);
+ break;
+ }
+}
+
+static const MemoryRegionOps acpi_pm_evt_ops = {
+ .read = acpi_pm_evt_read,
+ .write = acpi_pm_evt_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ls7a_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
+ MemoryRegion *parent, uint64_t offset)
+{
+ ar->pm1.evt.update_sci = update_sci;
+ memory_region_init_io(&ar->pm1.evt.io, memory_region_owner(parent),
+ &acpi_pm_evt_ops, ar, "acpi-evt", 8);
+ memory_region_add_subregion(parent, offset, &ar->pm1.evt.io);
+}
+
+static uint64_t acpi_pm_cnt_read(void *opaque, hwaddr addr, unsigned width)
+{
+ ACPIREGS *ar = opaque;
+ return ar->pm1.cnt.cnt;
+}
+
+/* ACPI PM1aCNT */
+static void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val)
+{
+ ar->pm1.cnt.cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
+
+ if (val & ACPI_BITMASK_SLEEP_ENABLE) {
+ /* Change suspend type */
+ uint16_t sus_typ = (val >> 10) & 7;
+ switch (sus_typ) {
+ /* Not support s3 s4 yet */
+ case 7: /* Soft power off */
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void acpi_pm_cnt_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+ acpi_pm1_cnt_write(opaque, val);
+}
+
+static const MemoryRegionOps acpi_pm_cnt_ops = {
+ .read = acpi_pm_cnt_read,
+ .write = acpi_pm_cnt_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void acpi_notify_wakeup(Notifier *notifier, void *data)
+{
+ ACPIREGS *ar = container_of(notifier, ACPIREGS, wakeup);
+ WakeupReason *reason = data;
+
+ switch (*reason) {
+ case QEMU_WAKEUP_REASON_RTC:
+ ar->pm1.evt.sts |=
+ (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_RT_CLOCK_STATUS);
+ break;
+ case QEMU_WAKEUP_REASON_PMTIMER:
+ ar->pm1.evt.sts |=
+ (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_TIMER_STATUS);
+ break;
+ case QEMU_WAKEUP_REASON_OTHER:
+ /*
+ * ACPI_BITMASK_WAKE_STATUS should be set on resume.
+ * Pretend that resume was caused by power button
+ */
+ ar->pm1.evt.sts |=
+ (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
+ break;
+ default:
+ break;
+ }
+}
+
+static void ls7a_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent,
+ uint64_t offset)
+{
+ ar->wakeup.notify = acpi_notify_wakeup;
+ qemu_register_wakeup_notifier(&ar->wakeup);
+ memory_region_init_io(&ar->pm1.cnt.io, memory_region_owner(parent),
+ &acpi_pm_cnt_ops, ar, "acpi-cnt", 4);
+ memory_region_add_subregion(parent, offset, &ar->pm1.cnt.io);
+}
+
+static void ls7a_pm_reset(DeviceState *d)
+{
+ LS7APMState *pm = LS7A_PM(d);
+
+ acpi_pm1_evt_reset(&pm->acpi_regs);
+ acpi_pm1_cnt_reset(&pm->acpi_regs);
+ acpi_pm_tmr_reset(&pm->acpi_regs);
+ acpi_gpe_reset(&pm->acpi_regs);
+
+ acpi_update_sci(&pm->acpi_regs, pm->irq);
+}
+
+static void pm_powerdown_req(Notifier *n, void *opaque)
+{
+ LS7APMState *pm = container_of(n, LS7APMState, powerdown_notifier);
+
+ acpi_pm1_evt_power_down(&pm->acpi_regs);
+}
+
+void ls7a_pm_init(DeviceState *ls7a_pm, qemu_irq pm_irq)
+{
+ LS7APMState *pm = LS7A_PM(ls7a_pm);
+ pm->irq = pm_irq;
+}
+
+static void ls7a_pm_realize(DeviceState *dev, Error **errp)
+{
+ LS7APMState *pm = LS7A_PM(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ /*
+ * ls7a board acpi hardware info, including
+ * acpi system io base address
+ * acpi gpe length
+ * acpi sci irq number
+ */
+
+ memory_region_init(&pm->iomem, OBJECT(pm), "ls7a_pm", ACPI_IO_SIZE);
+ sysbus_init_mmio(sbd, &pm->iomem);
+
+ ls7a_pm_tmr_init(&pm->acpi_regs, ls7a_pm_update_sci_fn,
+ &pm->iomem, LS7A_PM_TMR_BLK);
+ ls7a_pm1_evt_init(&pm->acpi_regs, ls7a_pm_update_sci_fn,
+ &pm->iomem, LS7A_PM_EVT_BLK);
+ ls7a_pm1_cnt_init(&pm->acpi_regs, &pm->iomem, LS7A_PM_CNT_BLK);
+
+ acpi_gpe_init(&pm->acpi_regs, ACPI_GPE0_LEN);
+ memory_region_init_io(&pm->iomem_gpe, OBJECT(pm), &ls7a_gpe_ops, pm,
+ "acpi-gpe0", ACPI_GPE0_LEN);
+ sysbus_init_mmio(sbd, &pm->iomem_gpe);
+
+ memory_region_init_io(&pm->iomem_reset, OBJECT(pm),
+ &ls7a_reset_ops, pm, "acpi-reset", 4);
+ sysbus_init_mmio(sbd, &pm->iomem_reset);
+
+ pm->powerdown_notifier.notify = pm_powerdown_req;
+ qemu_register_powerdown_notifier(&pm->powerdown_notifier);
+}
+
+static void ls7a_pm_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = ls7a_pm_realize;
+ dc->reset = ls7a_pm_reset;
+ dc->desc = "PM";
+ dc->vmsd = &vmstate_ls7a_pm;
+}
+
+static const TypeInfo ls7a_pm_info = {
+ .name = TYPE_LS7A_PM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LS7APMState),
+ .class_init = ls7a_pm_class_init,
+};
+
+static void ls7a_pm_register_types(void)
+{
+ type_register_static(&ls7a_pm_info);
+}
+
+type_init(ls7a_pm_register_types)
diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build
index adf6347bc4..52f851d52b 100644
--- a/hw/acpi/meson.build
+++ b/hw/acpi/meson.build
@@ -25,6 +25,7 @@ acpi_ss.add(when: 'CONFIG_ACPI_X86_ICH', if_true: files('ich9.c', 'tco.c'))
acpi_ss.add(when: 'CONFIG_IPMI', if_true: files('ipmi.c'), if_false: files('ipmi-stub.c'))
acpi_ss.add(when: 'CONFIG_PC', if_false: files('acpi-x86-stub.c'))
acpi_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c'))
+acpi_ss.add(when: 'CONFIG_ACPI_LOONGARCH', if_true: files('ls7a.c'))
softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-build-stub.c', 'ghes-stub.c'))
softmmu_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss)
softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c', 'aml-build-stub.c',
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 6e24e112b3..d3c8f8768e 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -15,6 +15,8 @@ config LOONGSON3_LS7A
select LS7A_RTC
select FW_CFG_LOONGARCH
select SMBIOS
+ select ACPI_LOONGARCH
+ select ACPI_PCI
config FW_CFG_LOONGARCH
bool
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
new file mode 100644
index 0000000000..ea189efe7d
--- /dev/null
+++ b/hw/loongarch/acpi-build.c
@@ -0,0 +1,636 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Support for generating ACPI tables and passing them to Guests
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/bitmap.h"
+#include "hw/pci/pci.h"
+#include "hw/core/cpu.h"
+#include "target/loongarch/cpu.h"
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/nvram/fw_cfg.h"
+#include "hw/acpi/bios-linker-loader.h"
+#include "migration/vmstate.h"
+#include "hw/mem/memory-device.h"
+#include "sysemu/reset.h"
+
+/* Supported chipsets: */
+#include "hw/pci-host/ls7a.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/acpi/aml-build.h"
+
+#include "hw/acpi/utils.h"
+#include "hw/acpi/pci.h"
+
+#include "qom/qom-qobject.h"
+
+#include "hw/acpi/ls7a.h"
+
+#define ACPI_BUILD_ALIGN_SIZE 0x1000
+#define ACPI_BUILD_TABLE_SIZE 0x20000
+
+#ifdef DEBUG_ACPI_BUILD
+#define ACPI_BUILD_DPRINTF(fmt, ...) \
+ do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
+#else
+#define ACPI_BUILD_DPRINTF(fmt, ...)
+#endif
+
+static void init_common_fadt_data(AcpiFadtData *data)
+{
+ AmlAddressSpace as = AML_AS_SYSTEM_MEMORY;
+ uint64_t base = LS7A_ACPI_REG_BASE;
+ AcpiFadtData fadt = {
+ .rev = 3,
+ .flags =
+ (1 << ACPI_FADT_F_WBINVD) |
+ (1 << ACPI_FADT_F_PROC_C1) |
+ (1 << ACPI_FADT_F_SLP_BUTTON) |
+ (1 << ACPI_FADT_F_TMR_VAL_EXT) |
+ (1 << ACPI_FADT_F_RESET_REG_SUP) ,
+ .plvl2_lat = 0xfff /* C2 state not supported */,
+ .plvl3_lat = 0xfff /* C3 state not supported */,
+ .smi_cmd = 0x00,
+ .sci_int = ACPI_SCI_IRQ,
+ .acpi_enable_cmd = 0x00,
+ .acpi_disable_cmd = 0x00,
+ .pm1a_evt = { .space_id = as, .bit_width = 8 * 8,
+ .address = base + LS7A_PM_EVT_BLK },
+ .pm1a_cnt = { .space_id = as, .bit_width = 4 * 8,
+ .address = base + LS7A_PM_CNT_BLK },
+ .pm_tmr = { .space_id = as, .bit_width = 4 * 8,
+ .address = base + LS7A_PM_TMR_BLK },
+ .gpe0_blk = { .space_id = as, .bit_width = 8 * 8,
+ .address = base + LS7A_GPE0_STS_REG},
+ .reset_reg = { .space_id = as, .bit_width = 4 * 8,
+ .address = base + LS7A_GPE0_RESET_REG},
+ .reset_val = 0x1,
+ };
+ *data = fadt;
+}
+
+static void acpi_align_size(GArray *blob, unsigned align)
+{
+ /*
+ * Align size to multiple of given size. This reduces the chance
+ * we need to change size in the future (breaking cross version migration).
+ */
+ g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
+}
+
+/*
+ * ACPI spec 1.0b,
+ * 5.2.6 Firmware ACPI Control Structure
+ */
+static void
+build_facs(GArray *table_data)
+{
+ const char *sig = "FACS";
+ const uint8_t reserved[40] = {};
+
+ g_array_append_vals(table_data, sig, 4); /* Signature */
+ build_append_int_noprefix(table_data, 64, 4); /* Length */
+ build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
+ build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
+ build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+ g_array_append_vals(table_data, reserved, 40); /* Reserved */
+}
+
+static void
+build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
+{
+ MachineState *ms = MACHINE(lams);
+ int i;
+ AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id,
+ .oem_table_id = lams->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+
+ /* Local APIC Address */
+ build_append_int_noprefix(table_data, 0, 4);
+ build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
+
+ for (i = 0; i < ms->smp.cpus; i++) {
+ /* Rev 1.0b, Table 5-13 Processor Core Interrupt Controller Structure */
+ build_append_int_noprefix(table_data, 17, 1); /* Type */
+ build_append_int_noprefix(table_data, 15, 1); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Version */
+ build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */
+ build_append_int_noprefix(table_data, i, 4); /* Core ID */
+ build_append_int_noprefix(table_data, 1, 4); /* Flags */
+ }
+
+ /* Rev 1.0b, Table 5-13 Extend I/O Interrupt Controller Structure */
+ build_append_int_noprefix(table_data, 20, 1); /* Type */
+ build_append_int_noprefix(table_data, 13, 1); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Version */
+ build_append_int_noprefix(table_data, 3, 1); /* Cascade */
+ build_append_int_noprefix(table_data, 0, 1); /* Node */
+ build_append_int_noprefix(table_data, 0xffff, 8); /* Node map */
+
+ /* Rev 1.0b, Table 5-13 MSI Interrupt Controller Structure */
+ build_append_int_noprefix(table_data, 21, 1); /* Type */
+ build_append_int_noprefix(table_data, 19, 1); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Version */
+ build_append_int_noprefix(table_data, 0x2ff00000, 8);/* Address */
+ build_append_int_noprefix(table_data, 0x40, 4); /* Start */
+ build_append_int_noprefix(table_data, 0xc0, 4); /* Count */
+
+ /* Rev 1.0b, Table 5-13 Bridge I/O Interrupt Controller Structure */
+ build_append_int_noprefix(table_data, 22, 1); /* Type */
+ build_append_int_noprefix(table_data, 17, 1); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Version */
+ build_append_int_noprefix(table_data, 0x10000000, 8);/* Address */
+ build_append_int_noprefix(table_data, 0x1000, 2); /* Size */
+ build_append_int_noprefix(table_data, 0, 2); /* Id */
+ build_append_int_noprefix(table_data, 0x40, 2); /* Base */
+
+ acpi_table_end(linker, &table);
+}
+
+/*
+ * ACPI spec, Revision 3.0
+ * 5.2.15 System Resource Affinity Table (SRAT)
+ */
+static void
+build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
+{
+ uint64_t i, mem_len, mem_base;
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
+ MachineState *ms = MACHINE(lams);
+ AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id,
+ .oem_table_id = lams->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+ build_append_int_noprefix(table_data, 1, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
+
+ for (i = 0; i < ms->smp.cpus; ++i) {
+ /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
+ build_append_int_noprefix(table_data, 0, 1); /* Type */
+ build_append_int_noprefix(table_data, 16, 1); /* Length */
+ /* Proximity Domain [7:0] */
+ build_append_int_noprefix(table_data, 0, 1);
+ build_append_int_noprefix(table_data, i, 1); /* APIC ID */
+ /* Flags, Table 5-36 */
+ build_append_int_noprefix(table_data, 1, 4);
+ build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
+ /* Proximity Domain [31:8] */
+ build_append_int_noprefix(table_data, 0, 3);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ }
+
+ mem_base = 0;
+ mem_len = 0x10000000;
+ build_srat_memory(table_data, mem_base, mem_len,
+ 0, MEM_AFFINITY_ENABLED);
+
+ mem_base = 0x90000000;
+ mem_len = machine->ram_size - 0x10000000;
+ build_srat_memory(table_data, mem_base, mem_len,
+ 0, MEM_AFFINITY_ENABLED);
+
+ acpi_table_end(linker, &table);
+}
+
+typedef
+struct AcpiBuildState {
+ /* Copy of table in RAM (for patching). */
+ MemoryRegion *table_mr;
+ /* Is table patched? */
+ uint8_t patched;
+ void *rsdp;
+ MemoryRegion *rsdp_mr;
+ MemoryRegion *linker_mr;
+} AcpiBuildState;
+
+static void build_ls7a_pci0_int(Aml *table)
+{
+ Aml *sb_scope = aml_scope("_SB");
+ Aml *pci0_scope = aml_scope("PCI0");
+ Aml *prt_pkg = aml_varpackage(128);
+ int slot, pin;
+
+ for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
+ for (pin = 0; pin < PCI_NUM_PINS; pin++) {
+ Aml *pkg = aml_package(4);
+ aml_append(pkg, aml_int((slot << 16) | 0xFFFF));
+ aml_append(pkg, aml_int(pin));
+ aml_append(pkg, aml_int(0));
+ aml_append(pkg, aml_int(80 + (slot * 4 + pin) % LS7A_PCI_IRQS));
+ aml_append(prt_pkg, pkg);
+ }
+ }
+ aml_append(pci0_scope, aml_name_decl("_PRT", prt_pkg));
+ aml_append(sb_scope, pci0_scope);
+ aml_append(table, sb_scope);
+}
+
+static void build_dbg_aml(Aml *table)
+{
+ Aml *field;
+ Aml *method;
+ Aml *while_ctx;
+ Aml *scope = aml_scope("\\");
+ Aml *buf = aml_local(0);
+ Aml *len = aml_local(1);
+ Aml *idx = aml_local(2);
+
+ aml_append(scope,
+ aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
+ field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("DBGB", 8));
+ aml_append(scope, field);
+
+ method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
+
+ aml_append(method, aml_to_hexstring(aml_arg(0), buf));
+ aml_append(method, aml_to_buffer(buf, buf));
+ aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
+ aml_append(method, aml_store(aml_int(0), idx));
+
+ while_ctx = aml_while(aml_lless(idx, len));
+ aml_append(while_ctx,
+ aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
+ aml_append(while_ctx, aml_increment(idx));
+ aml_append(method, while_ctx);
+ aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
+ aml_append(scope, method);
+ aml_append(table, scope);
+}
+
+static Aml *build_ls7a_osc_method(void)
+{
+ Aml *if_ctx;
+ Aml *if_ctx2;
+ Aml *else_ctx;
+ Aml *method;
+ Aml *a_cwd1 = aml_name("CDW1");
+ Aml *a_ctrl = aml_local(0);
+
+ method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
+ aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
+
+ if_ctx = aml_if(aml_equal(
+ aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
+ aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+ aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+ aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
+
+ /*
+ * Always allow native PME, AER (no dependencies)
+ * Allow SHPC (PCI bridges can have SHPC controller)
+ */
+ aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
+
+ if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
+ /* Unknown revision */
+ aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
+ aml_append(if_ctx, if_ctx2);
+
+ if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
+ /* Capabilities bits were masked */
+ aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
+ aml_append(if_ctx, if_ctx2);
+
+ /* Update DWORD3 in the buffer */
+ aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
+ aml_append(method, if_ctx);
+
+ else_ctx = aml_else();
+ /* Unrecognized UUID */
+ aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
+ aml_append(method, else_ctx);
+
+ aml_append(method, aml_return(aml_arg(3)));
+ return method;
+}
+
+static void build_ls7a_uart_device_aml(Aml *table)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *pkg0, *pkg1, *pkg2;
+ uint32_t uart_irq = LS7A_UART_IRQ;
+
+ Aml *scope = aml_scope("_SB");
+ dev = aml_device("COMA");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE,
+ 0, 0x1FE001E0, 0x1FE001E7, 0, 0x8));
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_SHARED, &uart_irq, 1));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ pkg0 = aml_package(0x2);
+ aml_append(pkg0, aml_int(0x05F5E100));
+ aml_append(pkg0, aml_string("clock-frenquency"));
+ pkg1 = aml_package(0x1);
+ aml_append(pkg1, pkg0);
+ pkg2 = aml_package(0x2);
+ aml_append(pkg2, aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"));
+ aml_append(pkg2, pkg1);
+ aml_append(dev, aml_name_decl("_DSD", pkg2));
+ aml_append(scope, dev);
+ aml_append(table, scope);
+}
+
+static void
+build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
+{
+ Aml *dsdt, *sb_scope, *scope, *dev, *crs, *pkg;
+ uint64_t base = LS7A_ACPI_REG_BASE;
+ int root_bus_limit = 0x7F;
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
+ AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = lams->oem_id,
+ .oem_table_id = lams->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+
+ dsdt = init_aml_allocator();
+
+ build_dbg_aml(dsdt);
+
+ sb_scope = aml_scope("_SB");
+ dev = aml_device("PCI0");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+ aml_append(dev, build_ls7a_osc_method());
+ aml_append(sb_scope, dev);
+ aml_append(dsdt, sb_scope);
+
+ build_ls7a_pci0_int(dsdt);
+ build_ls7a_uart_device_aml(dsdt);
+
+ scope = aml_scope("_GPE");
+ {
+ aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
+ }
+ aml_append(dsdt, scope);
+
+ scope = aml_scope("\\_SB.PCI0");
+ /* Build PCI0._CRS */
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ 0x0000, 0x0, root_bus_limit,
+ 0x0000, root_bus_limit + 1));
+ aml_append(crs,
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, AML_ENTIRE_RANGE,
+ 0x0000, 0x0000, 0xFFFF, 0x18000000, 0x10000));
+ aml_append(crs,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_CACHEABLE, AML_READ_WRITE,
+ 0, LS7A_PCI_MEM_BASE,
+ LS7A_PCI_MEM_BASE + LS7A_PCI_MEM_SIZE - 1,
+ 0, LS7A_PCI_MEM_BASE));
+ aml_append(scope, aml_name_decl("_CRS", crs));
+
+ /* Reserve GPE0 block resources */
+ dev = aml_device("GPE0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
+ aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
+ /* Device present, functioning, decoding, not shown in UI */
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_CACHEABLE, AML_READ_WRITE,
+ 0, base + LS7A_GPE0_STS_REG,
+ base + LS7A_GPE0_STS_REG + 0x3, 0, 0x4));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ aml_append(dsdt, scope);
+
+ scope = aml_scope("\\");
+ pkg = aml_package(4);
+ aml_append(pkg, aml_int(7)); /* PM1a_CNT.SLP_TYP */
+ aml_append(pkg, aml_int(7)); /* PM1b_CNT.SLP_TYP not impl. */
+ aml_append(pkg, aml_int(0)); /* Reserved */
+ aml_append(pkg, aml_int(0)); /* Reserved */
+ aml_append(scope, aml_name_decl("_S5", pkg));
+ aml_append(dsdt, scope);
+
+ /* Copy AML table into ACPI tables blob and patch header there */
+ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
+ acpi_table_end(linker, &table);
+ free_aml_allocator();
+}
+
+static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
+{
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
+ GArray *table_offsets;
+ AcpiFadtData fadt_data;
+ unsigned facs, rsdt, fadt, dsdt;
+ uint8_t *u;
+ size_t aml_len = 0;
+ GArray *tables_blob = tables->table_data;
+
+ init_common_fadt_data(&fadt_data);
+
+ table_offsets = g_array_new(false, true /* Clear */,
+ sizeof(uint32_t));
+ ACPI_BUILD_DPRINTF("init ACPI tables\n");
+
+ bios_linker_loader_alloc(tables->linker,
+ ACPI_BUILD_TABLE_FILE, tables_blob,
+ 64 /* Ensure FACS is aligned */,
+ false /* High memory */);
+
+ /*
+ * FACS is pointed to by FADT.
+ * We place it first since it's the only table that has alignment
+ * requirements.
+ */
+ facs = tables_blob->len;
+ build_facs(tables_blob);
+
+ /* DSDT is pointed to by FADT */
+ dsdt = tables_blob->len;
+ build_dsdt(tables_blob, tables->linker, machine);
+
+ /*
+ * Count the size of the DSDT, we will need it for
+ * legacy sizing of ACPI tables.
+ */
+ aml_len += tables_blob->len - dsdt;
+
+ /* ACPI tables pointed to by RSDT */
+ fadt = tables_blob->len;
+ acpi_add_table(table_offsets, tables_blob);
+ fadt_data.facs_tbl_offset = &facs;
+ fadt_data.dsdt_tbl_offset = &dsdt;
+ fadt_data.xdsdt_tbl_offset = &dsdt;
+ build_fadt(tables_blob, tables->linker, &fadt_data,
+ lams->oem_id, lams->oem_table_id);
+ aml_len += tables_blob->len - fadt;
+
+ acpi_add_table(table_offsets, tables_blob);
+ build_madt(tables_blob, tables->linker, lams);
+
+ acpi_add_table(table_offsets, tables_blob);
+ build_srat(tables_blob, tables->linker, machine);
+
+ acpi_add_table(table_offsets, tables_blob);
+ {
+ AcpiMcfgInfo mcfg = {
+ .base = cpu_to_le64(LS_PCIECFG_BASE),
+ .size = cpu_to_le64(LS_PCIECFG_SIZE),
+ };
+ build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id,
+ lams->oem_table_id);
+ }
+
+ /* Add tables supplied by user (if any) */
+ for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
+ unsigned len = acpi_table_len(u);
+
+ acpi_add_table(table_offsets, tables_blob);
+ g_array_append_vals(tables_blob, u, len);
+ }
+
+ /* RSDT is pointed to by RSDP */
+ rsdt = tables_blob->len;
+ build_rsdt(tables_blob, tables->linker, table_offsets,
+ lams->oem_id, lams->oem_table_id);
+
+ /* RSDP is in FSEG memory, so allocate it separately */
+ {
+ AcpiRsdpData rsdp_data = {
+ .revision = 0,
+ .oem_id = lams->oem_id,
+ .xsdt_tbl_offset = NULL,
+ .rsdt_tbl_offset = &rsdt,
+ };
+ build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
+ }
+
+ /*
+ * The align size is 128, warn if 64k is not enough therefore
+ * the align size could be resized.
+ */
+ if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
+ warn_report("ACPI table size %u exceeds %d bytes,"
+ " migration may not work",
+ tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
+ error_printf("Try removing CPUs, NUMA nodes, memory slots"
+ " or PCI bridges.");
+ }
+
+ acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
+
+ /* Cleanup memory that's no longer used. */
+ g_array_free(table_offsets, true);
+}
+
+static void acpi_ram_update(MemoryRegion *mr, GArray *data)
+{
+ uint32_t size = acpi_data_len(data);
+
+ /*
+ * Make sure RAM size is correct - in case it got changed
+ * e.g. by migration
+ */
+ memory_region_ram_resize(mr, size, &error_abort);
+
+ memcpy(memory_region_get_ram_ptr(mr), data->data, size);
+ memory_region_set_dirty(mr, 0, size);
+}
+
+static void acpi_build_update(void *build_opaque)
+{
+ AcpiBuildState *build_state = build_opaque;
+ AcpiBuildTables tables;
+
+ /* No state to update or already patched? Nothing to do. */
+ if (!build_state || build_state->patched) {
+ return;
+ }
+ build_state->patched = 1;
+
+ acpi_build_tables_init(&tables);
+
+ acpi_build(&tables, MACHINE(qdev_get_machine()));
+
+ acpi_ram_update(build_state->table_mr, tables.table_data);
+ acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
+ acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
+
+ acpi_build_tables_cleanup(&tables, true);
+}
+
+static void acpi_build_reset(void *build_opaque)
+{
+ AcpiBuildState *build_state = build_opaque;
+ build_state->patched = 0;
+}
+
+static const VMStateDescription vmstate_acpi_build = {
+ .name = "acpi_build",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(patched, AcpiBuildState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+void loongarch_acpi_setup(LoongArchMachineState *lams)
+{
+ AcpiBuildTables tables;
+ AcpiBuildState *build_state;
+
+ if (!lams->fw_cfg) {
+ ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
+ return;
+ }
+
+ if (!loongarch_is_acpi_enabled(lams)) {
+ ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
+ return;
+ }
+
+ build_state = g_malloc0(sizeof *build_state);
+
+ acpi_build_tables_init(&tables);
+ acpi_build(&tables, MACHINE(lams));
+
+ /* Now expose it all to Guest */
+ build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
+ build_state, tables.table_data,
+ ACPI_BUILD_TABLE_FILE);
+ assert(build_state->table_mr != NULL);
+
+ build_state->linker_mr =
+ acpi_add_rom_blob(acpi_build_update, build_state,
+ tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
+
+ build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
+ build_state, tables.rsdp,
+ ACPI_BUILD_RSDP_FILE);
+
+ qemu_register_reset(acpi_build_reset, build_state);
+ acpi_build_reset(build_state);
+ vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
+
+ /*
+ * Cleanup tables but don't free the memory: we track it
+ * in build_state.
+ */
+ acpi_build_tables_cleanup(&tables, false);
+}
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 8856225a99..17419c2bf4 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -25,9 +25,12 @@
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/pci-host/ls7a.h"
+#include "hw/acpi/ls7a.h"
#include "hw/misc/unimp.h"
#include "hw/loongarch/fw_cfg.h"
#include "hw/firmware/smbios.h"
+#include "hw/acpi/aml-build.h"
+#include "qapi/qapi-visit-common.h"
#define LOONGSON3_BIOSNAME "loongarch_bios.bin"
@@ -134,6 +137,7 @@ void loongarch_machine_done(Notifier *notifier, void *data)
{
LoongArchMachineState *lams = container_of(notifier,
LoongArchMachineState, machine_done);
+ loongarch_acpi_setup(lams);
loongarch_build_smbios(lams);
}
@@ -215,10 +219,10 @@ static void loongarch_cpu_set_irq(void *opaque, int irq, int level)
static void loongarch_devices_init(DeviceState *pch_pic)
{
- DeviceState *pciehost;
+ DeviceState *pciehost, *ls7a_pm;
SysBusDevice *d;
PCIBus *pci_bus;
- MemoryRegion *pio_alias;
+ MemoryRegion *pio_alias, *pm_reg;
int i;
pciehost = qdev_new(TYPE_LS7A_HOST_DEVICE);
@@ -279,6 +283,19 @@ static void loongarch_devices_init(DeviceState *pch_pic)
sysbus_create_simple("ls7a_rtc", LS7A_RTC_REG_BASE,
qdev_get_gpio_in(pch_pic,
LS7A_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
+
+ /* Init pm */
+ ls7a_pm = qdev_new(TYPE_LS7A_PM);
+ d = SYS_BUS_DEVICE(ls7a_pm);
+ sysbus_realize_and_unref(d, &error_fatal);
+ ls7a_pm_init(ls7a_pm, qdev_get_gpio_in(pch_pic,
+ ACPI_SCI_IRQ - PCH_PIC_IRQ_OFFSET));
+ pm_reg = sysbus_mmio_get_region(d, 0);
+ memory_region_add_subregion(get_system_memory(), ACPI_IO_BASE, pm_reg);
+ memory_region_add_subregion(pm_reg, LS7A_GPE0_STS_REG,
+ sysbus_mmio_get_region(d, 1));
+ memory_region_add_subregion(pm_reg, LS7A_GPE0_RESET_REG,
+ sysbus_mmio_get_region(d, 2));
}
static void loongarch_irq_init(LoongArchMachineState *lams)
@@ -461,6 +478,40 @@ static void loongarch_init(MachineState *machine)
loongarch_irq_init(lams);
}
+bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
+{
+ if (lams->acpi == ON_OFF_AUTO_OFF) {
+ return false;
+ }
+ return true;
+}
+
+static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
+ OnOffAuto acpi = lams->acpi;
+
+ visit_type_OnOffAuto(v, name, &acpi, errp);
+}
+
+static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
+
+ visit_type_OnOffAuto(v, name, &lams->acpi, errp);
+}
+
+static void loongarch_machine_initfn(Object *obj)
+{
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
+
+ lams->acpi = ON_OFF_AUTO_AUTO;
+ lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
+ lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
+}
+
static void loongarch_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -477,6 +528,12 @@ static void loongarch_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_VIRTIO;
mc->default_boot_order = "c";
mc->no_cdrom = 1;
+
+ object_class_property_add(oc, "acpi", "OnOffAuto",
+ loongarch_get_acpi, loongarch_set_acpi,
+ NULL, NULL);
+ object_class_property_set_description(oc, "acpi",
+ "Enable ACPI");
}
static const TypeInfo loongarch_machine_types[] = {
@@ -484,6 +541,7 @@ static const TypeInfo loongarch_machine_types[] = {
.name = TYPE_LOONGARCH_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(LoongArchMachineState),
+ .instance_init = loongarch_machine_initfn,
.class_init = loongarch_class_init,
}
};
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
index fed69dfb62..94e0e976d7 100644
--- a/hw/loongarch/meson.build
+++ b/hw/loongarch/meson.build
@@ -1,5 +1,6 @@
loongarch_ss = ss.source_set()
loongarch_ss.add(when: 'CONFIG_LOONGSON3_LS7A', if_true: files('loongson3.c'))
loongarch_ss.add(when: 'CONFIG_FW_CFG_LOONGARCH', if_true: files('fw_cfg.c'))
+loongarch_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-build.c'))
hw_arch += {'loongarch': loongarch_ss}
diff --git a/include/hw/acpi/ls7a.h b/include/hw/acpi/ls7a.h
new file mode 100644
index 0000000000..28fe23c8a3
--- /dev/null
+++ b/include/hw/acpi/ls7a.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU GMCH/LS7A PCI PM Emulation
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_ACPI_LS7A_H
+#define HW_ACPI_LS7A_H
+
+#include "hw/acpi/acpi.h"
+#include "hw/sysbus.h"
+
+#define LS7A_ACPI_IO_BASE 0x800
+#define LS7A_ACPI_IO_SIZE 0x100
+#define LS7A_PM_EVT_BLK (0x0C) /* 4 bytes */
+#define LS7A_PM_CNT_BLK (0x14) /* 2 bytes */
+#define LS7A_GPE0_STS_REG (0x28) /* 4 bytes */
+#define LS7A_GPE0_ENA_REG (0x2C) /* 4 bytes */
+#define LS7A_GPE0_RESET_REG (0x30) /* 4 bytes */
+#define LS7A_PM_TMR_BLK (0x18) /* 4 bytes */
+#define LS7A_GPE0_LEN (8)
+#define ACPI_IO_BASE (LS7A_ACPI_REG_BASE)
+#define ACPI_GPE0_LEN (LS7A_GPE0_LEN)
+#define ACPI_IO_SIZE (LS7A_ACPI_IO_SIZE)
+#define ACPI_SCI_IRQ (LS7A_SCI_IRQ)
+
+typedef struct LS7APMState {
+ SysBusDevice parent_obj;
+ /*
+ * In ls7a spec says that pm1_cnt register is 32bit width and
+ * that the upper 16bits are reserved and unused.
+ * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
+ */
+ ACPIREGS acpi_regs;
+
+ MemoryRegion iomem;
+ MemoryRegion iomem_gpe;
+ MemoryRegion iomem_reset;
+
+ qemu_irq irq; /* SCI */
+
+ uint32_t pm_io_base;
+ Notifier powerdown_notifier;
+} LS7APMState;
+
+#define TYPE_LS7A_PM "ls7a_pm"
+DECLARE_INSTANCE_CHECKER(struct LS7APMState, LS7A_PM, TYPE_LS7A_PM)
+
+void ls7a_pm_init(DeviceState *ls7a_pm, qemu_irq irq);
+
+extern const VMStateDescription vmstate_ls7a_pm;
+#endif /* HW_ACPI_LS7A_H */
diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
index 9080864804..6cbbc58efe 100644
--- a/include/hw/loongarch/loongarch.h
+++ b/include/hw/loongarch/loongarch.h
@@ -56,9 +56,15 @@ typedef struct LoongArchMachineState {
/* State for other subsystems/APIs: */
Notifier machine_done;
FWCfgState *fw_cfg;
+ OnOffAuto acpi;
+ char *oem_id;
+ char *oem_table_id;
} LoongArchMachineState;
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson3-ls7a")
DECLARE_INSTANCE_CHECKER(LoongArchMachineState, LOONGARCH_MACHINE,
TYPE_LOONGARCH_MACHINE)
+
+bool loongarch_is_acpi_enabled(LoongArchMachineState *lams);
+void loongarch_acpi_setup(LoongArchMachineState *lams);
#endif
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index d7d0cac049..cac72d0351 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -11,6 +11,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci-host/pam.h"
+#include "hw/acpi/ls7a.h"
#include "qemu/units.h"
#include "qemu/range.h"
#include "qom/object.h"
@@ -24,6 +25,8 @@
#define LS7A_PCI_IO_BASE 0x18004000UL
#define LS7A_PCI_IO_SIZE 0xC000
#define LS7A_PCI_IO_OFFSET 0x4000
+#define LS7A_PCI_MEM_BASE 0x40000000UL
+#define LS7A_PCI_MEM_SIZE 0x40000000UL
#define LS7A_PCH_REG_BASE 0x10000000UL
#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
@@ -44,6 +47,8 @@
#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000)
#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100)
#define LS7A_RTC_LEN 0x100
+#define LS7A_ACPI_REG_BASE (LS7A_MISC_REG_BASE + 0x00050000)
+#define LS7A_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4)
struct LS7APCIState {
/*< private >*/
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 29/30] hw/loongarch: Add fdt support.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (27 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 28/30] hw/loongarch: Add LoongArch acpi support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-08 9:14 ` [RFC PATCH v4 30/30] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
` (2 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
Add tree nodes for 3A5000 device tree.
- cpu nodes;
- fw_cfg nodes;
- pcie nodes.
The lastest loongarch bios have supported fdt.
- https://github.com/loongson/edk2
- https://github.com/loongson/edk2-platforms
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/loongson3.c | 136 +++++++++++++++++++++++++++++++
include/hw/loongarch/loongarch.h | 5 ++
target/loongarch/cpu.c | 2 +
target/loongarch/cpu.h | 3 +
4 files changed, 146 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 17419c2bf4..9574efa604 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -31,6 +31,9 @@
#include "hw/firmware/smbios.h"
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
+#include "sysemu/device_tree.h"
+
+#include <libfdt.h>
#define LOONGSON3_BIOSNAME "loongarch_bios.bin"
@@ -378,6 +381,125 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
loongarch_devices_init(pch_pic);
}
+static void create_fdt(LoongArchMachineState *lams)
+{
+ MachineState *ms = MACHINE(lams);
+
+ ms->fdt = create_device_tree(&lams->fdt_size);
+ if (!ms->fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+
+ /* Header */
+ qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "linux,dummy-loongson3");
+ qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
+ qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
+}
+
+static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
+{
+ int num;
+ const MachineState *ms = MACHINE(lams);
+ int smp_cpus = ms->smp.cpus;
+
+ qemu_fdt_add_subnode(ms->fdt, "/cpus");
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
+
+ /* cpu nodes */
+ for (num = smp_cpus - 1; num >= 0; num--) {
+ char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
+ LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
+
+ qemu_fdt_add_subnode(ms->fdt, nodename);
+ qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
+ cpu->dtb_compatible);
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
+ qemu_fdt_alloc_phandle(ms->fdt));
+ g_free(nodename);
+ }
+
+ /*cpu map */
+ qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
+
+ for (num = smp_cpus - 1; num >= 0; num--) {
+ char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
+ char *map_path;
+
+ if (ms->smp.threads > 1) {
+ map_path = g_strdup_printf(
+ "/cpus/cpu-map/socket%d/core%d/thread%d",
+ num / (ms->smp.cores * ms->smp.threads),
+ (num / ms->smp.threads) % ms->smp.cores,
+ num % ms->smp.threads);
+ } else {
+ map_path = g_strdup_printf(
+ "/cpus/cpu-map/socket%d/core%d",
+ num / ms->smp.cores,
+ num % ms->smp.cores);
+ }
+ qemu_fdt_add_path(ms->fdt, map_path);
+ qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
+
+ g_free(map_path);
+ g_free(cpu_path);
+ }
+}
+
+static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams)
+{
+ char *nodename;
+ hwaddr base = FW_CFG_ADDR;
+ const MachineState *ms = MACHINE(lams);
+
+ nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base);
+ qemu_fdt_add_subnode(ms->fdt, nodename);
+ qemu_fdt_setprop_string(ms->fdt, nodename,
+ "compatible", "qemu,fw-cfg-mmio");
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
+ 2, base, 2, 0x8);
+ qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
+ g_free(nodename);
+}
+
+static void fdt_add_pcie_node(const LoongArchMachineState *lams)
+{
+ char *nodename;
+ hwaddr base_mmio = LS7A_PCI_MEM_BASE;
+ hwaddr size_mmio = LS7A_PCI_MEM_SIZE;
+ hwaddr base_pio = LS7A_PCI_IO_BASE;
+ hwaddr size_pio = LS7A_PCI_IO_SIZE;
+ hwaddr base_pcie = LS_PCIECFG_BASE;
+ hwaddr size_pcie = LS_PCIECFG_SIZE;
+ hwaddr base = base_pcie;
+
+ const MachineState *ms = MACHINE(lams);
+
+ nodename = g_strdup_printf("/pcie@%" PRIx64, base);
+ qemu_fdt_add_subnode(ms->fdt, nodename);
+ qemu_fdt_setprop_string(ms->fdt, nodename,
+ "compatible", "pci-host-ecam-generic");
+ qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
+ PCIE_MMCFG_BUS(LS_PCIECFG_SIZE - 1));
+ qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
+ 2, base_pcie, 2, size_pcie);
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
+ 1, FDT_PCI_RANGE_IOPORT, 2, LS7A_PCI_IO_OFFSET,
+ 2, base_pio, 2, size_pio,
+ 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
+ 2, base_mmio, 2, size_mmio);
+ g_free(nodename);
+ qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
+}
+
static void loongarch_init(MachineState *machine)
{
const char *cpu_model = machine->cpu_type;
@@ -404,6 +526,8 @@ static void loongarch_init(MachineState *machine)
exit(1);
}
+ create_fdt(lams);
+
/* Init CPUs */
for (i = 0; i < machine->smp.cpus; i++) {
la_cpu = LOONGARCH_CPU(cpu_create(machine->cpu_type));
@@ -418,6 +542,8 @@ static void loongarch_init(MachineState *machine)
LOONGARCH_SIMPLE_MMIO_OPS(MISC_FUNC_REG, "loongarch_misc_func", 0x8, 3);
}
+ fdt_add_cpu_nodes(lams);
+
if (ram_size < 1 * GiB) {
error_report("ram_size must be greater than 1G due to the bios memory layout");
exit(1);
@@ -458,6 +584,8 @@ static void loongarch_init(MachineState *machine)
exit(1);
}
+ fdt_add_fw_cfg_node(lams);
+
if (kernel_filename) {
loaderparams.ram_size = ram_size;
loaderparams.kernel_filename = kernel_filename;
@@ -476,6 +604,14 @@ static void loongarch_init(MachineState *machine)
/* Initialize the IO interrupt subsystem */
loongarch_irq_init(lams);
+
+ fdt_add_pcie_node(lams);
+
+ /* load fdt */
+ MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
+ memory_region_init_rom(fdt_rom, NULL, "fdt", LA_FDT_SIZE, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), LA_FDT_BASE, fdt_rom);
+ rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, LA_FDT_BASE);
}
bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
index 6cbbc58efe..8b549a2fed 100644
--- a/include/hw/loongarch/loongarch.h
+++ b/include/hw/loongarch/loongarch.h
@@ -39,6 +39,9 @@
#define LA_BIOS_BASE 0x1c000000
#define LA_BIOS_SIZE (4 * 1024 * 1024)
+#define LA_FDT_BASE 0x1c400000
+#define LA_FDT_SIZE 0x100000
+
/* Kernels can be configured with 64KB pages */
#define INITRD_PAGE_SIZE (64 * KiB)
#define INITRD_BASE 0x04000000
@@ -59,6 +62,8 @@ typedef struct LoongArchMachineState {
OnOffAuto acpi;
char *oem_id;
char *oem_table_id;
+
+ int fdt_size;
} LoongArchMachineState;
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson3-ls7a")
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f97206ac67..db8ab603f7 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -333,6 +333,8 @@ static void loongarch_3a5000_initfn(Object *obj)
env->cpucfg[i] = 0x0;
}
+ cpu->dtb_compatible = "loongarch,Loongson-3A5000";
+
env->cpucfg[0] = 0x14c010; /* PRID */
uint32_t data = 0;
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 5d6ad4a5a4..9bfeeab25f 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -368,6 +368,9 @@ struct LoongArchCPU {
CPUNegativeOffsetState neg;
CPULoongArchState env;
QEMUTimer timer; /* Internal timer */
+
+ /* 'compatible' string for this CPU for Linux device trees */
+ const char *dtb_compatible;
};
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [RFC PATCH v4 30/30] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (28 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 29/30] hw/loongarch: Add fdt support Xiaojuan Yang
@ 2022-01-08 9:14 ` Xiaojuan Yang
2022-01-09 9:26 ` [RFC PATCH v4 00/30] Add LoongArch softmmu support WANG Xuerui
2022-01-15 14:11 ` Mark Cave-Ayland
31 siblings, 0 replies; 56+ messages in thread
From: Xiaojuan Yang @ 2022-01-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, mark.cave-ayland, richard.henderson, Song Gao
- We write a very minimal softmmu harness.
- This is a very simple smoke test with no need to run a full Linux/kernel.
- The Makefile.softmmu-target record the rule to run.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
tests/tcg/loongarch64/Makefile.softmmu-target | 33 +++++++
tests/tcg/loongarch64/system/boot.S | 58 +++++++++++++
tests/tcg/loongarch64/system/kernel.ld | 30 +++++++
tests/tcg/loongarch64/system/regdef.h | 86 +++++++++++++++++++
4 files changed, 207 insertions(+)
create mode 100644 tests/tcg/loongarch64/Makefile.softmmu-target
create mode 100644 tests/tcg/loongarch64/system/boot.S
create mode 100644 tests/tcg/loongarch64/system/kernel.ld
create mode 100644 tests/tcg/loongarch64/system/regdef.h
diff --git a/tests/tcg/loongarch64/Makefile.softmmu-target b/tests/tcg/loongarch64/Makefile.softmmu-target
new file mode 100644
index 0000000000..908f3a8c0f
--- /dev/null
+++ b/tests/tcg/loongarch64/Makefile.softmmu-target
@@ -0,0 +1,33 @@
+#
+# Loongarch64 system tests
+#
+
+LOONGARCH64_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/loongarch64/system
+VPATH+=$(LOONGARCH64_SYSTEM_SRC)
+
+# These objects provide the basic boot code and helper functions for all tests
+CRT_OBJS=boot.o
+
+LOONGARCH64_TEST_SRCS=$(wildcard $(LOONGARCH64_SYSTEM_SRC)/*.c)
+LOONGARCH64_TESTS = $(patsubst $(LOONGARCH64_SYSTEM_SRC)/%.c, %, $(LOONGARCH64_TEST_SRCS))
+
+CRT_PATH=$(LOONGARCH64_SYSTEM_SRC)
+LINK_SCRIPT=$(LOONGARCH64_SYSTEM_SRC)/kernel.ld
+LDFLAGS=-Wl,-T$(LINK_SCRIPT)
+TESTS+=$(LOONGARCH64_TESTS) $(MULTIARCH_TESTS)
+CFLAGS+=-nostdlib -g -O1 -march=loongarch64 -mabi=lp64d $(MINILIB_INC)
+LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
+
+# building head blobs
+.PRECIOUS: $(CRT_OBJS)
+
+%.o: $(CRT_PATH)/%.S
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@
+
+# Build and link the tests
+%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
+
+memory: CFLAGS+=-DCHECK_UNALIGNED=0
+# Running
+QEMU_OPTS+=-serial chardev:output -kernel
diff --git a/tests/tcg/loongarch64/system/boot.S b/tests/tcg/loongarch64/system/boot.S
new file mode 100644
index 0000000000..6a0671a5bf
--- /dev/null
+++ b/tests/tcg/loongarch64/system/boot.S
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Minimal LoongArch system boot code.
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "regdef.h"
+
+ .global _start
+ .align 16
+_start:
+ bl main
+
+ .type _start 2
+ .size _start, .-_start
+
+ .global _exit
+ .align 16
+_exit:
+2: /* QEMU ACPI poweroff */
+ li.w t0, 0x3c00
+ li.w t1, 0x100d0014
+ st.w t0, t1, 0
+ idle 0
+ bl 2b
+
+ .type _exit 2
+ .size _exit, .-_exit
+
+ .global __sys_outc
+__sys_outc:
+ li.d t1, 1000000
+loop:
+ lu12i.w t2, 0x1fe00
+ ori t0, t2, 0x1e5
+ lu52i.d t0, t0, -2048
+ ld.bu t0, t0, 0
+ andi t0, t0, 0x20
+ ext.w.b t0, t0
+ bnez t0, in
+ addi.w t1, t1, -1
+ bnez t1, loop
+in:
+ ext.w.b a0, a0
+ lu12i.w t0, 0x1fe00
+ ori t0, t0, 0x1e0
+ lu52i.d t0, t0, -2048
+ st.b a0, t0, 0
+ jirl $r0, ra, 0
+
+ .data
+ .align 4
+stack:
+ .skip 65536
+$stack_end:
+ .type stack,@object
+ .size stack, . - stack
diff --git a/tests/tcg/loongarch64/system/kernel.ld b/tests/tcg/loongarch64/system/kernel.ld
new file mode 100644
index 0000000000..f1a7c0168c
--- /dev/null
+++ b/tests/tcg/loongarch64/system/kernel.ld
@@ -0,0 +1,30 @@
+ENTRY(_start)
+
+SECTIONS
+{
+ /* Linux kernel legacy start address. */
+ . = 0x9000000000200000;
+ _text = .;
+ .text : {
+ *(.text)
+ }
+ .rodata : {
+ *(.rodata)
+ }
+ _etext = .;
+
+ . = ALIGN(8192);
+ _data = .;
+ .got : {
+ *(.got)
+ }
+ .data : {
+ *(.sdata)
+ *(.data)
+ }
+ _edata = .;
+ .bss : {
+ *(.bss)
+ }
+ _end = .;
+}
diff --git a/tests/tcg/loongarch64/system/regdef.h b/tests/tcg/loongarch64/system/regdef.h
new file mode 100644
index 0000000000..faa09b2377
--- /dev/null
+++ b/tests/tcg/loongarch64/system/regdef.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+#ifndef _ASM_REGDEF_H
+#define _ASM_REGDEF_H
+
+#define zero $r0 /* wired zero */
+#define ra $r1 /* return address */
+#define tp $r2
+#define sp $r3 /* stack pointer */
+#define v0 $r4 /* return value - caller saved */
+#define v1 $r5
+#define a0 $r4 /* argument registers */
+#define a1 $r5
+#define a2 $r6
+#define a3 $r7
+#define a4 $r8
+#define a5 $r9
+#define a6 $r10
+#define a7 $r11
+#define t0 $r12 /* caller saved */
+#define t1 $r13
+#define t2 $r14
+#define t3 $r15
+#define t4 $r16
+#define t5 $r17
+#define t6 $r18
+#define t7 $r19
+#define t8 $r20
+ /* $r21: Temporarily reserved */
+#define fp $r22 /* frame pointer */
+#define s0 $r23 /* callee saved */
+#define s1 $r24
+#define s2 $r25
+#define s3 $r26
+#define s4 $r27
+#define s5 $r28
+#define s6 $r29
+#define s7 $r30
+#define s8 $r31
+
+#define gr0 $r0
+#define gr1 $r1
+#define gr2 $r2
+#define gr3 $r3
+#define gr4 $r4
+#define gr5 $r5
+#define gr6 $r6
+#define gr7 $r7
+#define gr8 $r8
+#define gr9 $r9
+#define gr10 $r10
+#define gr11 $r11
+#define gr12 $r12
+#define gr13 $r13
+#define gr14 $r14
+#define gr15 $r15
+#define gr16 $r16
+#define gr17 $r17
+#define gr18 $r18
+#define gr19 $r19
+#define gr20 $r20
+#define gr21 $r21
+#define gr22 $r22
+#define gr23 $r23
+#define gr24 $r24
+#define gr25 $r25
+#define gr26 $r26
+#define gr27 $r27
+#define gr28 $r28
+#define gr29 $r29
+#define gr30 $r30
+#define gr31 $r31
+
+#define STT_NOTYPE 0
+#define STT_OBJECT 1
+#define STT_FUNC 2
+#define STT_SECTION 3
+#define STT_FILE 4
+#define STT_COMMON 5
+#define STT_TLS 6
+
+#define ASM_NL ;
+
+#endif /* _ASM_REGDEF_H */
--
2.27.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 00/30] Add LoongArch softmmu support.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (29 preceding siblings ...)
2022-01-08 9:14 ` [RFC PATCH v4 30/30] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
@ 2022-01-09 9:26 ` WANG Xuerui
2022-01-10 2:42 ` yangxiaojuan
2022-01-15 14:11 ` Mark Cave-Ayland
31 siblings, 1 reply; 56+ messages in thread
From: WANG Xuerui @ 2022-01-09 9:26 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: mark.cave-ayland, richard.henderson, philmd
Hi Xiaojuan,
I've just finished reviewing the first part (target modifications) as
I'm not familiar with QEMU device emulation. You may have to revise the
target part carefully, and re-organize at the series level to accelerate
upstreaming though, as Richard pointed out in the other patch series
(Song Gao's LoongArch linux-user support series) that the series as a
whole is blocked.
On 1/8/22 17:13, Xiaojuan Yang wrote:
> This series patch add softmmu support for LoongArch.
> Base on the linux-user emulation support V14 patch.
> *https://patchew.org/QEMU/20220106094200.1801206-1-gaosong@loongson.cn/
There's a recognized syntax for marking patch series dependency [1], so
that your series could be auto-applied by Patchew for ease of
consumption. You can look at Song Gao's v14 LoongArch linux-user series
for example usage.
[1]:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#base-patches-against-current-git-master
> The latest kernel:
> *https://github.com/loongson/linux/tree/loongarch-next
> The latest uefi:
> *https://github.com/loongson/edk2
> *https://github.com/loongson/edk2-platforms
> The manual:
> *https://github.com/loongson/LoongArch-Documentation/releases/tag/2021.10.11
>
>
> Changes for v4:
> 1. Uefi code is open and add some fdt interface to pass info between qemu and uefi.
> 2. Use a per cpu address space for iocsr.
> 3. Modify the tlb emulation.
> 4. Machine and board code mainly follow Mark's advice.
> 5. Adjust pci host space map.
> 6. Use more memregion to simplify the interrupt controller's emulate.
>
>
> Changes for v3:
> 1.Target code mainly follow Richard's code review comments.
> 2.Put the csr and iocsr read/write instruction emulate into 2 different patch.
> 3.Simply the tlb emulation.
> 4.Delete some unused csr registers defintion.
> 5.Machine and board code mainly follow Mark's advice, discard the obsolete interface.
> 6.NUMA function is removed for it is not completed.
> 7.Adjust some format problem and the Naming problem
>
>
> Changes for v2:
> 1.Combine patch 2 and 3 into one.
> 2.Adjust the order of the patch.
> 3.Put all the binaries on the github.
> 4.Modify some emulate errors when use the kernel from the github.
> 5.Adjust some format problem and the Naming problem
> 6.Others mainly follow Richard's code review comments.
>
> Please help review!
>
> Thanks
>
> Xiaojuan Yang (30):
> target/loongarch: Update README
> target/loongarch: Add CSR registers definition
> target/loongarch: Add basic vmstate description of CPU.
There are serious issues with your commit message...
First of all, some of your commit message titles end with a period,
while some don't; the QEMU convention is to NOT use one. So please fix
all commits like this to remove the trailing period.
> target/loongarch: Implement qmp_query_cpu_definitions()
> target/loongarch: Add constant timer support
"Implement the constant timer" would be more concise and idiomatic English.
> target/loongarch: Add MMU support for LoongArch CPU.
> target/loongarch: Add LoongArch CSR instruction
> target/loongarch: Add LoongArch IOCSR instruction
You don't need to emphasize "LoongArch" because the component prefix
"target/loongarch" says it all. Also all of these commits add support
for multiple instructions at once, so you would say "instructions". You
may need to check all places for simple plural form mistakes like these.
> target/loongarch: Add TLB instruction support
> target/loongarch: Add other core instructions support
> target/loongarch: Add LoongArch interrupt and exception handle
"handlers"?
> target/loongarch: Add timer related instructions support.
> target/loongarch: Add gdb support.
> hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3
> Platform
"Add the LS7A1000 PCIe host bridge" would be enough; although currently
the LS7A chip is only paired with Loongson 3 CPUs, there's no intrinsic
reasons to only support this combination ever.
> hw/loongarch: Add support loongson3-ls7a machine type.
"Support the loongson3-ls7a machine type"
> hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)
You may just say "Implement the LoongArch CPUINTC"; people naturally
look in the diff to get what CPUINTC means. Same for other following
commits with similar commit messages.
> hw/loongarch: Add LoongArch ipi interrupt support(IPI)
> hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
> hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
> hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
> hw/loongarch: Add irq hierarchy for the system
> Enable common virtio pci support for LoongArch
This patch is missing component prefix in its title.
> hw/loongarch: Add some devices support for 3A5000.
What's "some"? You may want to clarify a bit, or to split patches if you
cannot make your title short and concise.
> hw/loongarch: Add LoongArch ls7a rtc device support
The LS7A RTC is usable for MIPS-based Loongson systems too, like the
3A4000/LS7A1000 combination, so is this really LoongArch-specific?
> hw/loongarch: Add default bios startup support.
> hw/loongarch: Add -kernel and -initrd options support
> hw/loongarch: Add LoongArch smbios support
> hw/loongarch: Add LoongArch acpi support
> hw/loongarch: Add fdt support.
> tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
"for" loongarch64 systems
> .../devices/loongarch64-softmmu/default.mak | 3 +
> configs/targets/loongarch64-softmmu.mak | 4 +
> gdb-xml/loongarch-base64.xml | 43 +
> gdb-xml/loongarch-fpu64.xml | 57 ++
> hw/Kconfig | 1 +
> hw/acpi/Kconfig | 4 +
> hw/acpi/ls7a.c | 374 +++++++++
> hw/acpi/meson.build | 1 +
> hw/intc/Kconfig | 15 +
> hw/intc/loongarch_extioi.c | 376 +++++++++
> hw/intc/loongarch_ipi.c | 164 ++++
> hw/intc/loongarch_pch_msi.c | 75 ++
> hw/intc/loongarch_pch_pic.c | 428 ++++++++++
> hw/intc/meson.build | 4 +
> hw/intc/trace-events | 25 +
> hw/loongarch/Kconfig | 22 +
> hw/loongarch/acpi-build.c | 636 ++++++++++++++
> hw/loongarch/fw_cfg.c | 33 +
> hw/loongarch/fw_cfg.h | 15 +
> hw/loongarch/loongson3.c | 685 +++++++++++++++
> hw/loongarch/meson.build | 6 +
> hw/meson.build | 1 +
> hw/pci-host/Kconfig | 4 +
> hw/pci-host/ls7a.c | 218 +++++
> hw/pci-host/meson.build | 1 +
> hw/rtc/Kconfig | 3 +
> hw/rtc/ls7a_rtc.c | 322 ++++++++
> hw/rtc/meson.build | 1 +
> include/exec/poison.h | 2 +
> include/hw/acpi/ls7a.h | 53 ++
> include/hw/intc/loongarch_extioi.h | 69 ++
> include/hw/intc/loongarch_ipi.h | 48 ++
> include/hw/intc/loongarch_pch_msi.h | 21 +
> include/hw/intc/loongarch_pch_pic.h | 74 ++
> include/hw/loongarch/loongarch.h | 75 ++
> include/hw/pci-host/ls7a.h | 79 ++
> include/hw/pci/pci_ids.h | 3 +
> include/sysemu/arch_init.h | 1 +
> linux-user/loongarch64/cpu_loop.c | 8 +-
> qapi/machine-target.json | 6 +-
> qapi/machine.json | 2 +-
> softmmu/qdev-monitor.c | 3 +-
> target/Kconfig | 1 +
> target/loongarch/Kconfig | 2 +
> target/loongarch/README | 25 +
> target/loongarch/constant_timer.c | 63 ++
> target/loongarch/cpu-csr.h | 236 ++++++
> target/loongarch/cpu-param.h | 2 +-
> target/loongarch/cpu.c | 377 ++++++++-
> target/loongarch/cpu.h | 220 ++++-
> target/loongarch/csr_helper.c | 112 +++
> target/loongarch/disas.c | 57 ++
> target/loongarch/fpu_helper.c | 2 +-
> target/loongarch/gdbstub.c | 97 +++
> target/loongarch/helper.h | 26 +
> target/loongarch/insn_trans/trans_core.c.inc | 412 ++++++++++
> target/loongarch/insn_trans/trans_extra.c.inc | 36 +-
> target/loongarch/insns.decode | 44 +
> target/loongarch/internals.h | 29 +
> target/loongarch/iocsr_helper.c | 120 +++
> target/loongarch/machine.c | 101 +++
> target/loongarch/meson.build | 11 +
> target/loongarch/op_helper.c | 57 ++
> target/loongarch/tlb_helper.c | 777 ++++++++++++++++++
> target/loongarch/translate.c | 9 +-
> tests/tcg/loongarch64/Makefile.softmmu-target | 33 +
> tests/tcg/loongarch64/system/boot.S | 58 ++
> tests/tcg/loongarch64/system/kernel.ld | 30 +
> tests/tcg/loongarch64/system/regdef.h | 86 ++
> 69 files changed, 6958 insertions(+), 30 deletions(-)
> create mode 100644 configs/devices/loongarch64-softmmu/default.mak
> create mode 100644 configs/targets/loongarch64-softmmu.mak
> create mode 100644 gdb-xml/loongarch-base64.xml
> create mode 100644 gdb-xml/loongarch-fpu64.xml
> create mode 100644 hw/acpi/ls7a.c
> create mode 100644 hw/intc/loongarch_extioi.c
> create mode 100644 hw/intc/loongarch_ipi.c
> create mode 100644 hw/intc/loongarch_pch_msi.c
> create mode 100644 hw/intc/loongarch_pch_pic.c
> create mode 100644 hw/loongarch/Kconfig
> create mode 100644 hw/loongarch/acpi-build.c
> create mode 100644 hw/loongarch/fw_cfg.c
> create mode 100644 hw/loongarch/fw_cfg.h
> create mode 100644 hw/loongarch/loongson3.c
> create mode 100644 hw/loongarch/meson.build
> create mode 100644 hw/pci-host/ls7a.c
> create mode 100644 hw/rtc/ls7a_rtc.c
> create mode 100644 include/hw/acpi/ls7a.h
> create mode 100644 include/hw/intc/loongarch_extioi.h
> create mode 100644 include/hw/intc/loongarch_ipi.h
> create mode 100644 include/hw/intc/loongarch_pch_msi.h
> create mode 100644 include/hw/intc/loongarch_pch_pic.h
> create mode 100644 include/hw/loongarch/loongarch.h
> create mode 100644 include/hw/pci-host/ls7a.h
> create mode 100644 target/loongarch/Kconfig
> create mode 100644 target/loongarch/constant_timer.c
> create mode 100644 target/loongarch/cpu-csr.h
> create mode 100644 target/loongarch/csr_helper.c
> create mode 100644 target/loongarch/gdbstub.c
> create mode 100644 target/loongarch/insn_trans/trans_core.c.inc
> create mode 100644 target/loongarch/iocsr_helper.c
> create mode 100644 target/loongarch/machine.c
> create mode 100644 target/loongarch/tlb_helper.c
> create mode 100644 tests/tcg/loongarch64/Makefile.softmmu-target
> create mode 100644 tests/tcg/loongarch64/system/boot.S
> create mode 100644 tests/tcg/loongarch64/system/kernel.ld
> create mode 100644 tests/tcg/loongarch64/system/regdef.h
>
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 00/30] Add LoongArch softmmu support.
2022-01-09 9:26 ` [RFC PATCH v4 00/30] Add LoongArch softmmu support WANG Xuerui
@ 2022-01-10 2:42 ` yangxiaojuan
0 siblings, 0 replies; 56+ messages in thread
From: yangxiaojuan @ 2022-01-10 2:42 UTC (permalink / raw)
To: WANG Xuerui, qemu-devel; +Cc: mark.cave-ayland, richard.henderson, philmd
Hi, Xuerui
Thank you for all you advice, I will modify the target part carefully.
Xiaojuan
On 01/09/2022 05:26 PM, WANG Xuerui wrote:
> Hi Xiaojuan,
>
> I've just finished reviewing the first part (target modifications) as I'm not familiar with QEMU device emulation. You may have to revise the target part carefully, and re-organize at the series level to accelerate upstreaming though, as Richard pointed out in the other patch series (Song Gao's LoongArch linux-user support series) that the series as a whole is blocked.
>
>
> On 1/8/22 17:13, Xiaojuan Yang wrote:
>> This series patch add softmmu support for LoongArch.
>> Base on the linux-user emulation support V14 patch.
>> *https://patchew.org/QEMU/20220106094200.1801206-1-gaosong@loongson.cn/
>
> There's a recognized syntax for marking patch series dependency [1], so that your series could be auto-applied by Patchew for ease of consumption. You can look at Song Gao's v14 LoongArch linux-user series for example usage.
>
> [1]: https://www.qemu.org/docs/master/devel/submitting-a-patch.html#base-patches-against-current-git-master
>
>> The latest kernel:
>> *https://github.com/loongson/linux/tree/loongarch-next
>> The latest uefi:
>> *https://github.com/loongson/edk2
>> *https://github.com/loongson/edk2-platforms
>> The manual:
>> *https://github.com/loongson/LoongArch-Documentation/releases/tag/2021.10.11
>>
>>
>> Changes for v4:
>> 1. Uefi code is open and add some fdt interface to pass info between qemu and uefi.
>> 2. Use a per cpu address space for iocsr.
>> 3. Modify the tlb emulation.
>> 4. Machine and board code mainly follow Mark's advice.
>> 5. Adjust pci host space map.
>> 6. Use more memregion to simplify the interrupt controller's emulate.
>>
>>
>> Changes for v3:
>> 1.Target code mainly follow Richard's code review comments.
>> 2.Put the csr and iocsr read/write instruction emulate into 2 different patch.
>> 3.Simply the tlb emulation.
>> 4.Delete some unused csr registers defintion.
>> 5.Machine and board code mainly follow Mark's advice, discard the obsolete interface.
>> 6.NUMA function is removed for it is not completed.
>> 7.Adjust some format problem and the Naming problem
>>
>>
>> Changes for v2:
>> 1.Combine patch 2 and 3 into one.
>> 2.Adjust the order of the patch.
>> 3.Put all the binaries on the github.
>> 4.Modify some emulate errors when use the kernel from the github.
>> 5.Adjust some format problem and the Naming problem
>> 6.Others mainly follow Richard's code review comments.
>>
>> Please help review!
>>
>> Thanks
>>
>> Xiaojuan Yang (30):
>> target/loongarch: Update README
>> target/loongarch: Add CSR registers definition
>> target/loongarch: Add basic vmstate description of CPU.
>
> There are serious issues with your commit message...
>
> First of all, some of your commit message titles end with a period, while some don't; the QEMU convention is to NOT use one. So please fix all commits like this to remove the trailing period.
>
>> target/loongarch: Implement qmp_query_cpu_definitions()
>> target/loongarch: Add constant timer support
> "Implement the constant timer" would be more concise and idiomatic English.
>> target/loongarch: Add MMU support for LoongArch CPU.
>> target/loongarch: Add LoongArch CSR instruction
>> target/loongarch: Add LoongArch IOCSR instruction
> You don't need to emphasize "LoongArch" because the component prefix "target/loongarch" says it all. Also all of these commits add support for multiple instructions at once, so you would say "instructions". You may need to check all places for simple plural form mistakes like these.
>> target/loongarch: Add TLB instruction support
>> target/loongarch: Add other core instructions support
>> target/loongarch: Add LoongArch interrupt and exception handle
> "handlers"?
>> target/loongarch: Add timer related instructions support.
>> target/loongarch: Add gdb support.
>> hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3
>> Platform
> "Add the LS7A1000 PCIe host bridge" would be enough; although currently the LS7A chip is only paired with Loongson 3 CPUs, there's no intrinsic reasons to only support this combination ever.
>> hw/loongarch: Add support loongson3-ls7a machine type.
> "Support the loongson3-ls7a machine type"
>> hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)
> You may just say "Implement the LoongArch CPUINTC"; people naturally look in the diff to get what CPUINTC means. Same for other following commits with similar commit messages.
>> hw/loongarch: Add LoongArch ipi interrupt support(IPI)
>> hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
>> hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
>> hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
>> hw/loongarch: Add irq hierarchy for the system
>> Enable common virtio pci support for LoongArch
> This patch is missing component prefix in its title.
>> hw/loongarch: Add some devices support for 3A5000.
> What's "some"? You may want to clarify a bit, or to split patches if you cannot make your title short and concise.
>> hw/loongarch: Add LoongArch ls7a rtc device support
> The LS7A RTC is usable for MIPS-based Loongson systems too, like the 3A4000/LS7A1000 combination, so is this really LoongArch-specific?
>> hw/loongarch: Add default bios startup support.
>> hw/loongarch: Add -kernel and -initrd options support
>> hw/loongarch: Add LoongArch smbios support
>> hw/loongarch: Add LoongArch acpi support
>> hw/loongarch: Add fdt support.
>> tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
> "for" loongarch64 systems
>> .../devices/loongarch64-softmmu/default.mak | 3 +
>> configs/targets/loongarch64-softmmu.mak | 4 +
>> gdb-xml/loongarch-base64.xml | 43 +
>> gdb-xml/loongarch-fpu64.xml | 57 ++
>> hw/Kconfig | 1 +
>> hw/acpi/Kconfig | 4 +
>> hw/acpi/ls7a.c | 374 +++++++++
>> hw/acpi/meson.build | 1 +
>> hw/intc/Kconfig | 15 +
>> hw/intc/loongarch_extioi.c | 376 +++++++++
>> hw/intc/loongarch_ipi.c | 164 ++++
>> hw/intc/loongarch_pch_msi.c | 75 ++
>> hw/intc/loongarch_pch_pic.c | 428 ++++++++++
>> hw/intc/meson.build | 4 +
>> hw/intc/trace-events | 25 +
>> hw/loongarch/Kconfig | 22 +
>> hw/loongarch/acpi-build.c | 636 ++++++++++++++
>> hw/loongarch/fw_cfg.c | 33 +
>> hw/loongarch/fw_cfg.h | 15 +
>> hw/loongarch/loongson3.c | 685 +++++++++++++++
>> hw/loongarch/meson.build | 6 +
>> hw/meson.build | 1 +
>> hw/pci-host/Kconfig | 4 +
>> hw/pci-host/ls7a.c | 218 +++++
>> hw/pci-host/meson.build | 1 +
>> hw/rtc/Kconfig | 3 +
>> hw/rtc/ls7a_rtc.c | 322 ++++++++
>> hw/rtc/meson.build | 1 +
>> include/exec/poison.h | 2 +
>> include/hw/acpi/ls7a.h | 53 ++
>> include/hw/intc/loongarch_extioi.h | 69 ++
>> include/hw/intc/loongarch_ipi.h | 48 ++
>> include/hw/intc/loongarch_pch_msi.h | 21 +
>> include/hw/intc/loongarch_pch_pic.h | 74 ++
>> include/hw/loongarch/loongarch.h | 75 ++
>> include/hw/pci-host/ls7a.h | 79 ++
>> include/hw/pci/pci_ids.h | 3 +
>> include/sysemu/arch_init.h | 1 +
>> linux-user/loongarch64/cpu_loop.c | 8 +-
>> qapi/machine-target.json | 6 +-
>> qapi/machine.json | 2 +-
>> softmmu/qdev-monitor.c | 3 +-
>> target/Kconfig | 1 +
>> target/loongarch/Kconfig | 2 +
>> target/loongarch/README | 25 +
>> target/loongarch/constant_timer.c | 63 ++
>> target/loongarch/cpu-csr.h | 236 ++++++
>> target/loongarch/cpu-param.h | 2 +-
>> target/loongarch/cpu.c | 377 ++++++++-
>> target/loongarch/cpu.h | 220 ++++-
>> target/loongarch/csr_helper.c | 112 +++
>> target/loongarch/disas.c | 57 ++
>> target/loongarch/fpu_helper.c | 2 +-
>> target/loongarch/gdbstub.c | 97 +++
>> target/loongarch/helper.h | 26 +
>> target/loongarch/insn_trans/trans_core.c.inc | 412 ++++++++++
>> target/loongarch/insn_trans/trans_extra.c.inc | 36 +-
>> target/loongarch/insns.decode | 44 +
>> target/loongarch/internals.h | 29 +
>> target/loongarch/iocsr_helper.c | 120 +++
>> target/loongarch/machine.c | 101 +++
>> target/loongarch/meson.build | 11 +
>> target/loongarch/op_helper.c | 57 ++
>> target/loongarch/tlb_helper.c | 777 ++++++++++++++++++
>> target/loongarch/translate.c | 9 +-
>> tests/tcg/loongarch64/Makefile.softmmu-target | 33 +
>> tests/tcg/loongarch64/system/boot.S | 58 ++
>> tests/tcg/loongarch64/system/kernel.ld | 30 +
>> tests/tcg/loongarch64/system/regdef.h | 86 ++
>> 69 files changed, 6958 insertions(+), 30 deletions(-)
>> create mode 100644 configs/devices/loongarch64-softmmu/default.mak
>> create mode 100644 configs/targets/loongarch64-softmmu.mak
>> create mode 100644 gdb-xml/loongarch-base64.xml
>> create mode 100644 gdb-xml/loongarch-fpu64.xml
>> create mode 100644 hw/acpi/ls7a.c
>> create mode 100644 hw/intc/loongarch_extioi.c
>> create mode 100644 hw/intc/loongarch_ipi.c
>> create mode 100644 hw/intc/loongarch_pch_msi.c
>> create mode 100644 hw/intc/loongarch_pch_pic.c
>> create mode 100644 hw/loongarch/Kconfig
>> create mode 100644 hw/loongarch/acpi-build.c
>> create mode 100644 hw/loongarch/fw_cfg.c
>> create mode 100644 hw/loongarch/fw_cfg.h
>> create mode 100644 hw/loongarch/loongson3.c
>> create mode 100644 hw/loongarch/meson.build
>> create mode 100644 hw/pci-host/ls7a.c
>> create mode 100644 hw/rtc/ls7a_rtc.c
>> create mode 100644 include/hw/acpi/ls7a.h
>> create mode 100644 include/hw/intc/loongarch_extioi.h
>> create mode 100644 include/hw/intc/loongarch_ipi.h
>> create mode 100644 include/hw/intc/loongarch_pch_msi.h
>> create mode 100644 include/hw/intc/loongarch_pch_pic.h
>> create mode 100644 include/hw/loongarch/loongarch.h
>> create mode 100644 include/hw/pci-host/ls7a.h
>> create mode 100644 target/loongarch/Kconfig
>> create mode 100644 target/loongarch/constant_timer.c
>> create mode 100644 target/loongarch/cpu-csr.h
>> create mode 100644 target/loongarch/csr_helper.c
>> create mode 100644 target/loongarch/gdbstub.c
>> create mode 100644 target/loongarch/insn_trans/trans_core.c.inc
>> create mode 100644 target/loongarch/iocsr_helper.c
>> create mode 100644 target/loongarch/machine.c
>> create mode 100644 target/loongarch/tlb_helper.c
>> create mode 100644 tests/tcg/loongarch64/Makefile.softmmu-target
>> create mode 100644 tests/tcg/loongarch64/system/boot.S
>> create mode 100644 tests/tcg/loongarch64/system/kernel.ld
>> create mode 100644 tests/tcg/loongarch64/system/regdef.h
>>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH v4 00/30] Add LoongArch softmmu support.
2022-01-08 9:13 [RFC PATCH v4 00/30] Add LoongArch softmmu support Xiaojuan Yang
` (30 preceding siblings ...)
2022-01-09 9:26 ` [RFC PATCH v4 00/30] Add LoongArch softmmu support WANG Xuerui
@ 2022-01-15 14:11 ` Mark Cave-Ayland
2022-01-17 1:49 ` yangxiaojuan
31 siblings, 1 reply; 56+ messages in thread
From: Mark Cave-Ayland @ 2022-01-15 14:11 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel; +Cc: richard.henderson, philmd
On 08/01/2022 09:13, Xiaojuan Yang wrote:
> This series patch add softmmu support for LoongArch.
> Base on the linux-user emulation support V14 patch.
> * https://patchew.org/QEMU/20220106094200.1801206-1-gaosong@loongson.cn/
> The latest kernel:
> * https://github.com/loongson/linux/tree/loongarch-next
> The latest uefi:
> * https://github.com/loongson/edk2
> * https://github.com/loongson/edk2-platforms
> The manual:
> * https://github.com/loongson/LoongArch-Documentation/releases/tag/2021.10.11
>
>
> Changes for v4:
> 1. Uefi code is open and add some fdt interface to pass info between qemu and uefi.
> 2. Use a per cpu address space for iocsr.
> 3. Modify the tlb emulation.
> 4. Machine and board code mainly follow Mark's advice.
> 5. Adjust pci host space map.
> 6. Use more memregion to simplify the interrupt controller's emulate.
>
>
> Changes for v3:
> 1.Target code mainly follow Richard's code review comments.
> 2.Put the csr and iocsr read/write instruction emulate into 2 different patch.
> 3.Simply the tlb emulation.
> 4.Delete some unused csr registers defintion.
> 5.Machine and board code mainly follow Mark's advice, discard the obsolete interface.
> 6.NUMA function is removed for it is not completed.
> 7.Adjust some format problem and the Naming problem
>
>
> Changes for v2:
> 1.Combine patch 2 and 3 into one.
> 2.Adjust the order of the patch.
> 3.Put all the binaries on the github.
> 4.Modify some emulate errors when use the kernel from the github.
> 5.Adjust some format problem and the Naming problem
> 6.Others mainly follow Richard's code review comments.
>
> Please help review!
>
> Thanks
>
> Xiaojuan Yang (30):
> target/loongarch: Update README
> target/loongarch: Add CSR registers definition
> target/loongarch: Add basic vmstate description of CPU.
> target/loongarch: Implement qmp_query_cpu_definitions()
> target/loongarch: Add constant timer support
> target/loongarch: Add MMU support for LoongArch CPU.
> target/loongarch: Add LoongArch CSR instruction
> target/loongarch: Add LoongArch IOCSR instruction
> target/loongarch: Add TLB instruction support
> target/loongarch: Add other core instructions support
> target/loongarch: Add LoongArch interrupt and exception handle
> target/loongarch: Add timer related instructions support.
> target/loongarch: Add gdb support.
> hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3
> Platform
> hw/loongarch: Add support loongson3-ls7a machine type.
> hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)
> hw/loongarch: Add LoongArch ipi interrupt support(IPI)
> hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
> hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
> hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
> hw/loongarch: Add irq hierarchy for the system
> Enable common virtio pci support for LoongArch
> hw/loongarch: Add some devices support for 3A5000.
> hw/loongarch: Add LoongArch ls7a rtc device support
> hw/loongarch: Add default bios startup support.
> hw/loongarch: Add -kernel and -initrd options support
> hw/loongarch: Add LoongArch smbios support
> hw/loongarch: Add LoongArch acpi support
> hw/loongarch: Add fdt support.
> tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
>
> .../devices/loongarch64-softmmu/default.mak | 3 +
> configs/targets/loongarch64-softmmu.mak | 4 +
> gdb-xml/loongarch-base64.xml | 43 +
> gdb-xml/loongarch-fpu64.xml | 57 ++
> hw/Kconfig | 1 +
> hw/acpi/Kconfig | 4 +
> hw/acpi/ls7a.c | 374 +++++++++
> hw/acpi/meson.build | 1 +
> hw/intc/Kconfig | 15 +
> hw/intc/loongarch_extioi.c | 376 +++++++++
> hw/intc/loongarch_ipi.c | 164 ++++
> hw/intc/loongarch_pch_msi.c | 75 ++
> hw/intc/loongarch_pch_pic.c | 428 ++++++++++
> hw/intc/meson.build | 4 +
> hw/intc/trace-events | 25 +
> hw/loongarch/Kconfig | 22 +
> hw/loongarch/acpi-build.c | 636 ++++++++++++++
> hw/loongarch/fw_cfg.c | 33 +
> hw/loongarch/fw_cfg.h | 15 +
> hw/loongarch/loongson3.c | 685 +++++++++++++++
> hw/loongarch/meson.build | 6 +
> hw/meson.build | 1 +
> hw/pci-host/Kconfig | 4 +
> hw/pci-host/ls7a.c | 218 +++++
> hw/pci-host/meson.build | 1 +
> hw/rtc/Kconfig | 3 +
> hw/rtc/ls7a_rtc.c | 322 ++++++++
> hw/rtc/meson.build | 1 +
> include/exec/poison.h | 2 +
> include/hw/acpi/ls7a.h | 53 ++
> include/hw/intc/loongarch_extioi.h | 69 ++
> include/hw/intc/loongarch_ipi.h | 48 ++
> include/hw/intc/loongarch_pch_msi.h | 21 +
> include/hw/intc/loongarch_pch_pic.h | 74 ++
> include/hw/loongarch/loongarch.h | 75 ++
> include/hw/pci-host/ls7a.h | 79 ++
> include/hw/pci/pci_ids.h | 3 +
> include/sysemu/arch_init.h | 1 +
> linux-user/loongarch64/cpu_loop.c | 8 +-
> qapi/machine-target.json | 6 +-
> qapi/machine.json | 2 +-
> softmmu/qdev-monitor.c | 3 +-
> target/Kconfig | 1 +
> target/loongarch/Kconfig | 2 +
> target/loongarch/README | 25 +
> target/loongarch/constant_timer.c | 63 ++
> target/loongarch/cpu-csr.h | 236 ++++++
> target/loongarch/cpu-param.h | 2 +-
> target/loongarch/cpu.c | 377 ++++++++-
> target/loongarch/cpu.h | 220 ++++-
> target/loongarch/csr_helper.c | 112 +++
> target/loongarch/disas.c | 57 ++
> target/loongarch/fpu_helper.c | 2 +-
> target/loongarch/gdbstub.c | 97 +++
> target/loongarch/helper.h | 26 +
> target/loongarch/insn_trans/trans_core.c.inc | 412 ++++++++++
> target/loongarch/insn_trans/trans_extra.c.inc | 36 +-
> target/loongarch/insns.decode | 44 +
> target/loongarch/internals.h | 29 +
> target/loongarch/iocsr_helper.c | 120 +++
> target/loongarch/machine.c | 101 +++
> target/loongarch/meson.build | 11 +
> target/loongarch/op_helper.c | 57 ++
> target/loongarch/tlb_helper.c | 777 ++++++++++++++++++
> target/loongarch/translate.c | 9 +-
> tests/tcg/loongarch64/Makefile.softmmu-target | 33 +
> tests/tcg/loongarch64/system/boot.S | 58 ++
> tests/tcg/loongarch64/system/kernel.ld | 30 +
> tests/tcg/loongarch64/system/regdef.h | 86 ++
> 69 files changed, 6958 insertions(+), 30 deletions(-)
> create mode 100644 configs/devices/loongarch64-softmmu/default.mak
> create mode 100644 configs/targets/loongarch64-softmmu.mak
> create mode 100644 gdb-xml/loongarch-base64.xml
> create mode 100644 gdb-xml/loongarch-fpu64.xml
> create mode 100644 hw/acpi/ls7a.c
> create mode 100644 hw/intc/loongarch_extioi.c
> create mode 100644 hw/intc/loongarch_ipi.c
> create mode 100644 hw/intc/loongarch_pch_msi.c
> create mode 100644 hw/intc/loongarch_pch_pic.c
> create mode 100644 hw/loongarch/Kconfig
> create mode 100644 hw/loongarch/acpi-build.c
> create mode 100644 hw/loongarch/fw_cfg.c
> create mode 100644 hw/loongarch/fw_cfg.h
> create mode 100644 hw/loongarch/loongson3.c
> create mode 100644 hw/loongarch/meson.build
> create mode 100644 hw/pci-host/ls7a.c
> create mode 100644 hw/rtc/ls7a_rtc.c
> create mode 100644 include/hw/acpi/ls7a.h
> create mode 100644 include/hw/intc/loongarch_extioi.h
> create mode 100644 include/hw/intc/loongarch_ipi.h
> create mode 100644 include/hw/intc/loongarch_pch_msi.h
> create mode 100644 include/hw/intc/loongarch_pch_pic.h
> create mode 100644 include/hw/loongarch/loongarch.h
> create mode 100644 include/hw/pci-host/ls7a.h
> create mode 100644 target/loongarch/Kconfig
> create mode 100644 target/loongarch/constant_timer.c
> create mode 100644 target/loongarch/cpu-csr.h
> create mode 100644 target/loongarch/csr_helper.c
> create mode 100644 target/loongarch/gdbstub.c
> create mode 100644 target/loongarch/insn_trans/trans_core.c.inc
> create mode 100644 target/loongarch/iocsr_helper.c
> create mode 100644 target/loongarch/machine.c
> create mode 100644 target/loongarch/tlb_helper.c
> create mode 100644 tests/tcg/loongarch64/Makefile.softmmu-target
> create mode 100644 tests/tcg/loongarch64/system/boot.S
> create mode 100644 tests/tcg/loongarch64/system/kernel.ld
> create mode 100644 tests/tcg/loongarch64/system/regdef.h
I've just done another review for v4: this is looking much better to me, since
without knowing much about Loongarch I can now at least get a feel for the
IRQs/memory layouts by following the standard QEMU APIs.
There are some queries/questions about some MMIO regions (and initialisation of the
CPU in sysemu mode) but I don't think they will be too hard to fix once we understand
the memory layout.
Finally a couple of slightly more routine things that this series is missing: an
update to the MAINTAINERS file for the target/loongarch directory, and also some .rst
documentation describing the basic "virt" machine and its devices e.g. something like
https://qemu.readthedocs.io/en/latest/system/target-sparc64.html.
ATB,
Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [RFC PATCH v4 00/30] Add LoongArch softmmu support.
2022-01-15 14:11 ` Mark Cave-Ayland
@ 2022-01-17 1:49 ` yangxiaojuan
0 siblings, 0 replies; 56+ messages in thread
From: yangxiaojuan @ 2022-01-17 1:49 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel; +Cc: richard.henderson, philmd
Hi, Mark
On 01/15/2022 10:11 PM, Mark Cave-Ayland wrote:
> On 08/01/2022 09:13, Xiaojuan Yang wrote:
>
>> This series patch add softmmu support for LoongArch.
>> Base on the linux-user emulation support V14 patch.
>> * https://patchew.org/QEMU/20220106094200.1801206-1-gaosong@loongson.cn/
>> The latest kernel:
>> * https://github.com/loongson/linux/tree/loongarch-next
>> The latest uefi:
>> * https://github.com/loongson/edk2
>> * https://github.com/loongson/edk2-platforms
>> The manual:
>> * https://github.com/loongson/LoongArch-Documentation/releases/tag/2021.10.11
>>
>>
>> Changes for v4:
>> 1. Uefi code is open and add some fdt interface to pass info between qemu and uefi.
>> 2. Use a per cpu address space for iocsr.
>> 3. Modify the tlb emulation.
>> 4. Machine and board code mainly follow Mark's advice.
>> 5. Adjust pci host space map.
>> 6. Use more memregion to simplify the interrupt controller's emulate.
>>
>>
>> Changes for v3:
>> 1.Target code mainly follow Richard's code review comments.
>> 2.Put the csr and iocsr read/write instruction emulate into 2 different patch.
>> 3.Simply the tlb emulation.
>> 4.Delete some unused csr registers defintion.
>> 5.Machine and board code mainly follow Mark's advice, discard the obsolete interface.
>> 6.NUMA function is removed for it is not completed.
>> 7.Adjust some format problem and the Naming problem
>>
>>
>> Changes for v2:
>> 1.Combine patch 2 and 3 into one.
>> 2.Adjust the order of the patch.
>> 3.Put all the binaries on the github.
>> 4.Modify some emulate errors when use the kernel from the github.
>> 5.Adjust some format problem and the Naming problem
>> 6.Others mainly follow Richard's code review comments.
>>
>> Please help review!
>>
>> Thanks
>>
>> Xiaojuan Yang (30):
>> target/loongarch: Update README
>> target/loongarch: Add CSR registers definition
>> target/loongarch: Add basic vmstate description of CPU.
>> target/loongarch: Implement qmp_query_cpu_definitions()
>> target/loongarch: Add constant timer support
>> target/loongarch: Add MMU support for LoongArch CPU.
>> target/loongarch: Add LoongArch CSR instruction
>> target/loongarch: Add LoongArch IOCSR instruction
>> target/loongarch: Add TLB instruction support
>> target/loongarch: Add other core instructions support
>> target/loongarch: Add LoongArch interrupt and exception handle
>> target/loongarch: Add timer related instructions support.
>> target/loongarch: Add gdb support.
>> hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3
>> Platform
>> hw/loongarch: Add support loongson3-ls7a machine type.
>> hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)
>> hw/loongarch: Add LoongArch ipi interrupt support(IPI)
>> hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
>> hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
>> hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
>> hw/loongarch: Add irq hierarchy for the system
>> Enable common virtio pci support for LoongArch
>> hw/loongarch: Add some devices support for 3A5000.
>> hw/loongarch: Add LoongArch ls7a rtc device support
>> hw/loongarch: Add default bios startup support.
>> hw/loongarch: Add -kernel and -initrd options support
>> hw/loongarch: Add LoongArch smbios support
>> hw/loongarch: Add LoongArch acpi support
>> hw/loongarch: Add fdt support.
>> tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
>>
>> .../devices/loongarch64-softmmu/default.mak | 3 +
>> configs/targets/loongarch64-softmmu.mak | 4 +
>> gdb-xml/loongarch-base64.xml | 43 +
>> gdb-xml/loongarch-fpu64.xml | 57 ++
>> hw/Kconfig | 1 +
>> hw/acpi/Kconfig | 4 +
>> hw/acpi/ls7a.c | 374 +++++++++
>> hw/acpi/meson.build | 1 +
>> hw/intc/Kconfig | 15 +
>> hw/intc/loongarch_extioi.c | 376 +++++++++
>> hw/intc/loongarch_ipi.c | 164 ++++
>> hw/intc/loongarch_pch_msi.c | 75 ++
>> hw/intc/loongarch_pch_pic.c | 428 ++++++++++
>> hw/intc/meson.build | 4 +
>> hw/intc/trace-events | 25 +
>> hw/loongarch/Kconfig | 22 +
>> hw/loongarch/acpi-build.c | 636 ++++++++++++++
>> hw/loongarch/fw_cfg.c | 33 +
>> hw/loongarch/fw_cfg.h | 15 +
>> hw/loongarch/loongson3.c | 685 +++++++++++++++
>> hw/loongarch/meson.build | 6 +
>> hw/meson.build | 1 +
>> hw/pci-host/Kconfig | 4 +
>> hw/pci-host/ls7a.c | 218 +++++
>> hw/pci-host/meson.build | 1 +
>> hw/rtc/Kconfig | 3 +
>> hw/rtc/ls7a_rtc.c | 322 ++++++++
>> hw/rtc/meson.build | 1 +
>> include/exec/poison.h | 2 +
>> include/hw/acpi/ls7a.h | 53 ++
>> include/hw/intc/loongarch_extioi.h | 69 ++
>> include/hw/intc/loongarch_ipi.h | 48 ++
>> include/hw/intc/loongarch_pch_msi.h | 21 +
>> include/hw/intc/loongarch_pch_pic.h | 74 ++
>> include/hw/loongarch/loongarch.h | 75 ++
>> include/hw/pci-host/ls7a.h | 79 ++
>> include/hw/pci/pci_ids.h | 3 +
>> include/sysemu/arch_init.h | 1 +
>> linux-user/loongarch64/cpu_loop.c | 8 +-
>> qapi/machine-target.json | 6 +-
>> qapi/machine.json | 2 +-
>> softmmu/qdev-monitor.c | 3 +-
>> target/Kconfig | 1 +
>> target/loongarch/Kconfig | 2 +
>> target/loongarch/README | 25 +
>> target/loongarch/constant_timer.c | 63 ++
>> target/loongarch/cpu-csr.h | 236 ++++++
>> target/loongarch/cpu-param.h | 2 +-
>> target/loongarch/cpu.c | 377 ++++++++-
>> target/loongarch/cpu.h | 220 ++++-
>> target/loongarch/csr_helper.c | 112 +++
>> target/loongarch/disas.c | 57 ++
>> target/loongarch/fpu_helper.c | 2 +-
>> target/loongarch/gdbstub.c | 97 +++
>> target/loongarch/helper.h | 26 +
>> target/loongarch/insn_trans/trans_core.c.inc | 412 ++++++++++
>> target/loongarch/insn_trans/trans_extra.c.inc | 36 +-
>> target/loongarch/insns.decode | 44 +
>> target/loongarch/internals.h | 29 +
>> target/loongarch/iocsr_helper.c | 120 +++
>> target/loongarch/machine.c | 101 +++
>> target/loongarch/meson.build | 11 +
>> target/loongarch/op_helper.c | 57 ++
>> target/loongarch/tlb_helper.c | 777 ++++++++++++++++++
>> target/loongarch/translate.c | 9 +-
>> tests/tcg/loongarch64/Makefile.softmmu-target | 33 +
>> tests/tcg/loongarch64/system/boot.S | 58 ++
>> tests/tcg/loongarch64/system/kernel.ld | 30 +
>> tests/tcg/loongarch64/system/regdef.h | 86 ++
>> 69 files changed, 6958 insertions(+), 30 deletions(-)
>> create mode 100644 configs/devices/loongarch64-softmmu/default.mak
>> create mode 100644 configs/targets/loongarch64-softmmu.mak
>> create mode 100644 gdb-xml/loongarch-base64.xml
>> create mode 100644 gdb-xml/loongarch-fpu64.xml
>> create mode 100644 hw/acpi/ls7a.c
>> create mode 100644 hw/intc/loongarch_extioi.c
>> create mode 100644 hw/intc/loongarch_ipi.c
>> create mode 100644 hw/intc/loongarch_pch_msi.c
>> create mode 100644 hw/intc/loongarch_pch_pic.c
>> create mode 100644 hw/loongarch/Kconfig
>> create mode 100644 hw/loongarch/acpi-build.c
>> create mode 100644 hw/loongarch/fw_cfg.c
>> create mode 100644 hw/loongarch/fw_cfg.h
>> create mode 100644 hw/loongarch/loongson3.c
>> create mode 100644 hw/loongarch/meson.build
>> create mode 100644 hw/pci-host/ls7a.c
>> create mode 100644 hw/rtc/ls7a_rtc.c
>> create mode 100644 include/hw/acpi/ls7a.h
>> create mode 100644 include/hw/intc/loongarch_extioi.h
>> create mode 100644 include/hw/intc/loongarch_ipi.h
>> create mode 100644 include/hw/intc/loongarch_pch_msi.h
>> create mode 100644 include/hw/intc/loongarch_pch_pic.h
>> create mode 100644 include/hw/loongarch/loongarch.h
>> create mode 100644 include/hw/pci-host/ls7a.h
>> create mode 100644 target/loongarch/Kconfig
>> create mode 100644 target/loongarch/constant_timer.c
>> create mode 100644 target/loongarch/cpu-csr.h
>> create mode 100644 target/loongarch/csr_helper.c
>> create mode 100644 target/loongarch/gdbstub.c
>> create mode 100644 target/loongarch/insn_trans/trans_core.c.inc
>> create mode 100644 target/loongarch/iocsr_helper.c
>> create mode 100644 target/loongarch/machine.c
>> create mode 100644 target/loongarch/tlb_helper.c
>> create mode 100644 tests/tcg/loongarch64/Makefile.softmmu-target
>> create mode 100644 tests/tcg/loongarch64/system/boot.S
>> create mode 100644 tests/tcg/loongarch64/system/kernel.ld
>> create mode 100644 tests/tcg/loongarch64/system/regdef.h
>
> I've just done another review for v4: this is looking much better to me, since without knowing much about Loongarch I can now at least get a feel for the IRQs/memory layouts by following the standard QEMU APIs.
>
> There are some queries/questions about some MMIO regions (and initialisation of the CPU in sysemu mode) but I don't think they will be too hard to fix once we understand the memory layout.
>
> Finally a couple of slightly more routine things that this series is missing: an update to the MAINTAINERS file for the target/loongarch directory, and also some .rst documentation describing the basic "virt" machine and its devices e.g. something like https://qemu.readthedocs.io/en/latest/system/target-sparc64.html.
>
Thank you for your advice, I will learn more about the memory layout and modify the MMIO regions and fixup other things in the next version.
Thanks,
Xiaojuan
>
> ATB,
>
> Mark.
^ permalink raw reply [flat|nested] 56+ messages in thread