From: CK Hu <ck.hu@mediatek.com>
To: Fabien Parent <fparent@baylibre.com>, <matthias.bgg@gmail.com>,
<jitao.shi@mediatek.com>, <krzysztof.kozlowski+dt@linaro.org>,
<robh+dt@kernel.org>
Cc: <chunkuang.hu@kernel.org>, <p.zabel@pengutronix.de>,
<airlied@linux.ie>, <daniel@ffwll.ch>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 5/7] soc: mediatek: mt8365-mmsys: add DPI/HDMI display path
Date: Fri, 17 Jun 2022 13:53:34 +0800 [thread overview]
Message-ID: <3b5e4d1e3b8dd8593c4a0cf0edbb0cee4538fa8e.camel@mediatek.com> (raw)
In-Reply-To: <20220530201436.902505-5-fparent@baylibre.com>
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
> Right now only the DSI path connections are described in the mt8365
> mmsys driver. The external path will be DPI/HDMI. This commit adds
> the connections for DPI/HDMI.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> drivers/soc/mediatek/mt8365-mmsys.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h
> b/drivers/soc/mediatek/mt8365-mmsys.h
> index 24129a6c25f8..7abaf048d91e 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -10,6 +10,9 @@
> #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60
> #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64
> #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68
> +#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0
> +#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8
> +#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
>
> #define MT8365_RDMA0_SOUT_COLOR0 0x1
> #define MT8365_DITHER_MOUT_EN_DSI0 0x1
> @@ -18,6 +21,10 @@
> #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
> #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0
> #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0)
> +#define MT8365_RDMA1_SOUT_DPI0 0x1
> +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
> +#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1
> +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
>
> static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] =
> {
> {
> @@ -55,6 +62,21 @@ static const struct mtk_mmsys_routes
> mt8365_mmsys_routing_table[] = {
> MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
> MT8365_RDMA0_RSZ0_SEL_IN_RDMA0,
> MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
> },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
> + MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
> MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
> + MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
> + MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0
> + },
> };
>
> #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: Fabien Parent <fparent@baylibre.com>, <matthias.bgg@gmail.com>,
<jitao.shi@mediatek.com>, <krzysztof.kozlowski+dt@linaro.org>,
<robh+dt@kernel.org>
Cc: chunkuang.hu@kernel.org, devicetree@vger.kernel.org,
airlied@linux.ie, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 5/7] soc: mediatek: mt8365-mmsys: add DPI/HDMI display path
Date: Fri, 17 Jun 2022 13:53:34 +0800 [thread overview]
Message-ID: <3b5e4d1e3b8dd8593c4a0cf0edbb0cee4538fa8e.camel@mediatek.com> (raw)
In-Reply-To: <20220530201436.902505-5-fparent@baylibre.com>
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
> Right now only the DSI path connections are described in the mt8365
> mmsys driver. The external path will be DPI/HDMI. This commit adds
> the connections for DPI/HDMI.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> drivers/soc/mediatek/mt8365-mmsys.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h
> b/drivers/soc/mediatek/mt8365-mmsys.h
> index 24129a6c25f8..7abaf048d91e 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -10,6 +10,9 @@
> #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60
> #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64
> #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68
> +#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0
> +#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8
> +#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
>
> #define MT8365_RDMA0_SOUT_COLOR0 0x1
> #define MT8365_DITHER_MOUT_EN_DSI0 0x1
> @@ -18,6 +21,10 @@
> #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
> #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0
> #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0)
> +#define MT8365_RDMA1_SOUT_DPI0 0x1
> +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
> +#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1
> +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
>
> static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] =
> {
> {
> @@ -55,6 +62,21 @@ static const struct mtk_mmsys_routes
> mt8365_mmsys_routing_table[] = {
> MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
> MT8365_RDMA0_RSZ0_SEL_IN_RDMA0,
> MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
> },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
> + MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
> MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
> + MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
> + MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0
> + },
> };
>
> #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: Fabien Parent <fparent@baylibre.com>, <matthias.bgg@gmail.com>,
<jitao.shi@mediatek.com>, <krzysztof.kozlowski+dt@linaro.org>,
<robh+dt@kernel.org>
Cc: <chunkuang.hu@kernel.org>, <p.zabel@pengutronix.de>,
<airlied@linux.ie>, <daniel@ffwll.ch>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 5/7] soc: mediatek: mt8365-mmsys: add DPI/HDMI display path
Date: Fri, 17 Jun 2022 13:53:34 +0800 [thread overview]
Message-ID: <3b5e4d1e3b8dd8593c4a0cf0edbb0cee4538fa8e.camel@mediatek.com> (raw)
In-Reply-To: <20220530201436.902505-5-fparent@baylibre.com>
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
> Right now only the DSI path connections are described in the mt8365
> mmsys driver. The external path will be DPI/HDMI. This commit adds
> the connections for DPI/HDMI.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> drivers/soc/mediatek/mt8365-mmsys.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h
> b/drivers/soc/mediatek/mt8365-mmsys.h
> index 24129a6c25f8..7abaf048d91e 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -10,6 +10,9 @@
> #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60
> #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64
> #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68
> +#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0
> +#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8
> +#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
>
> #define MT8365_RDMA0_SOUT_COLOR0 0x1
> #define MT8365_DITHER_MOUT_EN_DSI0 0x1
> @@ -18,6 +21,10 @@
> #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
> #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0
> #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0)
> +#define MT8365_RDMA1_SOUT_DPI0 0x1
> +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
> +#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1
> +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
>
> static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] =
> {
> {
> @@ -55,6 +62,21 @@ static const struct mtk_mmsys_routes
> mt8365_mmsys_routing_table[] = {
> MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
> MT8365_RDMA0_RSZ0_SEL_IN_RDMA0,
> MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
> },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
> + MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
> MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
> + MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
> + MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0
> + },
> };
>
> #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
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next prev parent reply other threads:[~2022-06-17 5:53 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-30 20:14 [PATCH 1/7] dt-bindings: display: mediatek: dpi: add power-domains property Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` [PATCH 2/7] dt-bindings: display: mediatek: dpi: add binding for MT8365 Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-31 11:53 ` Krzysztof Kozlowski
2022-05-31 11:53 ` Krzysztof Kozlowski
2022-05-31 11:53 ` Krzysztof Kozlowski
2022-05-31 11:53 ` Krzysztof Kozlowski
2022-06-17 5:38 ` CK Hu
2022-06-17 5:38 ` CK Hu
2022-06-17 5:38 ` CK Hu
2022-05-30 20:14 ` [PATCH 3/7] dt-bindings: display: mediatek: add bindings for MT8365 SoC Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-06-17 5:44 ` CK Hu
2022-06-17 5:44 ` CK Hu
2022-06-17 5:44 ` CK Hu
2022-06-17 10:24 ` Matthias Brugger
2022-06-17 10:24 ` Matthias Brugger
2022-06-17 10:24 ` Matthias Brugger
2022-05-30 20:14 ` [PATCH 4/7] soc: mediatek: mutex: add MT8365 support Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-06-17 5:50 ` CK Hu
2022-06-17 5:50 ` CK Hu
2022-06-17 5:50 ` CK Hu
2022-06-17 10:26 ` Matthias Brugger
2022-06-17 10:26 ` Matthias Brugger
2022-06-17 10:26 ` Matthias Brugger
2022-05-30 20:14 ` [PATCH 5/7] soc: mediatek: mt8365-mmsys: add DPI/HDMI display path Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-06-17 5:53 ` CK Hu [this message]
2022-06-17 5:53 ` CK Hu
2022-06-17 5:53 ` CK Hu
2022-06-17 10:26 ` Matthias Brugger
2022-06-17 10:26 ` Matthias Brugger
2022-06-17 10:26 ` Matthias Brugger
2022-05-30 20:14 ` [PATCH 6/7] drm/mediatek: dpi: add support for dpi clock Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` [PATCH 7/7] drm/mediatek: add MT8365 SoC support Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-05-30 20:14 ` Fabien Parent
2022-06-17 5:58 ` CK Hu
2022-06-17 5:58 ` CK Hu
2022-06-17 5:58 ` CK Hu
2022-05-31 13:21 ` [PATCH 1/7] dt-bindings: display: mediatek: dpi: add power-domains property Rob Herring
2022-05-31 13:21 ` Rob Herring
2022-05-31 13:21 ` Rob Herring
2022-05-31 13:21 ` Rob Herring
2022-06-17 5:31 ` CK Hu
2022-06-17 5:31 ` CK Hu
2022-06-17 5:31 ` CK Hu
[not found] ` <PS1PR03MB5084CE11996065F4DD6959F9A6B09@PS1PR03MB5084.apcprd03.prod.outlook.com>
2022-06-20 13:32 ` FW: " xinlei.lee
2022-06-20 13:32 ` xinlei.lee
2022-06-20 13:32 ` xinlei.lee
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