[RFC PATCH 0/4] add support for CommonLPIAff field

[RFC PATCH 0/4] add support for CommonLPIAff field

[Yang Yingliang]

This patch set adjust struct rdists to support CommonLPIAff field.
This field is described in spec:

CommonLPIAff, bits [25:24]
The affinity level at which Redistributors share a LPI Configuration table.
00 All Redistributors must share a LPI Configuration table.
01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
10 All Redistributors
11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
table.

Yang Yingliang (4):
  irqchip/gic-v3: add common_aff_lpi field in struct rdists
  irqchip/gic-v3-its: replace alloc_pages() with alloc_pages_node()
  irqchip/gic-v3-its: change prop_page to per-cpu type to support
    CommonLPIAff field
  irqchip/gic-v3-its: sync config of LPIs if there are more than one
    prop_page

 drivers/irqchip/irq-gic-v3-its.c   | 125 +++++++++++++++++++++++++++----------
 drivers/irqchip/irq-gic-v3.c       |  20 ++++++
 include/linux/irqchip/arm-gic-v3.h |   9 ++-
 3 files changed, 121 insertions(+), 33 deletions(-)

-- 
1.8.3

[RFC PATCH 0/4] add support for CommonLPIAff field

[Yang Yingliang]

This patch set adjust struct rdists to support CommonLPIAff field.
This field is described in spec:

CommonLPIAff, bits [25:24]
The affinity level at which Redistributors share a LPI Configuration table.
00 All Redistributors must share a LPI Configuration table.
01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
10 All Redistributors
11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
table.

Yang Yingliang (4):
  irqchip/gic-v3: add common_aff_lpi field in struct rdists
  irqchip/gic-v3-its: replace alloc_pages() with alloc_pages_node()
  irqchip/gic-v3-its: change prop_page to per-cpu type to support
    CommonLPIAff field
  irqchip/gic-v3-its: sync config of LPIs if there are more than one
    prop_page

 drivers/irqchip/irq-gic-v3-its.c   | 125 +++++++++++++++++++++++++++----------
 drivers/irqchip/irq-gic-v3.c       |  20 ++++++
 include/linux/irqchip/arm-gic-v3.h |   9 ++-
 3 files changed, 121 insertions(+), 33 deletions(-)

-- 
1.8.3

[RFC PATCH 1/4] irqchip/gic-v3: add common_aff_lpi field in struct rdists

[Yang Yingliang]

Read CommonLPIAff from GICR_TYPER and check whether the
values are same in each register. If they are different,
prints warning message and set CommonLPIAff to zero.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3.c       | 20 ++++++++++++++++++++
 include/linux/irqchip/arm-gic-v3.h |  3 +++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index d99cc07..58f55da 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -598,6 +598,10 @@ static int gic_dist_supports_lpis(void)
 static void gic_cpu_init(void)
 {
 	void __iomem *rbase;
+	u32 typer;
+	unsigned long flags;
+	u16 common_aff_lpi;
+	int cpu = smp_processor_id();
 
 	/* Register ourselves with the rest of the world */
 	if (gic_populate_rdist())
@@ -612,6 +616,21 @@ static void gic_cpu_init(void)
 
 	gic_cpu_config(rbase, gic_redist_wait_for_rwp);
 
+	typer = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
+	common_aff_lpi = GICR_TYPER_COMMON_AFF_LPI(typer);
+	if (!cpu) {
+		gic_data.rdists.common_aff_lpi = common_aff_lpi;
+	} else {
+		raw_spin_lock_irqsave(&gic_data.rdists.lock, flags);
+		if (common_aff_lpi != gic_data.rdists.common_aff_lpi) {
+			pr_warn_once("The CommonLPIAff is not consistent.\
+				     It's %d in CPU0, but %d in CPU%d, set CommonLPIAff to 0.\n",
+			gic_data.rdists.common_aff_lpi, cpu, common_aff_lpi);
+			gic_data.rdists.common_aff_lpi = 0;
+		}
+		raw_spin_unlock_irqrestore(&gic_data.rdists.lock, flags);
+	}
+
 	/* Give LPIs a spin */
 	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
 		its_cpu_init();
@@ -1029,6 +1048,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
 	gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
 	gic_data.rdists.has_vlpis = true;
 	gic_data.rdists.has_direct_lpi = true;
+	raw_spin_lock_init(&gic_data.rdists.lock);
 
 	if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
 		err = -ENOMEM;
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index c00c4c33..6da670a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -108,6 +108,7 @@
 #define GICR_CTLR_ENABLE_LPIS		(1UL << 0)
 
 #define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)
+#define GICR_TYPER_COMMON_AFF_LPI(r)	(((r) >> 24) & 3)
 
 #define GICR_WAKER_ProcessorSleep	(1U << 1)
 #define GICR_WAKER_ChildrenAsleep	(1U << 2)
@@ -577,6 +578,8 @@ struct rdists {
 	u64			flags;
 	bool			has_vlpis;
 	bool			has_direct_lpi;
+	u16			common_aff_lpi;
+	raw_spinlock_t		lock;
 };
 
 struct irq_domain;
-- 
1.8.3

[RFC PATCH 1/4] irqchip/gic-v3: add common_aff_lpi field in struct rdists

[Yang Yingliang]

Read CommonLPIAff from GICR_TYPER and check whether the
values are same in each register. If they are different,
prints warning message and set CommonLPIAff to zero.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3.c       | 20 ++++++++++++++++++++
 include/linux/irqchip/arm-gic-v3.h |  3 +++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index d99cc07..58f55da 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -598,6 +598,10 @@ static int gic_dist_supports_lpis(void)
 static void gic_cpu_init(void)
 {
 	void __iomem *rbase;
+	u32 typer;
+	unsigned long flags;
+	u16 common_aff_lpi;
+	int cpu = smp_processor_id();
 
 	/* Register ourselves with the rest of the world */
 	if (gic_populate_rdist())
@@ -612,6 +616,21 @@ static void gic_cpu_init(void)
 
 	gic_cpu_config(rbase, gic_redist_wait_for_rwp);
 
+	typer = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
+	common_aff_lpi = GICR_TYPER_COMMON_AFF_LPI(typer);
+	if (!cpu) {
+		gic_data.rdists.common_aff_lpi = common_aff_lpi;
+	} else {
+		raw_spin_lock_irqsave(&gic_data.rdists.lock, flags);
+		if (common_aff_lpi != gic_data.rdists.common_aff_lpi) {
+			pr_warn_once("The CommonLPIAff is not consistent.\
+				     It's %d in CPU0, but %d in CPU%d, set CommonLPIAff to 0.\n",
+			gic_data.rdists.common_aff_lpi, cpu, common_aff_lpi);
+			gic_data.rdists.common_aff_lpi = 0;
+		}
+		raw_spin_unlock_irqrestore(&gic_data.rdists.lock, flags);
+	}
+
 	/* Give LPIs a spin */
 	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
 		its_cpu_init();
@@ -1029,6 +1048,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
 	gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
 	gic_data.rdists.has_vlpis = true;
 	gic_data.rdists.has_direct_lpi = true;
+	raw_spin_lock_init(&gic_data.rdists.lock);
 
 	if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
 		err = -ENOMEM;
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index c00c4c33..6da670a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -108,6 +108,7 @@
 #define GICR_CTLR_ENABLE_LPIS		(1UL << 0)
 
 #define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)
+#define GICR_TYPER_COMMON_AFF_LPI(r)	(((r) >> 24) & 3)
 
 #define GICR_WAKER_ProcessorSleep	(1U << 1)
 #define GICR_WAKER_ChildrenAsleep	(1U << 2)
@@ -577,6 +578,8 @@ struct rdists {
 	u64			flags;
 	bool			has_vlpis;
 	bool			has_direct_lpi;
+	u16			common_aff_lpi;
+	raw_spinlock_t		lock;
 };
 
 struct irq_domain;
-- 
1.8.3

[RFC PATCH 2/4] irqchip/gic-v3-its: replace alloc_pages() with alloc_pages_node()

[Yang Yingliang]

Use alloc_pages_node() to allocate pages on current node.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index a03e18e..4ebe131 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1557,11 +1557,11 @@ static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids)
 	kfree(bitmap);
 }
 
-static struct page *its_allocate_prop_table(gfp_t gfp_flags)
+static struct page *its_allocate_prop_table(int nid, gfp_t gfp_flags)
 {
 	struct page *prop_page;
 
-	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+	prop_page = alloc_pages_node(nid, gfp_flags, get_order(LPI_PROPBASE_SZ));
 	if (!prop_page)
 		return NULL;
 
@@ -1587,7 +1587,8 @@ static int __init its_alloc_lpi_tables(void)
 	phys_addr_t paddr;
 
 	lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
-	gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT);
+	gic_rdists->prop_page = its_allocate_prop_table(cpu_to_node(smp_processor_id()),
+							GFP_NOWAIT);
 	if (!gic_rdists->prop_page) {
 		pr_err("Failed to allocate PROPBASE\n");
 		return -ENOMEM;
@@ -2829,7 +2830,7 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 		return -ENOMEM;
 	}
 
-	vprop_page = its_allocate_prop_table(GFP_KERNEL);
+	vprop_page = its_allocate_prop_table(NUMA_NO_NODE, GFP_KERNEL);
 	if (!vprop_page) {
 		its_lpi_free_chunks(bitmap, base, nr_ids);
 		return -ENOMEM;
-- 
1.8.3

[RFC PATCH 2/4] irqchip/gic-v3-its: replace alloc_pages() with alloc_pages_node()

[Yang Yingliang]

Use alloc_pages_node() to allocate pages on current node.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index a03e18e..4ebe131 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1557,11 +1557,11 @@ static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids)
 	kfree(bitmap);
 }
 
-static struct page *its_allocate_prop_table(gfp_t gfp_flags)
+static struct page *its_allocate_prop_table(int nid, gfp_t gfp_flags)
 {
 	struct page *prop_page;
 
-	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+	prop_page = alloc_pages_node(nid, gfp_flags, get_order(LPI_PROPBASE_SZ));
 	if (!prop_page)
 		return NULL;
 
@@ -1587,7 +1587,8 @@ static int __init its_alloc_lpi_tables(void)
 	phys_addr_t paddr;
 
 	lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
-	gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT);
+	gic_rdists->prop_page = its_allocate_prop_table(cpu_to_node(smp_processor_id()),
+							GFP_NOWAIT);
 	if (!gic_rdists->prop_page) {
 		pr_err("Failed to allocate PROPBASE\n");
 		return -ENOMEM;
@@ -2829,7 +2830,7 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 		return -ENOMEM;
 	}
 
-	vprop_page = its_allocate_prop_table(GFP_KERNEL);
+	vprop_page = its_allocate_prop_table(NUMA_NO_NODE, GFP_KERNEL);
 	if (!vprop_page) {
 		its_lpi_free_chunks(bitmap, base, nr_ids);
 		return -ENOMEM;
-- 
1.8.3

[RFC PATCH 3/4] irqchip/gic-v3-its: change prop_page to per-cpu type to support CommonLPIAff field

[Yang Yingliang]

Change prop_page to per-cpu type and add its_cpu_allocate_prop_tables()
to allocate LPI property tables. This function is called by each oneline
cpu and allocate tables according to the value of CommonLPIAff.
The spec defines the field:
    CommonLPIAff, bits [25:24]
    The affinity level at which Redistributors share a LPI Configuration table.
    00 All Redistributors must share a LPI Configuration table.
    01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
    10 All Redistributors with the same Aff3.Aff2 value must share an LPI Configuration table.
    11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration table.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c   | 81 ++++++++++++++++++++++++++++----------
 include/linux/irqchip/arm-gic-v3.h |  6 ++-
 2 files changed, 65 insertions(+), 22 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 4ebe131..02a5d95 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1070,7 +1070,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
 		map->properties &= ~clr;
 		map->properties |= set | LPI_PROP_GROUP1;
 	} else {
-		prop_page = gic_rdists->prop_page;
+		prop_page = gic_data_rdist()->prop_page;
 		hwirq = d->hwirq;
 	}
 
@@ -1582,24 +1582,6 @@ static void its_free_prop_table(struct page *prop_page)
 		   get_order(LPI_PROPBASE_SZ));
 }
 
-static int __init its_alloc_lpi_tables(void)
-{
-	phys_addr_t paddr;
-
-	lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
-	gic_rdists->prop_page = its_allocate_prop_table(cpu_to_node(smp_processor_id()),
-							GFP_NOWAIT);
-	if (!gic_rdists->prop_page) {
-		pr_err("Failed to allocate PROPBASE\n");
-		return -ENOMEM;
-	}
-
-	paddr = page_to_phys(gic_rdists->prop_page);
-	pr_info("GIC: using LPI property table @%pa\n", &paddr);
-
-	return its_lpi_init(lpi_id_bits);
-}
-
 static const char *its_base_type_string[] = {
 	[GITS_BASER_TYPE_DEVICE]	= "Devices",
 	[GITS_BASER_TYPE_VCPU]		= "Virtual CPUs",
@@ -1935,7 +1917,7 @@ static void its_cpu_init_lpis(void)
 	dsb(sy);
 
 	/* set PROPBASE */
-	val = (page_to_phys(gic_rdists->prop_page) |
+	val = (page_to_phys(gic_data_rdist()->prop_page) |
 	       GICR_PROPBASER_InnerShareable |
 	       GICR_PROPBASER_RaWaWb |
 	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
@@ -2037,6 +2019,59 @@ static void its_cpu_init_collection(void)
 	spin_unlock(&its_lock);
 }
 
+static int __init its_cpu_allocate_prop_tables(void)
+{
+	phys_addr_t paddr;
+	unsigned long flags;
+	int match_cpu;
+	u64 aff_mask = 0;
+	struct page *prop_page = NULL;
+	int cpu = smp_processor_id();
+
+	switch (gic_rdists->common_aff_lpi) {
+	case GICR_COMMON_ALL_SHARE:
+		aff_mask = 0;
+		break;
+	case GICR_COMMON_AFF3_SHARE:
+		aff_mask = 0xffULL << MPIDR_LEVEL_SHIFT(3);
+		break;
+	case GICR_COMMON_AFF3_AFF2_SHARE:
+		aff_mask = (0xffULL << MPIDR_LEVEL_SHIFT(3)) |
+			   (0xffULL << MPIDR_LEVEL_SHIFT(2));
+		break;
+	case GICR_COMMON_AFF3_AFF2_AFF1_SHARE:
+		aff_mask = (0xffULL << MPIDR_LEVEL_SHIFT(3)) |
+			   (0xffULL << MPIDR_LEVEL_SHIFT(2)) |
+			   (0xffULL << MPIDR_LEVEL_SHIFT(1));
+		break;
+	default:
+		pr_err("Bad common_aff_lpi:%d\n", gic_rdists->common_aff_lpi);
+	}
+
+	raw_spin_lock_irqsave(&gic_rdists->lock, flags);
+	for_each_cpu(match_cpu, cpu_possible_mask) {
+		struct page *match_prop_page = per_cpu_ptr(gic_rdists->rdist, match_cpu)->prop_page;
+		if ((cpu_logical_map(cpu) & aff_mask) == (cpu_logical_map(match_cpu) & aff_mask) &&
+		    match_prop_page) {
+			prop_page = match_prop_page;
+			break;
+		}
+	}
+	if (!prop_page) {
+		prop_page = its_allocate_prop_table(cpu_to_node(cpu), GFP_NOWAIT);
+		pr_err("Failed to allocate PROPBASE\n");
+		raw_spin_unlock_irqrestore(&gic_rdists->lock, flags);
+		return -ENOMEM;
+	}
+	gic_data_rdist()->prop_page = prop_page;
+	raw_spin_unlock_irqrestore(&gic_rdists->lock, flags);
+
+	paddr = page_to_phys(gic_data_rdist()->prop_page);
+	pr_info("CPU%d using LPI property table @%pa\n", cpu, &paddr);
+
+	return 0;
+}
+
 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
 {
 	struct its_device *its_dev = NULL, *tmp;
@@ -3340,10 +3375,14 @@ static bool gic_rdists_supports_plpis(void)
 int its_cpu_init(void)
 {
 	if (!list_empty(&its_nodes)) {
+		int err;
 		if (!gic_rdists_supports_plpis()) {
 			pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
 			return -ENXIO;
 		}
+		err = its_cpu_allocate_prop_tables();
+		if (err)
+			return err;
 		its_cpu_init_lpis();
 		its_cpu_init_collection();
 	}
@@ -3551,7 +3590,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
 	}
 
 	gic_rdists = rdists;
-	err = its_alloc_lpi_tables();
+	err = its_lpi_init(min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS));
 	if (err)
 		return err;
 
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 6da670a..35cafd9 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -109,6 +109,10 @@
 
 #define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)
 #define GICR_TYPER_COMMON_AFF_LPI(r)	(((r) >> 24) & 3)
+#define GICR_COMMON_ALL_SHARE			0
+#define GICR_COMMON_AFF3_SHARE			1
+#define GICR_COMMON_AFF3_AFF2_SHARE		2
+#define GICR_COMMON_AFF3_AFF2_AFF1_SHARE	3
 
 #define GICR_WAKER_ProcessorSleep	(1U << 1)
 #define GICR_WAKER_ChildrenAsleep	(1U << 2)
@@ -571,9 +575,9 @@ struct rdists {
 	struct {
 		void __iomem	*rd_base;
 		struct page	*pend_page;
+		struct page	*prop_page;
 		phys_addr_t	phys_base;
 	} __percpu		*rdist;
-	struct page		*prop_page;
 	int			id_bits;
 	u64			flags;
 	bool			has_vlpis;
-- 
1.8.3

[RFC PATCH 3/4] irqchip/gic-v3-its: change prop_page to per-cpu type to support CommonLPIAff field

[Yang Yingliang]

Change prop_page to per-cpu type and add its_cpu_allocate_prop_tables()
to allocate LPI property tables. This function is called by each oneline
cpu and allocate tables according to the value of CommonLPIAff.
The spec defines the field:
    CommonLPIAff, bits [25:24]
    The affinity level at which Redistributors share a LPI Configuration table.
    00 All Redistributors must share a LPI Configuration table.
    01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
    10 All Redistributors with the same Aff3.Aff2 value must share an LPI Configuration table.
    11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration table.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c   | 81 ++++++++++++++++++++++++++++----------
 include/linux/irqchip/arm-gic-v3.h |  6 ++-
 2 files changed, 65 insertions(+), 22 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 4ebe131..02a5d95 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1070,7 +1070,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
 		map->properties &= ~clr;
 		map->properties |= set | LPI_PROP_GROUP1;
 	} else {
-		prop_page = gic_rdists->prop_page;
+		prop_page = gic_data_rdist()->prop_page;
 		hwirq = d->hwirq;
 	}
 
@@ -1582,24 +1582,6 @@ static void its_free_prop_table(struct page *prop_page)
 		   get_order(LPI_PROPBASE_SZ));
 }
 
-static int __init its_alloc_lpi_tables(void)
-{
-	phys_addr_t paddr;
-
-	lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
-	gic_rdists->prop_page = its_allocate_prop_table(cpu_to_node(smp_processor_id()),
-							GFP_NOWAIT);
-	if (!gic_rdists->prop_page) {
-		pr_err("Failed to allocate PROPBASE\n");
-		return -ENOMEM;
-	}
-
-	paddr = page_to_phys(gic_rdists->prop_page);
-	pr_info("GIC: using LPI property table @%pa\n", &paddr);
-
-	return its_lpi_init(lpi_id_bits);
-}
-
 static const char *its_base_type_string[] = {
 	[GITS_BASER_TYPE_DEVICE]	= "Devices",
 	[GITS_BASER_TYPE_VCPU]		= "Virtual CPUs",
@@ -1935,7 +1917,7 @@ static void its_cpu_init_lpis(void)
 	dsb(sy);
 
 	/* set PROPBASE */
-	val = (page_to_phys(gic_rdists->prop_page) |
+	val = (page_to_phys(gic_data_rdist()->prop_page) |
 	       GICR_PROPBASER_InnerShareable |
 	       GICR_PROPBASER_RaWaWb |
 	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
@@ -2037,6 +2019,59 @@ static void its_cpu_init_collection(void)
 	spin_unlock(&its_lock);
 }
 
+static int __init its_cpu_allocate_prop_tables(void)
+{
+	phys_addr_t paddr;
+	unsigned long flags;
+	int match_cpu;
+	u64 aff_mask = 0;
+	struct page *prop_page = NULL;
+	int cpu = smp_processor_id();
+
+	switch (gic_rdists->common_aff_lpi) {
+	case GICR_COMMON_ALL_SHARE:
+		aff_mask = 0;
+		break;
+	case GICR_COMMON_AFF3_SHARE:
+		aff_mask = 0xffULL << MPIDR_LEVEL_SHIFT(3);
+		break;
+	case GICR_COMMON_AFF3_AFF2_SHARE:
+		aff_mask = (0xffULL << MPIDR_LEVEL_SHIFT(3)) |
+			   (0xffULL << MPIDR_LEVEL_SHIFT(2));
+		break;
+	case GICR_COMMON_AFF3_AFF2_AFF1_SHARE:
+		aff_mask = (0xffULL << MPIDR_LEVEL_SHIFT(3)) |
+			   (0xffULL << MPIDR_LEVEL_SHIFT(2)) |
+			   (0xffULL << MPIDR_LEVEL_SHIFT(1));
+		break;
+	default:
+		pr_err("Bad common_aff_lpi:%d\n", gic_rdists->common_aff_lpi);
+	}
+
+	raw_spin_lock_irqsave(&gic_rdists->lock, flags);
+	for_each_cpu(match_cpu, cpu_possible_mask) {
+		struct page *match_prop_page = per_cpu_ptr(gic_rdists->rdist, match_cpu)->prop_page;
+		if ((cpu_logical_map(cpu) & aff_mask) == (cpu_logical_map(match_cpu) & aff_mask) &&
+		    match_prop_page) {
+			prop_page = match_prop_page;
+			break;
+		}
+	}
+	if (!prop_page) {
+		prop_page = its_allocate_prop_table(cpu_to_node(cpu), GFP_NOWAIT);
+		pr_err("Failed to allocate PROPBASE\n");
+		raw_spin_unlock_irqrestore(&gic_rdists->lock, flags);
+		return -ENOMEM;
+	}
+	gic_data_rdist()->prop_page = prop_page;
+	raw_spin_unlock_irqrestore(&gic_rdists->lock, flags);
+
+	paddr = page_to_phys(gic_data_rdist()->prop_page);
+	pr_info("CPU%d using LPI property table @%pa\n", cpu, &paddr);
+
+	return 0;
+}
+
 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
 {
 	struct its_device *its_dev = NULL, *tmp;
@@ -3340,10 +3375,14 @@ static bool gic_rdists_supports_plpis(void)
 int its_cpu_init(void)
 {
 	if (!list_empty(&its_nodes)) {
+		int err;
 		if (!gic_rdists_supports_plpis()) {
 			pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
 			return -ENXIO;
 		}
+		err = its_cpu_allocate_prop_tables();
+		if (err)
+			return err;
 		its_cpu_init_lpis();
 		its_cpu_init_collection();
 	}
@@ -3551,7 +3590,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
 	}
 
 	gic_rdists = rdists;
-	err = its_alloc_lpi_tables();
+	err = its_lpi_init(min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS));
 	if (err)
 		return err;
 
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 6da670a..35cafd9 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -109,6 +109,10 @@
 
 #define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)
 #define GICR_TYPER_COMMON_AFF_LPI(r)	(((r) >> 24) & 3)
+#define GICR_COMMON_ALL_SHARE			0
+#define GICR_COMMON_AFF3_SHARE			1
+#define GICR_COMMON_AFF3_AFF2_SHARE		2
+#define GICR_COMMON_AFF3_AFF2_AFF1_SHARE	3
 
 #define GICR_WAKER_ProcessorSleep	(1U << 1)
 #define GICR_WAKER_ChildrenAsleep	(1U << 2)
@@ -571,9 +575,9 @@ struct rdists {
 	struct {
 		void __iomem	*rd_base;
 		struct page	*pend_page;
+		struct page	*prop_page;
 		phys_addr_t	phys_base;
 	} __percpu		*rdist;
-	struct page		*prop_page;
 	int			id_bits;
 	u64			flags;
 	bool			has_vlpis;
-- 
1.8.3

[RFC PATCH 4/4] irqchip/gic-v3-its: sync config of LPIs if there are more than one prop_page

[Yang Yingliang]

The config of LPIs need to be same in each prop_page.
So if one prop_page is modified, other prop_page should
be updated too.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 39 ++++++++++++++++++++++++++++++---------
 1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 02a5d95..27306a5 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1051,11 +1051,25 @@ static inline u32 its_get_event_id(struct irq_data *d)
 	return d->hwirq - its_dev->event_map.lpi_base;
 }
 
+static inline void lpi_flush_config(u8 *cfg)
+{
+	/*
+	 * Make the above write visible to the redistributors.
+	 * And yes, we're flushing exactly: One. Single. Byte.
+	 * Humpf...
+	 */
+	if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
+		gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
+	else
+		dsb(ishst);
+}
+
 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
 {
 	irq_hw_number_t hwirq;
 	struct page *prop_page;
 	u8 *cfg;
+	int cpu;
 
 	if (irqd_is_forwarded_to_vcpu(d)) {
 		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
@@ -1078,15 +1092,22 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
 	*cfg &= ~clr;
 	*cfg |= set | LPI_PROP_GROUP1;
 
-	/*
-	 * Make the above write visible to the redistributors.
-	 * And yes, we're flushing exactly: One. Single. Byte.
-	 * Humpf...
-	 */
-	if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
-		gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
-	else
-		dsb(ishst);
+	if (gic_rdists->common_aff_lpi) {
+		/* It's protected by desc->lock, don't need lock any more. */
+		for_each_cpu(cpu, cpu_possible_mask) {
+			u8 *other_cfg;
+			struct page *other_prop_page = per_cpu_ptr(gic_rdists->rdist, cpu)->prop_page;
+
+			if (other_prop_page == prop_page)
+				continue;
+
+			other_cfg = page_address(other_prop_page) + hwirq - 8192;
+			*other_cfg = *cfg;
+			lpi_flush_config(other_cfg);
+		}
+	} else {
+		lpi_flush_config(cfg);
+	}
 }
 
 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
-- 
1.8.3

[RFC PATCH 4/4] irqchip/gic-v3-its: sync config of LPIs if there are more than one prop_page

[Yang Yingliang]

The config of LPIs need to be same in each prop_page.
So if one prop_page is modified, other prop_page should
be updated too.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 39 ++++++++++++++++++++++++++++++---------
 1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 02a5d95..27306a5 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1051,11 +1051,25 @@ static inline u32 its_get_event_id(struct irq_data *d)
 	return d->hwirq - its_dev->event_map.lpi_base;
 }
 
+static inline void lpi_flush_config(u8 *cfg)
+{
+	/*
+	 * Make the above write visible to the redistributors.
+	 * And yes, we're flushing exactly: One. Single. Byte.
+	 * Humpf...
+	 */
+	if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
+		gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
+	else
+		dsb(ishst);
+}
+
 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
 {
 	irq_hw_number_t hwirq;
 	struct page *prop_page;
 	u8 *cfg;
+	int cpu;
 
 	if (irqd_is_forwarded_to_vcpu(d)) {
 		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
@@ -1078,15 +1092,22 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
 	*cfg &= ~clr;
 	*cfg |= set | LPI_PROP_GROUP1;
 
-	/*
-	 * Make the above write visible to the redistributors.
-	 * And yes, we're flushing exactly: One. Single. Byte.
-	 * Humpf...
-	 */
-	if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
-		gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
-	else
-		dsb(ishst);
+	if (gic_rdists->common_aff_lpi) {
+		/* It's protected by desc->lock, don't need lock any more. */
+		for_each_cpu(cpu, cpu_possible_mask) {
+			u8 *other_cfg;
+			struct page *other_prop_page = per_cpu_ptr(gic_rdists->rdist, cpu)->prop_page;
+
+			if (other_prop_page == prop_page)
+				continue;
+
+			other_cfg = page_address(other_prop_page) + hwirq - 8192;
+			*other_cfg = *cfg;
+			lpi_flush_config(other_cfg);
+		}
+	} else {
+		lpi_flush_config(cfg);
+	}
 }
 
 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
-- 
1.8.3

Re: [RFC PATCH 0/4] add support for CommonLPIAff field

[Marc Zyngier]

On 12/03/18 06:49, Yang Yingliang wrote:
> This patch set adjust struct rdists to support CommonLPIAff field.
> This field is described in spec:
> 
> CommonLPIAff, bits [25:24]
> The affinity level at which Redistributors share a LPI Configuration table.
> 00 All Redistributors must share a LPI Configuration table.
> 01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
> 10 All Redistributors
> 11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
> table.

What are you trying to achieve here? We already share the same
configuration table across all the redistributors, irrelevant the of
CommonLPIAff. Why would we need to do anything else?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[RFC PATCH 0/4] add support for CommonLPIAff field

[Marc Zyngier]

On 12/03/18 06:49, Yang Yingliang wrote:
> This patch set adjust struct rdists to support CommonLPIAff field.
> This field is described in spec:
> 
> CommonLPIAff, bits [25:24]
> The affinity level at which Redistributors share a LPI Configuration table.
> 00 All Redistributors must share a LPI Configuration table.
> 01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
> 10 All Redistributors
> 11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
> table.

What are you trying to achieve here? We already share the same
configuration table across all the redistributors, irrelevant the of
CommonLPIAff. Why would we need to do anything else?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [RFC PATCH 0/4] add support for CommonLPIAff field

[Yang Yingliang]

On 2018/3/12 17:55, Marc Zyngier wrote:
> On 12/03/18 06:49, Yang Yingliang wrote:
>> This patch set adjust struct rdists to support CommonLPIAff field.
>> This field is described in spec:
>>
>> CommonLPIAff, bits [25:24]
>> The affinity level at which Redistributors share a LPI Configuration table.
>> 00 All Redistributors must share a LPI Configuration table.
>> 01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
>> 10 All Redistributors with the same Aff3.Aff2 value must share an LPI Configuration table.
>> 11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
>> table.
>
> What are you trying to achieve here? We already share the same
> configuration table across all the redistributors, irrelevant the of
> CommonLPIAff. Why would we need to do anything else?

In some cases, such as "with the same Aff3.Aff2 value must share an LPI
Configuration table", redistributors will access local memory node
only, it may improve the performance. And I don't have any beneficial
data now. I may provide it later.

Regards,
Yang
>
> Thanks,
>
> 	M.
>

[RFC PATCH 0/4] add support for CommonLPIAff field

[Yang Yingliang]

On 2018/3/12 17:55, Marc Zyngier wrote:
> On 12/03/18 06:49, Yang Yingliang wrote:
>> This patch set adjust struct rdists to support CommonLPIAff field.
>> This field is described in spec:
>>
>> CommonLPIAff, bits [25:24]
>> The affinity level at which Redistributors share a LPI Configuration table.
>> 00 All Redistributors must share a LPI Configuration table.
>> 01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
>> 10 All Redistributors with the same Aff3.Aff2 value must share an LPI Configuration table.
>> 11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
>> table.
>
> What are you trying to achieve here? We already share the same
> configuration table across all the redistributors, irrelevant the of
> CommonLPIAff. Why would we need to do anything else?

In some cases, such as "with the same Aff3.Aff2 value must share an LPI
Configuration table", redistributors will access local memory node
only, it may improve the performance. And I don't have any beneficial
data now. I may provide it later.

Regards,
Yang
>
> Thanks,
>
> 	M.
>

Re: [RFC PATCH 0/4] add support for CommonLPIAff field

[Marc Zyngier]

On 12/03/18 12:13, Yang Yingliang wrote:
> 
> 
> On 2018/3/12 17:55, Marc Zyngier wrote:
>> On 12/03/18 06:49, Yang Yingliang wrote:
>>> This patch set adjust struct rdists to support CommonLPIAff field.
>>> This field is described in spec:
>>>
>>> CommonLPIAff, bits [25:24]
>>> The affinity level at which Redistributors share a LPI Configuration table.
>>> 00 All Redistributors must share a LPI Configuration table.
>>> 01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
>>> 10 All Redistributors with the same Aff3.Aff2 value must share an LPI Configuration table.
>>> 11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
>>> table.
>>
>> What are you trying to achieve here? We already share the same
>> configuration table across all the redistributors, irrelevant the of
>> CommonLPIAff. Why would we need to do anything else?
> 
> In some cases, such as "with the same Aff3.Aff2 value must share an LPI
> Configuration table", redistributors will access local memory node
> only, it may improve the performance. And I don't have any beneficial
> data now. I may provide it later.

These are two different things.
- "must share" is what the kernel does *today*. No changes are required.
- NUMA behaviour has nothing to do with CommonLPIAff, and cannot be
based on that field.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[RFC PATCH 0/4] add support for CommonLPIAff field

[Marc Zyngier]

On 12/03/18 12:13, Yang Yingliang wrote:
> 
> 
> On 2018/3/12 17:55, Marc Zyngier wrote:
>> On 12/03/18 06:49, Yang Yingliang wrote:
>>> This patch set adjust struct rdists to support CommonLPIAff field.
>>> This field is described in spec:
>>>
>>> CommonLPIAff, bits [25:24]
>>> The affinity level at which Redistributors share a LPI Configuration table.
>>> 00 All Redistributors must share a LPI Configuration table.
>>> 01 All Redistributors with the same Aff3 value must share an LPI Configurationt table.
>>> 10 All Redistributors with the same Aff3.Aff2 value must share an LPI Configuration table.
>>> 11 All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration
>>> table.
>>
>> What are you trying to achieve here? We already share the same
>> configuration table across all the redistributors, irrelevant the of
>> CommonLPIAff. Why would we need to do anything else?
> 
> In some cases, such as "with the same Aff3.Aff2 value must share an LPI
> Configuration table", redistributors will access local memory node
> only, it may improve the performance. And I don't have any beneficial
> data now. I may provide it later.

These are two different things.
- "must share" is what the kernel does *today*. No changes are required.
- NUMA behaviour has nothing to do with CommonLPIAff, and cannot be
based on that field.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...