Re: [V6,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible

[kyrie.wu <kyrie.wu@mediatek.com>]

On Tue, 2022-08-16 at 10:26 -0600, Rob Herring wrote:
> On Fri, Jul 29, 2022 at 02:25:56PM +0800, Irui Wang wrote:
> > From: kyrie wu <kyrie.wu@mediatek.com>
> > 
> > Add mediatek,mt8195-jpgdec compatible to binding document.
> > 
> > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
> > Signed-off-by: irui wang <irui.wang@mediatek.com>
> > ---
> >  .../media/mediatek,mt8195-jpegdec.yaml        | 160
> > ++++++++++++++++++
> >  1 file changed, 160 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > b/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > new file mode 100644
> > index 000000000000..ebda0ade8153
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > @@ -0,0 +1,160 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml*__;Iw!!CTRNKA9wMg0ARbw!wMCZMPkHo2OpWyVWzw9r160qgCEZs9n6F3asqUcb2OqKXlrHCEAZCbpdjjhXD0JV$
> >  
> > +$schema: 
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!wMCZMPkHo2OpWyVWzw9r160qgCEZs9n6F3asqUcb2OqKXlrHCEAZCbpdjlBqY8-5$
> >  
> > +
> > +title: MediaTek JPEG Encoder Device Tree Bindings
> > +
> > +maintainers:
> > +  - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
> > +
> > +description:
> > +  MediaTek JPEG Decoder is the JPEG decode hardware present in
> > MediaTek SoCs
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: mediatek,mt8195-jpgdec
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  iommus:
> > +    maxItems: 6
> > +    description:
> > +      Points to the respective IOMMU block with master port as
> > argument, see
> > +      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > for details.
> > +      Ports are according to the HW.
> > +
> > +  "#address-cells":
> > +    const: 2
> > +
> > +  "#size-cells":
> > +    const: 2
> > +
> > +  ranges: true
> > +
> > +# Required child node:
> > +patternProperties:
> > +  "^jpgdec@[0-9a-f]+$":
> > +    type: object
> > +    description:
> > +      The jpeg decoder hardware device node which should be added
> > as subnodes to
> > +      the main jpeg node.
> > +
> > +    properties:
> > +      compatible:
> > +        const: mediatek,mt8195-jpgdec-hw
> > +
> > +      reg:
> > +        maxItems: 1
> > +
> > +      iommus:
> > +        minItems: 1
> > +        maxItems: 32
> > +        description:
> > +          List of the hardware port in respective IOMMU block for
> > current Socs.
> > +          Refer to bindings/iommu/mediatek,iommu.yaml.
> > +
> > +      interrupts:
> > +        maxItems: 1
> > +
> > +      clocks:
> > +        maxItems: 1
> > +
> > +      clock-names:
> > +        items:
> > +          - const: jpgdec
> > +
> > +      power-domains:
> > +        maxItems: 1
> > +
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - iommus
> > +      - interrupts
> > +      - clocks
> > +      - clock-names
> > +      - power-domains
> > +
> > +    additionalProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - power-domains
> > +  - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/memory/mt8195-memory-port.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/clock/mt8195-clk.h>
> > +    #include <dt-bindings/power/mt8195-power.h>
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        jpgdec_master {
> > +                compatible = "mediatek,mt8195-jpgdec";
> > +                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> > +                iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
> > +                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
> > +                     <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
> > +                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
> > +                     <&iommu_vpp
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > +                     <&iommu_vpp
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > +                #address-cells = <2>;
> > +                #size-cells = <2>;
> > +
> 
> Missing ranges.
> 
> Presumably at least 1 child node is required because there's no
> 'reg' 
> property in the parent to access the h/w. So 'ranges', "#address-
> cells', 
> and '#size-cells' should all be required.

Hello Rob,
Thanks for explanation why needs ranges.
I will add it in the next version.

Regards,
Kyrie.
> 
> > +                jpgdec@1a040000 {
> > +                    compatible = "mediatek,mt8195-jpgdec-hw";
> > +                    reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
> > +                    iommus = <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_WDMA0>,
> > +                        <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> > +                        <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> > +                        <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> > +                        <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > +                        <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > +                    interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +                    clocks = <&vencsys CLK_VENC_JPGDEC>;
> > +                    clock-names = "jpgdec";
> > +                    power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC0>;
> > +                };
> > +
> > +                jpgdec@1a050000 {
> > +                    compatible = "mediatek,mt8195-jpgdec-hw";
> > +                    reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
> > +                    iommus = <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_WDMA0>,
> > +                        <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> > +                        <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> > +                        <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> > +                        <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > +                        <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > +                    interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +                    clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
> > +                    clock-names = "jpgdec";
> > +                    power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC1>;
> > +                };
> > +
> > +                jpgdec@1b040000 {
> > +                    compatible = "mediatek,mt8195-jpgdec-hw";
> > +                    reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
> > +                    iommus = <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_WDMA0>,
> > +                        <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
> > +                        <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
> > +                        <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
> > +                        <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
> > +                        <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
> > +                    interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +                    clocks = <&vencsys_core1
> > CLK_VENC_CORE1_JPGDEC>;
> > +                    clock-names = "jpgdec";
> > +                    power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC2>;
> > +                };
> > +        };
> > +    };
> > -- 
> > 2.18.0
> > 
> >