* [PATCH 3/6] can: flexcan: add error passive state quirk
@ 2017-08-31 8:25 ZHU Yi (ST-FIR/ENG1-Zhu)
2017-08-31 11:44 ` Wolfgang Grandegger
0 siblings, 1 reply; 6+ messages in thread
From: ZHU Yi (ST-FIR/ENG1-Zhu) @ 2017-08-31 8:25 UTC (permalink / raw)
To: Wolfgang Grandegger, Marc Kleine-Budde, Andri Yngvason, linux-can
Cc: hs, RUAN Tingquan (ST-FIR/ENG1-Zhu), Jonas Mark (ST-FIR/ENG1)
From 916835bc515f24dff133526239c9e464b0153ba0 Mon Sep 17 00:00:00 2001
From: Zhu Yi <yi.zhu5@cn.bosch.com>
Date: Thu, 31 Aug 2017 09:21:24 +0800
Subject: [PATCH 3/6] can: flexcan: add error passive state quirk
Add FLEXCAN_QUIRK_BROKEN_PERR_STATE for better description
of the missing error passive interrupt quirk.
Signed-off-by: Zhu Yi <yi.zhu5@cn.bosch.com>
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
---
drivers/net/can/flexcan.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index e163c55..712b7de 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -198,6 +198,7 @@
#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
+#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
/* Structure of the message buffer */
struct flexcan_mb {
@@ -767,7 +768,8 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
/* state change interrupt or broken error state quirk fix is enabled */
if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
- (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
+ (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE) ||
+ (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE))
flexcan_irq_state(dev, reg_esr);
/* bus error IRQ - handle if bus error reporting is activated */
@@ -889,6 +891,7 @@ static int flexcan_chip_start(struct net_device *dev)
* any error warning or passive interrupts.
*/
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
+ priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE ||
priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
else
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/6] can: flexcan: add error passive state quirk
2017-08-31 8:25 [PATCH 3/6] can: flexcan: add error passive state quirk ZHU Yi (ST-FIR/ENG1-Zhu)
@ 2017-08-31 11:44 ` Wolfgang Grandegger
2017-09-01 6:10 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-09-04 10:00 ` ZHU Yi (ST-FIR/ENG1-Zhu)
0 siblings, 2 replies; 6+ messages in thread
From: Wolfgang Grandegger @ 2017-08-31 11:44 UTC (permalink / raw)
To: ZHU Yi (ST-FIR/ENG1-Zhu), Marc Kleine-Budde, Andri Yngvason, linux-can
Cc: hs, RUAN Tingquan (ST-FIR/ENG1-Zhu), Jonas Mark (ST-FIR/ENG1)
Am 31.08.2017 um 10:25 schrieb ZHU Yi (ST-FIR/ENG1-Zhu):
>>From 916835bc515f24dff133526239c9e464b0153ba0 Mon Sep 17 00:00:00 2001
> From: Zhu Yi <yi.zhu5@cn.bosch.com>
> Date: Thu, 31 Aug 2017 09:21:24 +0800
> Subject: [PATCH 3/6] can: flexcan: add error passive state quirk
>
> Add FLEXCAN_QUIRK_BROKEN_PERR_STATE for better description
> of the missing error passive interrupt quirk.
>
> Signed-off-by: Zhu Yi <yi.zhu5@cn.bosch.com>
> Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
> ---
> drivers/net/can/flexcan.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
> index e163c55..712b7de 100644
> --- a/drivers/net/can/flexcan.c
> +++ b/drivers/net/can/flexcan.c
> @@ -198,6 +198,7 @@
> #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
> #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
> #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
> +#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
>
> /* Structure of the message buffer */
> struct flexcan_mb {
> @@ -767,7 +768,8 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
>
> /* state change interrupt or broken error state quirk fix is enabled */
> if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
> - (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
> + (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE) ||
> + (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE))
(priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
FLEXCAN_QUIRK_BROKEN_PERR_STATE))
Is a bit more efficient. Here and in many other places.
> flexcan_irq_state(dev, reg_esr);
>
> /* bus error IRQ - handle if bus error reporting is activated */
> @@ -889,6 +891,7 @@ static int flexcan_chip_start(struct net_device *dev)
> * any error warning or passive interrupts.
> */
> if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
> + priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE ||
Ditto.
> priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
> reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
Do we want to enable the error interrupt from the beginning? We can
wait for the error warning interrupt!?
Wolfgang.
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 3/6] can: flexcan: add error passive state quirk
2017-08-31 11:44 ` Wolfgang Grandegger
@ 2017-09-01 6:10 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-09-04 10:00 ` ZHU Yi (ST-FIR/ENG1-Zhu)
1 sibling, 0 replies; 6+ messages in thread
From: ZHU Yi (ST-FIR/ENG1-Zhu) @ 2017-09-01 6:10 UTC (permalink / raw)
To: Wolfgang Grandegger, Marc Kleine-Budde, Andri Yngvason, linux-can
Cc: hs, RUAN Tingquan (ST-FIR/ENG1-Zhu), Jonas Mark (ST-FIR/ENG1)
Hello Wolfgang,
> From: Wolfgang Grandegger [mailto:wg@grandegger.com]
> Sent: Thursday, August 31, 2017 7:44 PM
>
> [...]
> > @@ -767,7 +768,8 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
> >
> > /* state change interrupt or broken error state quirk fix is enabled */
> > if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
> > - (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
> > + (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE) ||
> > + (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE))
>
> (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
> FLEXCAN_QUIRK_BROKEN_PERR_STATE))
>
>
> Is a bit more efficient. Here and in many other places.
Yes, that's a good catch, I'll fix this.
>
> > flexcan_irq_state(dev, reg_esr);
> >
> > /* bus error IRQ - handle if bus error reporting is activated */
> > @@ -889,6 +891,7 @@ static int flexcan_chip_start(struct net_device *dev)
> > * any error warning or passive interrupts.
> > */
> > if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
> > + priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE ||
>
> Ditto.
>
> > priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
> > reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
>
> Do we want to enable the error interrupt from the beginning? We can
> wait for the error warning interrupt!?
That's another good catch, if only FLEXCAN_QUIRK_BROKEN_PERR_STATE
been set, then it don't need to enable the error interrupt from the
beginning. This can save us at most 11 times error interrupts on
these cores when there are bus problems.
If FLEXCAN_QUIRK_BROKEN_WERR_STATE is set, then the error interrupt
is still enabled from the beginning (for the old core which do not
have [TR]WRN_INT connected).
However, this may complicates the handling inside flexcan_irq().
In sunny day scenario, that is flexcan_irq_state() will be called upon
every possible state transitions, then we can write code like below to
achieve this:
```
if (state_changed &&
(priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
switch (priv->can.state) {
case CAN_STATE_ERROR_PASSIVE:
// disable error interrupt
break;
case CAN_STATE_ERROR_WARNING:
// enable error interrupt
break;
case CAN_STATE_ERROR_ACTIVE:
if (!(priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
// disable error interrupt
break;
default:
break;
}
}
```
In rainy day scenario, that is due to some unbelievable reason,
flexcan_irq_state() maybe called jumps some state transitions,
hence we added:
1. explicitly disable error interrupt in bus off, to prevent
surprise of still get error interrupts when the error state
jump from active/warning to bus off (although in theory, bus
off should not generate any interrupts, even the interrupt
are enabled).
2. explicitly enable error interrupt in error active, to prevent
the error state jump from error passive to error active which
leaves error interrupt still disabled, then on the old core,
it cannot report correct state transitions again (in theory,
this should not happen too).
If we take these defensive thinking into account, then it will
results a complicated logic here - we need to differentiate the
old and new core, and handle them separately.
Maybe we're a bit paranoic here, but we think the decision should
be considered among performance, reliability and maintainability.
Here we think the performance gain is limited, because in worst case,
we get 11 times useless interrupt on the new core when every time the
bus has problem, and this is the best gain we can have. But on the
other hand, if we sacrifice this gain, we can get better reliability
(perhaps) and maintainability (same code for new and old core).
What do you think?
Best regards
Yi
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 3/6] can: flexcan: add error passive state quirk
2017-08-31 11:44 ` Wolfgang Grandegger
2017-09-01 6:10 ` ZHU Yi (ST-FIR/ENG1-Zhu)
@ 2017-09-04 10:00 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-09-04 19:57 ` Wolfgang Grandegger
1 sibling, 1 reply; 6+ messages in thread
From: ZHU Yi (ST-FIR/ENG1-Zhu) @ 2017-09-04 10:00 UTC (permalink / raw)
To: Wolfgang Grandegger, Marc Kleine-Budde, Andri Yngvason, linux-can
Cc: hs, RUAN Tingquan (ST-FIR/ENG1-Zhu), Jonas Mark (ST-FIR/ENG1)
Hello Wolfgang,
> > From: Wolfgang Grandegger [mailto:wg@grandegger.com]
> > Sent: Thursday, August 31, 2017 7:44 PM
> >
> > [...]
> >
> > Do we want to enable the error interrupt from the beginning? We can
> > wait for the error warning interrupt!?
> That's another good catch, if only FLEXCAN_QUIRK_BROKEN_PERR_STATE
> been set, then it don't need to enable the error interrupt from the
> beginning. This can save us at most 11 times error interrupts on
> these cores when there are bus problems.
>
> If FLEXCAN_QUIRK_BROKEN_WERR_STATE is set, then the error interrupt
> is still enabled from the beginning (for the old core which do not
> have [TR]WRN_INT connected).
>
> However, this may complicates the handling inside flexcan_irq().
>
> In sunny day scenario, [...]
>
> In rainy day scenario, that is due to some unbelievable reason,
> flexcan_irq_state() maybe called jumps some state transitions,
> hence we added:
> 1. explicitly disable error interrupt in bus off, to prevent
> surprise of still get error interrupts when the error state
> jump from active/warning to bus off (although in theory, bus
> off should not generate any interrupts, even the interrupt
> are enabled).
> 2. explicitly enable error interrupt in error active, to prevent
> the error state jump from error passive to error active which
> leaves error interrupt still disabled, then on the old core,
> it cannot report correct state transitions again (in theory,
> this should not happen too).
>
> If we take these defensive thinking into account, then it will
> results a complicated logic here - we need to differentiate the
> old and new core, and handle them separately.
>
> Maybe we're a bit paranoic here, but we think the decision should
> be considered among performance, reliability and maintainability.
>
> Here we think the performance gain is limited, because in worst case,
> we get 11 times useless interrupt on the new core when every time the
> bus has problem, and this is the best gain we can have. But on the
> other hand, if we sacrifice this gain, we can get better reliability
> (perhaps) and maintainability (same code for new and old core).
>
> What do you think?
After some deep thinking, we realized that actually we can achieve
all instead of sacrifice any one of aforementioned three points.
The pseudo code looks like below:
```
if (state_changed &&
(priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
switch (priv->can.state) {
case CAN_STATE_ERROR_PASSIVE:
case CAN_STATE_BUS_OFF:
// disable error interrupt
break;
case CAN_STATE_ERROR_WARNING:
// enable error interrupt
break;
case CAN_STATE_ERROR_ACTIVE:
if (!(priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
// disable error interrupt
else
// enable error interrupt
break;
default:
break;
}
}
```
In this way, we can achieve the optimization for the new core, and also
take care of the paranoic cases, and the readability IMHO looks not bad. :)
Below are the test results (based on v4.11 with the proposed patches).
Test case:
1. Disconnect the cable
2. "ip link set xxx type can bitrate 500000" and "ip link set xxx up"
3. "cansend xxx 123#ffffffffffffffff"
Enabled [TR]WRN_INT and FLEXCAN_QUIRK_BROKEN_PERR_STATE on i.MX6:
# dmesg | grep flexcan
[ 1.561013] flexcan 2090000.flexcan: 2090000.flexcan supply xceiver not found, using dummy regulator
[ 1.570393] flexcan 2090000.flexcan: can_rx_offload_init_queue: skb_queue_len_max=512
[ 1.570979] flexcan 2090000.flexcan: device registered (reg_base=e0a78000, irq=34)
[ 6.085287] flexcan 2090000.flexcan mob0: renamed from can0
[ 39.118751] flexcan 2090000.flexcan mob0: writing ctrl=0x013a2007
[ 39.118779] flexcan 2090000.flexcan mob0: flexcan_set_bittiming: mcr=0x5980000f ctrl=0x013a2007
[ 39.118797] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing mcr=0x59a3023f
[ 39.118813] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing ctrl=0x013a2057
[ 39.118910] flexcan 2090000.flexcan mob0: flexcan_chip_start: reading mcr=0x40a3023f ctrl=0x013aac57
[ 53.873593] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x62242
[ 53.873624] flexcan 2090000.flexcan mob0: New error state: 1
[ 53.873833] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 53.874089] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 53.874348] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 53.874608] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 53.874627] flexcan 2090000.flexcan mob0: New error state: 2
Disabled [TR]WRN_INT and enabled FLEXCAN_QUIRK_BROKEN_PERR_STATE +
FLEXCAN_QUIRK_BROKEN_WERR_STATE on i.MX6:
# dmesg | grep flexcan
[ 1.561071] flexcan 2090000.flexcan: 2090000.flexcan supply xceiver not found, using dummy regulator
[ 1.570452] flexcan 2090000.flexcan: can_rx_offload_init_queue: skb_queue_len_max=512
[ 1.571037] flexcan 2090000.flexcan: device registered (reg_base=e0a78000, irq=34)
[ 6.126949] flexcan 2090000.flexcan mob0: renamed from can0
[ 81.924194] flexcan 2090000.flexcan mob0: writing ctrl=0x013a2007
[ 81.924225] flexcan 2090000.flexcan mob0: flexcan_set_bittiming: mcr=0x5980000f ctrl=0x013a2007
[ 81.924243] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing mcr=0x5983023f
[ 81.924258] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing ctrl=0x013a2057
[ 81.924361] flexcan 2090000.flexcan mob0: flexcan_chip_start: reading mcr=0x4083023f ctrl=0x013ae057
[ 98.428902] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.429145] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.429400] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.429666] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.429975] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.430183] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.430442] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.430706] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.430962] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.431221] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.431484] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 98.431746] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 98.431775] flexcan 2090000.flexcan mob0: New error state: 1
[ 98.432001] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 98.432262] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 98.432523] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 98.432781] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 98.432806] flexcan 2090000.flexcan mob0: New error state: 2
Best regards
Yi
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/6] can: flexcan: add error passive state quirk
2017-09-04 10:00 ` ZHU Yi (ST-FIR/ENG1-Zhu)
@ 2017-09-04 19:57 ` Wolfgang Grandegger
2017-09-05 4:02 ` ZHU Yi (ST-FIR/ENG1-Zhu)
0 siblings, 1 reply; 6+ messages in thread
From: Wolfgang Grandegger @ 2017-09-04 19:57 UTC (permalink / raw)
To: ZHU Yi (ST-FIR/ENG1-Zhu), Marc Kleine-Budde, Andri Yngvason, linux-can
Cc: hs, RUAN Tingquan (ST-FIR/ENG1-Zhu), Jonas Mark (ST-FIR/ENG1)
Hello,
Am 04.09.2017 um 12:00 schrieb ZHU Yi (ST-FIR/ENG1-Zhu):
> Hello Wolfgang,
>
>>> From: Wolfgang Grandegger [mailto:wg@grandegger.com]
>>> Sent: Thursday, August 31, 2017 7:44 PM
>>>
>>> [...]
>>>
>>> Do we want to enable the error interrupt from the beginning? We can
>>> wait for the error warning interrupt!?
>> That's another good catch, if only FLEXCAN_QUIRK_BROKEN_PERR_STATE
>> been set, then it don't need to enable the error interrupt from the
>> beginning. This can save us at most 11 times error interrupts on
>> these cores when there are bus problems.
>>
>> If FLEXCAN_QUIRK_BROKEN_WERR_STATE is set, then the error interrupt
>> is still enabled from the beginning (for the old core which do not
>> have [TR]WRN_INT connected).
>>
>> However, this may complicates the handling inside flexcan_irq().
>>
>> In sunny day scenario, [...]
>>
>> In rainy day scenario, that is due to some unbelievable reason,
>> flexcan_irq_state() maybe called jumps some state transitions,
>> hence we added:
>> 1. explicitly disable error interrupt in bus off, to prevent
>> surprise of still get error interrupts when the error state
>> jump from active/warning to bus off (although in theory, bus
>> off should not generate any interrupts, even the interrupt
>> are enabled).
>> 2. explicitly enable error interrupt in error active, to prevent
>> the error state jump from error passive to error active which
>> leaves error interrupt still disabled, then on the old core,
>> it cannot report correct state transitions again (in theory,
>> this should not happen too).
>>
>> If we take these defensive thinking into account, then it will
>> results a complicated logic here - we need to differentiate the
>> old and new core, and handle them separately.
>>
>> Maybe we're a bit paranoic here, but we think the decision should
>> be considered among performance, reliability and maintainability.
>>
>> Here we think the performance gain is limited, because in worst case,
>> we get 11 times useless interrupt on the new core when every time the
>> bus has problem, and this is the best gain we can have. But on the
>> other hand, if we sacrifice this gain, we can get better reliability
>> (perhaps) and maintainability (same code for new and old core).
>>
>> What do you think?
> After some deep thinking, we realized that actually we can achieve
> all instead of sacrifice any one of aforementioned three points.
>
> The pseudo code looks like below:
> ```
> if (state_changed &&
> (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
> !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
> switch (priv->can.state) {
> case CAN_STATE_ERROR_PASSIVE:
> case CAN_STATE_BUS_OFF:
> // disable error interrupt
> break;
>
> case CAN_STATE_ERROR_WARNING:
> // enable error interrupt
> break;
>
> case CAN_STATE_ERROR_ACTIVE:
> if (!(priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
This means that you have both set, FLEXCAN_QUIRK_BROKEN_WERR_STATE and
FLEXCAN_QUIRK_BROKEN_PERR_STATE for the legacy cores.
> // disable error interrupt
> else
> // enable error interrupt
> break;
>
> default:
> break;
> }
> }
> ```
>
> In this way, we can achieve the optimization for the new core, and also
> take care of the paranoic cases, and the readability IMHO looks not bad. :)
>
> Below are the test results (based on v4.11 with the proposed patches).
>
> Test case:
> 1. Disconnect the cable
> 2. "ip link set xxx type can bitrate 500000" and "ip link set xxx up"
> 3. "cansend xxx 123#ffffffffffffffff"
>
> Enabled [TR]WRN_INT and FLEXCAN_QUIRK_BROKEN_PERR_STATE on i.MX6:
> # dmesg | grep flexcan
> [ 1.561013] flexcan 2090000.flexcan: 2090000.flexcan supply xceiver not found, using dummy regulator
> [ 1.570393] flexcan 2090000.flexcan: can_rx_offload_init_queue: skb_queue_len_max=512
> [ 1.570979] flexcan 2090000.flexcan: device registered (reg_base=e0a78000, irq=34)
> [ 6.085287] flexcan 2090000.flexcan mob0: renamed from can0
> [ 39.118751] flexcan 2090000.flexcan mob0: writing ctrl=0x013a2007
> [ 39.118779] flexcan 2090000.flexcan mob0: flexcan_set_bittiming: mcr=0x5980000f ctrl=0x013a2007
> [ 39.118797] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing mcr=0x59a3023f
> [ 39.118813] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing ctrl=0x013a2057
> [ 39.118910] flexcan 2090000.flexcan mob0: flexcan_chip_start: reading mcr=0x40a3023f ctrl=0x013aac57
> [ 53.873593] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x62242
> [ 53.873624] flexcan 2090000.flexcan mob0: New error state: 1
> [ 53.873833] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
> [ 53.874089] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
> [ 53.874348] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
> [ 53.874608] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
> [ 53.874627] flexcan 2090000.flexcan mob0: New error state: 2
>
> Disabled [TR]WRN_INT and enabled FLEXCAN_QUIRK_BROKEN_PERR_STATE +
> FLEXCAN_QUIRK_BROKEN_WERR_STATE on i.MX6:
> # dmesg | grep flexcan
> [ 1.561071] flexcan 2090000.flexcan: 2090000.flexcan supply xceiver not found, using dummy regulator
> [ 1.570452] flexcan 2090000.flexcan: can_rx_offload_init_queue: skb_queue_len_max=512
> [ 1.571037] flexcan 2090000.flexcan: device registered (reg_base=e0a78000, irq=34)
> [ 6.126949] flexcan 2090000.flexcan mob0: renamed from can0
> [ 81.924194] flexcan 2090000.flexcan mob0: writing ctrl=0x013a2007
> [ 81.924225] flexcan 2090000.flexcan mob0: flexcan_set_bittiming: mcr=0x5980000f ctrl=0x013a2007
> [ 81.924243] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing mcr=0x5983023f
> [ 81.924258] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing ctrl=0x013a2057
> [ 81.924361] flexcan 2090000.flexcan mob0: flexcan_chip_start: reading mcr=0x4083023f ctrl=0x013ae057
> [ 98.428902] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.429145] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.429400] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.429666] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.429975] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.430183] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.430442] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.430706] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.430962] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.431221] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.431484] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
> [ 98.431746] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
> [ 98.431775] flexcan 2090000.flexcan mob0: New error state: 1
> [ 98.432001] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
> [ 98.432262] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
> [ 98.432523] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
> [ 98.432781] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
> [ 98.432806] flexcan 2090000.flexcan mob0: New error state: 2
Could you please show the full trace when reconnecting the cable to see
how the state decreases. And then again unplug the cable. And send a
message.
Wolfgang.
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 3/6] can: flexcan: add error passive state quirk
2017-09-04 19:57 ` Wolfgang Grandegger
@ 2017-09-05 4:02 ` ZHU Yi (ST-FIR/ENG1-Zhu)
0 siblings, 0 replies; 6+ messages in thread
From: ZHU Yi (ST-FIR/ENG1-Zhu) @ 2017-09-05 4:02 UTC (permalink / raw)
To: Wolfgang Grandegger, Marc Kleine-Budde, Andri Yngvason, linux-can
Cc: hs, RUAN Tingquan (ST-FIR/ENG1-Zhu), Jonas Mark (ST-FIR/ENG1)
[-- Attachment #1: Type: text/plain, Size: 2293 bytes --]
Hello Wolfgang,
> From: Wolfgang Grandegger [mailto:wg@grandegger.com]
> Sent: Tuesday, September 05, 2017 3:57 AM
>
> [...]
> > The pseudo code looks like below:
> > ```
> > if (state_changed &&
> > (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE)
> &&
> > !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
> > switch (priv->can.state) {
> > case CAN_STATE_ERROR_PASSIVE:
> > case CAN_STATE_BUS_OFF:
> > // disable error interrupt
> > break;
> >
> > case CAN_STATE_ERROR_WARNING:
> > // enable error interrupt
> > break;
> >
> > case CAN_STATE_ERROR_ACTIVE:
> > if (!(priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
>
> This means that you have both set, FLEXCAN_QUIRK_BROKEN_WERR_STATE and
> FLEXCAN_QUIRK_BROKEN_PERR_STATE for the legacy cores.
Yes. The quirk needs to be set according to the hardware feature.
>
> > [...]
> > Below are the test results (based on v4.11 with the proposed patches).
> >
> > Test case:
> > 1. Disconnect the cable
> > 2. "ip link set xxx type can bitrate 500000" and "ip link set xxx up"
> > 3. "cansend xxx 123#ffffffffffffffff"
> >
> > [...]
>
> Could you please show the full trace when reconnecting the cable to see
> how the state decreases. And then again unplug the cable. And send a
> message.
Sure. Due to without Tx interrupt, the error state cannot decrease to
error active, so I changed above script a little, see below.
Test case (continued):
4. Connect the cable (observe state decrease to error warning)
5. "cangen xxx -i" and wait state decrease to error active
6. Disconnect the cable and wait state increase to error passive
7. Connect the cable and wait state decrease to error warning
8. Disconnect the cable and wait state increase to error passive
PS: I didn't wait error counter decrease to 0 when state change to
error active before unplug the cable again. So the "legacy core"
doesn't take multiple error interrupts to enter error warning again.
Enabled [TR]WRN_INT and FLEXCAN_QUIRK_BROKEN_PERR_STATE on i.MX6:
Please see attached new.log.
Disabled [TR]WRN_INT and enabled FLEXCAN_QUIRK_BROKEN_PERR_STATE +
FLEXCAN_QUIRK_BROKEN_WERR_STATE on i.MX6:
Please see attached legacy.log.
Best regards
Yi
[-- Attachment #2: new.log --]
[-- Type: application/octet-stream, Size: 7839 bytes --]
[ 1.561243] flexcan 2090000.flexcan: 2090000.flexcan supply xceiver not found, using dummy regulator
[ 1.570621] flexcan 2090000.flexcan: can_rx_offload_init_queue: skb_queue_len_max=512
[ 1.571200] flexcan 2090000.flexcan: device registered (reg_base=e0a78000, irq=34)
[ 6.094353] flexcan 2090000.flexcan mob0: renamed from can0
[ 25.834885] flexcan 2090000.flexcan mob0: writing ctrl=0x013a2007
[ 25.834914] flexcan 2090000.flexcan mob0: flexcan_set_bittiming: mcr=0x5980000f ctrl=0x013a2007
[ 25.834931] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing mcr=0x59a3023f
[ 25.834947] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing ctrl=0x013a2057
[ 25.835044] flexcan 2090000.flexcan mob0: flexcan_chip_start: reading mcr=0x40a3023f ctrl=0x013aac57
[ 74.523308] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x62242
[ 74.523337] flexcan 2090000.flexcan mob0: New error state: 1
[ 74.523550] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 74.523806] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 74.524064] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 74.524324] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 74.524342] flexcan 2090000.flexcan mob0: New error state: 2
[ 98.734548] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x42282
[ 98.734577] flexcan 2090000.flexcan mob0: New error state: 1
[ 109.005528] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 109.205829] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 109.406037] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 109.606770] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 109.807254] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 110.007481] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 110.208740] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 110.408917] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 110.609483] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 110.809711] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 111.011355] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 111.211496] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 111.411898] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 111.612257] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 111.813613] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 112.015330] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 112.215894] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 112.417498] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 112.618004] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 112.818423] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 113.019708] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 113.220028] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 113.420988] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 113.621734] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 113.822547] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 114.023521] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 114.224231] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 114.425793] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 114.626497] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 114.826901] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 115.027553] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 115.228618] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 115.228646] flexcan 2090000.flexcan mob0: New error state: 0
[ 115.429091] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 115.629604] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 115.829712] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 116.030186] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 116.231653] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 116.432111] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 116.632294] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 116.832672] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x62242
[ 116.832701] flexcan 2090000.flexcan mob0: New error state: 1
[ 116.832842] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 116.833027] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 116.833216] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 116.833407] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 116.833425] flexcan 2090000.flexcan mob0: New error state: 2
[ 124.248629] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x42282
[ 124.248657] flexcan 2090000.flexcan mob0: New error state: 1
[ 124.248806] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.249051] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.249314] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.249515] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.249713] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.249989] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.250272] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.250536] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.250838] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.251119] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.251317] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.251460] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.251679] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.251817] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.252631] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.253358] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.254079] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.254816] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.255545] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.256193] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.257008] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.257624] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.258472] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.259134] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.259947] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.260651] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.261405] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.262129] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.262869] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.263591] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.264326] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 124.264968] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 124.265139] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 124.265316] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 124.265490] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 124.265515] flexcan 2090000.flexcan mob0: New error state: 2
[-- Attachment #3: legacy.log --]
[-- Type: application/octet-stream, Size: 8066 bytes --]
[ 1.561212] flexcan 2090000.flexcan: 2090000.flexcan supply xceiver not found, using dummy regulator
[ 1.570591] flexcan 2090000.flexcan: can_rx_offload_init_queue: skb_queue_len_max=512
[ 1.571173] flexcan 2090000.flexcan: device registered (reg_base=e0a78000, irq=34)
[ 6.156988] flexcan 2090000.flexcan mob0: renamed from can0
[ 517.621009] flexcan 2090000.flexcan mob0: writing ctrl=0x013a2007
[ 517.621037] flexcan 2090000.flexcan mob0: flexcan_set_bittiming: mcr=0x5980000f ctrl=0x013a2007
[ 517.621055] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing mcr=0x5983023f
[ 517.621070] flexcan 2090000.flexcan mob0: flexcan_chip_start: writing ctrl=0x013a2057
[ 517.621166] flexcan 2090000.flexcan mob0: flexcan_chip_start: reading mcr=0x4083023f ctrl=0x013ae057
[ 535.058143] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.058379] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.058645] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.058907] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.059165] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.059428] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.059687] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.059977] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.060202] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.060467] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.060723] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42042
[ 535.060981] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 535.061007] flexcan 2090000.flexcan mob0: New error state: 1
[ 535.061241] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 535.061506] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 535.061767] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 535.062023] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 535.062046] flexcan 2090000.flexcan mob0: New error state: 2
[ 540.502581] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x42282
[ 540.502612] flexcan 2090000.flexcan mob0: New error state: 1
[ 550.250170] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 550.451286] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 550.651575] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 550.851733] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 551.052035] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 551.252829] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 551.453501] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 551.654182] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 551.854377] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 552.054767] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 552.255024] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 552.456236] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 552.656428] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 552.856761] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 553.057000] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 553.257392] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 553.457827] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 553.658390] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 553.858727] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 554.058960] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 554.260183] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 554.460807] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 554.661167] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 554.861433] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 555.061636] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 555.263100] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 555.463457] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 555.664165] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 555.864392] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 556.065158] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 556.266556] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 556.467605] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 556.467634] flexcan 2090000.flexcan mob0: New error state: 0
[ 556.668072] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 556.868474] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 557.068742] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 557.269752] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 557.470539] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 557.671396] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 557.872835] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40080
[ 558.073570] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 558.073599] flexcan 2090000.flexcan mob0: New error state: 1
[ 558.073694] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 558.073832] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 558.073971] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 558.074113] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 558.074133] flexcan 2090000.flexcan mob0: New error state: 2
[ 566.295066] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x42282
[ 566.295096] flexcan 2090000.flexcan mob0: New error state: 1
[ 566.295380] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.295647] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.295904] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.296170] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.296431] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.296696] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.296964] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.297113] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.297328] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.297492] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.297721] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.297988] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.298260] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.298537] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.298948] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.299676] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.300523] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.301248] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.301994] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.302607] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.303468] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.304174] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.304901] flexcan 2090000.flexcan mob0: reg_iflag1=0x2 reg_esr=0x40280
[ 566.305541] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 566.305592] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x4060a
[ 566.305758] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42242
[ 566.305915] flexcan 2090000.flexcan mob0: reg_iflag1=0x0 reg_esr=0x42252
[ 566.305944] flexcan 2090000.flexcan mob0: New error state: 2
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-09-05 4:02 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-31 8:25 [PATCH 3/6] can: flexcan: add error passive state quirk ZHU Yi (ST-FIR/ENG1-Zhu)
2017-08-31 11:44 ` Wolfgang Grandegger
2017-09-01 6:10 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-09-04 10:00 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-09-04 19:57 ` Wolfgang Grandegger
2017-09-05 4:02 ` ZHU Yi (ST-FIR/ENG1-Zhu)
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