* [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform
@ 2018-03-30 16:53 Dinh Nguyen
2018-03-30 19:45 ` Marek Vasut
0 siblings, 1 reply; 6+ messages in thread
From: Dinh Nguyen @ 2018-03-30 16:53 UTC (permalink / raw)
To: u-boot
Add a DM compatible reset driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
drivers/reset/Kconfig | 7 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 119 insertions(+)
create mode 100644 drivers/reset/reset-socfpga.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3964b9e..90b021f 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -83,4 +83,11 @@ config RESET_ROCKCHIP
though is that some reset signals, like I2C or MISC reset multiple
devices.
+config RESET_SOCFPGA
+ bool "Reset controller driver for SoCFPGA"
+ depends on DM_RESET && ARCH_SOCFPGA
+ default y
+ help
+ Support for reset controller on SoCFPGA platform.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 7d7e080..6f791ee 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
+obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
new file mode 100644
index 0000000..af585ec
--- /dev/null
+++ b/drivers/reset/reset-socfpga.c
@@ -0,0 +1,111 @@
+/*
+ * Socfpga Reset Controller Driver
+ *
+ * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * based on
+ * Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define BANK_INCREMENT 4
+#define NR_BANKS 8
+
+struct socfpga_reset_data {
+ void __iomem *membase;
+};
+
+static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+ unsigned long flags;
+ u32 reg;
+
+ reg = readl(data->membase + (bank * BANK_INCREMENT));
+ writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
+ return 0;
+}
+
+static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+ unsigned long flags;
+ u32 reg;
+
+ reg = readl(data->membase + (bank * BANK_INCREMENT));
+ writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
+ return 0;
+}
+
+static int socfpga_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int socfpga_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static const struct reset_ops socfpga_reset_ops = {
+ .request = socfpga_reset_request,
+ .free = socfpga_reset_free,
+ .rst_assert = socfpga_reset_assert,
+ .rst_deassert = socfpga_reset_deassert,
+};
+
+static int socfpga_reset_probe(struct udevice *dev)
+{
+ struct socfpga_reset_data *data = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ u32 modrst_offset;
+
+ data->membase = devfdt_get_addr_ptr(dev);
+
+ modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10);
+ data->membase += modrst_offset;
+
+ return 0;
+}
+
+static const struct udevice_id socfpga_reset_match[] = {
+ { .compatible = "altr,rst-mgr" },
+ { /* sentinel */ },
+};
+
+U_BOOT_DRIVER(socfpga_reset) = {
+ .name = "socfpga-reset",
+ .id = UCLASS_RESET,
+ .of_match = socfpga_reset_match,
+ .probe = socfpga_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
+ .ops = &socfpga_reset_ops,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform
2018-03-30 16:53 [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform Dinh Nguyen
@ 2018-03-30 19:45 ` Marek Vasut
2018-04-03 14:04 ` Dinh Nguyen
0 siblings, 1 reply; 6+ messages in thread
From: Marek Vasut @ 2018-03-30 19:45 UTC (permalink / raw)
To: u-boot
On 03/30/2018 06:53 PM, Dinh Nguyen wrote:
> Add a DM compatible reset driver for the SoCFPGA platform.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> drivers/reset/Kconfig | 7 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 119 insertions(+)
> create mode 100644 drivers/reset/reset-socfpga.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 3964b9e..90b021f 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -83,4 +83,11 @@ config RESET_ROCKCHIP
> though is that some reset signals, like I2C or MISC reset multiple
> devices.
>
> +config RESET_SOCFPGA
> + bool "Reset controller driver for SoCFPGA"
> + depends on DM_RESET && ARCH_SOCFPGA
> + default y
> + help
> + Support for reset controller on SoCFPGA platform.
> +
> endmenu
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 7d7e080..6f791ee 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
> obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
> +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> new file mode 100644
> index 0000000..af585ec
> --- /dev/null
> +++ b/drivers/reset/reset-socfpga.c
> @@ -0,0 +1,111 @@
> +/*
> + * Socfpga Reset Controller Driver
> + *
> + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
> + *
> + * based on
> + * Allwinner SoCs Reset Controller driver
> + *
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/of_access.h>
> +#include <reset-uclass.h>
> +#include <linux/bitops.h>
> +#include <linux/io.h>
> +#include <linux/sizes.h>
> +
> +#define BANK_INCREMENT 4
> +#define NR_BANKS 8
> +
> +struct socfpga_reset_data {
> + void __iomem *membase;
> +};
> +
> +static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
> +{
> + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
> + int id = reset_ctl->id;
> + int reg_width = sizeof(u32);
> + int bank = id / (reg_width * BITS_PER_BYTE);
> + int offset = id % (reg_width * BITS_PER_BYTE);
> + unsigned long flags;
> + u32 reg;
> +
> + reg = readl(data->membase + (bank * BANK_INCREMENT));
> + writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
setbits_le32() ?
> + return 0;
> +}
> +
> +static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
> +{
> + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
> + int id = reset_ctl->id;
> + int reg_width = sizeof(u32);
> + int bank = id / (reg_width * BITS_PER_BYTE);
> + int offset = id % (reg_width * BITS_PER_BYTE);
> + unsigned long flags;
> + u32 reg;
> +
> + reg = readl(data->membase + (bank * BANK_INCREMENT));
> + writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
clrbits_le32() ?
[...]
What I do not see is any user of this code, nor any conversion of
existing systems to use this code. Is that expected to happen ? I do not
want to see dead code piling up in U-Boot.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform
2018-03-30 19:45 ` Marek Vasut
@ 2018-04-03 14:04 ` Dinh Nguyen
2018-04-03 14:07 ` Marek Vasut
0 siblings, 1 reply; 6+ messages in thread
From: Dinh Nguyen @ 2018-04-03 14:04 UTC (permalink / raw)
To: u-boot
On 03/30/2018 02:45 PM, Marek Vasut wrote:
> On 03/30/2018 06:53 PM, Dinh Nguyen wrote:
>> Add a DM compatible reset driver for the SoCFPGA platform.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> drivers/reset/Kconfig | 7 +++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 119 insertions(+)
>> create mode 100644 drivers/reset/reset-socfpga.c
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 3964b9e..90b021f 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -83,4 +83,11 @@ config RESET_ROCKCHIP
>> though is that some reset signals, like I2C or MISC reset multiple
>> devices.
>>
>> +config RESET_SOCFPGA
>> + bool "Reset controller driver for SoCFPGA"
>> + depends on DM_RESET && ARCH_SOCFPGA
>> + default y
>> + help
>> + Support for reset controller on SoCFPGA platform.
>> +
>> endmenu
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 7d7e080..6f791ee 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
>> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>> obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
>> obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
>> +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
>> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
>> new file mode 100644
>> index 0000000..af585ec
>> --- /dev/null
>> +++ b/drivers/reset/reset-socfpga.c
>> @@ -0,0 +1,111 @@
>> +/*
>> + * Socfpga Reset Controller Driver
>> + *
>> + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
>> + *
>> + * based on
>> + * Allwinner SoCs Reset Controller driver
>> + *
>> + * Copyright 2013 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <dm/of_access.h>
>> +#include <reset-uclass.h>
>> +#include <linux/bitops.h>
>> +#include <linux/io.h>
>> +#include <linux/sizes.h>
>> +
>> +#define BANK_INCREMENT 4
>> +#define NR_BANKS 8
>> +
>> +struct socfpga_reset_data {
>> + void __iomem *membase;
>> +};
>> +
>> +static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
>> +{
>> + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
>> + int id = reset_ctl->id;
>> + int reg_width = sizeof(u32);
>> + int bank = id / (reg_width * BITS_PER_BYTE);
>> + int offset = id % (reg_width * BITS_PER_BYTE);
>> + unsigned long flags;
>> + u32 reg;
>> +
>> + reg = readl(data->membase + (bank * BANK_INCREMENT));
>> + writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
>
> setbits_le32() ?
>
Ok..
>> + return 0;
>> +}
>> +
>> +static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
>> +{
>> + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
>> + int id = reset_ctl->id;
>> + int reg_width = sizeof(u32);
>> + int bank = id / (reg_width * BITS_PER_BYTE);
>> + int offset = id % (reg_width * BITS_PER_BYTE);
>> + unsigned long flags;
>> + u32 reg;
>> +
>> + reg = readl(data->membase + (bank * BANK_INCREMENT));
>> + writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
>
> clrbits_le32() ?
>
Ok..
> [...]
>
> What I do not see is any user of this code, nor any conversion of
> existing systems to use this code. Is that expected to happen ? I do not
> want to see dead code piling up in U-Boot.
>
I have a patchset that tested this code, the i2c support in SoCFPGA was
converted to DM, and uses this reset framework. Should I send that along
with this patch in v2?
Dinh
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform
2018-04-03 14:04 ` Dinh Nguyen
@ 2018-04-03 14:07 ` Marek Vasut
2018-04-03 14:43 ` Dinh Nguyen
0 siblings, 1 reply; 6+ messages in thread
From: Marek Vasut @ 2018-04-03 14:07 UTC (permalink / raw)
To: u-boot
On 04/03/2018 04:04 PM, Dinh Nguyen wrote:
>
>
> On 03/30/2018 02:45 PM, Marek Vasut wrote:
>> On 03/30/2018 06:53 PM, Dinh Nguyen wrote:
>>> Add a DM compatible reset driver for the SoCFPGA platform.
>>>
>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>> ---
>>> drivers/reset/Kconfig | 7 +++
>>> drivers/reset/Makefile | 1 +
>>> drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 119 insertions(+)
>>> create mode 100644 drivers/reset/reset-socfpga.c
>>>
>>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>>> index 3964b9e..90b021f 100644
>>> --- a/drivers/reset/Kconfig
>>> +++ b/drivers/reset/Kconfig
>>> @@ -83,4 +83,11 @@ config RESET_ROCKCHIP
>>> though is that some reset signals, like I2C or MISC reset multiple
>>> devices.
>>>
>>> +config RESET_SOCFPGA
>>> + bool "Reset controller driver for SoCFPGA"
>>> + depends on DM_RESET && ARCH_SOCFPGA
>>> + default y
>>> + help
>>> + Support for reset controller on SoCFPGA platform.
>>> +
>>> endmenu
>>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>>> index 7d7e080..6f791ee 100644
>>> --- a/drivers/reset/Makefile
>>> +++ b/drivers/reset/Makefile
>>> @@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
>>> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>>> obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
>>> obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
>>> +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
>>> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
>>> new file mode 100644
>>> index 0000000..af585ec
>>> --- /dev/null
>>> +++ b/drivers/reset/reset-socfpga.c
>>> @@ -0,0 +1,111 @@
>>> +/*
>>> + * Socfpga Reset Controller Driver
>>> + *
>>> + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
>>> + *
>>> + * based on
>>> + * Allwinner SoCs Reset Controller driver
>>> + *
>>> + * Copyright 2013 Maxime Ripard
>>> + *
>>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <dm.h>
>>> +#include <dm/of_access.h>
>>> +#include <reset-uclass.h>
>>> +#include <linux/bitops.h>
>>> +#include <linux/io.h>
>>> +#include <linux/sizes.h>
>>> +
>>> +#define BANK_INCREMENT 4
>>> +#define NR_BANKS 8
>>> +
>>> +struct socfpga_reset_data {
>>> + void __iomem *membase;
>>> +};
>>> +
>>> +static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
>>> +{
>>> + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
>>> + int id = reset_ctl->id;
>>> + int reg_width = sizeof(u32);
>>> + int bank = id / (reg_width * BITS_PER_BYTE);
>>> + int offset = id % (reg_width * BITS_PER_BYTE);
>>> + unsigned long flags;
>>> + u32 reg;
>>> +
>>> + reg = readl(data->membase + (bank * BANK_INCREMENT));
>>> + writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
>>
>> setbits_le32() ?
>>
>
> Ok..
>
>>> + return 0;
>>> +}
>>> +
>>> +static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
>>> +{
>>> + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
>>> + int id = reset_ctl->id;
>>> + int reg_width = sizeof(u32);
>>> + int bank = id / (reg_width * BITS_PER_BYTE);
>>> + int offset = id % (reg_width * BITS_PER_BYTE);
>>> + unsigned long flags;
>>> + u32 reg;
>>> +
>>> + reg = readl(data->membase + (bank * BANK_INCREMENT));
>>> + writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
>>
>> clrbits_le32() ?
>>
>
> Ok..
>
>> [...]
>>
>> What I do not see is any user of this code, nor any conversion of
>> existing systems to use this code. Is that expected to happen ? I do not
>> want to see dead code piling up in U-Boot.
>>
>
> I have a patchset that tested this code, the i2c support in SoCFPGA was
> converted to DM, and uses this reset framework. Should I send that along
> with this patch in v2?
Yes please, otherwise this will be just another dead code.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform
2018-04-03 14:07 ` Marek Vasut
@ 2018-04-03 14:43 ` Dinh Nguyen
2018-04-03 17:33 ` Marek Vasut
0 siblings, 1 reply; 6+ messages in thread
From: Dinh Nguyen @ 2018-04-03 14:43 UTC (permalink / raw)
To: u-boot
On 04/03/2018 09:07 AM, Marek Vasut wrote:
[...]
>
>>
>> I have a patchset that tested this code, the i2c support in SoCFPGA was
>> converted to DM, and uses this reset framework. Should I send that along
>> with this patch in v2?
>
> Yes please, otherwise this will be just another dead code.
>
Ok will do! A question: ideally I'd like to have the Stratix10 SPL use
the reset manager framework, so I'd not have to add a another platform
specific reset_manager_s10. Would that be possible? I think it is, but
wanted to confirm.
Thanks,
Dinh
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform
2018-04-03 14:43 ` Dinh Nguyen
@ 2018-04-03 17:33 ` Marek Vasut
0 siblings, 0 replies; 6+ messages in thread
From: Marek Vasut @ 2018-04-03 17:33 UTC (permalink / raw)
To: u-boot
On 04/03/2018 04:43 PM, Dinh Nguyen wrote:
>
>
> On 04/03/2018 09:07 AM, Marek Vasut wrote:
>
> [...]
>>
>>>
>>> I have a patchset that tested this code, the i2c support in SoCFPGA was
>>> converted to DM, and uses this reset framework. Should I send that along
>>> with this patch in v2?
>>
>> Yes please, otherwise this will be just another dead code.
>>
>
> Ok will do! A question: ideally I'd like to have the Stratix10 SPL use
> the reset manager framework,
Awesome
> so I'd not have to add a another platform
> specific reset_manager_s10. Would that be possible? I think it is, but
> wanted to confirm.
I think so, the reset handling on socfpga looks trivial.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-04-03 17:33 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-30 16:53 [U-Boot] [PATCH] reset: socfpga: add reset driver for SoCFPGA platform Dinh Nguyen
2018-03-30 19:45 ` Marek Vasut
2018-04-03 14:04 ` Dinh Nguyen
2018-04-03 14:07 ` Marek Vasut
2018-04-03 14:43 ` Dinh Nguyen
2018-04-03 17:33 ` Marek Vasut
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