* [Qemu-devel] [RFC PATCH v4 0/1] SPARC64: add icount support
@ 2018-06-15 7:33 Mark Cave-Ayland
2018-06-15 7:33 ` [Qemu-devel] [RFC PATCH v4 1/1] " Mark Cave-Ayland
0 siblings, 1 reply; 4+ messages in thread
From: Mark Cave-Ayland @ 2018-06-15 7:33 UTC (permalink / raw)
To: qemu-devel, atar4qemu, richard.henderson, cota
This is a patch I've had in an earlier form for a while but never really developed
due to experiencing random hangs when writing to the SPARC64 CPU timers.
Fortunately it seems the recent icount timer fixes have resolved the underlying
issues and with this patch I am able to boot all my qemu-system-sparc64 OpenBIOS
test images.
I've marked this as an RFC for two reasons: firstly I'm not sure I've fully covered
all the cases where we need to exit the TB in order to allow the timer interrupt to
fire, and secondly I do occasionally see messages booting Milax in the form of
"WARNING: Time of Day clock error: reason [Jumped by 0x134]".
Hopefully more sets of eyes will be able to point me in the right direction related
to the Time of Day (m48t59) error and the TB exits in order to get this ready for
commit.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
v4:
- Convert sparc_tr_tb_stop() to use switch for DisasJumpType as suggested by Richard
v3:
- Implement feedback from Richard: use tb_cflags() for icount flag access,
unconditionally exit the TB when setting the timer registers, introduce DISAS_EXIT
to avoid repeating TB exit code pattern
v2:
- Rebase onto master
Mark Cave-Ayland (1):
SPARC64: add icount support
target/sparc/translate.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 110 insertions(+), 1 deletion(-)
--
2.11.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Qemu-devel] [RFC PATCH v4 1/1] SPARC64: add icount support
2018-06-15 7:33 [Qemu-devel] [RFC PATCH v4 0/1] SPARC64: add icount support Mark Cave-Ayland
@ 2018-06-15 7:33 ` Mark Cave-Ayland
2018-06-15 7:49 ` Artyom Tarasenko
2018-06-17 5:43 ` Richard Henderson
0 siblings, 2 replies; 4+ messages in thread
From: Mark Cave-Ayland @ 2018-06-15 7:33 UTC (permalink / raw)
To: qemu-devel, atar4qemu, richard.henderson, cota
This patch adds gen_io_start()/gen_io_end() to various instructions as required
in order to boot my OpenBIOS test images on qemu-system-sparc64 with icount
enabled.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/sparc/translate.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 110 insertions(+), 1 deletion(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index f3d430c1b2..74315cdf09 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -41,6 +41,8 @@
#define JUMP_PC 2 /* dynamic pc value which takes only two values
according to jump_pc[T2] */
+#define DISAS_EXIT DISAS_TARGET_0
+
/* global register indexes */
static TCGv_ptr cpu_regwptr;
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
@@ -3400,11 +3402,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_const = tcg_const_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
r_const);
tcg_temp_free_ptr(r_tickptr);
tcg_temp_free_i32(r_const);
gen_store_gpr(dc, rd, cpu_dst);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
}
break;
case 0x5: /* V9 rdpc */
@@ -3447,11 +3455,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_const = tcg_const_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, stick));
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
r_const);
tcg_temp_free_ptr(r_tickptr);
tcg_temp_free_i32(r_const);
gen_store_gpr(dc, rd, cpu_dst);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
}
break;
case 0x19: /* System tick compare */
@@ -3576,10 +3590,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_const = tcg_const_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_get_count(cpu_tmp0, cpu_env,
r_tickptr, r_const);
tcg_temp_free_ptr(r_tickptr);
tcg_temp_free_i32(r_const);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
}
break;
case 5: // tba
@@ -4385,9 +4405,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_set_limit(r_tickptr,
cpu_tick_cmpr);
tcg_temp_free_ptr(r_tickptr);
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_end();
+ }
+ /* End TB to handle timer interrupt */
+ dc->base.is_jmp = DISAS_EXIT;
}
break;
case 0x18: /* System tick */
@@ -4403,9 +4433,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, stick));
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_set_count(r_tickptr,
cpu_tmp0);
tcg_temp_free_ptr(r_tickptr);
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_end();
+ }
+ /* End TB to handle timer interrupt */
+ dc->base.is_jmp = DISAS_EXIT;
}
break;
case 0x19: /* System tick compare */
@@ -4421,9 +4461,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, stick));
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_set_limit(r_tickptr,
cpu_stick_cmpr);
tcg_temp_free_ptr(r_tickptr);
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_end();
+ }
+ /* End TB to handle timer interrupt */
+ dc->base.is_jmp = DISAS_EXIT;
}
break;
@@ -4531,9 +4581,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_set_count(r_tickptr,
cpu_tmp0);
tcg_temp_free_ptr(r_tickptr);
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_end();
+ }
+ /* End TB to handle timer interrupt */
+ dc->base.is_jmp = DISAS_EXIT;
}
break;
case 5: // tba
@@ -4541,7 +4601,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 6: // pstate
save_state(dc);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_wrpstate(cpu_env, cpu_tmp0);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
dc->npc = DYNAMIC_PC;
break;
case 7: // tl
@@ -4551,7 +4617,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
dc->npc = DYNAMIC_PC;
break;
case 8: // pil
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_wrpil(cpu_env, cpu_tmp0);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
break;
case 9: // cwp
gen_helper_wrcwp(cpu_env, cpu_tmp0);
@@ -4642,9 +4714,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, hstick));
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_tick_set_limit(r_tickptr,
cpu_hstick_cmpr);
tcg_temp_free_ptr(r_tickptr);
+ if (tb_cflags(dc->base.tb) &
+ CF_USE_ICOUNT) {
+ gen_io_end();
+ }
+ /* End TB to handle timer interrupt */
+ dc->base.is_jmp = DISAS_EXIT;
}
break;
case 6: // hver readonly
@@ -5265,14 +5347,26 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto priv_insn;
dc->npc = DYNAMIC_PC;
dc->pc = DYNAMIC_PC;
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_done(cpu_env);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
goto jmp_insn;
case 1:
if (!supervisor(dc))
goto priv_insn;
dc->npc = DYNAMIC_PC;
dc->pc = DYNAMIC_PC;
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_retry(cpu_env);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
goto jmp_insn;
default:
goto illegal_insn;
@@ -5822,7 +5916,9 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- if (dc->base.is_jmp != DISAS_NORETURN) {
+ switch (dc->base.is_jmp) {
+ case DISAS_NEXT:
+ case DISAS_TOO_MANY:
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
@@ -5834,6 +5930,19 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
save_npc(dc);
tcg_gen_exit_tb(NULL, 0);
}
+ break;
+
+ case DISAS_NORETURN:
+ break;
+
+ case DISAS_EXIT:
+ /* Exit TB */
+ save_state(dc);
+ tcg_gen_exit_tb(NULL, 0);
+ break;
+
+ default:
+ g_assert_not_reached();
}
}
--
2.11.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [RFC PATCH v4 1/1] SPARC64: add icount support
2018-06-15 7:33 ` [Qemu-devel] [RFC PATCH v4 1/1] " Mark Cave-Ayland
@ 2018-06-15 7:49 ` Artyom Tarasenko
2018-06-17 5:43 ` Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Artyom Tarasenko @ 2018-06-15 7:49 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: qemu-devel, richard.henderson, Emilio G. Cota
On Fri, Jun 15, 2018 at 9:33 AM, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
> This patch adds gen_io_start()/gen_io_end() to various instructions as required
> in order to boot my OpenBIOS test images on qemu-system-sparc64 with icount
> enabled.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
It's really good to have icount support for SPARC64. Good job, Mark!
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
> target/sparc/translate.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 110 insertions(+), 1 deletion(-)
>
> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
> index f3d430c1b2..74315cdf09 100644
> --- a/target/sparc/translate.c
> +++ b/target/sparc/translate.c
> @@ -41,6 +41,8 @@
> #define JUMP_PC 2 /* dynamic pc value which takes only two values
> according to jump_pc[T2] */
>
> +#define DISAS_EXIT DISAS_TARGET_0
> +
> /* global register indexes */
> static TCGv_ptr cpu_regwptr;
> static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
> @@ -3400,11 +3402,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_const = tcg_const_i32(dc->mem_idx);
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, tick));
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
> r_const);
> tcg_temp_free_ptr(r_tickptr);
> tcg_temp_free_i32(r_const);
> gen_store_gpr(dc, rd, cpu_dst);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> }
> break;
> case 0x5: /* V9 rdpc */
> @@ -3447,11 +3455,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_const = tcg_const_i32(dc->mem_idx);
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, stick));
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
> r_const);
> tcg_temp_free_ptr(r_tickptr);
> tcg_temp_free_i32(r_const);
> gen_store_gpr(dc, rd, cpu_dst);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> }
> break;
> case 0x19: /* System tick compare */
> @@ -3576,10 +3590,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_const = tcg_const_i32(dc->mem_idx);
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, tick));
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_get_count(cpu_tmp0, cpu_env,
> r_tickptr, r_const);
> tcg_temp_free_ptr(r_tickptr);
> tcg_temp_free_i32(r_const);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> }
> break;
> case 5: // tba
> @@ -4385,9 +4405,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_tickptr = tcg_temp_new_ptr();
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, tick));
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_set_limit(r_tickptr,
> cpu_tick_cmpr);
> tcg_temp_free_ptr(r_tickptr);
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> + /* End TB to handle timer interrupt */
> + dc->base.is_jmp = DISAS_EXIT;
> }
> break;
> case 0x18: /* System tick */
> @@ -4403,9 +4433,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_tickptr = tcg_temp_new_ptr();
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, stick));
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_set_count(r_tickptr,
> cpu_tmp0);
> tcg_temp_free_ptr(r_tickptr);
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> + /* End TB to handle timer interrupt */
> + dc->base.is_jmp = DISAS_EXIT;
> }
> break;
> case 0x19: /* System tick compare */
> @@ -4421,9 +4461,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_tickptr = tcg_temp_new_ptr();
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, stick));
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_set_limit(r_tickptr,
> cpu_stick_cmpr);
> tcg_temp_free_ptr(r_tickptr);
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> + /* End TB to handle timer interrupt */
> + dc->base.is_jmp = DISAS_EXIT;
> }
> break;
>
> @@ -4531,9 +4581,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_tickptr = tcg_temp_new_ptr();
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, tick));
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_set_count(r_tickptr,
> cpu_tmp0);
> tcg_temp_free_ptr(r_tickptr);
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> + /* End TB to handle timer interrupt */
> + dc->base.is_jmp = DISAS_EXIT;
> }
> break;
> case 5: // tba
> @@ -4541,7 +4601,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> break;
> case 6: // pstate
> save_state(dc);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_wrpstate(cpu_env, cpu_tmp0);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> dc->npc = DYNAMIC_PC;
> break;
> case 7: // tl
> @@ -4551,7 +4617,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> dc->npc = DYNAMIC_PC;
> break;
> case 8: // pil
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_wrpil(cpu_env, cpu_tmp0);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> break;
> case 9: // cwp
> gen_helper_wrcwp(cpu_env, cpu_tmp0);
> @@ -4642,9 +4714,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> r_tickptr = tcg_temp_new_ptr();
> tcg_gen_ld_ptr(r_tickptr, cpu_env,
> offsetof(CPUSPARCState, hstick));
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_tick_set_limit(r_tickptr,
> cpu_hstick_cmpr);
> tcg_temp_free_ptr(r_tickptr);
> + if (tb_cflags(dc->base.tb) &
> + CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> + /* End TB to handle timer interrupt */
> + dc->base.is_jmp = DISAS_EXIT;
> }
> break;
> case 6: // hver readonly
> @@ -5265,14 +5347,26 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> goto priv_insn;
> dc->npc = DYNAMIC_PC;
> dc->pc = DYNAMIC_PC;
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_done(cpu_env);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> goto jmp_insn;
> case 1:
> if (!supervisor(dc))
> goto priv_insn;
> dc->npc = DYNAMIC_PC;
> dc->pc = DYNAMIC_PC;
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_retry(cpu_env);
> + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + }
> goto jmp_insn;
> default:
> goto illegal_insn;
> @@ -5822,7 +5916,9 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *dc = container_of(dcbase, DisasContext, base);
>
> - if (dc->base.is_jmp != DISAS_NORETURN) {
> + switch (dc->base.is_jmp) {
> + case DISAS_NEXT:
> + case DISAS_TOO_MANY:
> if (dc->pc != DYNAMIC_PC &&
> (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
> /* static PC and NPC: we can use direct chaining */
> @@ -5834,6 +5930,19 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> save_npc(dc);
> tcg_gen_exit_tb(NULL, 0);
> }
> + break;
> +
> + case DISAS_NORETURN:
> + break;
> +
> + case DISAS_EXIT:
> + /* Exit TB */
> + save_state(dc);
> + tcg_gen_exit_tb(NULL, 0);
> + break;
> +
> + default:
> + g_assert_not_reached();
> }
> }
>
> --
> 2.11.0
>
--
Regards,
Artyom Tarasenko
SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [RFC PATCH v4 1/1] SPARC64: add icount support
2018-06-15 7:33 ` [Qemu-devel] [RFC PATCH v4 1/1] " Mark Cave-Ayland
2018-06-15 7:49 ` Artyom Tarasenko
@ 2018-06-17 5:43 ` Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2018-06-17 5:43 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, atar4qemu, cota
On 06/14/2018 09:33 PM, Mark Cave-Ayland wrote:
> This patch adds gen_io_start()/gen_io_end() to various instructions as required
> in order to boot my OpenBIOS test images on qemu-system-sparc64 with icount
> enabled.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> target/sparc/translate.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 110 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-06-17 5:43 UTC | newest]
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-- links below jump to the message on this page --
2018-06-15 7:33 [Qemu-devel] [RFC PATCH v4 0/1] SPARC64: add icount support Mark Cave-Ayland
2018-06-15 7:33 ` [Qemu-devel] [RFC PATCH v4 1/1] " Mark Cave-Ayland
2018-06-15 7:49 ` Artyom Tarasenko
2018-06-17 5:43 ` Richard Henderson
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