[PATCH 00/13] add support for more devices on Meson8 and Meson8b

[PATCH 00/13] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an
  error when trying to initialize one of the USB2 PHYs, but we have the
  same problem on some GXBB boards. it is working fine for me - on a board
  which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to
  have two 32-bit hardware random number generator registers, while the
  GX SoCs only have one. This is not handled by the meson-rng driver yet,
  but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory
  (currently only on Meson8 until I have a Meson8b device to test if the
  same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
  the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the
  SDIO clocks (a driver for this MMC controller is work-in-progress) as
  well as the corresponding pin definitions in meson8.dtsi
- this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
  SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
  LED) pins to meson8.dtsi

NOTE: the .dts changes from this series depend on my previous patch from
[0]: "ARM: dts: meson8: fix the IR receiver pins"


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html


Martin Blumenstingl (13):
  clk: meson8b: export the SAR ADC clocks
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the USB clocks
  clk: meson8b: export the ethernet gate clock
  ARM: dts: meson8: add the PWM_E and PWM_F pins
  ARM: dts: meson8: add the pins for the SDIO controller
  ARM: dts: meson: add the SAR ADC
  ARM: dts: meson8: add reserved memory zones
  ARM: dts: meson: add the hardware random number generator
  ARM: dts: meson: add USB support on Meson8 and Meson8b
  ARM: dts: meson8b: add the SCU device node
  ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

 arch/arm/boot/dts/meson.dtsi             |  51 +++++++++++++++
 arch/arm/boot/dts/meson8.dtsi            | 109 ++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/meson8b.dtsi           |  49 ++++++++++++++
 drivers/clk/meson/meson8b.h              |  20 +++---
 include/dt-bindings/clock/meson8b-clkc.h |  10 +++
 5 files changed, 228 insertions(+), 11 deletions(-)

-- 
2.13.1

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[PATCH 00/13] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an
  error when trying to initialize one of the USB2 PHYs, but we have the
  same problem on some GXBB boards. it is working fine for me - on a board
  which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to
  have two 32-bit hardware random number generator registers, while the
  GX SoCs only have one. This is not handled by the meson-rng driver yet,
  but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory
  (currently only on Meson8 until I have a Meson8b device to test if the
  same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
  the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the
  SDIO clocks (a driver for this MMC controller is work-in-progress) as
  well as the corresponding pin definitions in meson8.dtsi
- this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
  SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
  LED) pins to meson8.dtsi

NOTE: the .dts changes from this series depend on my previous patch from
[0]: "ARM: dts: meson8: fix the IR receiver pins"


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html


Martin Blumenstingl (13):
  clk: meson8b: export the SAR ADC clocks
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the USB clocks
  clk: meson8b: export the ethernet gate clock
  ARM: dts: meson8: add the PWM_E and PWM_F pins
  ARM: dts: meson8: add the pins for the SDIO controller
  ARM: dts: meson: add the SAR ADC
  ARM: dts: meson8: add reserved memory zones
  ARM: dts: meson: add the hardware random number generator
  ARM: dts: meson: add USB support on Meson8 and Meson8b
  ARM: dts: meson8b: add the SCU device node
  ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

 arch/arm/boot/dts/meson.dtsi             |  51 +++++++++++++++
 arch/arm/boot/dts/meson8.dtsi            | 109 ++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/meson8b.dtsi           |  49 ++++++++++++++
 drivers/clk/meson/meson8b.h              |  20 +++---
 include/dt-bindings/clock/meson8b-clkc.h |  10 +++
 5 files changed, 228 insertions(+), 11 deletions(-)

-- 
2.13.1

[PATCH 01/13] clk: meson8b: export the SAR ADC clocks

[Martin Blumenstingl]

Export the clocks for the SAR ADC so they can be used in the
dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/clk/meson/meson8b.h              | 4 ++--
 include/dt-bindings/clock/meson8b-clkc.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 3881defc8644..5447d4a5c9ba 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -87,7 +87,7 @@
 #define CLKID_PERIPHS		20
 #define CLKID_SPICC		21
 #define CLKID_I2C		22
-#define CLKID_SAR_ADC		23
+/* #define CLKID_SAR_ADC */
 #define CLKID_SMART_CARD	24
 #define CLKID_RNG0		25
 #define CLKID_UART0		26
@@ -133,7 +133,7 @@
 #define CLKID_MMC_PCLK		66
 #define CLKID_DVIN		67
 #define CLKID_UART2		68
-#define CLKID_SANA		69
+/* #define CLKID_SANA */
 #define CLKID_VPU_INTR		70
 #define CLKID_SEC_AHB_AHB3_BRIDGE	71
 #define CLKID_CLK81_A9		72
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index a55ff8c9b30f..1c7f090da440 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -21,5 +21,7 @@
 #define CLKID_ZERO		13
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
+#define CLKID_SAR_ADC		23
+#define CLKID_SANA		69
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.13.1

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[PATCH 01/13] clk: meson8b: export the SAR ADC clocks

[Martin Blumenstingl]

Export the clocks for the SAR ADC so they can be used in the
dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/meson8b.h              | 4 ++--
 include/dt-bindings/clock/meson8b-clkc.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 3881defc8644..5447d4a5c9ba 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -87,7 +87,7 @@
 #define CLKID_PERIPHS		20
 #define CLKID_SPICC		21
 #define CLKID_I2C		22
-#define CLKID_SAR_ADC		23
+/* #define CLKID_SAR_ADC */
 #define CLKID_SMART_CARD	24
 #define CLKID_RNG0		25
 #define CLKID_UART0		26
@@ -133,7 +133,7 @@
 #define CLKID_MMC_PCLK		66
 #define CLKID_DVIN		67
 #define CLKID_UART2		68
-#define CLKID_SANA		69
+/* #define CLKID_SANA */
 #define CLKID_VPU_INTR		70
 #define CLKID_SEC_AHB_AHB3_BRIDGE	71
 #define CLKID_CLK81_A9		72
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index a55ff8c9b30f..1c7f090da440 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -21,5 +21,7 @@
 #define CLKID_ZERO		13
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
+#define CLKID_SAR_ADC		23
+#define CLKID_SANA		69
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.13.1

[PATCH 02/13] clk: meson8b: export the SDIO clock

[Martin Blumenstingl]

Export the SDIO clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/clk/meson/meson8b.h              | 2 +-
 include/dt-bindings/clock/meson8b-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 5447d4a5c9ba..e0fb386ccc23 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -94,7 +94,7 @@
 #define CLKID_SDHC		27
 #define CLKID_STREAM		28
 #define CLKID_ASYNC_FIFO	29
-#define CLKID_SDIO		30
+/* #define CLKID_SDIO */
 #define CLKID_ABUF		31
 #define CLKID_HIU_IFACE		32
 #define CLKID_ASSIST_MISC	33
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 1c7f090da440..821b08574900 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -22,6 +22,7 @@
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
 #define CLKID_SAR_ADC		23
+#define CLKID_SDIO		30
 #define CLKID_SANA		69
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.13.1

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[PATCH 02/13] clk: meson8b: export the SDIO clock

[Martin Blumenstingl]

Export the SDIO clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/meson8b.h              | 2 +-
 include/dt-bindings/clock/meson8b-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 5447d4a5c9ba..e0fb386ccc23 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -94,7 +94,7 @@
 #define CLKID_SDHC		27
 #define CLKID_STREAM		28
 #define CLKID_ASYNC_FIFO	29
-#define CLKID_SDIO		30
+/* #define CLKID_SDIO */
 #define CLKID_ABUF		31
 #define CLKID_HIU_IFACE		32
 #define CLKID_ASSIST_MISC	33
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 1c7f090da440..821b08574900 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -22,6 +22,7 @@
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
 #define CLKID_SAR_ADC		23
+#define CLKID_SDIO		30
 #define CLKID_SANA		69
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.13.1

[PATCH 03/13] clk: meson8b: export the gate clock for the HW random number generator

[Martin Blumenstingl]

This exports the clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/clk/meson/meson8b.h              | 2 +-
 include/dt-bindings/clock/meson8b-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index e0fb386ccc23..51c3f6717180 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -89,7 +89,7 @@
 #define CLKID_I2C		22
 /* #define CLKID_SAR_ADC */
 #define CLKID_SMART_CARD	24
-#define CLKID_RNG0		25
+/* #define CLKID_RNG0 */
 #define CLKID_UART0		26
 #define CLKID_SDHC		27
 #define CLKID_STREAM		28
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 821b08574900..f004e6760b5d 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -22,6 +22,7 @@
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
 #define CLKID_SAR_ADC		23
+#define CLKID_RNG0		25
 #define CLKID_SDIO		30
 #define CLKID_SANA		69
 
-- 
2.13.1

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[PATCH 03/13] clk: meson8b: export the gate clock for the HW random number generator

[Martin Blumenstingl]

This exports the clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/meson8b.h              | 2 +-
 include/dt-bindings/clock/meson8b-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index e0fb386ccc23..51c3f6717180 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -89,7 +89,7 @@
 #define CLKID_I2C		22
 /* #define CLKID_SAR_ADC */
 #define CLKID_SMART_CARD	24
-#define CLKID_RNG0		25
+/* #define CLKID_RNG0 */
 #define CLKID_UART0		26
 #define CLKID_SDHC		27
 #define CLKID_STREAM		28
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 821b08574900..f004e6760b5d 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -22,6 +22,7 @@
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
 #define CLKID_SAR_ADC		23
+#define CLKID_RNG0		25
 #define CLKID_SDIO		30
 #define CLKID_SANA		69
 
-- 
2.13.1

[PATCH 04/13] clk: meson8b: export the USB clocks

[Martin Blumenstingl]

Export the USB related clocks (for the USB controller and the USB2 PHYs)
so they can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/clk/meson/meson8b.h              | 10 +++++-----
 include/dt-bindings/clock/meson8b-clkc.h |  5 +++++
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 51c3f6717180..17479c60864d 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -114,12 +114,12 @@
 #define CLKID_AIU		47
 #define CLKID_UART1		48
 #define CLKID_G2D		49
-#define CLKID_USB0		50
-#define CLKID_USB1		51
+/* #define CLKID_USB0 */
+/* #define CLKID_USB1 */
 #define CLKID_RESET		52
 #define CLKID_NAND		53
 #define CLKID_DOS_PARSER	54
-#define CLKID_USB		55
+/* #define CLKID_USB */
 #define CLKID_VDIN1		56
 #define CLKID_AHB_ARB0		57
 #define CLKID_EFUSE		58
@@ -128,8 +128,8 @@
 #define CLKID_AHB_CTRL_BUS	61
 #define CLKID_HDMI_INTR_SYNC	62
 #define CLKID_HDMI_PCLK		63
-#define CLKID_USB1_DDR_BRIDGE	64
-#define CLKID_USB0_DDR_BRIDGE	65
+/* CLKID_USB1_DDR_BRIDGE */
+/* CLKID_USB0_DDR_BRIDGE */
 #define CLKID_MMC_PCLK		66
 #define CLKID_DVIN		67
 #define CLKID_UART2		68
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index f004e6760b5d..04f0d1fcd308 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -24,6 +24,11 @@
 #define CLKID_SAR_ADC		23
 #define CLKID_RNG0		25
 #define CLKID_SDIO		30
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_USB		55
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
 #define CLKID_SANA		69
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.13.1

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[PATCH 04/13] clk: meson8b: export the USB clocks

[Martin Blumenstingl]

Export the USB related clocks (for the USB controller and the USB2 PHYs)
so they can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/meson8b.h              | 10 +++++-----
 include/dt-bindings/clock/meson8b-clkc.h |  5 +++++
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 51c3f6717180..17479c60864d 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -114,12 +114,12 @@
 #define CLKID_AIU		47
 #define CLKID_UART1		48
 #define CLKID_G2D		49
-#define CLKID_USB0		50
-#define CLKID_USB1		51
+/* #define CLKID_USB0 */
+/* #define CLKID_USB1 */
 #define CLKID_RESET		52
 #define CLKID_NAND		53
 #define CLKID_DOS_PARSER	54
-#define CLKID_USB		55
+/* #define CLKID_USB */
 #define CLKID_VDIN1		56
 #define CLKID_AHB_ARB0		57
 #define CLKID_EFUSE		58
@@ -128,8 +128,8 @@
 #define CLKID_AHB_CTRL_BUS	61
 #define CLKID_HDMI_INTR_SYNC	62
 #define CLKID_HDMI_PCLK		63
-#define CLKID_USB1_DDR_BRIDGE	64
-#define CLKID_USB0_DDR_BRIDGE	65
+/* CLKID_USB1_DDR_BRIDGE */
+/* CLKID_USB0_DDR_BRIDGE */
 #define CLKID_MMC_PCLK		66
 #define CLKID_DVIN		67
 #define CLKID_UART2		68
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index f004e6760b5d..04f0d1fcd308 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -24,6 +24,11 @@
 #define CLKID_SAR_ADC		23
 #define CLKID_RNG0		25
 #define CLKID_SDIO		30
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_USB		55
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
 #define CLKID_SANA		69
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.13.1

[PATCH 05/13] clk: meson8b: export the ethernet gate clock

[Martin Blumenstingl]

Export the ethernet gate clock to the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/clk/meson/meson8b.h              | 2 +-
 include/dt-bindings/clock/meson8b-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 17479c60864d..a687e02547dc 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -100,7 +100,7 @@
 #define CLKID_ASSIST_MISC	33
 #define CLKID_SPI		34
 #define CLKID_I2S_SPDIF		35
-#define CLKID_ETH		36
+/* #define CLKID_ETH */
 #define CLKID_DEMUX		37
 #define CLKID_AIU_GLUE		38
 #define CLKID_IEC958		39
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 04f0d1fcd308..e29227fb52a1 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -24,6 +24,7 @@
 #define CLKID_SAR_ADC		23
 #define CLKID_RNG0		25
 #define CLKID_SDIO		30
+#define CLKID_ETH		36
 #define CLKID_USB0		50
 #define CLKID_USB1		51
 #define CLKID_USB		55
-- 
2.13.1

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[PATCH 05/13] clk: meson8b: export the ethernet gate clock

[Martin Blumenstingl]

Export the ethernet gate clock to the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/meson8b.h              | 2 +-
 include/dt-bindings/clock/meson8b-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 17479c60864d..a687e02547dc 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -100,7 +100,7 @@
 #define CLKID_ASSIST_MISC	33
 #define CLKID_SPI		34
 #define CLKID_I2S_SPDIF		35
-#define CLKID_ETH		36
+/* #define CLKID_ETH */
 #define CLKID_DEMUX		37
 #define CLKID_AIU_GLUE		38
 #define CLKID_IEC958		39
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 04f0d1fcd308..e29227fb52a1 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -24,6 +24,7 @@
 #define CLKID_SAR_ADC		23
 #define CLKID_RNG0		25
 #define CLKID_SDIO		30
+#define CLKID_ETH		36
 #define CLKID_USB0		50
 #define CLKID_USB1		51
 #define CLKID_USB		55
-- 
2.13.1

[PATCH 06/13] ARM: dts: meson8: add the PWM_E and PWM_F pins

[Martin Blumenstingl]

This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to
meson8.dtsi, allowing devices to use them. PWM_E can be used on some
devices to generate the 32.768kHz clock for the SDIO wifi module, while
PWM_F can be used to control the power LED.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index e4f7357b4b31..93e437c91c61 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -123,6 +123,13 @@
 				function = "remote";
 			};
 		};
+
+		pwm_f_ao_pins: pwm-f-ao {
+			mux {
+				groups = "pwm_f_ao";
+				function = "pwm_f_ao";
+			};
+		};
 	};
 };
 
@@ -168,6 +175,13 @@
 				function = "ethernet";
 			};
 		};
+
+		pwm_e_pins: pwm-e {
+			mux {
+				groups = "pwm_e";
+				function = "pwm_e";
+			};
+		};
 	};
 };
 
-- 
2.13.1

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[PATCH 06/13] ARM: dts: meson8: add the PWM_E and PWM_F pins

[Martin Blumenstingl]

This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to
meson8.dtsi, allowing devices to use them. PWM_E can be used on some
devices to generate the 32.768kHz clock for the SDIO wifi module, while
PWM_F can be used to control the power LED.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index e4f7357b4b31..93e437c91c61 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -123,6 +123,13 @@
 				function = "remote";
 			};
 		};
+
+		pwm_f_ao_pins: pwm-f-ao {
+			mux {
+				groups = "pwm_f_ao";
+				function = "pwm_f_ao";
+			};
+		};
 	};
 };
 
@@ -168,6 +175,13 @@
 				function = "ethernet";
 			};
 		};
+
+		pwm_e_pins: pwm-e {
+			mux {
+				groups = "pwm_e";
+				function = "pwm_e";
+			};
+		};
 	};
 };
 
-- 
2.13.1

[PATCH 07/13] ARM: dts: meson8: add the pins for the SDIO controller

[Martin Blumenstingl]

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 93e437c91c61..1bbfc04c3f10 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -158,6 +158,30 @@
 			gpio-ranges = <&pinctrl_cbus 0 0 120>;
 		};
 
+		sd_a_pins: sd-a {
+			mux {
+				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
+					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
+				function = "sd_a";
+			};
+		};
+
+		sd_b_pins: sd-b {
+			mux {
+				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
+				function = "sd_b";
+			};
+		};
+
+		sd_c_pins: sd-c {
+			mux {
+				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
+					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
+				function = "sd_c";
+			};
+		};
+
 		spi_nor_pins: nor {
 			mux {
 				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
-- 
2.13.1

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[PATCH 07/13] ARM: dts: meson8: add the pins for the SDIO controller

[Martin Blumenstingl]

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 93e437c91c61..1bbfc04c3f10 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -158,6 +158,30 @@
 			gpio-ranges = <&pinctrl_cbus 0 0 120>;
 		};
 
+		sd_a_pins: sd-a {
+			mux {
+				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
+					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
+				function = "sd_a";
+			};
+		};
+
+		sd_b_pins: sd-b {
+			mux {
+				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
+				function = "sd_b";
+			};
+		};
+
+		sd_c_pins: sd-c {
+			mux {
+				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
+					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
+				function = "sd_c";
+			};
+		};
+
 		spi_nor_pins: nor {
 			mux {
 				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
-- 
2.13.1

[PATCH 08/13] ARM: dts: meson: add the SAR ADC

[Martin Blumenstingl]

This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson.dtsi   | 8 ++++++++
 arch/arm/boot/dts/meson8.dtsi  | 8 ++++++++
 arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 8d9c36970dfd..b05796bee088 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -101,6 +101,14 @@
 				status = "disabled";
 			};
 
+			saradc: adc@8680 {
+				compatible = "amlogic,meson-saradc";
+				reg = <0x8680 0x34>;
+				#io-channel-cells = <1>;
+				interrupts = <0 73 1>;
+				status = "disabled";
+			};
+
 			uart_C: serial@8700 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x8700 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 1bbfc04c3f10..8582490fcb52 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -232,6 +232,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &spifc {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index d9f116a418b2..1c09090ff4a5 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -177,6 +177,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &uart_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.1

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[PATCH 08/13] ARM: dts: meson: add the SAR ADC

[Martin Blumenstingl]

This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi   | 8 ++++++++
 arch/arm/boot/dts/meson8.dtsi  | 8 ++++++++
 arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 8d9c36970dfd..b05796bee088 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -101,6 +101,14 @@
 				status = "disabled";
 			};
 
+			saradc: adc at 8680 {
+				compatible = "amlogic,meson-saradc";
+				reg = <0x8680 0x34>;
+				#io-channel-cells = <1>;
+				interrupts = <0 73 1>;
+				status = "disabled";
+			};
+
 			uart_C: serial at 8700 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x8700 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 1bbfc04c3f10..8582490fcb52 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -232,6 +232,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &spifc {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index d9f116a418b2..1c09090ff4a5 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -177,6 +177,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &uart_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.1

[PATCH 09/13] ARM: dts: meson8: add reserved memory zones

[Martin Blumenstingl]

There seem to be two memory regions that need to be reserved, otherwise
the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
  --vm-keep -m 1

The first memory region is really crucial and without it the system
hangs. I could not find any references to this in Amlogic's GPL kernel
sources.
The second region is used by the "suspend firmware". The u-boot sources
(/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
the Amlogic GPL kernel sources. The "suspend firmware" is responsible
for waking up the system from suspend state.

This also fixes reading the full SD card as without this the system
would simply hang (probably related to the first memory region, if some
buffer is allocated there).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 8582490fcb52..cf011dfe050e 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -83,6 +83,33 @@
 			reg = <0x203>;
 		};
 	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* 2 MiB reserved for Hardware ROM Firmware? */
+		hwrom_reserved: hwrom@0 {
+			reg = <0x0 0x200000>;
+			no-map;
+		};
+
+		/*
+		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
+		 * code which is responsible for system suspend. It loads a
+		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
+		 * into SRAM, executes that and shuts down the (last) ARM core.
+		 * The arc_power firmware then checks various wakeup sources
+		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
+		 * simply the power key) and re-starts the ARM core once it
+		 * detects a wakeup request.
+		 */
+		suspend_firmware: secmon@4f00000 {
+			reg = <0x4f00000 0x100000>;
+			no-map;
+		};
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

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[PATCH 09/13] ARM: dts: meson8: add reserved memory zones

[Martin Blumenstingl]

There seem to be two memory regions that need to be reserved, otherwise
the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
  --vm-keep -m 1

The first memory region is really crucial and without it the system
hangs. I could not find any references to this in Amlogic's GPL kernel
sources.
The second region is used by the "suspend firmware". The u-boot sources
(/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
the Amlogic GPL kernel sources. The "suspend firmware" is responsible
for waking up the system from suspend state.

This also fixes reading the full SD card as without this the system
would simply hang (probably related to the first memory region, if some
buffer is allocated there).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 8582490fcb52..cf011dfe050e 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -83,6 +83,33 @@
 			reg = <0x203>;
 		};
 	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* 2 MiB reserved for Hardware ROM Firmware? */
+		hwrom_reserved: hwrom at 0 {
+			reg = <0x0 0x200000>;
+			no-map;
+		};
+
+		/*
+		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
+		 * code which is responsible for system suspend. It loads a
+		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
+		 * into SRAM, executes that and shuts down the (last) ARM core.
+		 * The arc_power firmware then checks various wakeup sources
+		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
+		 * simply the power key) and re-starts the ARM core once it
+		 * detects a wakeup request.
+		 */
+		suspend_firmware: secmon at 4f00000 {
+			reg = <0x4f00000 0x100000>;
+			no-map;
+		};
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

[PATCH 10/13] ARM: dts: meson: add the hardware random number generator

[Martin Blumenstingl]

All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson.dtsi   | 5 +++++
 arch/arm/boot/dts/meson8.dtsi  | 5 +++++
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index b05796bee088..a210084398dc 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -78,6 +78,11 @@
 			#size-cells = <1>;
 			ranges = <0x0 0xc1100000 0x200000>;
 
+			hwrng: rng@8100 {
+				compatible = "amlogic,meson-rng";
+				reg = <0x8100 0x8>;
+			};
+
 			uart_A: serial@84c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84c0 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index cf011dfe050e..a80181ddd416 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -241,6 +241,11 @@
 	clock-names = "stmmaceth";
 };
 
+&hwrng {
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &i2c_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 1c09090ff4a5..52aa3f68a6bd 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -171,6 +171,11 @@
 	};
 };
 
+&hwrng {
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &L2 {
 	arm,data-latency = <3 3 3>;
 	arm,tag-latency = <2 2 2>;
-- 
2.13.1

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[PATCH 10/13] ARM: dts: meson: add the hardware random number generator

[Martin Blumenstingl]

All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi   | 5 +++++
 arch/arm/boot/dts/meson8.dtsi  | 5 +++++
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index b05796bee088..a210084398dc 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -78,6 +78,11 @@
 			#size-cells = <1>;
 			ranges = <0x0 0xc1100000 0x200000>;
 
+			hwrng: rng at 8100 {
+				compatible = "amlogic,meson-rng";
+				reg = <0x8100 0x8>;
+			};
+
 			uart_A: serial at 84c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84c0 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index cf011dfe050e..a80181ddd416 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -241,6 +241,11 @@
 	clock-names = "stmmaceth";
 };
 
+&hwrng {
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &i2c_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 1c09090ff4a5..52aa3f68a6bd 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -171,6 +171,11 @@
 	};
 };
 
+&hwrng {
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &L2 {
 	arm,data-latency = <3 3 3>;
 	arm,tag-latency = <2 2 2>;
-- 
2.13.1

[PATCH 11/13] ARM: dts: meson: add USB support on Meson8 and Meson8b

[Martin Blumenstingl]

This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
nodes to meson.dtsi (as the same - or at least a very similar) IP block
is used on all SoCs (at the same physical address).
Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
initialized by the dwc2 driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson.dtsi   | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/meson8.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++
 3 files changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index a210084398dc..1a7a72005954 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -130,6 +130,20 @@
 				status = "disabled";
 			};
 
+			usb0_phy: phy@8800 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8800 0x20>;
+				status = "disabled";
+			};
+
+			usb1_phy: phy@8820 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8820 0x20>;
+				status = "disabled";
+			};
+
 			spifc: spi@8c80 {
 				compatible = "amlogic,meson6-spifc";
 				reg = <0x8c80 0x80>;
@@ -182,6 +196,30 @@
 			};
 		};
 
+		usb0: usb@c9040000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc9040000 0x40000>;
+			interrupts = <0 30 1>;
+			phys = <&usb0_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
+		usb1: usb@c90c0000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc90c0000 0x40000>;
+			interrupts = <0 31 1>;
+			phys = <&usb1_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
 		ethmac: ethernet@c9410000 {
 			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 			reg = <0xc9410000 0x10000
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index a80181ddd416..7bfce6d8d0af 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -291,3 +291,27 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 52aa3f68a6bd..aa4664713b66 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -205,3 +205,29 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
-- 
2.13.1

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[PATCH 11/13] ARM: dts: meson: add USB support on Meson8 and Meson8b

[Martin Blumenstingl]

This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
nodes to meson.dtsi (as the same - or at least a very similar) IP block
is used on all SoCs (at the same physical address).
Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
initialized by the dwc2 driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi   | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/meson8.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++
 3 files changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index a210084398dc..1a7a72005954 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -130,6 +130,20 @@
 				status = "disabled";
 			};
 
+			usb0_phy: phy at 8800 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8800 0x20>;
+				status = "disabled";
+			};
+
+			usb1_phy: phy at 8820 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8820 0x20>;
+				status = "disabled";
+			};
+
 			spifc: spi at 8c80 {
 				compatible = "amlogic,meson6-spifc";
 				reg = <0x8c80 0x80>;
@@ -182,6 +196,30 @@
 			};
 		};
 
+		usb0: usb at c9040000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc9040000 0x40000>;
+			interrupts = <0 30 1>;
+			phys = <&usb0_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
+		usb1: usb at c90c0000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc90c0000 0x40000>;
+			interrupts = <0 31 1>;
+			phys = <&usb1_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
 		ethmac: ethernet at c9410000 {
 			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 			reg = <0xc9410000 0x10000
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index a80181ddd416..7bfce6d8d0af 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -291,3 +291,27 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 52aa3f68a6bd..aa4664713b66 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -205,3 +205,29 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
-- 
2.13.1

[PATCH 12/13] ARM: dts: meson8b: add the SCU device node

[Martin Blumenstingl]

Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
used during SMP boot.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi  | 5 +++++
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 7bfce6d8d0af..f6816ea09aeb 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -110,6 +110,11 @@
 			no-map;
 		};
 	};
+
+	scu@c4300000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index aa4664713b66..2b13570b0e60 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -82,6 +82,11 @@
 			reg = <0x203>;
 		};
 	};
+
+	scu@c4300000 {
+		compatible = "arm,cortex-a5-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

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[PATCH 12/13] ARM: dts: meson8b: add the SCU device node

[Martin Blumenstingl]

Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
used during SMP boot.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi  | 5 +++++
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 7bfce6d8d0af..f6816ea09aeb 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -110,6 +110,11 @@
 			no-map;
 		};
 	};
+
+	scu at c4300000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index aa4664713b66..2b13570b0e60 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -82,6 +82,11 @@
 			reg = <0x203>;
 		};
 	};
+
+	scu at c4300000 {
+		compatible = "arm,cortex-a5-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

[PATCH 13/13] ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

[Martin Blumenstingl]

Until now clk81 was used as gate clock for the ethernet controller on
Meson8 whereas Meson8b did not configure a gate clock at all. Use
CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi  | 2 +-
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index f6816ea09aeb..d997185896b7 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -242,7 +242,7 @@
 };
 
 &ethmac {
-	clocks = <&clkc CLKID_CLK81>;
+	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
 };
 
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 2b13570b0e60..e57934f82098 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -176,6 +176,11 @@
 	};
 };
 
+&ethmac {
+	clocks = <&clkc CLKID_ETH>;
+	clock-names = "stmmaceth";
+};
+
 &hwrng {
 	clocks = <&clkc CLKID_RNG0>;
 	clock-names = "core";
-- 
2.13.1

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[PATCH 13/13] ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

[Martin Blumenstingl]

Until now clk81 was used as gate clock for the ethernet controller on
Meson8 whereas Meson8b did not configure a gate clock at all. Use
CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi  | 2 +-
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index f6816ea09aeb..d997185896b7 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -242,7 +242,7 @@
 };
 
 &ethmac {
-	clocks = <&clkc CLKID_CLK81>;
+	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
 };
 
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 2b13570b0e60..e57934f82098 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -176,6 +176,11 @@
 	};
 };
 
+&ethmac {
+	clocks = <&clkc CLKID_ETH>;
+	clock-names = "stmmaceth";
+};
+
 &hwrng {
 	clocks = <&clkc CLKID_RNG0>;
 	clock-names = "core";
-- 
2.13.1

Re: [PATCH 01/13] clk: meson8b: export the SAR ADC clocks

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the clocks for the SAR ADC so they can be used in the
> dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  drivers/clk/meson/meson8b.h              | 4 ++--
>  include/dt-bindings/clock/meson8b-clkc.h | 2 ++
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 3881defc8644..5447d4a5c9ba 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -87,7 +87,7 @@
>  #define CLKID_PERIPHS		20
>  #define CLKID_SPICC		21
>  #define CLKID_I2C		22
> -#define CLKID_SAR_ADC		23
> +/* #define CLKID_SAR_ADC */
>  #define CLKID_SMART_CARD	24
>  #define CLKID_RNG0		25
>  #define CLKID_UART0		26
> @@ -133,7 +133,7 @@
>  #define CLKID_MMC_PCLK		66
>  #define CLKID_DVIN		67
>  #define CLKID_UART2		68
> -#define CLKID_SANA		69
> +/* #define CLKID_SANA */
>  #define CLKID_VPU_INTR		70
>  #define CLKID_SEC_AHB_AHB3_BRIDGE	71
>  #define CLKID_CLK81_A9		72
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index a55ff8c9b30f..1c7f090da440 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -21,5 +21,7 @@
>  #define CLKID_ZERO		13
>  #define CLKID_MPEG_SEL		14
>  #define CLKID_MPEG_DIV		15
> +#define CLKID_SAR_ADC		23
> +#define CLKID_SANA		69
>  
>  #endif /* __MESON8B_CLKC_H */
> 


Acked-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 01/13] clk: meson8b: export the SAR ADC clocks

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the clocks for the SAR ADC so they can be used in the
> dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/meson/meson8b.h              | 4 ++--
>  include/dt-bindings/clock/meson8b-clkc.h | 2 ++
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 3881defc8644..5447d4a5c9ba 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -87,7 +87,7 @@
>  #define CLKID_PERIPHS		20
>  #define CLKID_SPICC		21
>  #define CLKID_I2C		22
> -#define CLKID_SAR_ADC		23
> +/* #define CLKID_SAR_ADC */
>  #define CLKID_SMART_CARD	24
>  #define CLKID_RNG0		25
>  #define CLKID_UART0		26
> @@ -133,7 +133,7 @@
>  #define CLKID_MMC_PCLK		66
>  #define CLKID_DVIN		67
>  #define CLKID_UART2		68
> -#define CLKID_SANA		69
> +/* #define CLKID_SANA */
>  #define CLKID_VPU_INTR		70
>  #define CLKID_SEC_AHB_AHB3_BRIDGE	71
>  #define CLKID_CLK81_A9		72
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index a55ff8c9b30f..1c7f090da440 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -21,5 +21,7 @@
>  #define CLKID_ZERO		13
>  #define CLKID_MPEG_SEL		14
>  #define CLKID_MPEG_DIV		15
> +#define CLKID_SAR_ADC		23
> +#define CLKID_SANA		69
>  
>  #endif /* __MESON8B_CLKC_H */
> 


Acked-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 02/13] clk: meson8b: export the SDIO clock

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the SDIO clock so it can be used in the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  drivers/clk/meson/meson8b.h              | 2 +-
>  include/dt-bindings/clock/meson8b-clkc.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 5447d4a5c9ba..e0fb386ccc23 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -94,7 +94,7 @@
>  #define CLKID_SDHC		27
>  #define CLKID_STREAM		28
>  #define CLKID_ASYNC_FIFO	29
> -#define CLKID_SDIO		30
> +/* #define CLKID_SDIO */
>  #define CLKID_ABUF		31
>  #define CLKID_HIU_IFACE		32
>  #define CLKID_ASSIST_MISC	33
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index 1c7f090da440..821b08574900 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -22,6 +22,7 @@
>  #define CLKID_MPEG_SEL		14
>  #define CLKID_MPEG_DIV		15
>  #define CLKID_SAR_ADC		23
> +#define CLKID_SDIO		30
>  #define CLKID_SANA		69
>  
>  #endif /* __MESON8B_CLKC_H */
> 


Acked-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 02/13] clk: meson8b: export the SDIO clock

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the SDIO clock so it can be used in the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/meson/meson8b.h              | 2 +-
>  include/dt-bindings/clock/meson8b-clkc.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 5447d4a5c9ba..e0fb386ccc23 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -94,7 +94,7 @@
>  #define CLKID_SDHC		27
>  #define CLKID_STREAM		28
>  #define CLKID_ASYNC_FIFO	29
> -#define CLKID_SDIO		30
> +/* #define CLKID_SDIO */
>  #define CLKID_ABUF		31
>  #define CLKID_HIU_IFACE		32
>  #define CLKID_ASSIST_MISC	33
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index 1c7f090da440..821b08574900 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -22,6 +22,7 @@
>  #define CLKID_MPEG_SEL		14
>  #define CLKID_MPEG_DIV		15
>  #define CLKID_SAR_ADC		23
> +#define CLKID_SDIO		30
>  #define CLKID_SANA		69
>  
>  #endif /* __MESON8B_CLKC_H */
> 


Acked-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 03/13] clk: meson8b: export the gate clock for the HW random number generator

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This exports the clock so it can be used in the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  drivers/clk/meson/meson8b.h              | 2 +-
>  include/dt-bindings/clock/meson8b-clkc.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index e0fb386ccc23..51c3f6717180 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -89,7 +89,7 @@
>  #define CLKID_I2C		22
>  /* #define CLKID_SAR_ADC */
>  #define CLKID_SMART_CARD	24
> -#define CLKID_RNG0		25
> +/* #define CLKID_RNG0 */
>  #define CLKID_UART0		26
>  #define CLKID_SDHC		27
>  #define CLKID_STREAM		28
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index 821b08574900..f004e6760b5d 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -22,6 +22,7 @@
>  #define CLKID_MPEG_SEL		14
>  #define CLKID_MPEG_DIV		15
>  #define CLKID_SAR_ADC		23
> +#define CLKID_RNG0		25
>  #define CLKID_SDIO		30
>  #define CLKID_SANA		69
>  
> 


Acked-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 03/13] clk: meson8b: export the gate clock for the HW random number generator

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This exports the clock so it can be used in the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/meson/meson8b.h              | 2 +-
>  include/dt-bindings/clock/meson8b-clkc.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index e0fb386ccc23..51c3f6717180 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -89,7 +89,7 @@
>  #define CLKID_I2C		22
>  /* #define CLKID_SAR_ADC */
>  #define CLKID_SMART_CARD	24
> -#define CLKID_RNG0		25
> +/* #define CLKID_RNG0 */
>  #define CLKID_UART0		26
>  #define CLKID_SDHC		27
>  #define CLKID_STREAM		28
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index 821b08574900..f004e6760b5d 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -22,6 +22,7 @@
>  #define CLKID_MPEG_SEL		14
>  #define CLKID_MPEG_DIV		15
>  #define CLKID_SAR_ADC		23
> +#define CLKID_RNG0		25
>  #define CLKID_SDIO		30
>  #define CLKID_SANA		69
>  
> 


Acked-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 04/13] clk: meson8b: export the USB clocks

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the USB related clocks (for the USB controller and the USB2 PHYs)
> so they can be used in the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  drivers/clk/meson/meson8b.h              | 10 +++++-----
>  include/dt-bindings/clock/meson8b-clkc.h |  5 +++++
>  2 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 51c3f6717180..17479c60864d 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -114,12 +114,12 @@
>  #define CLKID_AIU		47
>  #define CLKID_UART1		48
>  #define CLKID_G2D		49
> -#define CLKID_USB0		50
> -#define CLKID_USB1		51
> +/* #define CLKID_USB0 */
> +/* #define CLKID_USB1 */
>  #define CLKID_RESET		52
>  #define CLKID_NAND		53
>  #define CLKID_DOS_PARSER	54
> -#define CLKID_USB		55
> +/* #define CLKID_USB */
>  #define CLKID_VDIN1		56
>  #define CLKID_AHB_ARB0		57
>  #define CLKID_EFUSE		58
> @@ -128,8 +128,8 @@
>  #define CLKID_AHB_CTRL_BUS	61
>  #define CLKID_HDMI_INTR_SYNC	62
>  #define CLKID_HDMI_PCLK		63
> -#define CLKID_USB1_DDR_BRIDGE	64
> -#define CLKID_USB0_DDR_BRIDGE	65
> +/* CLKID_USB1_DDR_BRIDGE */
> +/* CLKID_USB0_DDR_BRIDGE */
>  #define CLKID_MMC_PCLK		66
>  #define CLKID_DVIN		67
>  #define CLKID_UART2		68
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index f004e6760b5d..04f0d1fcd308 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -24,6 +24,11 @@
>  #define CLKID_SAR_ADC		23
>  #define CLKID_RNG0		25
>  #define CLKID_SDIO		30
> +#define CLKID_USB0		50
> +#define CLKID_USB1		51
> +#define CLKID_USB		55
> +#define CLKID_USB1_DDR_BRIDGE	64
> +#define CLKID_USB0_DDR_BRIDGE	65
>  #define CLKID_SANA		69
>  
>  #endif /* __MESON8B_CLKC_H */
> 


Acked-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 04/13] clk: meson8b: export the USB clocks

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the USB related clocks (for the USB controller and the USB2 PHYs)
> so they can be used in the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/meson/meson8b.h              | 10 +++++-----
>  include/dt-bindings/clock/meson8b-clkc.h |  5 +++++
>  2 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 51c3f6717180..17479c60864d 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -114,12 +114,12 @@
>  #define CLKID_AIU		47
>  #define CLKID_UART1		48
>  #define CLKID_G2D		49
> -#define CLKID_USB0		50
> -#define CLKID_USB1		51
> +/* #define CLKID_USB0 */
> +/* #define CLKID_USB1 */
>  #define CLKID_RESET		52
>  #define CLKID_NAND		53
>  #define CLKID_DOS_PARSER	54
> -#define CLKID_USB		55
> +/* #define CLKID_USB */
>  #define CLKID_VDIN1		56
>  #define CLKID_AHB_ARB0		57
>  #define CLKID_EFUSE		58
> @@ -128,8 +128,8 @@
>  #define CLKID_AHB_CTRL_BUS	61
>  #define CLKID_HDMI_INTR_SYNC	62
>  #define CLKID_HDMI_PCLK		63
> -#define CLKID_USB1_DDR_BRIDGE	64
> -#define CLKID_USB0_DDR_BRIDGE	65
> +/* CLKID_USB1_DDR_BRIDGE */
> +/* CLKID_USB0_DDR_BRIDGE */
>  #define CLKID_MMC_PCLK		66
>  #define CLKID_DVIN		67
>  #define CLKID_UART2		68
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index f004e6760b5d..04f0d1fcd308 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -24,6 +24,11 @@
>  #define CLKID_SAR_ADC		23
>  #define CLKID_RNG0		25
>  #define CLKID_SDIO		30
> +#define CLKID_USB0		50
> +#define CLKID_USB1		51
> +#define CLKID_USB		55
> +#define CLKID_USB1_DDR_BRIDGE	64
> +#define CLKID_USB0_DDR_BRIDGE	65
>  #define CLKID_SANA		69
>  
>  #endif /* __MESON8B_CLKC_H */
> 


Acked-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 05/13] clk: meson8b: export the ethernet gate clock

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the ethernet gate clock to the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  drivers/clk/meson/meson8b.h              | 2 +-
>  include/dt-bindings/clock/meson8b-clkc.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 17479c60864d..a687e02547dc 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -100,7 +100,7 @@
>  #define CLKID_ASSIST_MISC	33
>  #define CLKID_SPI		34
>  #define CLKID_I2S_SPDIF		35
> -#define CLKID_ETH		36
> +/* #define CLKID_ETH */
>  #define CLKID_DEMUX		37
>  #define CLKID_AIU_GLUE		38
>  #define CLKID_IEC958		39
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index 04f0d1fcd308..e29227fb52a1 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -24,6 +24,7 @@
>  #define CLKID_SAR_ADC		23
>  #define CLKID_RNG0		25
>  #define CLKID_SDIO		30
> +#define CLKID_ETH		36
>  #define CLKID_USB0		50
>  #define CLKID_USB1		51
>  #define CLKID_USB		55
> 


Acked-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 05/13] clk: meson8b: export the ethernet gate clock

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Export the ethernet gate clock to the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/meson/meson8b.h              | 2 +-
>  include/dt-bindings/clock/meson8b-clkc.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 17479c60864d..a687e02547dc 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -100,7 +100,7 @@
>  #define CLKID_ASSIST_MISC	33
>  #define CLKID_SPI		34
>  #define CLKID_I2S_SPDIF		35
> -#define CLKID_ETH		36
> +/* #define CLKID_ETH */
>  #define CLKID_DEMUX		37
>  #define CLKID_AIU_GLUE		38
>  #define CLKID_IEC958		39
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index 04f0d1fcd308..e29227fb52a1 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -24,6 +24,7 @@
>  #define CLKID_SAR_ADC		23
>  #define CLKID_RNG0		25
>  #define CLKID_SDIO		30
> +#define CLKID_ETH		36
>  #define CLKID_USB0		50
>  #define CLKID_USB1		51
>  #define CLKID_USB		55
> 


Acked-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 09/13] ARM: dts: meson8: add reserved memory zones

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> There seem to be two memory regions that need to be reserved, otherwise
> the system just hangs when running:
> $ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
>   --vm-keep -m 1
> 
> The first memory region is really crucial and without it the system
> hangs. I could not find any references to this in Amlogic's GPL kernel
> sources.
> The second region is used by the "suspend firmware". The u-boot sources
> (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
> firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
> the Amlogic GPL kernel sources. The "suspend firmware" is responsible
> for waking up the system from suspend state.
> 
> This also fixes reading the full SD card as without this the system
> would simply hang (probably related to the first memory region, if some
> buffer is allocated there).
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 8582490fcb52..cf011dfe050e 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -83,6 +83,33 @@
>  			reg = <0x203>;
>  		};
>  	};
> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		/* 2 MiB reserved for Hardware ROM Firmware? */
> +		hwrom_reserved: hwrom@0 {
> +			reg = <0x0 0x200000>;
> +			no-map;
> +		};
> +
> +		/*
> +		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
> +		 * code which is responsible for system suspend. It loads a
> +		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
> +		 * into SRAM, executes that and shuts down the (last) ARM core.
> +		 * The arc_power firmware then checks various wakeup sources
> +		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
> +		 * simply the power key) and re-starts the ARM core once it
> +		 * detects a wakeup request.
> +		 */
> +		suspend_firmware: secmon@4f00000 {
> +			reg = <0x4f00000 0x100000>;
> +			no-map;
> +		};
> +	};
>  }; /* end of / */
>  
>  &aobus {
> 

Good, but maybe you could add _reserved to the secmon alias.

Apart of that :
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 09/13] ARM: dts: meson8: add reserved memory zones

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> There seem to be two memory regions that need to be reserved, otherwise
> the system just hangs when running:
> $ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
>   --vm-keep -m 1
> 
> The first memory region is really crucial and without it the system
> hangs. I could not find any references to this in Amlogic's GPL kernel
> sources.
> The second region is used by the "suspend firmware". The u-boot sources
> (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
> firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
> the Amlogic GPL kernel sources. The "suspend firmware" is responsible
> for waking up the system from suspend state.
> 
> This also fixes reading the full SD card as without this the system
> would simply hang (probably related to the first memory region, if some
> buffer is allocated there).
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 8582490fcb52..cf011dfe050e 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -83,6 +83,33 @@
>  			reg = <0x203>;
>  		};
>  	};
> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		/* 2 MiB reserved for Hardware ROM Firmware? */
> +		hwrom_reserved: hwrom at 0 {
> +			reg = <0x0 0x200000>;
> +			no-map;
> +		};
> +
> +		/*
> +		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
> +		 * code which is responsible for system suspend. It loads a
> +		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
> +		 * into SRAM, executes that and shuts down the (last) ARM core.
> +		 * The arc_power firmware then checks various wakeup sources
> +		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
> +		 * simply the power key) and re-starts the ARM core once it
> +		 * detects a wakeup request.
> +		 */
> +		suspend_firmware: secmon at 4f00000 {
> +			reg = <0x4f00000 0x100000>;
> +			no-map;
> +		};
> +	};
>  }; /* end of / */
>  
>  &aobus {
> 

Good, but maybe you could add _reserved to the secmon alias.

Apart of that :
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 00/13] add support for more devices on Meson8 and Meson8b

[Jerome Brunet]

On Sun, 2017-06-11 at 12:16 +0200, Martin Blumenstingl wrote:
> This series adds:
> - USB support on Meson8 and Meson8b (it seems that some boards show an
>   error when trying to initialize one of the USB2 PHYs, but we have the
>   same problem on some GXBB boards. it is working fine for me - on a board
>   which is not supported upstream yet)
> - hardware random number generator support (Meson8 and Meson8b seem to
>   have two 32-bit hardware random number generator registers, while the
>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>   but that can still be improved later on)
> - SAR ADC support
> - add reserved memory zones to fix random hangs when filling the memory
>   (currently only on Meson8 until I have a Meson8b device to test if the
>   same problem appears there as well)
> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>   the bootloader does not enable the gate clock
> - add the SCU (Snoop Control Unit) which is needed for SMP support
> - minor preparations for further .dts updates as this already exports the
>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>   well as the corresponding pin definitions in meson8.dtsi
> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>   LED) pins to meson8.dtsi
> 
> NOTE: the .dts changes from this series depend on my previous patch from
> [0]: "ARM: dts: meson8: fix the IR receiver pins"
> 
> 
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
> 
> 
> Martin Blumenstingl (13):
>   clk: meson8b: export the SAR ADC clocks
>   clk: meson8b: export the SDIO clock
>   clk: meson8b: export the gate clock for the HW random number generator
>   clk: meson8b: export the USB clocks
>   clk: meson8b: export the ethernet gate clock

Applied these 5 clk patches to next/headers with Neil's Acks.

>   ARM: dts: meson8: add the PWM_E and PWM_F pins
>   ARM: dts: meson8: add the pins for the SDIO controller
>   ARM: dts: meson: add the SAR ADC
>   ARM: dts: meson8: add reserved memory zones
>   ARM: dts: meson: add the hardware random number generator
>   ARM: dts: meson: add USB support on Meson8 and Meson8b
>   ARM: dts: meson8b: add the SCU device node
>   ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
> 
>  arch/arm/boot/dts/meson.dtsi             |  51 +++++++++++++++
>  arch/arm/boot/dts/meson8.dtsi            | 109
> ++++++++++++++++++++++++++++++-
>  arch/arm/boot/dts/meson8b.dtsi           |  49 ++++++++++++++
>  drivers/clk/meson/meson8b.h              |  20 +++---
>  include/dt-bindings/clock/meson8b-clkc.h |  10 +++
>  5 files changed, 228 insertions(+), 11 deletions(-)
> 

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[PATCH 00/13] add support for more devices on Meson8 and Meson8b

[Jerome Brunet]

On Sun, 2017-06-11 at 12:16 +0200, Martin Blumenstingl wrote:
> This series adds:
> - USB support on Meson8 and Meson8b (it seems that some boards show an
> ? error when trying to initialize one of the USB2 PHYs, but we have the
> ? same problem on some GXBB boards. it is working fine for me - on a board
> ? which is not supported upstream yet)
> - hardware random number generator support (Meson8 and Meson8b seem to
> ? have two 32-bit hardware random number generator registers, while the
> ? GX SoCs only have one. This is not handled by the meson-rng driver yet,
> ? but that can still be improved later on)
> - SAR ADC support
> - add reserved memory zones to fix random hangs when filling the memory
> ? (currently only on Meson8 until I have a Meson8b device to test if the
> ? same problem appears there as well)
> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
> ? the bootloader does not enable the gate clock
> - add the SCU (Snoop Control Unit) which is needed for SMP support
> - minor preparations for further .dts updates as this already exports the
> ? SDIO clocks (a driver for this MMC controller is work-in-progress) as
> ? well as the corresponding pin definitions in meson8.dtsi
> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
> ? SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
> ? LED) pins to meson8.dtsi
> 
> NOTE: the .dts changes from this series depend on my previous patch from
> [0]: "ARM: dts: meson8: fix the IR receiver pins"
> 
> 
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
> 
> 
> Martin Blumenstingl (13):
> ? clk: meson8b: export the SAR ADC clocks
> ? clk: meson8b: export the SDIO clock
> ? clk: meson8b: export the gate clock for the HW random number generator
> ? clk: meson8b: export the USB clocks
> ? clk: meson8b: export the ethernet gate clock

Applied these 5 clk patches to next/headers with Neil's Acks.

> ? ARM: dts: meson8: add the PWM_E and PWM_F pins
> ? ARM: dts: meson8: add the pins for the SDIO controller
> ? ARM: dts: meson: add the SAR ADC
> ? ARM: dts: meson8: add reserved memory zones
> ? ARM: dts: meson: add the hardware random number generator
> ? ARM: dts: meson: add USB support on Meson8 and Meson8b
> ? ARM: dts: meson8b: add the SCU device node
> ? ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
> 
> ?arch/arm/boot/dts/meson.dtsi?????????????|??51 +++++++++++++++
> ?arch/arm/boot/dts/meson8.dtsi????????????| 109
> ++++++++++++++++++++++++++++++-
> ?arch/arm/boot/dts/meson8b.dtsi???????????|??49 ++++++++++++++
> ?drivers/clk/meson/meson8b.h??????????????|??20 +++---
> ?include/dt-bindings/clock/meson8b-clkc.h |??10 +++
> ?5 files changed, 228 insertions(+), 11 deletions(-)
> 

Re: [PATCH 06/13] ARM: dts: meson8: add the PWM_E and PWM_F pins

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to
> meson8.dtsi, allowing devices to use them. PWM_E can be used on some
> devices to generate the 32.768kHz clock for the SDIO wifi module, while
> PWM_F can be used to control the power LED.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index e4f7357b4b31..93e437c91c61 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -123,6 +123,13 @@
>  				function = "remote";
>  			};
>  		};
> +
> +		pwm_f_ao_pins: pwm-f-ao {
> +			mux {
> +				groups = "pwm_f_ao";
> +				function = "pwm_f_ao";
> +			};
> +		};
>  	};
>  };
>  
> @@ -168,6 +175,13 @@
>  				function = "ethernet";
>  			};
>  		};
> +
> +		pwm_e_pins: pwm-e {
> +			mux {
> +				groups = "pwm_e";
> +				function = "pwm_e";
> +			};
> +		};
>  	};
>  };
>  
> 

Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 06/13] ARM: dts: meson8: add the PWM_E and PWM_F pins

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to
> meson8.dtsi, allowing devices to use them. PWM_E can be used on some
> devices to generate the 32.768kHz clock for the SDIO wifi module, while
> PWM_F can be used to control the power LED.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index e4f7357b4b31..93e437c91c61 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -123,6 +123,13 @@
>  				function = "remote";
>  			};
>  		};
> +
> +		pwm_f_ao_pins: pwm-f-ao {
> +			mux {
> +				groups = "pwm_f_ao";
> +				function = "pwm_f_ao";
> +			};
> +		};
>  	};
>  };
>  
> @@ -168,6 +175,13 @@
>  				function = "ethernet";
>  			};
>  		};
> +
> +		pwm_e_pins: pwm-e {
> +			mux {
> +				groups = "pwm_e";
> +				function = "pwm_e";
> +			};
> +		};
>  	};
>  };
>  
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 07/13] ARM: dts: meson8: add the pins for the SDIO controller

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 93e437c91c61..1bbfc04c3f10 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -158,6 +158,30 @@
>  			gpio-ranges = <&pinctrl_cbus 0 0 120>;
>  		};
>  
> +		sd_a_pins: sd-a {
> +			mux {
> +				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
> +					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
> +				function = "sd_a";
> +			};
> +		};
> +
> +		sd_b_pins: sd-b {
> +			mux {
> +				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
> +					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
> +				function = "sd_b";
> +			};
> +		};
> +
> +		sd_c_pins: sd-c {
> +			mux {
> +				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
> +					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
> +				function = "sd_c";
> +			};
> +		};
> +
>  		spi_nor_pins: nor {
>  			mux {
>  				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
> 

Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 07/13] ARM: dts: meson8: add the pins for the SDIO controller

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 93e437c91c61..1bbfc04c3f10 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -158,6 +158,30 @@
>  			gpio-ranges = <&pinctrl_cbus 0 0 120>;
>  		};
>  
> +		sd_a_pins: sd-a {
> +			mux {
> +				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
> +					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
> +				function = "sd_a";
> +			};
> +		};
> +
> +		sd_b_pins: sd-b {
> +			mux {
> +				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
> +					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
> +				function = "sd_b";
> +			};
> +		};
> +
> +		sd_c_pins: sd-c {
> +			mux {
> +				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
> +					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
> +				function = "sd_c";
> +			};
> +		};
> +
>  		spi_nor_pins: nor {
>  			mux {
>  				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 08/13] ARM: dts: meson: add the SAR ADC

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
> and Meson8b to allow boards to use it. Some boards use it to connect a
> button to it.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson.dtsi   | 8 ++++++++
>  arch/arm/boot/dts/meson8.dtsi  | 8 ++++++++
>  arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
>  3 files changed, 24 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index 8d9c36970dfd..b05796bee088 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -101,6 +101,14 @@
>  				status = "disabled";
>  			};
>  
> +			saradc: adc@8680 {
> +				compatible = "amlogic,meson-saradc";
> +				reg = <0x8680 0x34>;
> +				#io-channel-cells = <1>;
> +				interrupts = <0 73 1>;

Can you use the correct GIC_ and IRQ_TYPE_ ... defines for the IRQ property ?

> +				status = "disabled";
> +			};
> +
>  			uart_C: serial@8700 {
>  				compatible = "amlogic,meson-uart";
>  				reg = <0x8700 0x18>;
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 1bbfc04c3f10..8582490fcb52 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -232,6 +232,14 @@
>  	arm,filter-ranges = <0x100000 0xc0000000>;
>  };
>  
> +&saradc {
> +	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
> +	clocks = <&clkc CLKID_XTAL>,
> +		<&clkc CLKID_SAR_ADC>,
> +		<&clkc CLKID_SANA>;
> +	clock-names = "clkin", "core", "sana";
> +};
> +
>  &spifc {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index d9f116a418b2..1c09090ff4a5 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -177,6 +177,14 @@
>  	arm,filter-ranges = <0x100000 0xc0000000>;
>  };
>  
> +&saradc {
> +	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
> +	clocks = <&clkc CLKID_XTAL>,
> +		<&clkc CLKID_SAR_ADC>,
> +		<&clkc CLKID_SANA>;
> +	clock-names = "clkin", "core", "sana";
> +};
> +
>  &uart_AO {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> 

Apart from that :
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 08/13] ARM: dts: meson: add the SAR ADC

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
> and Meson8b to allow boards to use it. Some boards use it to connect a
> button to it.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson.dtsi   | 8 ++++++++
>  arch/arm/boot/dts/meson8.dtsi  | 8 ++++++++
>  arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
>  3 files changed, 24 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index 8d9c36970dfd..b05796bee088 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -101,6 +101,14 @@
>  				status = "disabled";
>  			};
>  
> +			saradc: adc at 8680 {
> +				compatible = "amlogic,meson-saradc";
> +				reg = <0x8680 0x34>;
> +				#io-channel-cells = <1>;
> +				interrupts = <0 73 1>;

Can you use the correct GIC_ and IRQ_TYPE_ ... defines for the IRQ property ?

> +				status = "disabled";
> +			};
> +
>  			uart_C: serial at 8700 {
>  				compatible = "amlogic,meson-uart";
>  				reg = <0x8700 0x18>;
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 1bbfc04c3f10..8582490fcb52 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -232,6 +232,14 @@
>  	arm,filter-ranges = <0x100000 0xc0000000>;
>  };
>  
> +&saradc {
> +	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
> +	clocks = <&clkc CLKID_XTAL>,
> +		<&clkc CLKID_SAR_ADC>,
> +		<&clkc CLKID_SANA>;
> +	clock-names = "clkin", "core", "sana";
> +};
> +
>  &spifc {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index d9f116a418b2..1c09090ff4a5 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -177,6 +177,14 @@
>  	arm,filter-ranges = <0x100000 0xc0000000>;
>  };
>  
> +&saradc {
> +	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
> +	clocks = <&clkc CLKID_XTAL>,
> +		<&clkc CLKID_SAR_ADC>,
> +		<&clkc CLKID_SANA>;
> +	clock-names = "clkin", "core", "sana";
> +};
> +
>  &uart_AO {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> 

Apart from that :
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 10/13] ARM: dts: meson: add the hardware random number generator

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> All supported Meson SoCs have a random number generator in CBUS.
> Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
> register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
> 32-bit random number registers. The existing meson-rng driver only
> supports the lower 32-bit - but it still works fine on the older SoCs
> apart from this small limitation.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson.dtsi   | 5 +++++
>  arch/arm/boot/dts/meson8.dtsi  | 5 +++++
>  arch/arm/boot/dts/meson8b.dtsi | 5 +++++
>  3 files changed, 15 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index b05796bee088..a210084398dc 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -78,6 +78,11 @@
>  			#size-cells = <1>;
>  			ranges = <0x0 0xc1100000 0x200000>;
>  
> +			hwrng: rng@8100 {
> +				compatible = "amlogic,meson-rng";
> +				reg = <0x8100 0x8>;
> +			};
> +

Maybe you can add a "amlogic,mesonX-rng" before the "amlogic,meson-rng" here so you will
be able to support the different register layout and put the correct number in the meson8
and meson8b dtsi files.

>  			uart_A: serial@84c0 {
>  				compatible = "amlogic,meson-uart";
>  				reg = <0x84c0 0x18>;
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index cf011dfe050e..a80181ddd416 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -241,6 +241,11 @@
>  	clock-names = "stmmaceth";
>  };
>  
> +&hwrng {
> +	clocks = <&clkc CLKID_RNG0>;
> +	clock-names = "core";
> +};
> +
>  &i2c_AO {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 1c09090ff4a5..52aa3f68a6bd 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -171,6 +171,11 @@
>  	};
>  };
>  
> +&hwrng {
> +	clocks = <&clkc CLKID_RNG0>;
> +	clock-names = "core";
> +};
> +
>  &L2 {
>  	arm,data-latency = <3 3 3>;
>  	arm,tag-latency = <2 2 2>;
> 

Apart from that :
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH 10/13] ARM: dts: meson: add the hardware random number generator

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> All supported Meson SoCs have a random number generator in CBUS.
> Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
> register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
> 32-bit random number registers. The existing meson-rng driver only
> supports the lower 32-bit - but it still works fine on the older SoCs
> apart from this small limitation.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson.dtsi   | 5 +++++
>  arch/arm/boot/dts/meson8.dtsi  | 5 +++++
>  arch/arm/boot/dts/meson8b.dtsi | 5 +++++
>  3 files changed, 15 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index b05796bee088..a210084398dc 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -78,6 +78,11 @@
>  			#size-cells = <1>;
>  			ranges = <0x0 0xc1100000 0x200000>;
>  
> +			hwrng: rng at 8100 {
> +				compatible = "amlogic,meson-rng";
> +				reg = <0x8100 0x8>;
> +			};
> +

Maybe you can add a "amlogic,mesonX-rng" before the "amlogic,meson-rng" here so you will
be able to support the different register layout and put the correct number in the meson8
and meson8b dtsi files.

>  			uart_A: serial at 84c0 {
>  				compatible = "amlogic,meson-uart";
>  				reg = <0x84c0 0x18>;
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index cf011dfe050e..a80181ddd416 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -241,6 +241,11 @@
>  	clock-names = "stmmaceth";
>  };
>  
> +&hwrng {
> +	clocks = <&clkc CLKID_RNG0>;
> +	clock-names = "core";
> +};
> +
>  &i2c_AO {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 1c09090ff4a5..52aa3f68a6bd 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -171,6 +171,11 @@
>  	};
>  };
>  
> +&hwrng {
> +	clocks = <&clkc CLKID_RNG0>;
> +	clock-names = "core";
> +};
> +
>  &L2 {
>  	arm,data-latency = <3 3 3>;
>  	arm,tag-latency = <2 2 2>;
> 

Apart from that :
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 11/13] ARM: dts: meson: add USB support on Meson8 and Meson8b

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
> nodes to meson.dtsi (as the same - or at least a very similar) IP block
> is used on all SoCs (at the same physical address).
> Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
> DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
> initialized by the dwc2 driver.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson.dtsi   | 38 ++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/meson8.dtsi  | 24 ++++++++++++++++++++++++
>  arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++
>  3 files changed, 88 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index a210084398dc..1a7a72005954 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -130,6 +130,20 @@
>  				status = "disabled";
>  			};
>  
> +			usb0_phy: phy@8800 {
> +				compatible = "amlogic,meson-mx-usb2-phy";
> +				#phy-cells = <0>;
> +				reg = <0x8800 0x20>;
> +				status = "disabled";
> +			};
> +
> +			usb1_phy: phy@8820 {
> +				compatible = "amlogic,meson-mx-usb2-phy";
> +				#phy-cells = <0>;
> +				reg = <0x8820 0x20>;
> +				status = "disabled";
> +			};
> +
>  			spifc: spi@8c80 {
>  				compatible = "amlogic,meson6-spifc";
>  				reg = <0x8c80 0x80>;
> @@ -182,6 +196,30 @@
>  			};
>  		};
>  
> +		usb0: usb@c9040000 {
> +			compatible = "snps,dwc2";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xc9040000 0x40000>;
> +			interrupts = <0 30 1>;

Same as patch 8

> +			phys = <&usb0_phy>;
> +			phy-names = "usb2-phy";
> +			dr_mode = "host";
> +			status = "disabled";
> +		};
> +
> +		usb1: usb@c90c0000 {
> +			compatible = "snps,dwc2";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xc90c0000 0x40000>;
> +			interrupts = <0 31 1>;

Same as patch 8

> +			phys = <&usb1_phy>;
> +			phy-names = "usb2-phy";
> +			dr_mode = "host";
> +			status = "disabled";
> +		};
> +
>  		ethmac: ethernet@c9410000 {
>  			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
>  			reg = <0xc9410000 0x10000
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index a80181ddd416..7bfce6d8d0af 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -291,3 +291,27 @@
>  &uart_C {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> +
> +&usb0 {
> +	compatible = "amlogic,meson8-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb1 {
> +	compatible = "amlogic,meson8-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb0_phy {
> +	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
> +	clock-names = "usb_general", "usb";
> +};
> +
> +&usb1_phy {
> +	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
> +	clock-names = "usb_general", "usb";
> +};
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 52aa3f68a6bd..aa4664713b66 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -205,3 +205,29 @@
>  &uart_C {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> +
> +&usb0 {
> +	compatible = "amlogic,meson8b-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb1 {
> +	compatible = "amlogic,meson8b-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb0_phy {
> +	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
> +	clock-names = "usb_general", "usb";
> +	resets = <&reset RESET_USB_OTG>;
> +};
> +
> +&usb1_phy {
> +	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
> +	clock-names = "usb_general", "usb";
> +	resets = <&reset RESET_USB_OTG>;
> +};
> 

Apart from that :
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH 11/13] ARM: dts: meson: add USB support on Meson8 and Meson8b

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
> nodes to meson.dtsi (as the same - or at least a very similar) IP block
> is used on all SoCs (at the same physical address).
> Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
> DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
> initialized by the dwc2 driver.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson.dtsi   | 38 ++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/meson8.dtsi  | 24 ++++++++++++++++++++++++
>  arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++
>  3 files changed, 88 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index a210084398dc..1a7a72005954 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -130,6 +130,20 @@
>  				status = "disabled";
>  			};
>  
> +			usb0_phy: phy at 8800 {
> +				compatible = "amlogic,meson-mx-usb2-phy";
> +				#phy-cells = <0>;
> +				reg = <0x8800 0x20>;
> +				status = "disabled";
> +			};
> +
> +			usb1_phy: phy at 8820 {
> +				compatible = "amlogic,meson-mx-usb2-phy";
> +				#phy-cells = <0>;
> +				reg = <0x8820 0x20>;
> +				status = "disabled";
> +			};
> +
>  			spifc: spi at 8c80 {
>  				compatible = "amlogic,meson6-spifc";
>  				reg = <0x8c80 0x80>;
> @@ -182,6 +196,30 @@
>  			};
>  		};
>  
> +		usb0: usb at c9040000 {
> +			compatible = "snps,dwc2";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xc9040000 0x40000>;
> +			interrupts = <0 30 1>;

Same as patch 8

> +			phys = <&usb0_phy>;
> +			phy-names = "usb2-phy";
> +			dr_mode = "host";
> +			status = "disabled";
> +		};
> +
> +		usb1: usb at c90c0000 {
> +			compatible = "snps,dwc2";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xc90c0000 0x40000>;
> +			interrupts = <0 31 1>;

Same as patch 8

> +			phys = <&usb1_phy>;
> +			phy-names = "usb2-phy";
> +			dr_mode = "host";
> +			status = "disabled";
> +		};
> +
>  		ethmac: ethernet at c9410000 {
>  			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
>  			reg = <0xc9410000 0x10000
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index a80181ddd416..7bfce6d8d0af 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -291,3 +291,27 @@
>  &uart_C {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> +
> +&usb0 {
> +	compatible = "amlogic,meson8-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb1 {
> +	compatible = "amlogic,meson8-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb0_phy {
> +	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
> +	clock-names = "usb_general", "usb";
> +};
> +
> +&usb1_phy {
> +	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
> +	clock-names = "usb_general", "usb";
> +};
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 52aa3f68a6bd..aa4664713b66 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -205,3 +205,29 @@
>  &uart_C {
>  	clocks = <&clkc CLKID_CLK81>;
>  };
> +
> +&usb0 {
> +	compatible = "amlogic,meson8b-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb1 {
> +	compatible = "amlogic,meson8b-usb", "snps,dwc2";
> +	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
> +	clock-names = "otg";
> +};
> +
> +&usb0_phy {
> +	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
> +	clock-names = "usb_general", "usb";
> +	resets = <&reset RESET_USB_OTG>;
> +};
> +
> +&usb1_phy {
> +	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
> +	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
> +	clock-names = "usb_general", "usb";
> +	resets = <&reset RESET_USB_OTG>;
> +};
> 

Apart from that :
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 12/13] ARM: dts: meson8b: add the SCU device node

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
> other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
> used during SMP boot.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson8.dtsi  | 5 +++++
>  arch/arm/boot/dts/meson8b.dtsi | 5 +++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 7bfce6d8d0af..f6816ea09aeb 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -110,6 +110,11 @@
>  			no-map;
>  		};
>  	};
> +
> +	scu@c4300000 {
> +		compatible = "arm,cortex-a9-scu";
> +		reg = <0xc4300000 0x100>;
> +	};
>  }; /* end of / */
>  
>  &aobus {
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index aa4664713b66..2b13570b0e60 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -82,6 +82,11 @@
>  			reg = <0x203>;
>  		};
>  	};
> +
> +	scu@c4300000 {
> +		compatible = "arm,cortex-a5-scu";
> +		reg = <0xc4300000 0x100>;
> +	};
>  }; /* end of / */
>  
>  &aobus {
> 

Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 12/13] ARM: dts: meson8b: add the SCU device node

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
> other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
> used during SMP boot.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8.dtsi  | 5 +++++
>  arch/arm/boot/dts/meson8b.dtsi | 5 +++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 7bfce6d8d0af..f6816ea09aeb 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -110,6 +110,11 @@
>  			no-map;
>  		};
>  	};
> +
> +	scu at c4300000 {
> +		compatible = "arm,cortex-a9-scu";
> +		reg = <0xc4300000 0x100>;
> +	};
>  }; /* end of / */
>  
>  &aobus {
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index aa4664713b66..2b13570b0e60 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -82,6 +82,11 @@
>  			reg = <0x203>;
>  		};
>  	};
> +
> +	scu at c4300000 {
> +		compatible = "arm,cortex-a5-scu";
> +		reg = <0xc4300000 0x100>;
> +	};
>  }; /* end of / */
>  
>  &aobus {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 13/13] ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Until now clk81 was used as gate clock for the ethernet controller on
> Meson8 whereas Meson8b did not configure a gate clock at all. Use
> CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
> controller.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson8.dtsi  | 2 +-
>  arch/arm/boot/dts/meson8b.dtsi | 5 +++++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index f6816ea09aeb..d997185896b7 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -242,7 +242,7 @@
>  };
>  
>  &ethmac {
> -	clocks = <&clkc CLKID_CLK81>;
> +	clocks = <&clkc CLKID_ETH>;
>  	clock-names = "stmmaceth";
>  };
>  
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 2b13570b0e60..e57934f82098 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -176,6 +176,11 @@
>  	};
>  };
>  
> +&ethmac {
> +	clocks = <&clkc CLKID_ETH>;
> +	clock-names = "stmmaceth";
> +};
> +
>  &hwrng {
>  	clocks = <&clkc CLKID_RNG0>;
>  	clock-names = "core";
> 

Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH 13/13] ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

[Neil Armstrong]

On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
> Until now clk81 was used as gate clock for the ethernet controller on
> Meson8 whereas Meson8b did not configure a gate clock at all. Use
> CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
> controller.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8.dtsi  | 2 +-
>  arch/arm/boot/dts/meson8b.dtsi | 5 +++++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index f6816ea09aeb..d997185896b7 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -242,7 +242,7 @@
>  };
>  
>  &ethmac {
> -	clocks = <&clkc CLKID_CLK81>;
> +	clocks = <&clkc CLKID_ETH>;
>  	clock-names = "stmmaceth";
>  };
>  
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 2b13570b0e60..e57934f82098 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -176,6 +176,11 @@
>  	};
>  };
>  
> +&ethmac {
> +	clocks = <&clkc CLKID_ETH>;
> +	clock-names = "stmmaceth";
> +};
> +
>  &hwrng {
>  	clocks = <&clkc CLKID_RNG0>;
>  	clock-names = "core";
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 00/13] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

Hi Jerome,

On Mon, Jun 12, 2017 at 9:32 AM, Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
> On Sun, 2017-06-11 at 12:16 +0200, Martin Blumenstingl wrote:
>> This series adds:
>> - USB support on Meson8 and Meson8b (it seems that some boards show an
>>   error when trying to initialize one of the USB2 PHYs, but we have the
>>   same problem on some GXBB boards. it is working fine for me - on a board
>>   which is not supported upstream yet)
>> - hardware random number generator support (Meson8 and Meson8b seem to
>>   have two 32-bit hardware random number generator registers, while the
>>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>>   but that can still be improved later on)
>> - SAR ADC support
>> - add reserved memory zones to fix random hangs when filling the memory
>>   (currently only on Meson8 until I have a Meson8b device to test if the
>>   same problem appears there as well)
>> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>>   the bootloader does not enable the gate clock
>> - add the SCU (Snoop Control Unit) which is needed for SMP support
>> - minor preparations for further .dts updates as this already exports the
>>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>>   well as the corresponding pin definitions in meson8.dtsi
>> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>>   LED) pins to meson8.dtsi
>>
>> NOTE: the .dts changes from this series depend on my previous patch from
>> [0]: "ARM: dts: meson8: fix the IR receiver pins"
>>
>>
>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
>>
>>
>> Martin Blumenstingl (13):
>>   clk: meson8b: export the SAR ADC clocks
>>   clk: meson8b: export the SDIO clock
>>   clk: meson8b: export the gate clock for the HW random number generator
>>   clk: meson8b: export the USB clocks
>>   clk: meson8b: export the ethernet gate clock
>
> Applied these 5 clk patches to next/headers with Neil's Acks.
thank you!

>>   ARM: dts: meson8: add the PWM_E and PWM_F pins
>>   ARM: dts: meson8: add the pins for the SDIO controller
>>   ARM: dts: meson: add the SAR ADC
>>   ARM: dts: meson8: add reserved memory zones
>>   ARM: dts: meson: add the hardware random number generator
>>   ARM: dts: meson: add USB support on Meson8 and Meson8b
>>   ARM: dts: meson8b: add the SCU device node
>>   ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
I will send a v2 (which will address Neil's comments on these) soon

>>  arch/arm/boot/dts/meson.dtsi             |  51 +++++++++++++++
>>  arch/arm/boot/dts/meson8.dtsi            | 109
>> ++++++++++++++++++++++++++++++-
>>  arch/arm/boot/dts/meson8b.dtsi           |  49 ++++++++++++++
>>  drivers/clk/meson/meson8b.h              |  20 +++---
>>  include/dt-bindings/clock/meson8b-clkc.h |  10 +++
>>  5 files changed, 228 insertions(+), 11 deletions(-)
>>
>
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[PATCH 00/13] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

Hi Jerome,

On Mon, Jun 12, 2017 at 9:32 AM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun, 2017-06-11 at 12:16 +0200, Martin Blumenstingl wrote:
>> This series adds:
>> - USB support on Meson8 and Meson8b (it seems that some boards show an
>>   error when trying to initialize one of the USB2 PHYs, but we have the
>>   same problem on some GXBB boards. it is working fine for me - on a board
>>   which is not supported upstream yet)
>> - hardware random number generator support (Meson8 and Meson8b seem to
>>   have two 32-bit hardware random number generator registers, while the
>>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>>   but that can still be improved later on)
>> - SAR ADC support
>> - add reserved memory zones to fix random hangs when filling the memory
>>   (currently only on Meson8 until I have a Meson8b device to test if the
>>   same problem appears there as well)
>> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>>   the bootloader does not enable the gate clock
>> - add the SCU (Snoop Control Unit) which is needed for SMP support
>> - minor preparations for further .dts updates as this already exports the
>>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>>   well as the corresponding pin definitions in meson8.dtsi
>> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>>   LED) pins to meson8.dtsi
>>
>> NOTE: the .dts changes from this series depend on my previous patch from
>> [0]: "ARM: dts: meson8: fix the IR receiver pins"
>>
>>
>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
>>
>>
>> Martin Blumenstingl (13):
>>   clk: meson8b: export the SAR ADC clocks
>>   clk: meson8b: export the SDIO clock
>>   clk: meson8b: export the gate clock for the HW random number generator
>>   clk: meson8b: export the USB clocks
>>   clk: meson8b: export the ethernet gate clock
>
> Applied these 5 clk patches to next/headers with Neil's Acks.
thank you!

>>   ARM: dts: meson8: add the PWM_E and PWM_F pins
>>   ARM: dts: meson8: add the pins for the SDIO controller
>>   ARM: dts: meson: add the SAR ADC
>>   ARM: dts: meson8: add reserved memory zones
>>   ARM: dts: meson: add the hardware random number generator
>>   ARM: dts: meson: add USB support on Meson8 and Meson8b
>>   ARM: dts: meson8b: add the SCU device node
>>   ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
I will send a v2 (which will address Neil's comments on these) soon

>>  arch/arm/boot/dts/meson.dtsi             |  51 +++++++++++++++
>>  arch/arm/boot/dts/meson8.dtsi            | 109
>> ++++++++++++++++++++++++++++++-
>>  arch/arm/boot/dts/meson8b.dtsi           |  49 ++++++++++++++
>>  drivers/clk/meson/meson8b.h              |  20 +++---
>>  include/dt-bindings/clock/meson8b-clkc.h |  10 +++
>>  5 files changed, 228 insertions(+), 11 deletions(-)
>>
>

Re: [PATCH 09/13] ARM: dts: meson8: add reserved memory zones

[Martin Blumenstingl]

On Mon, Jun 12, 2017 at 9:32 AM, Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
> On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
>> There seem to be two memory regions that need to be reserved, otherwise
>> the system just hangs when running:
>> $ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
>>   --vm-keep -m 1
>>
>> The first memory region is really crucial and without it the system
>> hangs. I could not find any references to this in Amlogic's GPL kernel
>> sources.
>> The second region is used by the "suspend firmware". The u-boot sources
>> (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
>> firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
>> the Amlogic GPL kernel sources. The "suspend firmware" is responsible
>> for waking up the system from suspend state.
>>
>> This also fixes reading the full SD card as without this the system
>> would simply hang (probably related to the first memory region, if some
>> buffer is allocated there).
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>> ---
>>  arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
>>  1 file changed, 27 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>> index 8582490fcb52..cf011dfe050e 100644
>> --- a/arch/arm/boot/dts/meson8.dtsi
>> +++ b/arch/arm/boot/dts/meson8.dtsi
>> @@ -83,6 +83,33 @@
>>                       reg = <0x203>;
>>               };
>>       };
>> +
>> +     reserved-memory {
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             ranges;
>> +
>> +             /* 2 MiB reserved for Hardware ROM Firmware? */
>> +             hwrom_reserved: hwrom@0 {
>> +                     reg = <0x0 0x200000>;
>> +                     no-map;
>> +             };
>> +
>> +             /*
>> +              * 1 MiB reserved for the "ARM Power Firmware": this is ARM
>> +              * code which is responsible for system suspend. It loads a
>> +              * piece of ARC code ("arc_power" in the vendor u-boot tree)
>> +              * into SRAM, executes that and shuts down the (last) ARM core.
>> +              * The arc_power firmware then checks various wakeup sources
>> +              * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
>> +              * simply the power key) and re-starts the ARM core once it
>> +              * detects a wakeup request.
>> +              */
>> +             suspend_firmware: secmon@4f00000 {
>> +                     reg = <0x4f00000 0x100000>;
>> +                     no-map;
>> +             };
>> +     };
>>  }; /* end of / */
>>
>>  &aobus {
>>
>
> Good, but maybe you could add _reserved to the secmon alias.
good catch, thanks
it seems that "secmon@" is still a copy-and-paste left-over so I'd
rather change the whole line to "power_firmware:
power-firmware-memory@4f00000" (as it's definitely not the secure
monitor firmware) instead
does that also sound good for you?


Regards,
Martin
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[PATCH 09/13] ARM: dts: meson8: add reserved memory zones

[Martin Blumenstingl]

On Mon, Jun 12, 2017 at 9:32 AM, Neil Armstrong <narmstrong@baylibre.com> wrote:
> On 06/11/2017 12:16 PM, Martin Blumenstingl wrote:
>> There seem to be two memory regions that need to be reserved, otherwise
>> the system just hangs when running:
>> $ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
>>   --vm-keep -m 1
>>
>> The first memory region is really crucial and without it the system
>> hangs. I could not find any references to this in Amlogic's GPL kernel
>> sources.
>> The second region is used by the "suspend firmware". The u-boot sources
>> (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
>> firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
>> the Amlogic GPL kernel sources. The "suspend firmware" is responsible
>> for waking up the system from suspend state.
>>
>> This also fixes reading the full SD card as without this the system
>> would simply hang (probably related to the first memory region, if some
>> buffer is allocated there).
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>>  arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
>>  1 file changed, 27 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>> index 8582490fcb52..cf011dfe050e 100644
>> --- a/arch/arm/boot/dts/meson8.dtsi
>> +++ b/arch/arm/boot/dts/meson8.dtsi
>> @@ -83,6 +83,33 @@
>>                       reg = <0x203>;
>>               };
>>       };
>> +
>> +     reserved-memory {
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             ranges;
>> +
>> +             /* 2 MiB reserved for Hardware ROM Firmware? */
>> +             hwrom_reserved: hwrom at 0 {
>> +                     reg = <0x0 0x200000>;
>> +                     no-map;
>> +             };
>> +
>> +             /*
>> +              * 1 MiB reserved for the "ARM Power Firmware": this is ARM
>> +              * code which is responsible for system suspend. It loads a
>> +              * piece of ARC code ("arc_power" in the vendor u-boot tree)
>> +              * into SRAM, executes that and shuts down the (last) ARM core.
>> +              * The arc_power firmware then checks various wakeup sources
>> +              * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
>> +              * simply the power key) and re-starts the ARM core once it
>> +              * detects a wakeup request.
>> +              */
>> +             suspend_firmware: secmon at 4f00000 {
>> +                     reg = <0x4f00000 0x100000>;
>> +                     no-map;
>> +             };
>> +     };
>>  }; /* end of / */
>>
>>  &aobus {
>>
>
> Good, but maybe you could add _reserved to the secmon alias.
good catch, thanks
it seems that "secmon@" is still a copy-and-paste left-over so I'd
rather change the whole line to "power_firmware:
power-firmware-memory at 4f00000" (as it's definitely not the secure
monitor firmware) instead
does that also sound good for you?


Regards,
Martin

[PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an
  error when trying to initialize one of the USB2 PHYs, but we have the
  same problem on some GXBB boards. it is working fine for me - on a board
  which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to
  have two 32-bit hardware random number generator registers, while the
  GX SoCs only have one. This is not handled by the meson-rng driver yet,
  but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory
  (currently only on Meson8 until I have a Meson8b device to test if the
  same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
  the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the
  SDIO clocks (a driver for this MMC controller is work-in-progress) as
  well as the corresponding pin definitions in meson8.dtsi
- this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
  SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
  LED) pins to meson8.dtsi

NOTE: the .dts changes from this series depend on my previous patch from
[0]: "ARM: dts: meson8: fix the IR receiver pins"


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html


Changes since v1:
- dropped patches 1-5 which export various clock IDs as these are
  already applied by Jerome to clk-meson's next/headers branch
- added new patch "ARM: dts: meson: use C preprocessor friendly include
  syntax" so we can use preprocessor macros like GIC_SPI and
  IRQ_TYPE_EDGE_RISING in the SAR ADC and USB patches
- added new patch "ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING
  macros" so the GIC_SPI and IRQ_TYPE_EDGE_RISING preprocessor macros
  are available for the SAR ADC and USB patches (as a side-effect this
  also provides a nice cleanup)
- use GIC_SPI and IRQ_TYPE_EDGE_RISING instead of magic numbers in patch
  "ARM: dts: meson: add the SAR ADC" and "ARM: dts: meson: add USB
  support on Meson8 and Meson8b"
- added (currently unused) "amlogic,meson8-rng" and "amlogic,meson8b-rng"
  compatibles in "ARM: dts: meson: add the hardware random number
  generator"
- fixed node name (it's the memory region of the ARM Power Firmware,
  not the secure monitor firmware) and dropped node alias (of both
  reserved memory zones) in "ARM: dts: meson8: add reserved memory zones"
- added Neil's Reviewed-By


Martin Blumenstingl (10):
  ARM: dts: meson: use C preprocessor friendly include syntax
  ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros
  ARM: dts: meson8: add the PWM_E and PWM_F pins
  ARM: dts: meson8: add the pins for the SDIO controller
  ARM: dts: meson: add the SAR ADC
  ARM: dts: meson8: add reserved memory zones
  ARM: dts: meson: add the hardware random number generator
  ARM: dts: meson: add USB support on Meson8 and Meson8b
  ARM: dts: meson8b: add the SCU device node
  ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

 arch/arm/boot/dts/meson.dtsi         |  75 +++++++++++++++++++----
 arch/arm/boot/dts/meson6-atv1200.dts |   2 +-
 arch/arm/boot/dts/meson6.dtsi        |   2 +-
 arch/arm/boot/dts/meson8.dtsi        | 112 ++++++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/meson8b.dtsi       |  50 ++++++++++++++++
 5 files changed, 226 insertions(+), 15 deletions(-)

-- 
2.13.1

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[PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an
  error when trying to initialize one of the USB2 PHYs, but we have the
  same problem on some GXBB boards. it is working fine for me - on a board
  which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to
  have two 32-bit hardware random number generator registers, while the
  GX SoCs only have one. This is not handled by the meson-rng driver yet,
  but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory
  (currently only on Meson8 until I have a Meson8b device to test if the
  same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
  the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the
  SDIO clocks (a driver for this MMC controller is work-in-progress) as
  well as the corresponding pin definitions in meson8.dtsi
- this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
  SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
  LED) pins to meson8.dtsi

NOTE: the .dts changes from this series depend on my previous patch from
[0]: "ARM: dts: meson8: fix the IR receiver pins"


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html


Changes since v1:
- dropped patches 1-5 which export various clock IDs as these are
  already applied by Jerome to clk-meson's next/headers branch
- added new patch "ARM: dts: meson: use C preprocessor friendly include
  syntax" so we can use preprocessor macros like GIC_SPI and
  IRQ_TYPE_EDGE_RISING in the SAR ADC and USB patches
- added new patch "ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING
  macros" so the GIC_SPI and IRQ_TYPE_EDGE_RISING preprocessor macros
  are available for the SAR ADC and USB patches (as a side-effect this
  also provides a nice cleanup)
- use GIC_SPI and IRQ_TYPE_EDGE_RISING instead of magic numbers in patch
  "ARM: dts: meson: add the SAR ADC" and "ARM: dts: meson: add USB
  support on Meson8 and Meson8b"
- added (currently unused) "amlogic,meson8-rng" and "amlogic,meson8b-rng"
  compatibles in "ARM: dts: meson: add the hardware random number
  generator"
- fixed node name (it's the memory region of the ARM Power Firmware,
  not the secure monitor firmware) and dropped node alias (of both
  reserved memory zones) in "ARM: dts: meson8: add reserved memory zones"
- added Neil's Reviewed-By


Martin Blumenstingl (10):
  ARM: dts: meson: use C preprocessor friendly include syntax
  ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros
  ARM: dts: meson8: add the PWM_E and PWM_F pins
  ARM: dts: meson8: add the pins for the SDIO controller
  ARM: dts: meson: add the SAR ADC
  ARM: dts: meson8: add reserved memory zones
  ARM: dts: meson: add the hardware random number generator
  ARM: dts: meson: add USB support on Meson8 and Meson8b
  ARM: dts: meson8b: add the SCU device node
  ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

 arch/arm/boot/dts/meson.dtsi         |  75 +++++++++++++++++++----
 arch/arm/boot/dts/meson6-atv1200.dts |   2 +-
 arch/arm/boot/dts/meson6.dtsi        |   2 +-
 arch/arm/boot/dts/meson8.dtsi        | 112 ++++++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/meson8b.dtsi       |  50 ++++++++++++++++
 5 files changed, 226 insertions(+), 15 deletions(-)

-- 
2.13.1

[PATCH v2 01/10] ARM: dts: meson: use C preprocessor friendly include syntax

[Martin Blumenstingl]

This replaces the "/include/" syntax with the "#include" syntax in all
Amlogic Meson .dts and .dtsi files. That is required to use preprocessor
defines (like GIC_SPI and IRQ_TYPE_EDGE_RISING) in meson.dtsi (all files
which directly or indirectly include meson.dtsi need to use the
"#include" syntax, otherwise the .dts files cannot be compiled).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson6-atv1200.dts | 2 +-
 arch/arm/boot/dts/meson6.dtsi        | 2 +-
 arch/arm/boot/dts/meson8.dtsi        | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index 1237faa63ce6..9444b0d9628f 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -46,7 +46,7 @@
  */
 
 /dts-v1/;
-/include/ "meson6.dtsi"
+#include "meson6.dtsi"
 
 / {
 	model = "Geniatech ATV1200";
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index b0fc91ffd6a1..8557b6117a4b 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -45,7 +45,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "meson.dtsi"
+#include "meson.dtsi"
 
 / {
 	model = "Amlogic Meson6 SoC";
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index e4f7357b4b31..c5d73b999773 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -45,7 +45,7 @@
 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
-/include/ "meson.dtsi"
+#include "meson.dtsi"
 
 / {
 	model = "Amlogic Meson8 SoC";
-- 
2.13.1

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[PATCH v2 01/10] ARM: dts: meson: use C preprocessor friendly include syntax

[Martin Blumenstingl]

This replaces the "/include/" syntax with the "#include" syntax in all
Amlogic Meson .dts and .dtsi files. That is required to use preprocessor
defines (like GIC_SPI and IRQ_TYPE_EDGE_RISING) in meson.dtsi (all files
which directly or indirectly include meson.dtsi need to use the
"#include" syntax, otherwise the .dts files cannot be compiled).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson6-atv1200.dts | 2 +-
 arch/arm/boot/dts/meson6.dtsi        | 2 +-
 arch/arm/boot/dts/meson8.dtsi        | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index 1237faa63ce6..9444b0d9628f 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -46,7 +46,7 @@
  */
 
 /dts-v1/;
-/include/ "meson6.dtsi"
+#include "meson6.dtsi"
 
 / {
 	model = "Geniatech ATV1200";
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index b0fc91ffd6a1..8557b6117a4b 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -45,7 +45,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "meson.dtsi"
+#include "meson.dtsi"
 
 / {
 	model = "Amlogic Meson6 SoC";
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index e4f7357b4b31..c5d73b999773 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -45,7 +45,7 @@
 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
-/include/ "meson.dtsi"
+#include "meson.dtsi"
 
 / {
 	model = "Amlogic Meson8 SoC";
-- 
2.13.1

[PATCH v2 02/10] ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros

[Martin Blumenstingl]

This makes meson.dtsi easier to read as we are not using magic numbers
for the GIC interrupt type (GIC_SPI) and the interrupt polarity
(IRQ_TYPE_EDGE_RISING).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson.dtsi | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 8d9c36970dfd..d287f606e06f 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -45,6 +45,8 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 /include/ "skeleton.dtsi"
 
 / {
@@ -81,21 +83,21 @@
 			uart_A: serial@84c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84c0 0x18>;
-				interrupts = <0 26 1>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial@84dc {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84dc 0x18>;
-				interrupts = <0 75 1>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			i2c_A: i2c@8500 {
 				compatible = "amlogic,meson6-i2c";
 				reg = <0x8500 0x20>;
-				interrupts = <0 21 1>;
+				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -104,14 +106,14 @@
 			uart_C: serial@8700 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x8700 0x18>;
-				interrupts = <0 93 1>;
+				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			i2c_B: i2c@87c0 {
 				compatible = "amlogic,meson6-i2c";
 				reg = <0x87c0 0x20>;
-				interrupts = <0 128 1>;
+				interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -128,13 +130,13 @@
 			wdt: watchdog@9900 {
 				compatible = "amlogic,meson6-wdt";
 				reg = <0x9900 0x8>;
-				interrupts = <0 0 1>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
 			};
 
 			timer@9940 {
 				compatible = "amlogic,meson6-timer";
 				reg = <0x9940 0x18>;
-				interrupts = <0 10 1>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
 			};
 		};
 
@@ -148,21 +150,21 @@
 			ir_receiver: ir-receiver@480 {
 				compatible= "amlogic,meson6-ir";
 				reg = <0x480 0x20>;
-				interrupts = <0 15 1>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_AO: serial@4c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x4c0 0x18>;
-				interrupts = <0 90 1>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			i2c_AO: i2c@500 {
 				compatible = "amlogic,meson6-i2c";
 				reg = <0x500 0x20>;
-				interrupts = <0 92 1>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -173,7 +175,7 @@
 			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 			reg = <0xc9410000 0x10000
 			       0xc1108108 0x4>;
-			interrupts = <0 8 1>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "macirq";
 			status = "disabled";
 		};
-- 
2.13.1

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[PATCH v2 02/10] ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros

[Martin Blumenstingl]

This makes meson.dtsi easier to read as we are not using magic numbers
for the GIC interrupt type (GIC_SPI) and the interrupt polarity
(IRQ_TYPE_EDGE_RISING).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 8d9c36970dfd..d287f606e06f 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -45,6 +45,8 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 /include/ "skeleton.dtsi"
 
 / {
@@ -81,21 +83,21 @@
 			uart_A: serial at 84c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84c0 0x18>;
-				interrupts = <0 26 1>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial at 84dc {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84dc 0x18>;
-				interrupts = <0 75 1>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			i2c_A: i2c at 8500 {
 				compatible = "amlogic,meson6-i2c";
 				reg = <0x8500 0x20>;
-				interrupts = <0 21 1>;
+				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -104,14 +106,14 @@
 			uart_C: serial at 8700 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x8700 0x18>;
-				interrupts = <0 93 1>;
+				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			i2c_B: i2c at 87c0 {
 				compatible = "amlogic,meson6-i2c";
 				reg = <0x87c0 0x20>;
-				interrupts = <0 128 1>;
+				interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -128,13 +130,13 @@
 			wdt: watchdog at 9900 {
 				compatible = "amlogic,meson6-wdt";
 				reg = <0x9900 0x8>;
-				interrupts = <0 0 1>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
 			};
 
 			timer at 9940 {
 				compatible = "amlogic,meson6-timer";
 				reg = <0x9940 0x18>;
-				interrupts = <0 10 1>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
 			};
 		};
 
@@ -148,21 +150,21 @@
 			ir_receiver: ir-receiver at 480 {
 				compatible= "amlogic,meson6-ir";
 				reg = <0x480 0x20>;
-				interrupts = <0 15 1>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_AO: serial at 4c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x4c0 0x18>;
-				interrupts = <0 90 1>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			i2c_AO: i2c at 500 {
 				compatible = "amlogic,meson6-i2c";
 				reg = <0x500 0x20>;
-				interrupts = <0 92 1>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -173,7 +175,7 @@
 			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 			reg = <0xc9410000 0x10000
 			       0xc1108108 0x4>;
-			interrupts = <0 8 1>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "macirq";
 			status = "disabled";
 		};
-- 
2.13.1

[PATCH v2 03/10] ARM: dts: meson8: add the PWM_E and PWM_F pins

[Martin Blumenstingl]

This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to
meson8.dtsi, allowing devices to use them. PWM_E can be used on some
devices to generate the 32.768kHz clock for the SDIO wifi module, while
PWM_F can be used to control the power LED.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index c5d73b999773..5ff7903964c6 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -123,6 +123,13 @@
 				function = "remote";
 			};
 		};
+
+		pwm_f_ao_pins: pwm-f-ao {
+			mux {
+				groups = "pwm_f_ao";
+				function = "pwm_f_ao";
+			};
+		};
 	};
 };
 
@@ -168,6 +175,13 @@
 				function = "ethernet";
 			};
 		};
+
+		pwm_e_pins: pwm-e {
+			mux {
+				groups = "pwm_e";
+				function = "pwm_e";
+			};
+		};
 	};
 };
 
-- 
2.13.1

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[PATCH v2 03/10] ARM: dts: meson8: add the PWM_E and PWM_F pins

[Martin Blumenstingl]

This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to
meson8.dtsi, allowing devices to use them. PWM_E can be used on some
devices to generate the 32.768kHz clock for the SDIO wifi module, while
PWM_F can be used to control the power LED.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index c5d73b999773..5ff7903964c6 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -123,6 +123,13 @@
 				function = "remote";
 			};
 		};
+
+		pwm_f_ao_pins: pwm-f-ao {
+			mux {
+				groups = "pwm_f_ao";
+				function = "pwm_f_ao";
+			};
+		};
 	};
 };
 
@@ -168,6 +175,13 @@
 				function = "ethernet";
 			};
 		};
+
+		pwm_e_pins: pwm-e {
+			mux {
+				groups = "pwm_e";
+				function = "pwm_e";
+			};
+		};
 	};
 };
 
-- 
2.13.1

[PATCH v2 04/10] ARM: dts: meson8: add the pins for the SDIO controller

[Martin Blumenstingl]

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 5ff7903964c6..bb3608bddc98 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -158,6 +158,30 @@
 			gpio-ranges = <&pinctrl_cbus 0 0 120>;
 		};
 
+		sd_a_pins: sd-a {
+			mux {
+				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
+					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
+				function = "sd_a";
+			};
+		};
+
+		sd_b_pins: sd-b {
+			mux {
+				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
+				function = "sd_b";
+			};
+		};
+
+		sd_c_pins: sd-c {
+			mux {
+				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
+					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
+				function = "sd_c";
+			};
+		};
+
 		spi_nor_pins: nor {
 			mux {
 				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
-- 
2.13.1

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[PATCH v2 04/10] ARM: dts: meson8: add the pins for the SDIO controller

[Martin Blumenstingl]

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 5ff7903964c6..bb3608bddc98 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -158,6 +158,30 @@
 			gpio-ranges = <&pinctrl_cbus 0 0 120>;
 		};
 
+		sd_a_pins: sd-a {
+			mux {
+				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
+					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
+				function = "sd_a";
+			};
+		};
+
+		sd_b_pins: sd-b {
+			mux {
+				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
+				function = "sd_b";
+			};
+		};
+
+		sd_c_pins: sd-c {
+			mux {
+				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
+					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
+				function = "sd_c";
+			};
+		};
+
 		spi_nor_pins: nor {
 			mux {
 				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
-- 
2.13.1

[PATCH v2 05/10] ARM: dts: meson: add the SAR ADC

[Martin Blumenstingl]

This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson.dtsi   | 8 ++++++++
 arch/arm/boot/dts/meson8.dtsi  | 8 ++++++++
 arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index d287f606e06f..46706d74a145 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -103,6 +103,14 @@
 				status = "disabled";
 			};
 
+			saradc: adc@8680 {
+				compatible = "amlogic,meson-saradc";
+				reg = <0x8680 0x34>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+			};
+
 			uart_C: serial@8700 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x8700 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index bb3608bddc98..6687b1b4c7c9 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -232,6 +232,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &spifc {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index d9f116a418b2..1c09090ff4a5 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -177,6 +177,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &uart_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.1

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[PATCH v2 05/10] ARM: dts: meson: add the SAR ADC

[Martin Blumenstingl]

This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson.dtsi   | 8 ++++++++
 arch/arm/boot/dts/meson8.dtsi  | 8 ++++++++
 arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index d287f606e06f..46706d74a145 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -103,6 +103,14 @@
 				status = "disabled";
 			};
 
+			saradc: adc at 8680 {
+				compatible = "amlogic,meson-saradc";
+				reg = <0x8680 0x34>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+			};
+
 			uart_C: serial at 8700 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x8700 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index bb3608bddc98..6687b1b4c7c9 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -232,6 +232,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &spifc {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index d9f116a418b2..1c09090ff4a5 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -177,6 +177,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &uart_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.1

[PATCH v2 06/10] ARM: dts: meson8: add reserved memory zones

[Martin Blumenstingl]

There seem to be two memory regions that need to be reserved, otherwise
the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
  --vm-keep -m 1

The first memory region is really crucial and without it the system
hangs. I could not find any references to this in Amlogic's GPL kernel
sources.
The second region is used by the "suspend firmware". The u-boot sources
(/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
the Amlogic GPL kernel sources. The "suspend firmware" is responsible
for waking up the system from suspend state.

This also fixes reading the full SD card as without this the system
would simply hang (probably related to the first memory region, if some
buffer is allocated there).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6687b1b4c7c9..df79a34a3530 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -83,6 +83,33 @@
 			reg = <0x203>;
 		};
 	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* 2 MiB reserved for Hardware ROM Firmware? */
+		hwrom@0 {
+			reg = <0x0 0x200000>;
+			no-map;
+		};
+
+		/*
+		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
+		 * code which is responsible for system suspend. It loads a
+		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
+		 * into SRAM, executes that and shuts down the (last) ARM core.
+		 * The arc_power firmware then checks various wakeup sources
+		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
+		 * simply the power key) and re-starts the ARM core once it
+		 * detects a wakeup request.
+		 */
+		power-firmware@4f00000 {
+			reg = <0x4f00000 0x100000>;
+			no-map;
+		};
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

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[PATCH v2 06/10] ARM: dts: meson8: add reserved memory zones

[Martin Blumenstingl]

There seem to be two memory regions that need to be reserved, otherwise
the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
  --vm-keep -m 1

The first memory region is really crucial and without it the system
hangs. I could not find any references to this in Amlogic's GPL kernel
sources.
The second region is used by the "suspend firmware". The u-boot sources
(/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
the Amlogic GPL kernel sources. The "suspend firmware" is responsible
for waking up the system from suspend state.

This also fixes reading the full SD card as without this the system
would simply hang (probably related to the first memory region, if some
buffer is allocated there).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6687b1b4c7c9..df79a34a3530 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -83,6 +83,33 @@
 			reg = <0x203>;
 		};
 	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* 2 MiB reserved for Hardware ROM Firmware? */
+		hwrom at 0 {
+			reg = <0x0 0x200000>;
+			no-map;
+		};
+
+		/*
+		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
+		 * code which is responsible for system suspend. It loads a
+		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
+		 * into SRAM, executes that and shuts down the (last) ARM core.
+		 * The arc_power firmware then checks various wakeup sources
+		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
+		 * simply the power key) and re-starts the ARM core once it
+		 * detects a wakeup request.
+		 */
+		power-firmware at 4f00000 {
+			reg = <0x4f00000 0x100000>;
+			no-map;
+		};
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

[PATCH v2 07/10] ARM: dts: meson: add the hardware random number generator

[Martin Blumenstingl]

All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson.dtsi   | 5 +++++
 arch/arm/boot/dts/meson8.dtsi  | 6 ++++++
 arch/arm/boot/dts/meson8b.dtsi | 6 ++++++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 46706d74a145..bf37606ba82e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -80,6 +80,11 @@
 			#size-cells = <1>;
 			ranges = <0x0 0xc1100000 0x200000>;
 
+			hwrng: rng@8100 {
+				compatible = "amlogic,meson-rng";
+				reg = <0x8100 0x8>;
+			};
+
 			uart_A: serial@84c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84c0 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index df79a34a3530..b4c5fdd7b451 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -241,6 +241,12 @@
 	clock-names = "stmmaceth";
 };
 
+&hwrng {
+	compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &i2c_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 1c09090ff4a5..a9d7074e6369 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -171,6 +171,12 @@
 	};
 };
 
+&hwrng {
+	compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &L2 {
 	arm,data-latency = <3 3 3>;
 	arm,tag-latency = <2 2 2>;
-- 
2.13.1

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[PATCH v2 07/10] ARM: dts: meson: add the hardware random number generator

[Martin Blumenstingl]

All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson.dtsi   | 5 +++++
 arch/arm/boot/dts/meson8.dtsi  | 6 ++++++
 arch/arm/boot/dts/meson8b.dtsi | 6 ++++++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 46706d74a145..bf37606ba82e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -80,6 +80,11 @@
 			#size-cells = <1>;
 			ranges = <0x0 0xc1100000 0x200000>;
 
+			hwrng: rng at 8100 {
+				compatible = "amlogic,meson-rng";
+				reg = <0x8100 0x8>;
+			};
+
 			uart_A: serial at 84c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x84c0 0x18>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index df79a34a3530..b4c5fdd7b451 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -241,6 +241,12 @@
 	clock-names = "stmmaceth";
 };
 
+&hwrng {
+	compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &i2c_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 1c09090ff4a5..a9d7074e6369 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -171,6 +171,12 @@
 	};
 };
 
+&hwrng {
+	compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &L2 {
 	arm,data-latency = <3 3 3>;
 	arm,tag-latency = <2 2 2>;
-- 
2.13.1

[PATCH v2 08/10] ARM: dts: meson: add USB support on Meson8 and Meson8b

[Martin Blumenstingl]

This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
nodes to meson.dtsi (as the same - or at least a very similar) IP block
is used on all SoCs (at the same physical address).
Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
initialized by the dwc2 driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson.dtsi   | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/meson8.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++
 3 files changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index bf37606ba82e..15204e44161d 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -132,6 +132,20 @@
 				status = "disabled";
 			};
 
+			usb0_phy: phy@8800 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8800 0x20>;
+				status = "disabled";
+			};
+
+			usb1_phy: phy@8820 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8820 0x20>;
+				status = "disabled";
+			};
+
 			spifc: spi@8c80 {
 				compatible = "amlogic,meson6-spifc";
 				reg = <0x8c80 0x80>;
@@ -184,6 +198,30 @@
 			};
 		};
 
+		usb0: usb@c9040000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc9040000 0x40000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>;
+			phys = <&usb0_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
+		usb1: usb@c90c0000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc90c0000 0x40000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
+			phys = <&usb1_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
 		ethmac: ethernet@c9410000 {
 			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 			reg = <0xc9410000 0x10000
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index b4c5fdd7b451..17a4c6255589 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -292,3 +292,27 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index a9d7074e6369..521be5dfa8ef 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -206,3 +206,29 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
-- 
2.13.1

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[PATCH v2 08/10] ARM: dts: meson: add USB support on Meson8 and Meson8b

[Martin Blumenstingl]

This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
nodes to meson.dtsi (as the same - or at least a very similar) IP block
is used on all SoCs (at the same physical address).
Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
initialized by the dwc2 driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson.dtsi   | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/meson8.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++
 3 files changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index bf37606ba82e..15204e44161d 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -132,6 +132,20 @@
 				status = "disabled";
 			};
 
+			usb0_phy: phy at 8800 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8800 0x20>;
+				status = "disabled";
+			};
+
+			usb1_phy: phy at 8820 {
+				compatible = "amlogic,meson-mx-usb2-phy";
+				#phy-cells = <0>;
+				reg = <0x8820 0x20>;
+				status = "disabled";
+			};
+
 			spifc: spi at 8c80 {
 				compatible = "amlogic,meson6-spifc";
 				reg = <0x8c80 0x80>;
@@ -184,6 +198,30 @@
 			};
 		};
 
+		usb0: usb at c9040000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc9040000 0x40000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>;
+			phys = <&usb0_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
+		usb1: usb at c90c0000 {
+			compatible = "snps,dwc2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc90c0000 0x40000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
+			phys = <&usb1_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
+			status = "disabled";
+		};
+
 		ethmac: ethernet at c9410000 {
 			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 			reg = <0xc9410000 0x10000
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index b4c5fdd7b451..17a4c6255589 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -292,3 +292,27 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index a9d7074e6369..521be5dfa8ef 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -206,3 +206,29 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8b-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+	resets = <&reset RESET_USB_OTG>;
+};
-- 
2.13.1

[PATCH v2 09/10] ARM: dts: meson8b: add the SCU device node

[Martin Blumenstingl]

Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
used during SMP boot.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi  | 5 +++++
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 17a4c6255589..dfe83364eceb 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -110,6 +110,11 @@
 			no-map;
 		};
 	};
+
+	scu@c4300000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 521be5dfa8ef..173b12a999e6 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -82,6 +82,11 @@
 			reg = <0x203>;
 		};
 	};
+
+	scu@c4300000 {
+		compatible = "arm,cortex-a5-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

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[PATCH v2 09/10] ARM: dts: meson8b: add the SCU device node

[Martin Blumenstingl]

Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
used during SMP boot.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson8.dtsi  | 5 +++++
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 17a4c6255589..dfe83364eceb 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -110,6 +110,11 @@
 			no-map;
 		};
 	};
+
+	scu at c4300000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 521be5dfa8ef..173b12a999e6 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -82,6 +82,11 @@
 			reg = <0x203>;
 		};
 	};
+
+	scu at c4300000 {
+		compatible = "arm,cortex-a5-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
-- 
2.13.1

[PATCH v2 10/10] ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

[Martin Blumenstingl]

Until now clk81 was used as gate clock for the ethernet controller on
Meson8 whereas Meson8b did not configure a gate clock at all. Use
CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi  | 2 +-
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index dfe83364eceb..cada35828931 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -242,7 +242,7 @@
 };
 
 &ethmac {
-	clocks = <&clkc CLKID_CLK81>;
+	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
 };
 
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 173b12a999e6..72e4f425f190 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -176,6 +176,11 @@
 	};
 };
 
+&ethmac {
+	clocks = <&clkc CLKID_ETH>;
+	clock-names = "stmmaceth";
+};
+
 &hwrng {
 	compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 	clocks = <&clkc CLKID_RNG0>;
-- 
2.13.1

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[PATCH v2 10/10] ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b

[Martin Blumenstingl]

Until now clk81 was used as gate clock for the ethernet controller on
Meson8 whereas Meson8b did not configure a gate clock at all. Use
CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/boot/dts/meson8.dtsi  | 2 +-
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index dfe83364eceb..cada35828931 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -242,7 +242,7 @@
 };
 
 &ethmac {
-	clocks = <&clkc CLKID_CLK81>;
+	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
 };
 
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 173b12a999e6..72e4f425f190 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -176,6 +176,11 @@
 	};
 };
 
+&ethmac {
+	clocks = <&clkc CLKID_ETH>;
+	clock-names = "stmmaceth";
+};
+
 &hwrng {
 	compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 	clocks = <&clkc CLKID_RNG0>;
-- 
2.13.1

Re: [PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:

> This series adds:
> - USB support on Meson8 and Meson8b (it seems that some boards show an
>   error when trying to initialize one of the USB2 PHYs, but we have the
>   same problem on some GXBB boards. it is working fine for me - on a board
>   which is not supported upstream yet)
> - hardware random number generator support (Meson8 and Meson8b seem to
>   have two 32-bit hardware random number generator registers, while the
>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>   but that can still be improved later on)
> - SAR ADC support
> - add reserved memory zones to fix random hangs when filling the memory
>   (currently only on Meson8 until I have a Meson8b device to test if the
>   same problem appears there as well)
> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>   the bootloader does not enable the gate clock
> - add the SCU (Snoop Control Unit) which is needed for SMP support
> - minor preparations for further .dts updates as this already exports the
>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>   well as the corresponding pin definitions in meson8.dtsi
> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>   LED) pins to meson8.dtsi
>
> NOTE: the .dts changes from this series depend on my previous patch from
> [0]: "ARM: dts: meson8: fix the IR receiver pins"

Thanks for the reminder, I had missed that one.

This series now applied to v4.13/dt (after merging in the clock headers
deps from Jerome) and will go in the 2nd round of pull requests to
arm-soc, probably early next week.

Thanks for the continued great work Martin!

Kevin
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[PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> This series adds:
> - USB support on Meson8 and Meson8b (it seems that some boards show an
>   error when trying to initialize one of the USB2 PHYs, but we have the
>   same problem on some GXBB boards. it is working fine for me - on a board
>   which is not supported upstream yet)
> - hardware random number generator support (Meson8 and Meson8b seem to
>   have two 32-bit hardware random number generator registers, while the
>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>   but that can still be improved later on)
> - SAR ADC support
> - add reserved memory zones to fix random hangs when filling the memory
>   (currently only on Meson8 until I have a Meson8b device to test if the
>   same problem appears there as well)
> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>   the bootloader does not enable the gate clock
> - add the SCU (Snoop Control Unit) which is needed for SMP support
> - minor preparations for further .dts updates as this already exports the
>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>   well as the corresponding pin definitions in meson8.dtsi
> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>   LED) pins to meson8.dtsi
>
> NOTE: the .dts changes from this series depend on my previous patch from
> [0]: "ARM: dts: meson8: fix the IR receiver pins"

Thanks for the reminder, I had missed that one.

This series now applied to v4.13/dt (after merging in the clock headers
deps from Jerome) and will go in the 2nd round of pull requests to
arm-soc, probably early next week.

Thanks for the continued great work Martin!

Kevin

Re: [PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:

> This series adds:
> - USB support on Meson8 and Meson8b (it seems that some boards show an
>   error when trying to initialize one of the USB2 PHYs, but we have the
>   same problem on some GXBB boards. it is working fine for me - on a board
>   which is not supported upstream yet)
> - hardware random number generator support (Meson8 and Meson8b seem to
>   have two 32-bit hardware random number generator registers, while the
>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>   but that can still be improved later on)
> - SAR ADC support
> - add reserved memory zones to fix random hangs when filling the memory
>   (currently only on Meson8 until I have a Meson8b device to test if the
>   same problem appears there as well)
> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>   the bootloader does not enable the gate clock
> - add the SCU (Snoop Control Unit) which is needed for SMP support
> - minor preparations for further .dts updates as this already exports the
>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>   well as the corresponding pin definitions in meson8.dtsi
> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>   LED) pins to meson8.dtsi

Oh, one minor nit... When you send a v2 of a series, please start a new
thread.  You sent this one in-reply-to the original series.  When you do
that, it risks getting missed when I mark the previous series as read.

Thanks,

Kevin

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[PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> This series adds:
> - USB support on Meson8 and Meson8b (it seems that some boards show an
>   error when trying to initialize one of the USB2 PHYs, but we have the
>   same problem on some GXBB boards. it is working fine for me - on a board
>   which is not supported upstream yet)
> - hardware random number generator support (Meson8 and Meson8b seem to
>   have two 32-bit hardware random number generator registers, while the
>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>   but that can still be improved later on)
> - SAR ADC support
> - add reserved memory zones to fix random hangs when filling the memory
>   (currently only on Meson8 until I have a Meson8b device to test if the
>   same problem appears there as well)
> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>   the bootloader does not enable the gate clock
> - add the SCU (Snoop Control Unit) which is needed for SMP support
> - minor preparations for further .dts updates as this already exports the
>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>   well as the corresponding pin definitions in meson8.dtsi
> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>   LED) pins to meson8.dtsi

Oh, one minor nit... When you send a v2 of a series, please start a new
thread.  You sent this one in-reply-to the original series.  When you do
that, it risks getting missed when I mark the previous series as read.

Thanks,

Kevin

Re: [PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

Hi Kevin,

On Fri, Jun 16, 2017 at 9:12 PM, Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
> Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:
>
>> This series adds:
>> - USB support on Meson8 and Meson8b (it seems that some boards show an
>>   error when trying to initialize one of the USB2 PHYs, but we have the
>>   same problem on some GXBB boards. it is working fine for me - on a board
>>   which is not supported upstream yet)
>> - hardware random number generator support (Meson8 and Meson8b seem to
>>   have two 32-bit hardware random number generator registers, while the
>>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>>   but that can still be improved later on)
>> - SAR ADC support
>> - add reserved memory zones to fix random hangs when filling the memory
>>   (currently only on Meson8 until I have a Meson8b device to test if the
>>   same problem appears there as well)
>> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>>   the bootloader does not enable the gate clock
>> - add the SCU (Snoop Control Unit) which is needed for SMP support
>> - minor preparations for further .dts updates as this already exports the
>>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>>   well as the corresponding pin definitions in meson8.dtsi
>> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>>   LED) pins to meson8.dtsi
>
> Oh, one minor nit... When you send a v2 of a series, please start a new
> thread.  You sent this one in-reply-to the original series.  When you do
> that, it risks getting missed when I mark the previous series as read.
oh, thanks for letting me know - I though that sending the update as
reply was "good practice"! noted for the next batch of changes :)

> Thanks,
you're welcome - it's nice to put all these puzzle pieces together to
get a specific SoC from "there's output on the serial console and
Linux boots" to "now you can use USB, the SD card slot, ADC, ..."

Regards,
Martin
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[PATCH v2 00/10] add support for more devices on Meson8 and Meson8b

[Martin Blumenstingl]

Hi Kevin,

On Fri, Jun 16, 2017 at 9:12 PM, Kevin Hilman <khilman@baylibre.com> wrote:
> Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
>
>> This series adds:
>> - USB support on Meson8 and Meson8b (it seems that some boards show an
>>   error when trying to initialize one of the USB2 PHYs, but we have the
>>   same problem on some GXBB boards. it is working fine for me - on a board
>>   which is not supported upstream yet)
>> - hardware random number generator support (Meson8 and Meson8b seem to
>>   have two 32-bit hardware random number generator registers, while the
>>   GX SoCs only have one. This is not handled by the meson-rng driver yet,
>>   but that can still be improved later on)
>> - SAR ADC support
>> - add reserved memory zones to fix random hangs when filling the memory
>>   (currently only on Meson8 until I have a Meson8b device to test if the
>>   same problem appears there as well)
>> - use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
>>   the bootloader does not enable the gate clock
>> - add the SCU (Snoop Control Unit) which is needed for SMP support
>> - minor preparations for further .dts updates as this already exports the
>>   SDIO clocks (a driver for this MMC controller is work-in-progress) as
>>   well as the corresponding pin definitions in meson8.dtsi
>> - this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the
>>   SDIO wifi chip) and pwm_f (used on some boards for the dimmable power
>>   LED) pins to meson8.dtsi
>
> Oh, one minor nit... When you send a v2 of a series, please start a new
> thread.  You sent this one in-reply-to the original series.  When you do
> that, it risks getting missed when I mark the previous series as read.
oh, thanks for letting me know - I though that sending the update as
reply was "good practice"! noted for the next batch of changes :)

> Thanks,
you're welcome - it's nice to put all these puzzle pieces together to
get a specific SoC from "there's output on the serial console and
Linux boots" to "now you can use USB, the SD card slot, ADC, ..."

Regards,
Martin