* [PATCH 0/3] ARM: dts: NSP: dma-coherent and USB3 changes
@ 2017-07-25 22:06 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: Florian Fainelli, Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list, devicetree, linux-arm-kernel, linux-kernel
Add dma-coherent to the relevant DT entries, and add USB3 support
Jon Mason (3):
ARM: dts: NSP: Add dma-coherent to relevant DT entries
ARM: dts: NSP: Rearrage USB entries
ARM: dts: NSP: Add USB3 and USB3 PHY to NSP
arch/arm/boot/dts/bcm-nsp.dtsi | 61 +++++++++++++++++++++++++++++---------
arch/arm/boot/dts/bcm958522er.dts | 8 +++++
arch/arm/boot/dts/bcm958525er.dts | 8 +++++
arch/arm/boot/dts/bcm958525xmc.dts | 8 +++++
arch/arm/boot/dts/bcm958622hr.dts | 8 +++++
arch/arm/boot/dts/bcm958623hr.dts | 8 +++++
arch/arm/boot/dts/bcm958625hr.dts | 8 +++++
arch/arm/boot/dts/bcm958625k.dts | 8 +++++
8 files changed, 103 insertions(+), 14 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 0/3] ARM: dts: NSP: dma-coherent and USB3 changes
@ 2017-07-25 22:06 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: Florian Fainelli, Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Add dma-coherent to the relevant DT entries, and add USB3 support
Jon Mason (3):
ARM: dts: NSP: Add dma-coherent to relevant DT entries
ARM: dts: NSP: Rearrage USB entries
ARM: dts: NSP: Add USB3 and USB3 PHY to NSP
arch/arm/boot/dts/bcm-nsp.dtsi | 61 +++++++++++++++++++++++++++++---------
arch/arm/boot/dts/bcm958522er.dts | 8 +++++
arch/arm/boot/dts/bcm958525er.dts | 8 +++++
arch/arm/boot/dts/bcm958525xmc.dts | 8 +++++
arch/arm/boot/dts/bcm958622hr.dts | 8 +++++
arch/arm/boot/dts/bcm958623hr.dts | 8 +++++
arch/arm/boot/dts/bcm958625hr.dts | 8 +++++
arch/arm/boot/dts/bcm958625k.dts | 8 +++++
8 files changed, 103 insertions(+), 14 deletions(-)
--
2.7.4
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 0/3] ARM: dts: NSP: dma-coherent and USB3 changes
@ 2017-07-25 22:06 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: linux-arm-kernel
Add dma-coherent to the relevant DT entries, and add USB3 support
Jon Mason (3):
ARM: dts: NSP: Add dma-coherent to relevant DT entries
ARM: dts: NSP: Rearrage USB entries
ARM: dts: NSP: Add USB3 and USB3 PHY to NSP
arch/arm/boot/dts/bcm-nsp.dtsi | 61 +++++++++++++++++++++++++++++---------
arch/arm/boot/dts/bcm958522er.dts | 8 +++++
arch/arm/boot/dts/bcm958525er.dts | 8 +++++
arch/arm/boot/dts/bcm958525xmc.dts | 8 +++++
arch/arm/boot/dts/bcm958622hr.dts | 8 +++++
arch/arm/boot/dts/bcm958623hr.dts | 8 +++++
arch/arm/boot/dts/bcm958625hr.dts | 8 +++++
arch/arm/boot/dts/bcm958625k.dts | 8 +++++
8 files changed, 103 insertions(+), 14 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
2017-07-25 22:06 ` Jon Mason
@ 2017-07-25 22:06 ` Jon Mason
-1 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: Florian Fainelli, Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list, devicetree, linux-arm-kernel, linux-kernel
Cache related issues with DMA rings and performance issues related to
caching are being caused by not properly setting the "dma-coherent" flag
in the device tree entries. Adding it here to correct the issue.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
---
arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 7204d1def23d..c8d734d9f5fc 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -207,6 +207,7 @@
clocks = <&iprocslow>;
clock-names = "apb_pclk";
#dma-cells = <1>;
+ dma-coherent;
};
sdio: sdhci@21000 {
@@ -215,6 +216,7 @@
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
+ dma-coherent;
status = "disabled";
};
@@ -224,6 +226,7 @@
<0x110000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -233,6 +236,7 @@
<0x111000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -242,6 +246,7 @@
<0x112000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -252,6 +257,7 @@
#mbox-cells = <1>;
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
+ dma-coherent;
};
nand: nand@26000 {
@@ -325,6 +331,7 @@
compatible = "generic-ehci";
reg = <0x2a000 0x100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -332,6 +339,7 @@
compatible = "generic-ohci";
reg = <0x2b000 0x100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -364,6 +372,7 @@
#address-cells = <1>;
#size-cells = <0>;
+ dma-coherent;
status = "disabled";
/* ports are defined in board DTS */
@@ -376,6 +385,7 @@
#size-cells = <0>;
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
+ dma-coherent;
status = "disabled";
};
@@ -446,6 +456,7 @@
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ dma-coherent;
status = "disabled";
sata0: sata-port@0 {
@@ -483,6 +494,7 @@
*/
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi0>;
@@ -519,6 +531,7 @@
*/
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi1>;
@@ -555,6 +568,7 @@
*/
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi2>;
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
@ 2017-07-25 22:06 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: linux-arm-kernel
Cache related issues with DMA rings and performance issues related to
caching are being caused by not properly setting the "dma-coherent" flag
in the device tree entries. Adding it here to correct the issue.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
---
arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 7204d1def23d..c8d734d9f5fc 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -207,6 +207,7 @@
clocks = <&iprocslow>;
clock-names = "apb_pclk";
#dma-cells = <1>;
+ dma-coherent;
};
sdio: sdhci at 21000 {
@@ -215,6 +216,7 @@
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
+ dma-coherent;
status = "disabled";
};
@@ -224,6 +226,7 @@
<0x110000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -233,6 +236,7 @@
<0x111000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -242,6 +246,7 @@
<0x112000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -252,6 +257,7 @@
#mbox-cells = <1>;
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
+ dma-coherent;
};
nand: nand at 26000 {
@@ -325,6 +331,7 @@
compatible = "generic-ehci";
reg = <0x2a000 0x100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -332,6 +339,7 @@
compatible = "generic-ohci";
reg = <0x2b000 0x100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -364,6 +372,7 @@
#address-cells = <1>;
#size-cells = <0>;
+ dma-coherent;
status = "disabled";
/* ports are defined in board DTS */
@@ -376,6 +385,7 @@
#size-cells = <0>;
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
+ dma-coherent;
status = "disabled";
};
@@ -446,6 +456,7 @@
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ dma-coherent;
status = "disabled";
sata0: sata-port at 0 {
@@ -483,6 +494,7 @@
*/
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi0>;
@@ -519,6 +531,7 @@
*/
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi1>;
@@ -555,6 +568,7 @@
*/
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi2>;
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/3] ARM: dts: NSP: Rearrage USB entries
2017-07-25 22:06 ` Jon Mason
@ 2017-07-25 22:06 ` Jon Mason
-1 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: Florian Fainelli, Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list, devicetree, linux-arm-kernel, linux-kernel
The rest of the DTSI file is in incrementing addresses, but the USB
OHCI/ECHI entries are out of sequence. Move them to put them in the
proper place.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index c8d734d9f5fc..770aa2e7970c 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -303,6 +303,22 @@
#size-cells = <0>;
};
+ ehci0: usb@2a000 {
+ compatible = "generic-ehci";
+ reg = <0x2a000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ ohci0: usb@2b000 {
+ compatible = "generic-ohci";
+ reg = <0x2b000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
crypto@2f000 {
compatible = "brcm,spum-nsp-crypto";
reg = <0x2f000 0x900>;
@@ -327,22 +343,6 @@
status = "disabled";
};
- ehci0: usb@2a000 {
- compatible = "generic-ehci";
- reg = <0x2a000 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
- ohci0: usb@2b000 {
- compatible = "generic-ohci";
- reg = <0x2b000 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/3] ARM: dts: NSP: Rearrage USB entries
@ 2017-07-25 22:06 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: linux-arm-kernel
The rest of the DTSI file is in incrementing addresses, but the USB
OHCI/ECHI entries are out of sequence. Move them to put them in the
proper place.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index c8d734d9f5fc..770aa2e7970c 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -303,6 +303,22 @@
#size-cells = <0>;
};
+ ehci0: usb at 2a000 {
+ compatible = "generic-ehci";
+ reg = <0x2a000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ ohci0: usb at 2b000 {
+ compatible = "generic-ohci";
+ reg = <0x2b000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
crypto at 2f000 {
compatible = "brcm,spum-nsp-crypto";
reg = <0x2f000 0x900>;
@@ -327,22 +343,6 @@
status = "disabled";
};
- ehci0: usb at 2a000 {
- compatible = "generic-ehci";
- reg = <0x2a000 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
- ohci0: usb at 2b000 {
- compatible = "generic-ohci";
- reg = <0x2b000 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
rng: rng at 33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/3] ARM: dts: NSP: Add USB3 and USB3 PHY to NSP
2017-07-25 22:06 ` Jon Mason
@ 2017-07-25 22:06 ` Jon Mason
-1 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: Florian Fainelli, Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list, devicetree, linux-arm-kernel, linux-kernel
This uses the existing Northstar USB3 PHY driver to enable the USB3
ports on NSP.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 19 +++++++++++++++++++
arch/arm/boot/dts/bcm958522er.dts | 8 ++++++++
arch/arm/boot/dts/bcm958525er.dts | 8 ++++++++
arch/arm/boot/dts/bcm958525xmc.dts | 8 ++++++++
arch/arm/boot/dts/bcm958622hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958623hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958625hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958625k.dts | 8 ++++++++
8 files changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 770aa2e7970c..8ba53b834cc8 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -303,6 +303,16 @@
#size-cells = <0>;
};
+ xhci: usb@29000 {
+ compatible = "generic-xhci";
+ reg = <0x29000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb3-phy";
+ dma-coherent;
+ status = "disabled";
+ };
+
ehci0: usb@2a000 {
compatible = "generic-ehci";
reg = <0x2a000 0x100>;
@@ -471,6 +481,15 @@
phy-names = "sata-phy";
};
};
+
+ usb3_phy: usb3-phy@104000 {
+ compatible = "brcm,ns-bx-usb3-phy";
+ reg = <0x104000 0x1000>,
+ <0x032000 0x1000>;
+ reg-names = "dmp", "ccb-mii";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
pcie0: pcie@18012000 {
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index f5c42962c201..f9dd342cc2ae 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -170,3 +170,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index efcb1f67bdad..374508a9cfbf 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -182,3 +182,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index b335ce02e32f..403250c5ad8e 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -202,3 +202,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index 16ab2d82a14b..fd8b8c689ffe 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -219,3 +219,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index 9b921c6aa8f8..3bc50849d013 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -227,3 +227,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index 006b08e41a3b..d94d14b3c745 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -229,3 +229,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 64740f85cf4c..2cf2392483b2 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -264,3 +264,11 @@
&uart1 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/3] ARM: dts: NSP: Add USB3 and USB3 PHY to NSP
@ 2017-07-25 22:06 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-25 22:06 UTC (permalink / raw)
To: linux-arm-kernel
This uses the existing Northstar USB3 PHY driver to enable the USB3
ports on NSP.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 19 +++++++++++++++++++
arch/arm/boot/dts/bcm958522er.dts | 8 ++++++++
arch/arm/boot/dts/bcm958525er.dts | 8 ++++++++
arch/arm/boot/dts/bcm958525xmc.dts | 8 ++++++++
arch/arm/boot/dts/bcm958622hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958623hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958625hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958625k.dts | 8 ++++++++
8 files changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 770aa2e7970c..8ba53b834cc8 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -303,6 +303,16 @@
#size-cells = <0>;
};
+ xhci: usb at 29000 {
+ compatible = "generic-xhci";
+ reg = <0x29000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb3-phy";
+ dma-coherent;
+ status = "disabled";
+ };
+
ehci0: usb at 2a000 {
compatible = "generic-ehci";
reg = <0x2a000 0x100>;
@@ -471,6 +481,15 @@
phy-names = "sata-phy";
};
};
+
+ usb3_phy: usb3-phy at 104000 {
+ compatible = "brcm,ns-bx-usb3-phy";
+ reg = <0x104000 0x1000>,
+ <0x032000 0x1000>;
+ reg-names = "dmp", "ccb-mii";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
pcie0: pcie at 18012000 {
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index f5c42962c201..f9dd342cc2ae 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -170,3 +170,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index efcb1f67bdad..374508a9cfbf 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -182,3 +182,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index b335ce02e32f..403250c5ad8e 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -202,3 +202,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index 16ab2d82a14b..fd8b8c689ffe 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -219,3 +219,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index 9b921c6aa8f8..3bc50849d013 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -227,3 +227,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index 006b08e41a3b..d94d14b3c745 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -229,3 +229,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 64740f85cf4c..2cf2392483b2 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -264,3 +264,11 @@
&uart1 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
[not found] ` <1501020372-19607-2-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-08-07 17:28 ` [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT Florian Fainelli
@ 2017-07-26 10:19 ` Robin Murphy
1 sibling, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2017-07-26 10:19 UTC (permalink / raw)
To: Jon Mason, Florian Fainelli, Rob Herring, Mark Rutland
Cc: devicetree, bcm-kernel-feedback-list, linux-kernel, linux-arm-kernel
Hi Jon,
On 25/07/17 23:06, Jon Mason wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index 7204d1def23d..c8d734d9f5fc 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -207,6 +207,7 @@
> clocks = <&iprocslow>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> + dma-coherent;
Just to check, does this actually work? I ask because the pl330 driver
currently never sets src_cache_ctrl/dst_cache_ctrl to anything other
than noncacheable nonbufferable, so if your interconnect respects those
attributes this seems liable to make things go wrong under current
kernels, even if it is an accurate description of the hardware. If on
the other hand the interconnect does its own magic and will manage to
snoop caches appropriately regardless of AXI attributes, then I guess
it's fine, if a little scary ;)
Robin.
> };
>
> sdio: sdhci@21000 {
> @@ -215,6 +216,7 @@
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> sdhci,auto-cmd12;
> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -224,6 +226,7 @@
> <0x110000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -233,6 +236,7 @@
> <0x111000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -242,6 +246,7 @@
> <0x112000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -252,6 +257,7 @@
> #mbox-cells = <1>;
> brcm,rx-status-len = <32>;
> brcm,use-bcm-hdr;
> + dma-coherent;
> };
>
> nand: nand@26000 {
> @@ -325,6 +331,7 @@
> compatible = "generic-ehci";
> reg = <0x2a000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -332,6 +339,7 @@
> compatible = "generic-ohci";
> reg = <0x2b000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -364,6 +372,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> + dma-coherent;
> status = "disabled";
>
> /* ports are defined in board DTS */
> @@ -376,6 +385,7 @@
> #size-cells = <0>;
> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
> clock-frequency = <100000>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -446,6 +456,7 @@
> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + dma-coherent;
> status = "disabled";
>
> sata0: sata-port@0 {
> @@ -483,6 +494,7 @@
> */
> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi0>;
> @@ -519,6 +531,7 @@
> */
> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi1>;
> @@ -555,6 +568,7 @@
> */
> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi2>;
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
@ 2017-07-26 10:19 ` Robin Murphy
0 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2017-07-26 10:19 UTC (permalink / raw)
To: Jon Mason, Florian Fainelli, Rob Herring, Mark Rutland
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi Jon,
On 25/07/17 23:06, Jon Mason wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index 7204d1def23d..c8d734d9f5fc 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -207,6 +207,7 @@
> clocks = <&iprocslow>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> + dma-coherent;
Just to check, does this actually work? I ask because the pl330 driver
currently never sets src_cache_ctrl/dst_cache_ctrl to anything other
than noncacheable nonbufferable, so if your interconnect respects those
attributes this seems liable to make things go wrong under current
kernels, even if it is an accurate description of the hardware. If on
the other hand the interconnect does its own magic and will manage to
snoop caches appropriately regardless of AXI attributes, then I guess
it's fine, if a little scary ;)
Robin.
> };
>
> sdio: sdhci@21000 {
> @@ -215,6 +216,7 @@
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> sdhci,auto-cmd12;
> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -224,6 +226,7 @@
> <0x110000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -233,6 +236,7 @@
> <0x111000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -242,6 +246,7 @@
> <0x112000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -252,6 +257,7 @@
> #mbox-cells = <1>;
> brcm,rx-status-len = <32>;
> brcm,use-bcm-hdr;
> + dma-coherent;
> };
>
> nand: nand@26000 {
> @@ -325,6 +331,7 @@
> compatible = "generic-ehci";
> reg = <0x2a000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -332,6 +339,7 @@
> compatible = "generic-ohci";
> reg = <0x2b000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -364,6 +372,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> + dma-coherent;
> status = "disabled";
>
> /* ports are defined in board DTS */
> @@ -376,6 +385,7 @@
> #size-cells = <0>;
> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
> clock-frequency = <100000>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -446,6 +456,7 @@
> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + dma-coherent;
> status = "disabled";
>
> sata0: sata-port@0 {
> @@ -483,6 +494,7 @@
> */
> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi0>;
> @@ -519,6 +531,7 @@
> */
> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi1>;
> @@ -555,6 +568,7 @@
> */
> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi2>;
>
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
@ 2017-07-26 10:19 ` Robin Murphy
0 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2017-07-26 10:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jon,
On 25/07/17 23:06, Jon Mason wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index 7204d1def23d..c8d734d9f5fc 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -207,6 +207,7 @@
> clocks = <&iprocslow>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> + dma-coherent;
Just to check, does this actually work? I ask because the pl330 driver
currently never sets src_cache_ctrl/dst_cache_ctrl to anything other
than noncacheable nonbufferable, so if your interconnect respects those
attributes this seems liable to make things go wrong under current
kernels, even if it is an accurate description of the hardware. If on
the other hand the interconnect does its own magic and will manage to
snoop caches appropriately regardless of AXI attributes, then I guess
it's fine, if a little scary ;)
Robin.
> };
>
> sdio: sdhci at 21000 {
> @@ -215,6 +216,7 @@
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> sdhci,auto-cmd12;
> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -224,6 +226,7 @@
> <0x110000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -233,6 +236,7 @@
> <0x111000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -242,6 +246,7 @@
> <0x112000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -252,6 +257,7 @@
> #mbox-cells = <1>;
> brcm,rx-status-len = <32>;
> brcm,use-bcm-hdr;
> + dma-coherent;
> };
>
> nand: nand at 26000 {
> @@ -325,6 +331,7 @@
> compatible = "generic-ehci";
> reg = <0x2a000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -332,6 +339,7 @@
> compatible = "generic-ohci";
> reg = <0x2b000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -364,6 +372,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> + dma-coherent;
> status = "disabled";
>
> /* ports are defined in board DTS */
> @@ -376,6 +385,7 @@
> #size-cells = <0>;
> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
> clock-frequency = <100000>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -446,6 +456,7 @@
> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + dma-coherent;
> status = "disabled";
>
> sata0: sata-port at 0 {
> @@ -483,6 +494,7 @@
> */
> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi0>;
> @@ -519,6 +531,7 @@
> */
> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi1>;
> @@ -555,6 +568,7 @@
> */
> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi2>;
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
2017-07-26 10:19 ` Robin Murphy
(?)
(?)
@ 2017-07-26 22:45 ` Jon Mason
-1 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-26 22:45 UTC (permalink / raw)
To: Robin Murphy
Cc: Florian Fainelli, Rob Herring, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
BCM Kernel Feedback, open list, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 6653 bytes --]
On Wed, Jul 26, 2017 at 6:19 AM, Robin Murphy <robin.murphy@arm.com> wrote:
> Hi Jon,
>
> On 25/07/17 23:06, Jon Mason wrote:
> > Cache related issues with DMA rings and performance issues related to
> > caching are being caused by not properly setting the "dma-coherent" flag
> > in the device tree entries. Adding it here to correct the issue.
> >
> > Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> > Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> > Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> > Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> > Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> > Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> > Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device
> tree")
> > Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block
> node")
> > Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> > Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> > Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> > ---
> > arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.
> dtsi
> > index 7204d1def23d..c8d734d9f5fc 100644
> > --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> > +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> > @@ -207,6 +207,7 @@
> > clocks = <&iprocslow>;
> > clock-names = "apb_pclk";
> > #dma-cells = <1>;
> > + dma-coherent;
>
> Just to check, does this actually work? I ask because the pl330 driver
> currently never sets src_cache_ctrl/dst_cache_ctrl to anything other
> than noncacheable nonbufferable, so if your interconnect respects those
> attributes this seems liable to make things go wrong under current
> kernels, even if it is an accurate description of the hardware. If on
> the other hand the interconnect does its own magic and will manage to
> snoop caches appropriately regardless of AXI attributes, then I guess
> it's fine, if a little scary ;)
>
This is what we've being using in-house for some time without any noticed
side effects, though it is possible there are some.
We've been basing the dma-coherent enablement on an internal register on
each IP block that enables/disables the coherency for it. It could be
possible that we've made the block coherent in this register in the
bootloader (or the power-on default is enabled). However, your comment
above concerns me greatly. I will remove this portion from this patch for
v2, and bottom out internally on whether this is a bug or not.
Thanks for the eyeballs :)
Thanks,
Jon
>
> Robin.
>
> > };
> >
> > sdio: sdhci@21000 {
> > @@ -215,6 +216,7 @@
> > interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> > sdhci,auto-cmd12;
> > clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
> > + dma-coherent;
> > status = "disabled";
> > };
> >
> > @@ -224,6 +226,7 @@
> > <0x110000 0x1000>;
> > reg-names = "amac_base", "idm_base";
> > interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > status = "disabled";
> > };
> >
> > @@ -233,6 +236,7 @@
> > <0x111000 0x1000>;
> > reg-names = "amac_base", "idm_base";
> > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > status = "disabled";
> > };
> >
> > @@ -242,6 +246,7 @@
> > <0x112000 0x1000>;
> > reg-names = "amac_base", "idm_base";
> > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > status = "disabled";
> > };
> >
> > @@ -252,6 +257,7 @@
> > #mbox-cells = <1>;
> > brcm,rx-status-len = <32>;
> > brcm,use-bcm-hdr;
> > + dma-coherent;
> > };
> >
> > nand: nand@26000 {
> > @@ -325,6 +331,7 @@
> > compatible = "generic-ehci";
> > reg = <0x2a000 0x100>;
> > interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > status = "disabled";
> > };
> >
> > @@ -332,6 +339,7 @@
> > compatible = "generic-ohci";
> > reg = <0x2b000 0x100>;
> > interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > status = "disabled";
> > };
> >
> > @@ -364,6 +372,7 @@
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > + dma-coherent;
> > status = "disabled";
> >
> > /* ports are defined in board DTS */
> > @@ -376,6 +385,7 @@
> > #size-cells = <0>;
> > interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
> > clock-frequency = <100000>;
> > + dma-coherent;
> > status = "disabled";
> > };
> >
> > @@ -446,6 +456,7 @@
> > interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + dma-coherent;
> > status = "disabled";
> >
> > sata0: sata-port@0 {
> > @@ -483,6 +494,7 @@
> > */
> > ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
> >
> > + dma-coherent;
> > status = "disabled";
> >
> > msi-parent = <&msi0>;
> > @@ -519,6 +531,7 @@
> > */
> > ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
> >
> > + dma-coherent;
> > status = "disabled";
> >
> > msi-parent = <&msi1>;
> > @@ -555,6 +568,7 @@
> > */
> > ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
> >
> > + dma-coherent;
> > status = "disabled";
> >
> > msi-parent = <&msi2>;
> >
>
>
[-- Attachment #2: Type: text/html, Size: 9645 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
[not found] ` <1501020372-19607-2-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-08-07 17:28 ` [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT Florian Fainelli
@ 2017-07-29 0:03 ` Florian Fainelli
1 sibling, 0 replies; 23+ messages in thread
From: Florian Fainelli @ 2017-07-29 0:03 UTC (permalink / raw)
To: Jon Mason, Florian Fainelli, Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list, devicetree, linux-arm-kernel, linux-kernel
On 07/25/2017 03:06 PM, Jon Mason wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
The SRAB block is not DMA capable, so this seems a bit superfluous here.
Do you want to submit a patch that omits PL330 for now and adds it
eventually later so I can proceed with applying patches 2 & 3 for this
cycle?
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index 7204d1def23d..c8d734d9f5fc 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -207,6 +207,7 @@
> clocks = <&iprocslow>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> + dma-coherent;
> };
>
> sdio: sdhci@21000 {
> @@ -215,6 +216,7 @@
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> sdhci,auto-cmd12;
> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -224,6 +226,7 @@
> <0x110000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -233,6 +236,7 @@
> <0x111000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -242,6 +246,7 @@
> <0x112000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -252,6 +257,7 @@
> #mbox-cells = <1>;
> brcm,rx-status-len = <32>;
> brcm,use-bcm-hdr;
> + dma-coherent;
> };
>
> nand: nand@26000 {
> @@ -325,6 +331,7 @@
> compatible = "generic-ehci";
> reg = <0x2a000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -332,6 +339,7 @@
> compatible = "generic-ohci";
> reg = <0x2b000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -364,6 +372,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> + dma-coherent;
> status = "disabled";
>
> /* ports are defined in board DTS */
> @@ -376,6 +385,7 @@
> #size-cells = <0>;
> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
> clock-frequency = <100000>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -446,6 +456,7 @@
> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + dma-coherent;
> status = "disabled";
>
> sata0: sata-port@0 {
> @@ -483,6 +494,7 @@
> */
> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi0>;
> @@ -519,6 +531,7 @@
> */
> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi1>;
> @@ -555,6 +568,7 @@
> */
> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi2>;
>
--
Florian
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
@ 2017-07-29 0:03 ` Florian Fainelli
0 siblings, 0 replies; 23+ messages in thread
From: Florian Fainelli @ 2017-07-29 0:03 UTC (permalink / raw)
To: Jon Mason, Florian Fainelli, Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 07/25/2017 03:06 PM, Jon Mason wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
The SRAB block is not DMA capable, so this seems a bit superfluous here.
Do you want to submit a patch that omits PL330 for now and adds it
eventually later so I can proceed with applying patches 2 & 3 for this
cycle?
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index 7204d1def23d..c8d734d9f5fc 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -207,6 +207,7 @@
> clocks = <&iprocslow>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> + dma-coherent;
> };
>
> sdio: sdhci@21000 {
> @@ -215,6 +216,7 @@
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> sdhci,auto-cmd12;
> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -224,6 +226,7 @@
> <0x110000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -233,6 +236,7 @@
> <0x111000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -242,6 +246,7 @@
> <0x112000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -252,6 +257,7 @@
> #mbox-cells = <1>;
> brcm,rx-status-len = <32>;
> brcm,use-bcm-hdr;
> + dma-coherent;
> };
>
> nand: nand@26000 {
> @@ -325,6 +331,7 @@
> compatible = "generic-ehci";
> reg = <0x2a000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -332,6 +339,7 @@
> compatible = "generic-ohci";
> reg = <0x2b000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -364,6 +372,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> + dma-coherent;
> status = "disabled";
>
> /* ports are defined in board DTS */
> @@ -376,6 +385,7 @@
> #size-cells = <0>;
> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
> clock-frequency = <100000>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -446,6 +456,7 @@
> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + dma-coherent;
> status = "disabled";
>
> sata0: sata-port@0 {
> @@ -483,6 +494,7 @@
> */
> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi0>;
> @@ -519,6 +531,7 @@
> */
> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi1>;
> @@ -555,6 +568,7 @@
> */
> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi2>;
>
--
Florian
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
@ 2017-07-29 0:03 ` Florian Fainelli
0 siblings, 0 replies; 23+ messages in thread
From: Florian Fainelli @ 2017-07-29 0:03 UTC (permalink / raw)
To: linux-arm-kernel
On 07/25/2017 03:06 PM, Jon Mason wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
The SRAB block is not DMA capable, so this seems a bit superfluous here.
Do you want to submit a patch that omits PL330 for now and adds it
eventually later so I can proceed with applying patches 2 & 3 for this
cycle?
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index 7204d1def23d..c8d734d9f5fc 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -207,6 +207,7 @@
> clocks = <&iprocslow>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> + dma-coherent;
> };
>
> sdio: sdhci at 21000 {
> @@ -215,6 +216,7 @@
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> sdhci,auto-cmd12;
> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -224,6 +226,7 @@
> <0x110000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -233,6 +236,7 @@
> <0x111000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -242,6 +246,7 @@
> <0x112000 0x1000>;
> reg-names = "amac_base", "idm_base";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -252,6 +257,7 @@
> #mbox-cells = <1>;
> brcm,rx-status-len = <32>;
> brcm,use-bcm-hdr;
> + dma-coherent;
> };
>
> nand: nand at 26000 {
> @@ -325,6 +331,7 @@
> compatible = "generic-ehci";
> reg = <0x2a000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -332,6 +339,7 @@
> compatible = "generic-ohci";
> reg = <0x2b000 0x100>;
> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -364,6 +372,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> + dma-coherent;
> status = "disabled";
>
> /* ports are defined in board DTS */
> @@ -376,6 +385,7 @@
> #size-cells = <0>;
> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
> clock-frequency = <100000>;
> + dma-coherent;
> status = "disabled";
> };
>
> @@ -446,6 +456,7 @@
> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + dma-coherent;
> status = "disabled";
>
> sata0: sata-port at 0 {
> @@ -483,6 +494,7 @@
> */
> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi0>;
> @@ -519,6 +531,7 @@
> */
> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi1>;
> @@ -555,6 +568,7 @@
> */
> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>
> + dma-coherent;
> status = "disabled";
>
> msi-parent = <&msi2>;
>
--
Florian
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
2017-07-29 0:03 ` Florian Fainelli
(?)
@ 2017-07-31 15:21 ` Jon Mason
-1 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-31 15:21 UTC (permalink / raw)
To: Florian Fainelli
Cc: Rob Herring, Mark Rutland, BCM Kernel Feedback,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, open list
On Fri, Jul 28, 2017 at 8:03 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 07/25/2017 03:06 PM, Jon Mason wrote:
>> Cache related issues with DMA rings and performance issues related to
>> caching are being caused by not properly setting the "dma-coherent" flag
>> in the device tree entries. Adding it here to correct the issue.
>>
>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
>> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
>> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
>> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
>> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
>> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
>> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
>
> The SRAB block is not DMA capable, so this seems a bit superfluous here.
I'll double check on that part as well.
> Do you want to submit a patch that omits PL330 for now and adds it
> eventually later so I can proceed with applying patches 2 & 3 for this
> cycle?
Yes, I'll do a v2 with those 2 portions removed, and double back to
add (if necessary) once I've bottomed out internally.
Thanks,
Jon
>> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
>> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
>> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
>> ---
>> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
>> index 7204d1def23d..c8d734d9f5fc 100644
>> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
>> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
>> @@ -207,6 +207,7 @@
>> clocks = <&iprocslow>;
>> clock-names = "apb_pclk";
>> #dma-cells = <1>;
>> + dma-coherent;
>> };
>>
>> sdio: sdhci@21000 {
>> @@ -215,6 +216,7 @@
>> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
>> sdhci,auto-cmd12;
>> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -224,6 +226,7 @@
>> <0x110000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -233,6 +236,7 @@
>> <0x111000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -242,6 +246,7 @@
>> <0x112000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -252,6 +257,7 @@
>> #mbox-cells = <1>;
>> brcm,rx-status-len = <32>;
>> brcm,use-bcm-hdr;
>> + dma-coherent;
>> };
>>
>> nand: nand@26000 {
>> @@ -325,6 +331,7 @@
>> compatible = "generic-ehci";
>> reg = <0x2a000 0x100>;
>> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -332,6 +339,7 @@
>> compatible = "generic-ohci";
>> reg = <0x2b000 0x100>;
>> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -364,6 +372,7 @@
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> /* ports are defined in board DTS */
>> @@ -376,6 +385,7 @@
>> #size-cells = <0>;
>> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
>> clock-frequency = <100000>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -446,6 +456,7 @@
>> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + dma-coherent;
>> status = "disabled";
>>
>> sata0: sata-port@0 {
>> @@ -483,6 +494,7 @@
>> */
>> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi0>;
>> @@ -519,6 +531,7 @@
>> */
>> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi1>;
>> @@ -555,6 +568,7 @@
>> */
>> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi2>;
>>
>
>
> --
> Florian
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
@ 2017-07-31 15:21 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-31 15:21 UTC (permalink / raw)
To: Florian Fainelli
Cc: Rob Herring, Mark Rutland, BCM Kernel Feedback,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, open list
On Fri, Jul 28, 2017 at 8:03 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 07/25/2017 03:06 PM, Jon Mason wrote:
>> Cache related issues with DMA rings and performance issues related to
>> caching are being caused by not properly setting the "dma-coherent" flag
>> in the device tree entries. Adding it here to correct the issue.
>>
>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
>> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
>> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
>> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
>> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
>> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
>> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
>
> The SRAB block is not DMA capable, so this seems a bit superfluous here.
I'll double check on that part as well.
> Do you want to submit a patch that omits PL330 for now and adds it
> eventually later so I can proceed with applying patches 2 & 3 for this
> cycle?
Yes, I'll do a v2 with those 2 portions removed, and double back to
add (if necessary) once I've bottomed out internally.
Thanks,
Jon
>> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
>> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
>> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
>> ---
>> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
>> index 7204d1def23d..c8d734d9f5fc 100644
>> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
>> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
>> @@ -207,6 +207,7 @@
>> clocks = <&iprocslow>;
>> clock-names = "apb_pclk";
>> #dma-cells = <1>;
>> + dma-coherent;
>> };
>>
>> sdio: sdhci@21000 {
>> @@ -215,6 +216,7 @@
>> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
>> sdhci,auto-cmd12;
>> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -224,6 +226,7 @@
>> <0x110000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -233,6 +236,7 @@
>> <0x111000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -242,6 +246,7 @@
>> <0x112000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -252,6 +257,7 @@
>> #mbox-cells = <1>;
>> brcm,rx-status-len = <32>;
>> brcm,use-bcm-hdr;
>> + dma-coherent;
>> };
>>
>> nand: nand@26000 {
>> @@ -325,6 +331,7 @@
>> compatible = "generic-ehci";
>> reg = <0x2a000 0x100>;
>> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -332,6 +339,7 @@
>> compatible = "generic-ohci";
>> reg = <0x2b000 0x100>;
>> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -364,6 +372,7 @@
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> /* ports are defined in board DTS */
>> @@ -376,6 +385,7 @@
>> #size-cells = <0>;
>> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
>> clock-frequency = <100000>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -446,6 +456,7 @@
>> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + dma-coherent;
>> status = "disabled";
>>
>> sata0: sata-port@0 {
>> @@ -483,6 +494,7 @@
>> */
>> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi0>;
>> @@ -519,6 +531,7 @@
>> */
>> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi1>;
>> @@ -555,6 +568,7 @@
>> */
>> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi2>;
>>
>
>
> --
> Florian
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries
@ 2017-07-31 15:21 ` Jon Mason
0 siblings, 0 replies; 23+ messages in thread
From: Jon Mason @ 2017-07-31 15:21 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 28, 2017 at 8:03 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 07/25/2017 03:06 PM, Jon Mason wrote:
>> Cache related issues with DMA rings and performance issues related to
>> caching are being caused by not properly setting the "dma-coherent" flag
>> in the device tree entries. Adding it here to correct the issue.
>>
>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
>> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
>> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
>> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
>> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
>> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
>> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
>
> The SRAB block is not DMA capable, so this seems a bit superfluous here.
I'll double check on that part as well.
> Do you want to submit a patch that omits PL330 for now and adds it
> eventually later so I can proceed with applying patches 2 & 3 for this
> cycle?
Yes, I'll do a v2 with those 2 portions removed, and double back to
add (if necessary) once I've bottomed out internally.
Thanks,
Jon
>> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
>> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
>> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
>> ---
>> arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
>> index 7204d1def23d..c8d734d9f5fc 100644
>> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
>> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
>> @@ -207,6 +207,7 @@
>> clocks = <&iprocslow>;
>> clock-names = "apb_pclk";
>> #dma-cells = <1>;
>> + dma-coherent;
>> };
>>
>> sdio: sdhci at 21000 {
>> @@ -215,6 +216,7 @@
>> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
>> sdhci,auto-cmd12;
>> clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -224,6 +226,7 @@
>> <0x110000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -233,6 +236,7 @@
>> <0x111000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -242,6 +246,7 @@
>> <0x112000 0x1000>;
>> reg-names = "amac_base", "idm_base";
>> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -252,6 +257,7 @@
>> #mbox-cells = <1>;
>> brcm,rx-status-len = <32>;
>> brcm,use-bcm-hdr;
>> + dma-coherent;
>> };
>>
>> nand: nand at 26000 {
>> @@ -325,6 +331,7 @@
>> compatible = "generic-ehci";
>> reg = <0x2a000 0x100>;
>> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -332,6 +339,7 @@
>> compatible = "generic-ohci";
>> reg = <0x2b000 0x100>;
>> interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -364,6 +372,7 @@
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> /* ports are defined in board DTS */
>> @@ -376,6 +385,7 @@
>> #size-cells = <0>;
>> interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
>> clock-frequency = <100000>;
>> + dma-coherent;
>> status = "disabled";
>> };
>>
>> @@ -446,6 +456,7 @@
>> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + dma-coherent;
>> status = "disabled";
>>
>> sata0: sata-port at 0 {
>> @@ -483,6 +494,7 @@
>> */
>> ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi0>;
>> @@ -519,6 +531,7 @@
>> */
>> ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi1>;
>> @@ -555,6 +568,7 @@
>> */
>> ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
>>
>> + dma-coherent;
>> status = "disabled";
>>
>> msi-parent = <&msi2>;
>>
>
>
> --
> Florian
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT
[not found] ` <1501020372-19607-2-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
@ 2017-08-07 17:28 ` Florian Fainelli
2017-08-07 17:28 ` Florian Fainelli
1 sibling, 0 replies; 23+ messages in thread
From: Florian Fainelli @ 2017-08-07 17:28 UTC (permalink / raw)
To: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Jon Mason, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
On Tue, 25 Jul 2017 18:06:10 -0400, Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
Applied, thanks!
--
Florian
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT
[not found] ` <1501020372-19607-2-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-08-07 17:28 ` [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT Florian Fainelli
@ 2017-08-07 17:28 ` Florian Fainelli
1 sibling, 0 replies; 23+ messages in thread
From: Florian Fainelli @ 2017-08-07 17:28 UTC (permalink / raw)
To: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Jon Mason, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
On Tue, 25 Jul 2017 18:06:10 -0400, Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
> Cache related issues with DMA rings and performance issues related to
> caching are being caused by not properly setting the "dma-coherent" flag
> in the device tree entries. Adding it here to correct the issue.
>
> Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")
> Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support")
> Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries")
> Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2")
> Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
> Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
> Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node")
> Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
> Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry")
> Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
> ---
Applied, thanks!
--
Florian
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/3] ARM: dts: NSP: Rearrage USB entries
[not found] ` <1501020372-19607-3-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
@ 2017-08-07 17:28 ` Florian Fainelli
0 siblings, 0 replies; 23+ messages in thread
From: Florian Fainelli @ 2017-08-07 17:28 UTC (permalink / raw)
To: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Jon Mason, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
On Tue, 25 Jul 2017 18:06:11 -0400, Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
> The rest of the DTSI file is in incrementing addresses, but the USB
> OHCI/ECHI entries are out of sequence. Move them to put them in the
> proper place.
>
> Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> ---
Applied, thanks!
--
Florian
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/3] ARM: dts: NSP: Add USB3 and USB3 PHY to NSP
[not found] ` <1501020372-19607-4-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
@ 2017-08-07 17:28 ` Florian Fainelli
0 siblings, 0 replies; 23+ messages in thread
From: Florian Fainelli @ 2017-08-07 17:28 UTC (permalink / raw)
To: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Jon Mason, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
On Tue, 25 Jul 2017 18:06:12 -0400, Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
> This uses the existing Northstar USB3 PHY driver to enable the USB3
> ports on NSP.
>
> Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> ---
Applied, thanks!
--
Florian
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^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2017-08-07 17:28 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-25 22:06 [PATCH 0/3] ARM: dts: NSP: dma-coherent and USB3 changes Jon Mason
2017-07-25 22:06 ` Jon Mason
2017-07-25 22:06 ` Jon Mason
2017-07-25 22:06 ` [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries Jon Mason
2017-07-25 22:06 ` Jon Mason
2017-07-26 10:19 ` Robin Murphy
2017-07-26 10:19 ` Robin Murphy
2017-07-26 10:19 ` Robin Murphy
2017-07-26 22:45 ` Jon Mason
2017-07-29 0:03 ` Florian Fainelli
2017-07-29 0:03 ` Florian Fainelli
2017-07-29 0:03 ` Florian Fainelli
2017-07-31 15:21 ` Jon Mason
2017-07-31 15:21 ` Jon Mason
2017-07-31 15:21 ` Jon Mason
2017-07-25 22:06 ` [PATCH 2/3] ARM: dts: NSP: Rearrage USB entries Jon Mason
2017-07-25 22:06 ` Jon Mason
2017-07-25 22:06 ` [PATCH 3/3] ARM: dts: NSP: Add USB3 and USB3 PHY to NSP Jon Mason
2017-07-25 22:06 ` Jon Mason
[not found] ` <1501020372-19607-2-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-08-07 17:28 ` [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT Florian Fainelli
2017-08-07 17:28 ` Florian Fainelli
[not found] ` <1501020372-19607-3-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-08-07 17:28 ` [PATCH 2/3] ARM: dts: NSP: Rearrage USB entries Florian Fainelli
[not found] ` <1501020372-19607-4-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-08-07 17:28 ` [PATCH 3/3] ARM: dts: NSP: Add USB3 and USB3 PHY to NSP Florian Fainelli
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